tu102 = {
  'NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO': (0x0, 0x00100A18, {'full': (0, 0)}),
  'NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE': 0x0,
  'NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE': 0x1,
  'NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE': (0x0, 64, {}),
  'NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE': (0x0, 132, {}),
  'NV_PFB_PRI_MMU_WPR2_ADDR_LO': (0x0, 0x001FA824, {'val': (4, 31)}),
  'NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT': 0x0000000c,
  'NV_PFB_PRI_MMU_WPR2_ADDR_HI': (0x0, 0x001FA828, {'val': (4, 31)}),
  'NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT': 0x0000000c,
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET': (0x0, 0x00000000, {}),
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE': (0x0, 0x00000000, {}),
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE': (0x0, 0x00000001, {}),
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO': (0x0, 0x00000000, {}),
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES': (0x0, 0x00000001, {}),
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE': (0x0, 0x00000000, {}),
  'NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE': (0x0, 0x00000001, {}),
  'NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT': (0x0, 0x00100E78, {'total': (0, 15), 'unique': (16, 31)}),
  'NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT': 0,
  'NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT': 0,
  'NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT': (0x0, 0x00100E8C, {'total': (0, 15), 'unique': (16, 31)}),
  'NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT': 0,
  'NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT': 0,
  'NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT': (0x0, 0x00100EA0, {'total': (0, 15), 'unique': (16, 31)}),
  'NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT': 0,
  'NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT': 0,
}