forked from tinygrad/tinygrad
* ops_risk * risk sim * guessing is for winners * minor * better * matmal with risk * conv doesn't work * closer * conv2d works * ops_risk * opt2 works * opt1 may not be possible * opt1 is a mulacc * arty * attosoc example building on mac * minor * riscv assembler * gucci gang * we got C code * not a scam * hello * make risk mergeable into master * unop support
16 lines
239 B
Python
Executable File
16 lines
239 B
Python
Executable File
#!/usr/bin/env python3
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import time
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import pyftdi.serialext
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port = pyftdi.serialext.serial_for_url('ftdi://ftdi:2232h/2', baudrate=115200)
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print(port)
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while 1:
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#port.write(b'a')
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data = port.read(1)
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print(data)
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time.sleep(0.01)
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