b1tgandGitHub 81108f91ee amd tc: 16x16x32 (#12874) ...

* amd tc: 16x16x32

* test

* clean, test amd_cdna4

2025-10-22 13:48:01 -04:00

..

__init__.py

new linearizer with early endrange (#12823)

2025-10-21 17:37:48 +08:00

cstyle.py

amd tc: 16x16x32 (#12874)

2025-10-22 13:48:01 -04:00

llvmir.py

amd tc: 16x16x32 (#12874)

2025-10-22 13:48:01 -04:00

nir.py

rename Ops.ENDRANGE -> Ops.END (#12824)

2025-10-21 11:32:18 +08:00

ptx.py

late ifs try 2 (#12865)

2025-10-22 18:49:27 +08:00

wgsl.py

add allow_any_len to gated load patterns in renderers (#12406)

2025-10-01 20:35:32 +02:00