forked from tinygrad/tinygrad
105 lines
3.4 KiB
Python
105 lines
3.4 KiB
Python
import unittest
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from tinygrad import Tensor, UOp
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from tinygrad.device import Device
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from tinygrad.dtype import AddrSpace, dtypes
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from tinygrad.renderer.nir import NIRRenderer
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from tinygrad.renderer.isa.x86 import X86Renderer
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from tinygrad.uop.ops import KernelInfo
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def wait_loop_kernel(C:UOp) -> UOp:
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N = 10
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# a RANGE with no src is a bound-less loop header: a jump target with no induction variable.
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# the compare and conditional backedge are expanded by the renderers from the loop RANGE/END
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l = UOp.loop(0)
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i = UOp.placeholder((1,), dtypes.int, 0, addrspace=AddrSpace.REG)
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# i = 0
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i = i.after(i[0].store(0))
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# i + 1, read loop-carried through after(l)
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inc = i.after(l)[0].load() + 1
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# i = inc; END(store, l, cond): conditional backedge, loop again while inc < N (do-while)
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# NOTE: the cond uses the computed value, not a reload of the register
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st = i[0].store(inc)
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i = i.after(st.end(l, inc < N))
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return C[0].store(i[0].load()).sink(arg=KernelInfo(name="wait_loop"))
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def nested_loop_kernel(C:UOp) -> UOp:
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r = UOp.range(4, 0)
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l = UOp.loop(1)
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i = UOp.placeholder((1,), dtypes.int, 0, addrspace=AddrSpace.REG)
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i = i.after(i[0].store(0))
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inc = i.after(l, r)[0].load() + 1
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st = i[0].store(inc)
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lend = st.end(l, inc < (r.cast(dtypes.int)+1)*3)
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i = i.after(lend.end(r))
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return C[0].store(i[0].load()).sink(arg=KernelInfo(name="nested_loop", opts_to_apply=()))
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def two_loops_kernel(C:UOp) -> UOp:
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# two sequential loops on the same counter: ++ until 10, then ++ until 25
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l1, l2 = UOp.loop(0), UOp.loop(1)
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i = UOp.placeholder((1,), dtypes.int, 0, addrspace=AddrSpace.REG)
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i = i.after(i[0].store(0))
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inc1 = i.after(l1)[0].load() + 1
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i = i.after(i[0].store(inc1).end(l1, inc1 < 10))
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inc2 = i.after(l2)[0].load() + 1
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i = i.after(i[0].store(inc2).end(l2, inc2 < 25))
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return C[0].store(i[0].load()).sink(arg=KernelInfo(name="two_loops", opts_to_apply=()))
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def loop_in_loop_kernel(C:UOp) -> UOp:
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# outer loop while i < 12, inner loop increments until i % 4 == 0 -> 12
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l1, l2 = UOp.loop(0), UOp.loop(1)
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i = UOp.placeholder((1,), dtypes.int, 0, addrspace=AddrSpace.REG)
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i = i.after(i[0].store(0))
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inc = i.after(l1, l2)[0].load() + 1
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st = i[0].store(inc)
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# the outer END closes the inner END, and its cond reloads the register after the inner loop (in scope at the outer level)
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e2 = st.end(l2, inc % 4 != 0)
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oc = i.after(e2)[0].load()
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i = i.after(e2.end(l1, oc < 12))
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return C[0].store(i[0].load()).sink(arg=KernelInfo(name="loop_in_loop", opts_to_apply=()))
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@unittest.skipIf(isinstance(Device[Device.DEFAULT].renderer, (NIRRenderer, X86Renderer)), "loops are not supported in LVP and X86")
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class TestWaitLoop(unittest.TestCase):
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def test_wait_loop(self):
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c = Tensor.empty(1, dtype=dtypes.int)
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c = Tensor.custom_kernel(c, fxn=wait_loop_kernel)[0]
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c.realize()
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self.assertEqual(c.item(), 10)
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def test_nested_loop_in_range(self):
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c = Tensor.empty(1, dtype=dtypes.int)
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c = Tensor.custom_kernel(c, fxn=nested_loop_kernel)[0]
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c.realize()
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self.assertEqual(c.item(), 12)
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def test_two_sequential_loops(self):
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c = Tensor.empty(1, dtype=dtypes.int)
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c = Tensor.custom_kernel(c, fxn=two_loops_kernel)[0]
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c.realize()
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self.assertEqual(c.item(), 25)
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def test_loop_in_loop(self):
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c = Tensor.empty(1, dtype=dtypes.int)
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c = Tensor.custom_kernel(c, fxn=loop_in_loop_kernel)[0]
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c.realize()
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self.assertEqual(c.item(), 12)
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if __name__ == "__main__": unittest.main()
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