forked from tinygrad/tinygrad
30bd6a619f
* start gpu * progress * fixes * read correct * libusb * libusb works * support asm24 * hmm * one access file * fix extra * start AMBar * works on am * back to usb * patch fw * full fast write into a bar * ugh, minus one gpus, next please * mute libusb for now * usb for asm24 * 63 * hmm * ops * rescan * and gpu shoudl be there * enumerate them? * usbgpu bus 4, 100% reliable (draft) * lil * works * comments * add DEBUG * cleaner * simplest * Revert "simplest" This reverts commit1d00354c16. * Revert "cleaner" This reverts commitc5662de956. * assert we find gpu * that's simpler * this back * simpler? * correcT * work * nonsense * works with more checks * this works * the 6s in the right place * reliable now * fix after reboot * set config * 1s timeouts * close to fw loading * streams * usbhub works * endpoints * fix * want to test tiny10 * move to tiny 10 * fix gpu * ugly speed * smth * mostly broken, but signals and dmas * do not reset gpu every time * changes to run kernels * ugh, not working * t10 * pg and sc files * some prog * um? * somehow it works * patched for 24 * some tries * minimal * moving * back to working * so sloooooow * move to controller * usb.py rewrite * rework * cleaner 1 * cleaner 2 * cleaner 3 * new abstractions * aft merge * init controller * cleaner 4 * cleaner 5 * patcher + tiny changes * ignore that * cleaner 6 * after rebase * cleaner 7 * bring it back * start linter war * linter 2 * autogen was missing * fix autogen * typing * better? * mypy * extra/legacy rename and cleaner * shuffle * better printing * tiny changes and tests --------- Co-authored-by: George Hotz <[email protected]>
39 lines
1.2 KiB
Python
39 lines
1.2 KiB
Python
import unittest, time
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from tinygrad.runtime.support.usb import ASM24Controller
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class TestASMController(unittest.TestCase):
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@classmethod
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def setUpClass(cls):
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cls.ctrl = ASM24Controller()
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def test_write_and_read(self):
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base = 0xF000
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data = b"hello!"
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self.ctrl.write(base, data)
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out = self.ctrl.read(base, len(data))
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self.assertEqual(out, data)
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def test_scsi_write_and_read_from_f000(self):
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payload = bytes([0x5B]) * 4096
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self.ctrl.scsi_write(payload, lba=0)
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back = self.ctrl.read(0xF000, len(payload))
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self.assertEqual(back, payload)
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def test_scsi_write_speed_4k(self):
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payload = bytes([0x5A]) * 4096
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start = time.perf_counter()
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self.ctrl.scsi_write(payload, lba=0)
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dur_ms = (time.perf_counter() - start) * 1000
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print(f"scsi_write 4K took {dur_ms:.3f} ms")
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def test_read_speed_4k(self):
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payload = bytes([0xA5]) * 4096
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self.ctrl.write(0xF000, payload)
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start = time.perf_counter()
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out = self.ctrl.read(0xF000, 4096)
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dur_ms = (time.perf_counter() - start) * 1000
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print(f"read 4K took {dur_ms:.3f} ms")
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self.assertEqual(out, payload)
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if __name__ == "__main__":
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unittest.main() |