tu102 = {
  'NV_MMU_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
  'NV_MMU_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_PDE_SIZE_FULL': 0x00000000,
  'NV_MMU_PDE_SIZE_HALF': 0x00000001,
  'NV_MMU_PDE_SIZE_QUARTER': 0x00000002,
  'NV_MMU_PDE_SIZE_EIGHTH': 0x00000003,
  'NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_PDE__SIZE': 8,
  'NV_MMU_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'lock': ((1*32+3), (1*32+3)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'read_disable': ((1*32+30), (1*32+30)), 'write_disable': ((1*32+31), (1*32+31)), 'kind': ((1*32+4), (1*32+11))}),
  'NV_MMU_PTE_VALID_TRUE': 0x1,
  'NV_MMU_PTE_VALID_FALSE': 0x0,
  'NV_MMU_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_PTE_LOCK_TRUE': 0x1,
  'NV_MMU_PTE_LOCK_FALSE': 0x0,
  'NV_MMU_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_PTE_READ_DISABLE_TRUE': 0x1,
  'NV_MMU_PTE_READ_DISABLE_FALSE': 0x0,
  'NV_MMU_PTE_WRITE_DISABLE_TRUE': 0x1,
  'NV_MMU_PTE_WRITE_DISABLE_FALSE': 0x0,
  'NV_MMU_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_PTE__SIZE': 8,
  'NV_MMU_PTE_COMPTAGS_NONE': 0x0,
  'NV_MMU_PTE_COMPTAGS_1': 0x1,
  'NV_MMU_PTE_COMPTAGS_2': 0x2,
  'NV_MMU_PTE_KIND_INVALID': 0x07,
  'NV_MMU_PTE_KIND_PITCH': 0x00,
  'NV_MMU_PTE_KIND_GENERIC_MEMORY': 0x06,
  'NV_MMU_PTE_KIND_Z16': 0x01,
  'NV_MMU_PTE_KIND_S8': 0x02,
  'NV_MMU_PTE_KIND_S8Z24': 0x03,
  'NV_MMU_PTE_KIND_ZF32_X24S8': 0x04,
  'NV_MMU_PTE_KIND_Z24S8': 0x05,
  'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE': 0x08,
  'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC': 0x09,
  'NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC': 0x0A,
  'NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC': 0x0B,
  'NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC': 0x0C,
  'NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC': 0x0D,
  'NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC': 0x0E,
  'NV_MMU_PTE_KIND_SMSKED_MESSAGE': 0x0F,
  'NV_MMU_PTE_KIND_Z16_2C': 0x2a,
  'NV_MMU_PTE_KIND_Z16_MS2_2C': 0x11,
  'NV_MMU_PTE_KIND_Z16_MS4_2C': 0xC3,
  'NV_MMU_PTE_KIND_Z16_MS8_2C': 0x46,
  'NV_MMU_PTE_KIND_Z16_MS16_2C': 0x6c,
  'NV_MMU_PTE_KIND_Z16_2Z': 0x6b,
  'NV_MMU_PTE_KIND_Z16_MS2_2Z': 0x10,
  'NV_MMU_PTE_KIND_Z16_MS4_2Z': 0x60,
  'NV_MMU_PTE_KIND_Z16_MS8_2Z': 0x61,
  'NV_MMU_PTE_KIND_Z16_MS16_2Z': 0x62,
  'NV_MMU_PTE_KIND_Z16_2CZ': 0x36,
  'NV_MMU_PTE_KIND_Z16_MS2_2CZ': 0x37,
  'NV_MMU_PTE_KIND_Z16_MS4_2CZ': 0x38,
  'NV_MMU_PTE_KIND_Z16_MS8_2CZ': 0x39,
  'NV_MMU_PTE_KIND_Z16_MS16_2CZ': 0x5f,
  'NV_MMU_PTE_KIND_S8Z24_1Z': 0x12,
  'NV_MMU_PTE_KIND_S8Z24_MS2_1Z': 0x13,
  'NV_MMU_PTE_KIND_S8Z24_MS4_1Z': 0x14,
  'NV_MMU_PTE_KIND_S8Z24_MS8_1Z': 0x15,
  'NV_MMU_PTE_KIND_S8Z24_MS16_1Z': 0x16,
  'NV_MMU_PTE_KIND_S8Z24_2CZ': 0x17,
  'NV_MMU_PTE_KIND_S8Z24_MS2_2CZ': 0x18,
  'NV_MMU_PTE_KIND_S8Z24_MS4_2CZ': 0x19,
  'NV_MMU_PTE_KIND_S8Z24_MS8_2CZ': 0x1a,
  'NV_MMU_PTE_KIND_S8Z24_MS16_2CZ': 0x1b,
  'NV_MMU_PTE_KIND_S8Z24_2CS': 0x1c,
  'NV_MMU_PTE_KIND_S8Z24_MS2_2CS': 0x1d,
  'NV_MMU_PTE_KIND_S8Z24_MS4_2CS': 0x1e,
  'NV_MMU_PTE_KIND_S8Z24_MS8_2CS': 0x1f,
  'NV_MMU_PTE_KIND_S8Z24_MS16_2CS': 0x20,
  'NV_MMU_PTE_KIND_S8Z24_4CSZV': 0x21,
  'NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV': 0x22,
  'NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV': 0x23,
  'NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV': 0x24,
  'NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV': 0x25,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC12': 0x26,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC4': 0x27,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC8': 0x28,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC24': 0x29,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV': 0x2e,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV': 0x2f,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV': 0x30,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV': 0x31,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS': 0x32,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS': 0x33,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS': 0x34,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS': 0x35,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV': 0x3a,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV': 0x3b,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV': 0x3c,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV': 0x3d,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV': 0x3e,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV': 0x3f,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV': 0x40,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV': 0x41,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV': 0x42,
  'NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV': 0x43,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV': 0x44,
  'NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV': 0x45,
  'NV_MMU_PTE_KIND_Z24S8_1Z': 0x47,
  'NV_MMU_PTE_KIND_Z24S8_MS2_1Z': 0x48,
  'NV_MMU_PTE_KIND_Z24S8_MS4_1Z': 0x49,
  'NV_MMU_PTE_KIND_Z24S8_MS8_1Z': 0x4a,
  'NV_MMU_PTE_KIND_Z24S8_MS16_1Z': 0x4b,
  'NV_MMU_PTE_KIND_Z24S8_2CS': 0x4c,
  'NV_MMU_PTE_KIND_Z24S8_MS2_2CS': 0x4d,
  'NV_MMU_PTE_KIND_Z24S8_MS4_2CS': 0x4e,
  'NV_MMU_PTE_KIND_Z24S8_MS8_2CS': 0x4f,
  'NV_MMU_PTE_KIND_Z24S8_MS16_2CS': 0x50,
  'NV_MMU_PTE_KIND_Z24S8_2CZ': 0x51,
  'NV_MMU_PTE_KIND_Z24S8_MS2_2CZ': 0x52,
  'NV_MMU_PTE_KIND_Z24S8_MS4_2CZ': 0x53,
  'NV_MMU_PTE_KIND_Z24S8_MS8_2CZ': 0x54,
  'NV_MMU_PTE_KIND_Z24S8_MS16_2CZ': 0x55,
  'NV_MMU_PTE_KIND_Z24S8_4CSZV': 0x56,
  'NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV': 0x57,
  'NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV': 0x58,
  'NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV': 0x59,
  'NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV': 0x5a,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC12': 0x5b,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC4': 0x5c,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC8': 0x5d,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC24': 0x5e,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV': 0x63,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV': 0x64,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV': 0x65,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV': 0x66,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS': 0x67,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS': 0x68,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS': 0x69,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS': 0x6a,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV': 0x6f,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV': 0x70,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV': 0x71,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV': 0x72,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV': 0x73,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV': 0x74,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV': 0x75,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV': 0x76,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV': 0x77,
  'NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV': 0x78,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV': 0x79,
  'NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV': 0x7a,
  'NV_MMU_PTE_KIND_ZF32': 0x7b,
  'NV_MMU_PTE_KIND_ZF32_1Z': 0x7c,
  'NV_MMU_PTE_KIND_ZF32_MS2_1Z': 0x7d,
  'NV_MMU_PTE_KIND_ZF32_MS4_1Z': 0x7e,
  'NV_MMU_PTE_KIND_ZF32_MS8_1Z': 0x7f,
  'NV_MMU_PTE_KIND_ZF32_MS16_1Z': 0x80,
  'NV_MMU_PTE_KIND_ZF32_2CS': 0x81,
  'NV_MMU_PTE_KIND_ZF32_MS2_2CS': 0x82,
  'NV_MMU_PTE_KIND_ZF32_MS4_2CS': 0x83,
  'NV_MMU_PTE_KIND_ZF32_MS8_2CS': 0x84,
  'NV_MMU_PTE_KIND_ZF32_MS16_2CS': 0x85,
  'NV_MMU_PTE_KIND_ZF32_2CZ': 0x86,
  'NV_MMU_PTE_KIND_ZF32_MS2_2CZ': 0x87,
  'NV_MMU_PTE_KIND_ZF32_MS4_2CZ': 0x88,
  'NV_MMU_PTE_KIND_ZF32_MS8_2CZ': 0x89,
  'NV_MMU_PTE_KIND_ZF32_MS16_2CZ': 0x8a,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12': 0x8b,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4': 0x8c,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8': 0x8d,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24': 0x8e,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS': 0x8f,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS': 0x90,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS': 0x91,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS': 0x92,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV': 0x97,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV': 0x98,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV': 0x99,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV': 0x9a,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV': 0x9b,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV': 0x9c,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV': 0x9d,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV': 0x9e,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS': 0x9f,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS': 0xa0,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS': 0xa1,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS': 0xa2,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV': 0xa3,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV': 0xa4,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV': 0xa5,
  'NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV': 0xa6,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12': 0xa7,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4': 0xa8,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8': 0xa9,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24': 0xaa,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS': 0xab,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS': 0xac,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS': 0xad,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS': 0xae,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV': 0xb3,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV': 0xb4,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV': 0xb5,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV': 0xb6,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV': 0xb7,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV': 0xb8,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV': 0xb9,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV': 0xba,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS': 0xbb,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS': 0xbc,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS': 0xbd,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS': 0xbe,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV': 0xbf,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV': 0xc0,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV': 0xc1,
  'NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV': 0xc2,
  'NV_MMU_PTE_KIND_ZF32_X24S8_1CS': 0xc4,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS': 0xc5,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS': 0xc6,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS': 0xc7,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS': 0xc8,
  'NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV': 0xce,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV': 0xcf,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV': 0xd0,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV': 0xd1,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV': 0xd2,
  'NV_MMU_PTE_KIND_ZF32_X24S8_2CS': 0xd3,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS': 0xd4,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS': 0xd5,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS': 0xd6,
  'NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS': 0xd7,
  'NV_MMU_PTE_KIND_S8_2S': 0x2b,
  'NV_MMU_PTE_KIND_GENERIC_16BX2': 0xfe,
  'NV_MMU_PTE_KIND_C32_2C': 0xd8,
  'NV_MMU_PTE_KIND_C32_2CBR': 0xd9,
  'NV_MMU_PTE_KIND_C32_2CBA': 0xda,
  'NV_MMU_PTE_KIND_C32_2CRA': 0xdb,
  'NV_MMU_PTE_KIND_C32_2BRA': 0xdc,
  'NV_MMU_PTE_KIND_C32_MS2_2C': 0xdd,
  'NV_MMU_PTE_KIND_C32_MS2_2CBR': 0xde,
  'NV_MMU_PTE_KIND_C32_MS2_4CBRA': 0xcc,
  'NV_MMU_PTE_KIND_C32_MS4_2C': 0xdf,
  'NV_MMU_PTE_KIND_C32_MS4_2CBR': 0xe0,
  'NV_MMU_PTE_KIND_C32_MS4_2CBA': 0xe1,
  'NV_MMU_PTE_KIND_C32_MS4_2CRA': 0xe2,
  'NV_MMU_PTE_KIND_C32_MS4_2BRA': 0xe3,
  'NV_MMU_PTE_KIND_C32_MS4_4CBRA': 0x2c,
  'NV_MMU_PTE_KIND_C32_MS8_MS16_2C': 0xe4,
  'NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA': 0xe5,
  'NV_MMU_PTE_KIND_C64_2C': 0xe6,
  'NV_MMU_PTE_KIND_C64_2CBR': 0xe7,
  'NV_MMU_PTE_KIND_C64_2CBA': 0xe8,
  'NV_MMU_PTE_KIND_C64_2CRA': 0xe9,
  'NV_MMU_PTE_KIND_C64_2BRA': 0xea,
  'NV_MMU_PTE_KIND_C64_MS2_2C': 0xeb,
  'NV_MMU_PTE_KIND_C64_MS2_2CBR': 0xec,
  'NV_MMU_PTE_KIND_C64_MS2_4CBRA': 0xcd,
  'NV_MMU_PTE_KIND_C64_MS4_2C': 0xed,
  'NV_MMU_PTE_KIND_C64_MS4_2CBR': 0xee,
  'NV_MMU_PTE_KIND_C64_MS4_2CBA': 0xef,
  'NV_MMU_PTE_KIND_C64_MS4_2CRA': 0xf0,
  'NV_MMU_PTE_KIND_C64_MS4_2BRA': 0xf1,
  'NV_MMU_PTE_KIND_C64_MS4_4CBRA': 0x2d,
  'NV_MMU_PTE_KIND_C64_MS8_MS16_2C': 0xf2,
  'NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA': 0xf3,
  'NV_MMU_PTE_KIND_C128_2C': 0xf4,
  'NV_MMU_PTE_KIND_C128_2CR': 0xf5,
  'NV_MMU_PTE_KIND_C128_MS2_2C': 0xf6,
  'NV_MMU_PTE_KIND_C128_MS2_2CR': 0xf7,
  'NV_MMU_PTE_KIND_C128_MS4_2C': 0xf8,
  'NV_MMU_PTE_KIND_C128_MS4_2CR': 0xf9,
  'NV_MMU_PTE_KIND_C128_MS8_MS16_2C': 0xfa,
  'NV_MMU_PTE_KIND_C128_MS8_MS16_2CR': 0xfb,
  'NV_MMU_PTE_KIND_X8C24': 0xfc,
  'NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE': 0xfd,
  'NV_MMU_PTE_KIND_SMHOST_MESSAGE': 0xcb,
  'NV_MMU_VER1_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
  'NV_MMU_VER1_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER1_PDE_SIZE_FULL': 0x00000000,
  'NV_MMU_VER1_PDE_SIZE_HALF': 0x00000001,
  'NV_MMU_VER1_PDE_SIZE_QUARTER': 0x00000002,
  'NV_MMU_VER1_PDE_SIZE_EIGHTH': 0x00000003,
  'NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER1_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_VER1_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_VER1_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_VER1_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_VER1_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER1_PDE__SIZE': 8,
  'NV_MMU_VER1_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'kind': ((1*32+4), (1*32+11))}),
  'NV_MMU_VER1_PTE_VALID_TRUE': 0x1,
  'NV_MMU_VER1_PTE_VALID_FALSE': 0x0,
  'NV_MMU_VER1_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_VER1_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_VER1_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_VER1_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_VER1_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_VER1_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_VER1_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_VER1_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_VER1_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER1_PTE__SIZE': 8,
  'NV_MMU_VER1_PTE_COMPTAGS_NONE': 0x0,
  'NV_MMU_VER1_PTE_COMPTAGS_1': 0x1,
  'NV_MMU_VER1_PTE_COMPTAGS_2': 0x2,
  'NV_MMU_NEW_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
  'NV_MMU_NEW_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_NEW_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_NEW_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_NEW_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_NEW_PDE_VALID_TRUE': 0x1,
  'NV_MMU_NEW_PDE_VALID_FALSE': 0x0,
  'NV_MMU_NEW_PDE_APERTURE_INVALID': 0x00000000,
  'NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_PDE_VOL_TRUE': 0x00000001,
  'NV_MMU_NEW_PDE_VOL_FALSE': 0x00000000,
  'NV_MMU_NEW_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_NEW_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_NEW_PDE__SIZE': 8,
  'NV_MMU_NEW_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
  'NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_VALID_TRUE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_VALID_FALSE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
  'NV_MMU_NEW_DUAL_PDE__SIZE': 16,
  'NV_MMU_NEW_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
  'NV_MMU_NEW_PTE_VALID_TRUE': 0x1,
  'NV_MMU_NEW_PTE_VALID_FALSE': 0x0,
  'NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_NEW_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_NEW_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_NEW_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_NEW_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_NEW_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_NEW_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_NEW_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_NEW_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_NEW_PTE__SIZE': 8,
  'NV_MMU_VER2_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
  'NV_MMU_VER2_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_VER2_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_VER2_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_VER2_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_VER2_PDE_VALID_TRUE': 0x1,
  'NV_MMU_VER2_PDE_VALID_FALSE': 0x0,
  'NV_MMU_VER2_PDE_APERTURE_INVALID': 0x00000000,
  'NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_PDE_VOL_TRUE': 0x00000001,
  'NV_MMU_VER2_PDE_VOL_FALSE': 0x00000000,
  'NV_MMU_VER2_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_VER2_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER2_PDE__SIZE': 8,
  'NV_MMU_VER2_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
  'NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_VALID_TRUE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_VALID_FALSE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
  'NV_MMU_VER2_DUAL_PDE__SIZE': 16,
  'NV_MMU_VER2_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
  'NV_MMU_VER2_PTE_VALID_TRUE': 0x1,
  'NV_MMU_VER2_PTE_VALID_FALSE': 0x0,
  'NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_VER2_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_VER2_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_VER2_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_VER2_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_VER2_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_VER2_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_VER2_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_VER2_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER2_PTE__SIZE': 8,
  'NV_MMU_CLIENT': (None, None, {'kind': (0, 2)}),
  'NV_MMU_CLIENT_KIND_Z16': 0x1,
  'NV_MMU_CLIENT_KIND_S8': 0x2,
  'NV_MMU_CLIENT_KIND_S8Z24': 0x3,
  'NV_MMU_CLIENT_KIND_ZF32_X24S8': 0x4,
  'NV_MMU_CLIENT_KIND_Z24S8': 0x5,
  'NV_MMU_CLIENT_KIND_GENERIC_MEMORY': 0x6,
  'NV_MMU_CLIENT_KIND_INVALID': 0x7,
}
gh100 = {
  'NV_MMU_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
  'NV_MMU_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_PDE_SIZE_FULL': 0x00000000,
  'NV_MMU_PDE_SIZE_HALF': 0x00000001,
  'NV_MMU_PDE_SIZE_QUARTER': 0x00000002,
  'NV_MMU_PDE_SIZE_EIGHTH': 0x00000003,
  'NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_PDE__SIZE': 8,
  'NV_MMU_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'lock': ((1*32+3), (1*32+3)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'read_disable': ((1*32+30), (1*32+30)), 'write_disable': ((1*32+31), (1*32+31)), 'kind': ((1*32+4), (1*32+7))}),
  'NV_MMU_PTE_VALID_TRUE': 0x1,
  'NV_MMU_PTE_VALID_FALSE': 0x0,
  'NV_MMU_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_PTE_LOCK_TRUE': 0x1,
  'NV_MMU_PTE_LOCK_FALSE': 0x0,
  'NV_MMU_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_PTE_READ_DISABLE_TRUE': 0x1,
  'NV_MMU_PTE_READ_DISABLE_FALSE': 0x0,
  'NV_MMU_PTE_WRITE_DISABLE_TRUE': 0x1,
  'NV_MMU_PTE_WRITE_DISABLE_FALSE': 0x0,
  'NV_MMU_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_PTE__SIZE': 8,
  'NV_MMU_PTE_COMPTAGS_NONE': 0x0,
  'NV_MMU_PTE_COMPTAGS_1': 0x1,
  'NV_MMU_PTE_COMPTAGS_2': 0x2,
  'NV_MMU_PTE_KIND_INVALID': 0x07,
  'NV_MMU_PTE_KIND_PITCH': 0x00,
  'NV_MMU_PTE_KIND_GENERIC_MEMORY': 0x6,
  'NV_MMU_PTE_KIND_Z16': 0x1,
  'NV_MMU_PTE_KIND_S8': 0x2,
  'NV_MMU_PTE_KIND_S8Z24': 0x3,
  'NV_MMU_PTE_KIND_ZF32_X24S8': 0x4,
  'NV_MMU_PTE_KIND_Z24S8': 0x5,
  'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE': 0x8,
  'NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC': 0x9,
  'NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC': 0xA,
  'NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC': 0xB,
  'NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC': 0xC,
  'NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC': 0xD,
  'NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC': 0xE,
  'NV_MMU_PTE_KIND_SMSKED_MESSAGE': 0xF,
  'NV_MMU_VER1_PDE': (None, None, {'aperture_big': ((0*32+0), (0*32+1)), 'size': ((0*32+2), (0*32+3)), 'address_big_sys': ((0*32+4), (0*32+31)), 'address_big_vid': ((0*32+4), (0*32+31-3)), 'address_big_vid_peer': ((0*32+32-3), (0*32+31)), 'aperture_small': ((1*32+0), (1*32+1)), 'vol_small': ((1*32+2), (1*32+2)), 'vol_big': ((1*32+3), (1*32+3)), 'address_small_sys': ((1*32+4), (1*32+31)), 'address_small_vid': ((1*32+4), (1*32+31-3)), 'address_small_vid_peer': ((1*32+32-3), (1*32+31))}),
  'NV_MMU_VER1_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER1_PDE_SIZE_FULL': 0x00000000,
  'NV_MMU_VER1_PDE_SIZE_HALF': 0x00000001,
  'NV_MMU_VER1_PDE_SIZE_QUARTER': 0x00000002,
  'NV_MMU_VER1_PDE_SIZE_EIGHTH': 0x00000003,
  'NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER1_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_VER1_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_VER1_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_VER1_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_VER1_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER1_PDE__SIZE': 8,
  'NV_MMU_VER1_PTE': (None, None, {'valid': ((0*32+0), (0*32+0)), 'privilege': ((0*32+1), (0*32+1)), 'read_only': ((0*32+2), (0*32+2)), 'encrypted': ((0*32+3), (0*32+3)), 'address_sys': ((0*32+4), (0*32+31)), 'address_vid': ((0*32+4), (0*32+31-3)), 'address_vid_peer': ((0*32+32-3), (0*32+31)), 'vol': ((1*32+0), (1*32+0)), 'aperture': ((1*32+1), (1*32+2)), 'atomic_disable': ((1*32+3), (1*32+3)), 'comptagline': ((1*32+12), (1*32+20+11)), 'kind': ((1*32+4), (1*32+11))}),
  'NV_MMU_VER1_PTE_VALID_TRUE': 0x1,
  'NV_MMU_VER1_PTE_VALID_FALSE': 0x0,
  'NV_MMU_VER1_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_VER1_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_VER1_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_VER1_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_VER1_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_VER1_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_VER1_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_VER1_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_VER1_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER1_PTE__SIZE': 8,
  'NV_MMU_VER1_PTE_COMPTAGS_NONE': 0x0,
  'NV_MMU_VER1_PTE_COMPTAGS_1': 0x1,
  'NV_MMU_VER1_PTE_COMPTAGS_2': 0x2,
  'NV_MMU_NEW_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
  'NV_MMU_NEW_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_NEW_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_NEW_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_NEW_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_NEW_PDE_VALID_TRUE': 0x1,
  'NV_MMU_NEW_PDE_VALID_FALSE': 0x0,
  'NV_MMU_NEW_PDE_APERTURE_INVALID': 0x00000000,
  'NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_PDE_VOL_TRUE': 0x00000001,
  'NV_MMU_NEW_PDE_VOL_FALSE': 0x00000000,
  'NV_MMU_NEW_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_NEW_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_NEW_PDE__SIZE': 8,
  'NV_MMU_NEW_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
  'NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_VALID_TRUE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_VALID_FALSE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
  'NV_MMU_NEW_DUAL_PDE__SIZE': 16,
  'NV_MMU_NEW_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
  'NV_MMU_NEW_PTE_VALID_TRUE': 0x1,
  'NV_MMU_NEW_PTE_VALID_FALSE': 0x0,
  'NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_NEW_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_NEW_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_NEW_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_NEW_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_NEW_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_NEW_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_NEW_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_NEW_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_NEW_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_NEW_PTE__SIZE': 8,
  'NV_MMU_VER2_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'no_ats': (5, 5), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35)}),
  'NV_MMU_VER2_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_VER2_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_VER2_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_VER2_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_VER2_PDE_VALID_TRUE': 0x1,
  'NV_MMU_VER2_PDE_VALID_FALSE': 0x0,
  'NV_MMU_VER2_PDE_APERTURE_INVALID': 0x00000000,
  'NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_PDE_VOL_TRUE': 0x00000001,
  'NV_MMU_VER2_PDE_VOL_FALSE': 0x00000000,
  'NV_MMU_VER2_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_VER2_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER2_PDE__SIZE': 8,
  'NV_MMU_VER2_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'is_pde': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'vol_big': (3, 3), 'no_ats': (5, 5), 'address_big_sys': ((8-4), 53), 'address_big_vid': ((8-4), (35-3)), 'address_big_vid_peer': ((36-3), 35), 'aperture_small': (65, 66), 'vol_small': (67, 67), 'address_small_sys': (72, 117), 'address_small_vid': (72, (99-3)), 'address_small_vid_peer': ((100-3), 99)}),
  'NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_VALID_TRUE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_VALID_FALSE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE': 0x1,
  'NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE': 0x0,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE': 0x00000001,
  'NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
  'NV_MMU_VER2_DUAL_PDE__SIZE': 16,
  'NV_MMU_VER2_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'vol': (3, 3), 'encrypted': (4, 4), 'privilege': (5, 5), 'read_only': (6, 6), 'atomic_disable': (7, 7), 'address_sys': (8, 53), 'address_vid': (8, (35-3)), 'address_vid_peer': ((36-3), 35), 'comptagline': (36, (20+35)), 'kind': (56, 63)}),
  'NV_MMU_VER2_PTE_VALID_TRUE': 0x1,
  'NV_MMU_VER2_PTE_VALID_FALSE': 0x0,
  'NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER2_PTE_VOL_TRUE': 0x00000001,
  'NV_MMU_VER2_PTE_VOL_FALSE': 0x00000000,
  'NV_MMU_VER2_PTE_ENCRYPTED_TRUE': 0x00000001,
  'NV_MMU_VER2_PTE_ENCRYPTED_FALSE': 0x00000000,
  'NV_MMU_VER2_PTE_PRIVILEGE_TRUE': 0x1,
  'NV_MMU_VER2_PTE_PRIVILEGE_FALSE': 0x0,
  'NV_MMU_VER2_PTE_READ_ONLY_TRUE': 0x1,
  'NV_MMU_VER2_PTE_READ_ONLY_FALSE': 0x0,
  'NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE': 0x1,
  'NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE': 0x0,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0': 0x00000000,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1': 0x00000001,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2': 0x00000002,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3': 0x00000003,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4': 0x00000004,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5': 0x00000005,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6': 0x00000006,
  'NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7': 0x00000007,
  'NV_MMU_VER2_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER2_PTE__SIZE': 8,
  'NV_MMU_VER3_PDE': (None, None, {'is_pte': (0, 0), 'valid': (0, 0), 'aperture': (1, 2), 'pcf': (3, 5), 'address': (12, 51)}),
  'NV_MMU_VER3_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_VER3_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_VER3_PDE_VALID_TRUE': 0x1,
  'NV_MMU_VER3_PDE_VALID_FALSE': 0x0,
  'NV_MMU_VER3_PDE_APERTURE_INVALID': 0x00000000,
  'NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER3_PDE__SIZE': 8,
  'NV_MMU_VER3_DUAL_PDE': (None, None, {'is_pte': (0, 0), 'valid': (0, 0), 'aperture_big': (1, 2), 'pcf_big': (3, 5), 'address_big': (8, 51), 'aperture_small': (65, 66), 'pcf_small': (67, 69), 'address_small': (76, 115)}),
  'NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE': 0x1,
  'NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE': 0x0,
  'NV_MMU_VER3_DUAL_PDE_VALID_TRUE': 0x1,
  'NV_MMU_VER3_DUAL_PDE_VALID_FALSE': 0x0,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED': 0x00000000,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED': 0x00000001,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED': 0x00000002,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED': 0x00000003,
  'NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT': 8,
  'NV_MMU_VER3_DUAL_PDE__SIZE': 16,
  'NV_MMU_VER3_PTE': (None, None, {'valid': (0, 0), 'aperture': (1, 2), 'pcf': (3, 7), 'kind': (8, 11), 'address': (12, 51), 'address_sys': (12, 51), 'address_peer': (12, 51), 'address_vid': (12, 39), 'peer_id': ((64-3), 63)}),
  'NV_MMU_VER3_PTE_VALID_TRUE': 0x1,
  'NV_MMU_VER3_PTE_VALID_FALSE': 0x0,
  'NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY': 0x00000000,
  'NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY': 0x00000001,
  'NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY': 0x00000002,
  'NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY': 0x00000003,
  'NV_MMU_VER3_PTE_PCF_INVALID': 0x00000000,
  'NV_MMU_VER3_PTE_PCF_SPARSE': 0x00000001,
  'NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE': 0x00000002,
  'NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE': 0x00000003,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE': 0x00000000,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE': 0x00000001,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE': 0x00000002,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE': 0x00000003,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE': 0x00000004,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE': 0x00000005,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE': 0x00000006,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE': 0x00000007,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE': 0x00000008,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE': 0x00000009,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE': 0x0000000A,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE': 0x0000000B,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE': 0x0000000C,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE': 0x0000000D,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE': 0x0000000E,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE': 0x0000000F,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD': 0x00000010,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD': 0x00000011,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD': 0x00000012,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD': 0x00000013,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD': 0x00000014,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD': 0x00000015,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD': 0x00000016,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD': 0x00000017,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD': 0x00000018,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD': 0x00000019,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD': 0x0000001A,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD': 0x0000001B,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD': 0x0000001C,
  'NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD': 0x0000001D,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD': 0x0000001E,
  'NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD': 0x0000001F,
  'NV_MMU_VER3_PTE_PEER_ID_0': 0x00000000,
  'NV_MMU_VER3_PTE_PEER_ID_1': 0x00000001,
  'NV_MMU_VER3_PTE_PEER_ID_2': 0x00000002,
  'NV_MMU_VER3_PTE_PEER_ID_3': 0x00000003,
  'NV_MMU_VER3_PTE_PEER_ID_4': 0x00000004,
  'NV_MMU_VER3_PTE_PEER_ID_5': 0x00000005,
  'NV_MMU_VER3_PTE_PEER_ID_6': 0x00000006,
  'NV_MMU_VER3_PTE_PEER_ID_7': 0x00000007,
  'NV_MMU_VER3_PTE_ADDRESS_SHIFT': 0x0000000c,
  'NV_MMU_VER3_PTE__SIZE': 8,
  'NV_MMU_CLIENT': (None, None, {'kind': (0, 2)}),
  'NV_MMU_CLIENT_KIND_Z16': 0x1,
  'NV_MMU_CLIENT_KIND_S8': 0x2,
  'NV_MMU_CLIENT_KIND_S8Z24': 0x3,
  'NV_MMU_CLIENT_KIND_ZF32_X24S8': 0x4,
  'NV_MMU_CLIENT_KIND_Z24S8': 0x5,
  'NV_MMU_CLIENT_KIND_GENERIC_MEMORY': 0x6,
  'NV_MMU_CLIENT_KIND_INVALID': 0x7,
}