From 36d679196cd801aa2a5f3d2cc5cc772f85c05dc1 Mon Sep 17 00:00:00 2001 From: George Hotz Date: Wed, 1 Oct 2025 14:29:00 +0800 Subject: [PATCH] fix realize --- tinygrad/schedule/rangeify.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tinygrad/schedule/rangeify.py b/tinygrad/schedule/rangeify.py index 19a23b194c..dbb422b790 100644 --- a/tinygrad/schedule/rangeify.py +++ b/tinygrad/schedule/rangeify.py @@ -68,12 +68,14 @@ def realize_parents(ctx:dict[UOp, None], rb:UOp) -> None: def realize_assign(ctx:dict[UOp, None], a:UOp) -> None: if a.src[1].op not in ALWAYS_CONTIGUOUS: ctx[a.src[1]] = None + # if it's a kernel, we don't realize it + if a.src[1].op is not Ops.KERNEL: ctx[a] = None do_realize = PatternMatcher([ # always realize SINK parents (UPat(Ops.SINK, name="s"), lambda ctx,s: ctx.update((x.base, None) for x in s.src if x.base.op not in ALWAYS_CONTIGUOUS)), # always realize ASSIGN/COPY/BUFFER_VIEW/CONTIGUOUS - (UPat({Ops.ASSIGN, Ops.COPY, Ops.BUFFER_VIEW, Ops.CONTIGUOUS}, name="tr"), realize), + (UPat({Ops.COPY, Ops.BUFFER_VIEW, Ops.CONTIGUOUS}, name="tr"), realize), # realize parents of COPY, MSELECT, MSTACK (UPat((Ops.COPY, Ops.MSELECT, Ops.MSTACK), name="rb"), realize_parents), # realize input to assign (might be optimized out)