From 614783693e97f57166e9e97d447ea6a6388d1519 Mon Sep 17 00:00:00 2001 From: nimlgen <138685161+nimlgen@users.noreply.github.com> Date: Sun, 9 Nov 2025 21:43:19 +0800 Subject: [PATCH] nv: remove hardcoded expansion_rom_off (#13180) * nv: remove hardcoded expansion_rom_off * to max size --- autogen_stubs.sh | 2 +- extra/nv_gpu_driver/pci_exp_table.h | 134 ++++++++++++++++++++++++++ tinygrad/runtime/autogen/nv/nv.py | 142 +++++++++++++++++++++++++++- tinygrad/runtime/support/nv/ip.py | 14 ++- 4 files changed, 285 insertions(+), 7 deletions(-) create mode 100644 extra/nv_gpu_driver/pci_exp_table.h diff --git a/autogen_stubs.sh b/autogen_stubs.sh index 4dde2064d5..0235ad7a5c 100755 --- a/autogen_stubs.sh +++ b/autogen_stubs.sh @@ -188,6 +188,7 @@ nv_status_codes = {} extra/nv_gpu_driver/g_rpc-message-header.h \ extra/nv_gpu_driver/gsp_static_config.h \ extra/nv_gpu_driver/vbios.h \ + extra/nv_gpu_driver/pci_exp_table.h \ --clang-args="-DRPC_MESSAGE_STRUCTURES -DRPC_STRUCTURES -include $NVKERN_SRC/src/common/sdk/nvidia/inc/nvtypes.h -I$NVKERN_SRC/src/nvidia/generated -I$NVKERN_SRC/src/common/inc -I$NVKERN_SRC/src/nvidia/inc -I$NVKERN_SRC/src/nvidia/interface/ -I$NVKERN_SRC/src/nvidia/inc/kernel -I$NVKERN_SRC/src/nvidia/inc/libraries -I$NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc -I$NVKERN_SRC/kernel-open/nvidia-uvm -I$NVKERN_SRC/kernel-open/common/inc -I$NVKERN_SRC/src/common/sdk/nvidia/inc -I$NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include -I$NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl" \ -o $BASE/nv/nv.py @@ -549,7 +550,6 @@ elif [ "$1" == "kfd" ]; then generate_kfd elif [ "$1" == "nv" ]; then generate_nv elif [ "$1" == "amd" ]; then generate_amd elif [ "$1" == "am" ]; then generate_am -elif [ "$1" == "nvdrv" ]; then generate_nvdrv elif [ "$1" == "sqtt" ]; then generate_sqtt elif [ "$1" == "qcom" ]; then generate_qcom elif [ "$1" == "io_uring" ]; then generate_io_uring diff --git a/extra/nv_gpu_driver/pci_exp_table.h b/extra/nv_gpu_driver/pci_exp_table.h new file mode 100644 index 0000000000..e83101341e --- /dev/null +++ b/extra/nv_gpu_driver/pci_exp_table.h @@ -0,0 +1,134 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef PCIEXPTBL_H +#define PCIEXPTBL_H + +#define NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE 0x00 +#define NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT 0xE0 + +// +// The VBIOS object comes from walking the PCI expansion code block +// The following structure holds the expansion code format. +// +#define PCI_EXP_ROM_SIGNATURE 0xaa55 +#define PCI_EXP_ROM_SIGNATURE_NV 0x4e56 // "VN" in word format +#define PCI_EXP_ROM_SIGNATURE_NV2 0xbb77 +#define IS_VALID_PCI_ROM_SIG(sig) ((sig == PCI_EXP_ROM_SIGNATURE) || \ + (sig == PCI_EXP_ROM_SIGNATURE_NV) || \ + (sig == PCI_EXP_ROM_SIGNATURE_NV2)) + +#define OFFSETOF_PCI_EXP_ROM_SIG 0x0 +#define OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET 0x16 +#define OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR 0x18 + +#pragma pack(1) +typedef struct _PCI_EXP_ROM_STANDARD +{ + NvU16 sig; // 00h: ROM Signature 0xaa55 + NvU8 reserved [0x16]; // 02h: Reserved (processor architecture unique data) + NvU16 pciDataStrucPtr; // 18h: Pointer to PCI Data Structure + NvU32 sizeOfBlock; // 1Ah: +} PCI_EXP_ROM_STANDARD, *PPCI_EXP_ROM_STANDARD; +#pragma pack() + +#pragma pack(1) +typedef struct _PCI_EXP_ROM_NBSI +{ + NvU16 sig; // 00h: ROM Signature 0xaa55 + NvU8 reserved [0x14]; // 02h: Reserved (processor architecture unique data) + NvU16 nbsiDataOffset; // 16h: Offset from header to NBSI image + NvU16 pciDataStrucPtr; // 18h: Pointer to PCI Data Structure + NvU32 sizeOfBlock; // 1Ah: +} PCI_EXP_ROM_NBSI, *PPCI_EXP_ROM_NBSI; +#pragma pack() + +typedef union _PCI_EXP_ROM { + PCI_EXP_ROM_STANDARD standard; + PCI_EXP_ROM_NBSI nbsi; +} PCI_EXP_ROM, *PPCI_EXP_ROM; + +#define PCI_DATA_STRUCT_SIGNATURE 0x52494350 // "PCIR" in dword format +#define PCI_DATA_STRUCT_SIGNATURE_NV 0x5344504E // "NPDS" in dword format +#define PCI_DATA_STRUCT_SIGNATURE_NV2 0x53494752 // "RGIS" in dword format +#define IS_VALID_PCI_DATA_SIG(sig) ((sig == PCI_DATA_STRUCT_SIGNATURE) || \ + (sig == PCI_DATA_STRUCT_SIGNATURE_NV) || \ + (sig == PCI_DATA_STRUCT_SIGNATURE_NV2)) + +#define PCI_LAST_IMAGE NVBIT(7) +#define PCI_ROM_IMAGE_BLOCK_SIZE 512U + +#define OFFSETOF_PCI_DATA_STRUCT_SIG 0x0 +#define OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID 0x4 +#define OFFSETOF_PCI_DATA_STRUCT_LEN 0xa +#define OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE 0xd +#define OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE 0x14 +#define OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN 0x10 +#define OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE 0x15 + +#pragma pack(1) +typedef struct _PCI_DATA_STRUCT +{ + NvU32 sig; // 00h: Signature, the string "PCIR" or NVIDIA's alternate "NPDS" + NvU16 vendorID; // 04h: Vendor Identification + NvU16 deviceID; // 06h: Device Identification + NvU16 deviceListPtr; // 08h: Device List Pointer + NvU16 pciDataStructLen; // 0Ah: PCI Data Structure Length + NvU8 pciDataStructRev; // 0Ch: PCI Data Structure Revision + NvU8 classCode[3]; // 0Dh: Class Code + NvU16 imageLen; // 10h: Image Length (units of 512 bytes) + NvU16 vendorRomRev; // 12h: Revision Level of the Vendor's ROM + NvU8 codeType; // 14h: holds NBSI_OBJ_CODE_TYPE (0x70) and others + NvU8 lastImage; // 15h: Last Image Indicator: bit7=1 is lastImage + NvU16 maxRunTimeImageLen; // 16h: Maximum Run-time Image Length (units of 512 bytes) +} PCI_DATA_STRUCT, *PPCI_DATA_STRUCT; +#pragma pack() + +#define NV_PCI_DATA_EXT_SIG 0x4544504E // "NPDE" in dword format +#define NV_PCI_DATA_EXT_REV_10 0x100 // 1.0 +#define NV_PCI_DATA_EXT_REV_11 0x101 // 1.1 + +#define OFFSETOF_PCI_DATA_EXT_STRUCT_SIG 0x0 +#define OFFSETOF_PCI_DATA_EXT_STRUCT_LEN 0x6 +#define OFFSETOF_PCI_DATA_EXT_STRUCT_REV 0x4 +#define OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN 0x8 +#define OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE 0xa +#define OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS 0xb + +#define PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED 0x04 + +#pragma pack(1) +typedef struct _NV_PCI_DATA_EXT_STRUCT +{ + NvU32 signature; // 00h: Signature, the string "NPDE" + NvU16 nvPciDataExtRev; // 04h: NVIDIA PCI Data Extension Revision + NvU16 nvPciDataExtLen; // 06h: NVIDIA PCI Data Extension Length + NvU16 subimageLen; // 08h: Sub-image Length + NvU8 privLastImage; // 0Ah: Private Last Image Indicator + NvU8 flags; // 0Bh: Private images enabled if bit0=1 +} NV_PCI_DATA_EXT_STRUCT, *PNV_PCI_DATA_EXT_STRUCT; +#pragma pack() + +#endif // PCIEXPTBL_H + + diff --git a/tinygrad/runtime/autogen/nv/nv.py b/tinygrad/runtime/autogen/nv/nv.py index ad389a3fb6..0516ebd5ba 100644 --- a/tinygrad/runtime/autogen/nv/nv.py +++ b/tinygrad/runtime/autogen/nv/nv.py @@ -7357,6 +7357,113 @@ class struct_c__SA_FWSECLIC_FRTS_CMD(Structure): ] FWSECLIC_FRTS_CMD = struct_c__SA_FWSECLIC_FRTS_CMD +PCIEXPTBL_H = True # macro +NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE = 0x00 # macro +NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT = 0xE0 # macro +PCI_EXP_ROM_SIGNATURE = 0xaa55 # macro +PCI_EXP_ROM_SIGNATURE_NV = 0x4e56 # macro +PCI_EXP_ROM_SIGNATURE_NV2 = 0xbb77 # macro +def IS_VALID_PCI_ROM_SIG(sig): # macro + return ((sig==0xaa55) or (sig==0x4e56) or (sig==0xbb77)) +OFFSETOF_PCI_EXP_ROM_SIG = 0x0 # macro +OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET = 0x16 # macro +OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR = 0x18 # macro +PCI_DATA_STRUCT_SIGNATURE = 0x52494350 # macro +PCI_DATA_STRUCT_SIGNATURE_NV = 0x5344504E # macro +PCI_DATA_STRUCT_SIGNATURE_NV2 = 0x53494752 # macro +def IS_VALID_PCI_DATA_SIG(sig): # macro + return ((sig==0x52494350) or (sig==0x5344504E) or (sig==0x53494752)) +# PCI_LAST_IMAGE = NVBIT ( 7 ) # macro +PCI_ROM_IMAGE_BLOCK_SIZE = 512 # macro +OFFSETOF_PCI_DATA_STRUCT_SIG = 0x0 # macro +OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID = 0x4 # macro +OFFSETOF_PCI_DATA_STRUCT_LEN = 0xa # macro +OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE = 0xd # macro +OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE = 0x14 # macro +OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN = 0x10 # macro +OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE = 0x15 # macro +NV_PCI_DATA_EXT_SIG = 0x4544504E # macro +NV_PCI_DATA_EXT_REV_10 = 0x100 # macro +NV_PCI_DATA_EXT_REV_11 = 0x101 # macro +OFFSETOF_PCI_DATA_EXT_STRUCT_SIG = 0x0 # macro +OFFSETOF_PCI_DATA_EXT_STRUCT_LEN = 0x6 # macro +OFFSETOF_PCI_DATA_EXT_STRUCT_REV = 0x4 # macro +OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN = 0x8 # macro +OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE = 0xa # macro +OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS = 0xb # macro +PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED = 0x04 # macro +class struct__PCI_EXP_ROM_STANDARD(Structure): + pass + +struct__PCI_EXP_ROM_STANDARD._pack_ = 1 # source:False +struct__PCI_EXP_ROM_STANDARD._fields_ = [ + ('sig', ctypes.c_uint16), + ('reserved', ctypes.c_ubyte * 22), + ('pciDataStrucPtr', ctypes.c_uint16), + ('sizeOfBlock', ctypes.c_uint32), +] + +PCI_EXP_ROM_STANDARD = struct__PCI_EXP_ROM_STANDARD +PPCI_EXP_ROM_STANDARD = ctypes.POINTER(struct__PCI_EXP_ROM_STANDARD) +class struct__PCI_EXP_ROM_NBSI(Structure): + pass + +struct__PCI_EXP_ROM_NBSI._pack_ = 1 # source:False +struct__PCI_EXP_ROM_NBSI._fields_ = [ + ('sig', ctypes.c_uint16), + ('reserved', ctypes.c_ubyte * 20), + ('nbsiDataOffset', ctypes.c_uint16), + ('pciDataStrucPtr', ctypes.c_uint16), + ('sizeOfBlock', ctypes.c_uint32), +] + +PCI_EXP_ROM_NBSI = struct__PCI_EXP_ROM_NBSI +PPCI_EXP_ROM_NBSI = ctypes.POINTER(struct__PCI_EXP_ROM_NBSI) +class union__PCI_EXP_ROM(Union): + _pack_ = 1 # source:False + _fields_ = [ + ('standard', PCI_EXP_ROM_STANDARD), + ('nbsi', PCI_EXP_ROM_NBSI), + ] + +PCI_EXP_ROM = union__PCI_EXP_ROM +PPCI_EXP_ROM = ctypes.POINTER(union__PCI_EXP_ROM) +class struct__PCI_DATA_STRUCT(Structure): + pass + +struct__PCI_DATA_STRUCT._pack_ = 1 # source:False +struct__PCI_DATA_STRUCT._fields_ = [ + ('sig', ctypes.c_uint32), + ('vendorID', ctypes.c_uint16), + ('deviceID', ctypes.c_uint16), + ('deviceListPtr', ctypes.c_uint16), + ('pciDataStructLen', ctypes.c_uint16), + ('pciDataStructRev', ctypes.c_ubyte), + ('classCode', ctypes.c_ubyte * 3), + ('imageLen', ctypes.c_uint16), + ('vendorRomRev', ctypes.c_uint16), + ('codeType', ctypes.c_ubyte), + ('lastImage', ctypes.c_ubyte), + ('maxRunTimeImageLen', ctypes.c_uint16), +] + +PCI_DATA_STRUCT = struct__PCI_DATA_STRUCT +PPCI_DATA_STRUCT = ctypes.POINTER(struct__PCI_DATA_STRUCT) +class struct__NV_PCI_DATA_EXT_STRUCT(Structure): + pass + +struct__NV_PCI_DATA_EXT_STRUCT._pack_ = 1 # source:False +struct__NV_PCI_DATA_EXT_STRUCT._fields_ = [ + ('signature', ctypes.c_uint32), + ('nvPciDataExtRev', ctypes.c_uint16), + ('nvPciDataExtLen', ctypes.c_uint16), + ('subimageLen', ctypes.c_uint16), + ('privLastImage', ctypes.c_ubyte), + ('flags', ctypes.c_ubyte), +] + +NV_PCI_DATA_EXT_STRUCT = struct__NV_PCI_DATA_EXT_STRUCT +PNV_PCI_DATA_EXT_STRUCT = ctypes.POINTER(struct__NV_PCI_DATA_EXT_STRUCT) __all__ = \ ['ACPI_DATA', 'ACPI_DSM_CACHE', 'ACPI_DSM_FUNCTION_COUNT', 'ACPI_DSM_FUNCTION_CURRENT', 'ACPI_DSM_FUNCTION_GPS', @@ -7480,12 +7587,16 @@ __all__ = \ 'NVDM_TYPE_UEFI_XTL_DEBUG_INTR', 'NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX', 'NVGPU_ENGINE_CAPS_MASK_BITS', 'NV_ACPI_GENERIC_FUNC_COUNT', + 'NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE', + 'NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_AVAILABLE', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_UNAVAILABLE', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V1', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V2', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V3', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_VERSION_V4', + 'NV_PCI_DATA_EXT_REV_10', 'NV_PCI_DATA_EXT_REV_11', + 'NV_PCI_DATA_EXT_SIG', 'NV_PCI_DATA_EXT_STRUCT', 'NV_RPC_UPDATE_PDE_BAR_1', 'NV_RPC_UPDATE_PDE_BAR_2', 'NV_RPC_UPDATE_PDE_BAR_INVALID', 'NV_RPC_UPDATE_PDE_BAR_TYPE', 'NV_RPC_UPDATE_PDE_BAR_TYPE__enumvalues', @@ -7775,8 +7886,31 @@ __all__ = \ 'NV_VGPU_PTE_64_INDEX_SHIFT', 'NV_VGPU_PTE_64_PAGE_SIZE', 'NV_VGPU_PTE_64_SIZE', 'NV_VGPU_PTE_INDEX_MASK', 'NV_VGPU_PTE_INDEX_SHIFT', 'NV_VGPU_PTE_PAGE_SIZE', - 'NV_VGPU_PTE_SIZE', 'PACKED_REGISTRY_ENTRY', - 'PACKED_REGISTRY_TABLE', 'REGISTRY_TABLE_ENTRY_TYPE_BINARY', + 'NV_VGPU_PTE_SIZE', 'OFFSETOF_PCI_DATA_EXT_STRUCT_FLAGS', + 'OFFSETOF_PCI_DATA_EXT_STRUCT_LAST_IMAGE', + 'OFFSETOF_PCI_DATA_EXT_STRUCT_LEN', + 'OFFSETOF_PCI_DATA_EXT_STRUCT_REV', + 'OFFSETOF_PCI_DATA_EXT_STRUCT_SIG', + 'OFFSETOF_PCI_DATA_EXT_STRUCT_SUBIMAGE_LEN', + 'OFFSETOF_PCI_DATA_STRUCT_CLASS_CODE', + 'OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE', + 'OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN', + 'OFFSETOF_PCI_DATA_STRUCT_LAST_IMAGE', + 'OFFSETOF_PCI_DATA_STRUCT_LEN', 'OFFSETOF_PCI_DATA_STRUCT_SIG', + 'OFFSETOF_PCI_DATA_STRUCT_VENDOR_ID', + 'OFFSETOF_PCI_EXP_ROM_NBSI_DATA_OFFSET', + 'OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR', + 'OFFSETOF_PCI_EXP_ROM_SIG', 'PACKED_REGISTRY_ENTRY', + 'PACKED_REGISTRY_TABLE', 'PCIEXPTBL_H', + 'PCI_DATA_EXT_STRUCT_FLAGS_CHECKSUM_DISABLED', 'PCI_DATA_STRUCT', + 'PCI_DATA_STRUCT_SIGNATURE', 'PCI_DATA_STRUCT_SIGNATURE_NV', + 'PCI_DATA_STRUCT_SIGNATURE_NV2', 'PCI_EXP_ROM', + 'PCI_EXP_ROM_NBSI', 'PCI_EXP_ROM_SIGNATURE', + 'PCI_EXP_ROM_SIGNATURE_NV', 'PCI_EXP_ROM_SIGNATURE_NV2', + 'PCI_EXP_ROM_STANDARD', 'PCI_ROM_IMAGE_BLOCK_SIZE', + 'PNV_PCI_DATA_EXT_STRUCT', 'PPCI_DATA_STRUCT', 'PPCI_EXP_ROM', + 'PPCI_EXP_ROM_NBSI', 'PPCI_EXP_ROM_STANDARD', + 'REGISTRY_TABLE_ENTRY_TYPE_BINARY', 'REGISTRY_TABLE_ENTRY_TYPE_DWORD', 'REGISTRY_TABLE_ENTRY_TYPE_STRING', 'REGISTRY_TABLE_ENTRY_TYPE_UNKNOWN', 'RM_ENGINE_TYPE', @@ -8343,6 +8477,8 @@ __all__ = \ 'struct_UpdateBarPde_v15_00', 'struct_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS', 'struct_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS', + 'struct__NV_PCI_DATA_EXT_STRUCT', 'struct__PCI_DATA_STRUCT', + 'struct__PCI_EXP_ROM_NBSI', 'struct__PCI_EXP_ROM_STANDARD', 'struct_alloc_object_FERMI_CONTEXT_SHARE_A_v04_00', 'struct_alloc_object_FERMI_VASPACE_A_v03_00', 'struct_alloc_object_GF100_DISP_SW_v03_00', @@ -8595,7 +8731,7 @@ __all__ = \ 'union_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v26_04', 'union_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D', 'union_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04', - 'union_alloc_object_params_v25_08', + 'union__PCI_EXP_ROM', 'union_alloc_object_params_v25_08', 'union_alloc_object_params_v26_00', 'union_alloc_object_params_v27_00', 'union_alloc_object_params_v29_06', 'union_c__SA_GspFwWprMeta_0', diff --git a/tinygrad/runtime/support/nv/ip.py b/tinygrad/runtime/support/nv/ip.py index bf2b972923..dce413602d 100644 --- a/tinygrad/runtime/support/nv/ip.py +++ b/tinygrad/runtime/support/nv/ip.py @@ -89,10 +89,18 @@ class NV_FLCN(NV_IP): self.prep_booter() def prep_ucode(self): - expansion_rom_off, bit_addr = {"GA": 0x16600, "AD": 0x14e00}[self.nvdev.chip_name[:2]], 0x1b0 - vbios_bytes = bytes(array.array('I', self.nvdev.mmio[0x00300000//4:(0x00300000+0x98e00)//4])) + vbios_bytes, vbios_off = memoryview(bytes(array.array('I', self.nvdev.mmio[0x00300000//4:(0x00300000+0x100000)//4]))), 0 + while True: + pci_blck = vbios_bytes[vbios_off + nv.OFFSETOF_PCI_EXP_ROM_PCI_DATA_STRUCT_PTR:].cast('H')[0] + imglen = vbios_bytes[vbios_off + pci_blck + nv.OFFSETOF_PCI_DATA_STRUCT_IMAGE_LEN:].cast('H')[0] * nv.PCI_ROM_IMAGE_BLOCK_SIZE + match vbios_bytes[vbios_off + pci_blck + nv.OFFSETOF_PCI_DATA_STRUCT_CODE_TYPE]: + case nv.NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_BASE: block_size = imglen + case nv.NV_BCRT_HASH_INFO_BASE_CODE_TYPE_VBIOS_EXT: + expansion_rom_off = vbios_off - block_size + break + vbios_off += imglen - bit_header = nv.BIT_HEADER_V1_00.from_buffer_copy(vbios_bytes[bit_addr:bit_addr + ctypes.sizeof(nv.BIT_HEADER_V1_00)]) + bit_header = nv.BIT_HEADER_V1_00.from_buffer_copy(vbios_bytes[(bit_addr:=0x1b0):bit_addr + ctypes.sizeof(nv.BIT_HEADER_V1_00)]) assert bit_header.Signature == 0x00544942, f"Invalid BIT header signature {hex(bit_header.Signature)}" for i in range(bit_header.TokenEntries):