From b596f77e330c3b3d89d675589b9eaab10a237a1f Mon Sep 17 00:00:00 2001 From: George Hotz Date: Wed, 31 Dec 2025 16:59:02 -0500 Subject: [PATCH] assembly/amd: add pcode ds ops --- extra/assembly/amd/autogen/cdna/gen_pcode.py | 1741 ++++++++++++++++- extra/assembly/amd/autogen/rdna3/gen_pcode.py | 1334 ++++++++++++- extra/assembly/amd/autogen/rdna4/gen_pcode.py | 1383 ++++++++++++- extra/assembly/amd/emu.py | 58 +- extra/assembly/amd/pcode.py | 49 +- extra/assembly/amd/pdf.py | 34 +- extra/assembly/amd/test/test_emu.py | 214 ++ 7 files changed, 4750 insertions(+), 63 deletions(-) diff --git a/extra/assembly/amd/autogen/cdna/gen_pcode.py b/extra/assembly/amd/autogen/cdna/gen_pcode.py index d6d79c1a84..5eac144f6c 100644 --- a/extra/assembly/amd/autogen/cdna/gen_pcode.py +++ b/extra/assembly/amd/autogen/cdna/gen_pcode.py @@ -2,7 +2,7 @@ # to regenerate: python -m extra.assembly.amd.pdf --arch cdna # ruff: noqa: E501,F405,F403 # mypy: ignore-errors -from extra.assembly.amd.autogen.cdna.enum import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3POp, VOPCOp, VOP3AOp, VOP3BOp +from extra.assembly.amd.autogen.cdna.enum import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3POp, VOPCOp, VOP3AOp, VOP3BOp, DSOp from extra.assembly.amd.pcode import * def _SOP1Op_S_MOV_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None): @@ -3077,12 +3077,6 @@ def _VOPCOp_V_CMPX_GE_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, def _VOPCOp_V_CMPX_T_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None): EXEC.u64[laneId] = D0.u64[laneId] = 1 - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) return {'D0': D0, 'EXEC': EXEC} VOPCOp_FUNCTIONS = { @@ -4148,12 +4142,6 @@ def _VOP3AOp_V_CMPX_GE_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR def _VOP3AOp_V_CMPX_T_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None): EXEC.u64[laneId] = D0.u64[laneId] = 1 - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) - addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) - tmp = Reg(MEM[addr].u32) return {'D0': D0} def _VOP3AOp_V_MOV_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None): @@ -6270,6 +6258,1732 @@ VOP3BOp_FUNCTIONS = { VOP3BOp.V_MAD_I64_I32: _VOP3BOp_V_MAD_I64_I32, } +def _DSOp_DS_ADD_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 += DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 -= DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 = DATA.u32 - MEM[addr].u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp & DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp | DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp ^ DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRITE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + return {} + +def _DSOp_DS_WRITE2_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET0.u32 * 4].b32 = DATA[31 : 0] + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET1.u32 * 4].b32 = DATA2[31 : 0] + return {} + +def _DSOp_DS_WRITE2ST64_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET0.u32 * 256].b32 = DATA[31 : 0] + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET1.u32 * 256].b32 = DATA2[31 : 0] + return {} + +def _DSOp_DS_CMPST_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + src = DATA2.b32 + cmp = DATA.b32 + MEM[addr].b32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPST_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + src = DATA2.f32 + cmp = DATA.f32 + MEM[addr].f32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + src = DATA.f32 + MEM[addr].f32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + src = DATA.f32 + MEM[addr].f32 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + MEM[addr].f32 += DATA.f32 + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PK_ADD_F16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR]) + src = DATA + dst[31 : 16].f16 = tmp[31 : 16].f16 + src[31 : 16].f16 + dst[15 : 0].f16 = tmp[15 : 0].f16 + src[15 : 0].f16 + MEM[ADDR] = dst.b32 + RETURN_DATA = tmp + return {} + +def _DSOp_DS_PK_ADD_BF16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR]) + src = DATA + dst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16 + dst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16 + MEM[ADDR] = dst.b32 + RETURN_DATA = tmp + return {} + +def _DSOp_DS_WRITE_ADDTID_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[(_pack(OFFSET1, OFFSET0) + M0[15 : 0]) + laneID.i32 * 4].u32 = DATA0.u32 + return {} + +def _DSOp_DS_WRITE_B8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b8 = DATA[7 : 0] + return {} + +def _DSOp_DS_WRITE_B16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b16 = DATA[15 : 0] + return {} + +def _DSOp_DS_ADD_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 += DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 -= DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 = DATA.u32 - MEM[addr].u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp & DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp | DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp ^ DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRXCHG_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = DATA.b32 + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRXCHG2_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b32 + tmp2 = MEM[addr2].b32 + MEM[addr1].b32 = DATA.b32 + MEM[addr2].b32 = DATA2.b32 + RETURN_DATA[31 : 0] = tmp1 + RETURN_DATA[63 : 32] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRXCHG2ST64_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b32 + tmp2 = MEM[addr2].b32 + MEM[addr1].b32 = DATA.b32 + MEM[addr2].b32 = DATA2.b32 + RETURN_DATA[31 : 0] = tmp1 + RETURN_DATA[63 : 32] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPST_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b32) + src = DATA2.b32 + cmp = DATA.b32 + MEM[addr].b32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPST_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + src = DATA2.f32 + cmp = DATA.f32 + MEM[addr].f32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + src = DATA.f32 + MEM[addr].f32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + src = DATA.f32 + MEM[addr].f32 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRAP_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 = ((tmp - DATA.u32) if (tmp >= DATA.u32) else (tmp + DATA2.u32)) + RETURN_DATA = tmp + return {} + +def _DSOp_DS_ADD_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f32) + MEM[addr].f32 += DATA.f32 + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ2_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 4].b32 + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ2ST64_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 256].b32 + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 256].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_I8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.i32 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_U8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_I16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.i32 = (signext(MEM[ADDR].i16)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_U16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = (_pack(0, MEM[ADDR].u16)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PERMUTE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + VDST = Reg(vdst_idx) + ADDR = S0._val + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + for i in range(0, int(63)+1): + tmp[i] = 0x0 + for i in range(0, int(63)+1): + if EXEC[i].u1: + dst_lane = (VGPR[i][ADDR].u32 + OFFSET.u32) / 4 % 64 + tmp[dst_lane] = VGPR[i][DATA0] + for i in range(0, int(63)+1): + if EXEC[i].u1: + VGPR[i][VDST] = tmp[i] + return {} + +def _DSOp_DS_BPERMUTE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + VDST = Reg(vdst_idx) + ADDR = S0._val + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + for i in range(0, int(63)+1): + tmp[i] = 0x0 + for i in range(0, int(63)+1): + src_lane = (VGPR[i][ADDR].u32 + OFFSET.u32) / 4 % 64 + if EXEC[src_lane].u1: + tmp[i] = VGPR[src_lane][DATA0] + for i in range(0, int(63)+1): + if EXEC[i].u1: + VGPR[i][VDST] = tmp[i] + return {} + +def _DSOp_DS_ADD_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 += DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 -= DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 = DATA.u64 - MEM[addr].u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp & DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp | DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp ^ DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRITE_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + MEM[addr + OFFSET.u32 + 4].b32 = DATA[63 : 32] + return {} + +def _DSOp_DS_WRITE2_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET0.u32 * 8].b32 = DATA[31 : 0] + MEM[addr + OFFSET0.u32 * 8 + 4].b32 = DATA[63 : 32] + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET1.u32 * 8].b32 = DATA2[31 : 0] + MEM[addr + OFFSET1.u32 * 8 + 4].b32 = DATA2[63 : 32] + return {} + +def _DSOp_DS_WRITE2ST64_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET0.u32 * 512].b32 = DATA[31 : 0] + MEM[addr + OFFSET0.u32 * 512 + 4].b32 = DATA[63 : 32] + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET1.u32 * 512].b32 = DATA2[31 : 0] + MEM[addr + OFFSET1.u32 * 512 + 4].b32 = DATA2[63 : 32] + return {} + +def _DSOp_DS_CMPST_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + src = DATA2.b64 + cmp = DATA.b64 + MEM[addr].b64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPST_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f64) + src = DATA2.f64 + cmp = DATA.f64 + MEM[addr].f64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f64) + src = DATA.f64 + MEM[addr].f64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f64) + src = DATA.f64 + MEM[addr].f64 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRITE_B8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b8 = DATA[23 : 16] + return {} + +def _DSOp_DS_WRITE_B16_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b16 = DATA[31 : 16] + return {} + +def _DSOp_DS_READ_U8_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].u16 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_U8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].u16 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_I8_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].i16 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_I8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].i16 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_U16_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].u16 = MEM[ADDR].u16 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_U16_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].u16 = MEM[ADDR].u16 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + MEM[ADDR].f64 += DATA.f64 + RETURN_DATA = tmp + return {} + +def _DSOp_DS_ADD_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 += DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 -= DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 = DATA.u64 - MEM[addr].u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp & DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp | DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp ^ DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRXCHG_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = DATA.b64 + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRXCHG2_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b64 + tmp2 = MEM[addr2].b64 + MEM[addr1].b64 = DATA.b64 + MEM[addr2].b64 = DATA2.b64 + RETURN_DATA[63 : 0] = tmp1 + RETURN_DATA[127 : 64] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRXCHG2ST64_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b64 + tmp2 = MEM[addr2].b64 + MEM[addr1].b64 = DATA.b64 + MEM[addr2].b64 = DATA2.b64 + RETURN_DATA[63 : 0] = tmp1 + RETURN_DATA[127 : 64] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPST_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].b64) + src = DATA2.b64 + cmp = DATA.b64 + MEM[addr].b64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPST_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f64) + src = DATA2.f64 + cmp = DATA.f64 + MEM[addr].f64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f64) + src = DATA.f64 + MEM[addr].f64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32) + tmp = Reg(MEM[addr].f64) + src = DATA.f64 + MEM[addr].f64 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ2_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 8].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 8 + 4].b32 + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 8].b32 + RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 8 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ2ST64_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 512].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 512 + 4].b32 + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 512].b32 + RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 512 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + MEM[ADDR].f64 += DATA.f64 + RETURN_DATA = tmp + return {} + +def _DSOp_DS_CONDXCHG32_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + ADDR = S0.u32 + DATA = S1.u64 + offset = _pack(OFFSET1, OFFSET0) + RETURN_DATA[0] = LDS[ADDR0].u32 + if DATA[31]: + LDS[ADDR0] = _pack(0, DATA[30 : 0]) + RETURN_DATA[1] = LDS[ADDR1].u32 + if DATA[63]: + LDS[ADDR1] = _pack(0, DATA[62 : 32]) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_ADDTID_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = MEM[(_pack(OFFSET1, OFFSET0) + M0[15 : 0]) + laneID.i32 * 4].u32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PK_ADD_RTN_F16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR]) + src = DATA + dst[31 : 16].f16 = tmp[31 : 16].f16 + src[31 : 16].f16 + dst[15 : 0].f16 = tmp[15 : 0].f16 + src[15 : 0].f16 + MEM[ADDR] = dst.b32 + RETURN_DATA = tmp + return {} + +def _DSOp_DS_PK_ADD_RTN_BF16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR]) + src = DATA + dst[31 : 16].bf16 = tmp[31 : 16].bf16 + src[31 : 16].bf16 + dst[15 : 0].bf16 = tmp[15 : 0].bf16 + src[15 : 0].bf16 + MEM[ADDR] = dst.b32 + RETURN_DATA = tmp + return {} + +def _DSOp_DS_WRITE_B96(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + MEM[addr + OFFSET.u32 + 4].b32 = DATA[63 : 32] + MEM[addr + OFFSET.u32 + 8].b32 = DATA[95 : 64] + return {} + +def _DSOp_DS_WRITE_B128(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + MEM[addr + OFFSET.u32 + 4].b32 = DATA[63 : 32] + MEM[addr + OFFSET.u32 + 8].b32 = DATA[95 : 64] + MEM[addr + OFFSET.u32 + 12].b32 = DATA[127 : 96] + return {} + +def _DSOp_DS_READ_B96(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4].b32 + RETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_READ_B128(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(ADDR.b32, 0x0, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4].b32 + RETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8].b32 + RETURN_DATA[127 : 96] = MEM[addr + OFFSET.u32 + 12].b32 + addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32) + VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]) + addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32) + VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]) + VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]) + return {'RETURN_DATA': RETURN_DATA} + +DSOp_FUNCTIONS = { + DSOp.DS_ADD_U32: _DSOp_DS_ADD_U32, + DSOp.DS_SUB_U32: _DSOp_DS_SUB_U32, + DSOp.DS_RSUB_U32: _DSOp_DS_RSUB_U32, + DSOp.DS_INC_U32: _DSOp_DS_INC_U32, + DSOp.DS_DEC_U32: _DSOp_DS_DEC_U32, + DSOp.DS_MIN_I32: _DSOp_DS_MIN_I32, + DSOp.DS_MAX_I32: _DSOp_DS_MAX_I32, + DSOp.DS_MIN_U32: _DSOp_DS_MIN_U32, + DSOp.DS_MAX_U32: _DSOp_DS_MAX_U32, + DSOp.DS_AND_B32: _DSOp_DS_AND_B32, + DSOp.DS_OR_B32: _DSOp_DS_OR_B32, + DSOp.DS_XOR_B32: _DSOp_DS_XOR_B32, + DSOp.DS_MSKOR_B32: _DSOp_DS_MSKOR_B32, + DSOp.DS_WRITE_B32: _DSOp_DS_WRITE_B32, + DSOp.DS_WRITE2_B32: _DSOp_DS_WRITE2_B32, + DSOp.DS_WRITE2ST64_B32: _DSOp_DS_WRITE2ST64_B32, + DSOp.DS_CMPST_B32: _DSOp_DS_CMPST_B32, + DSOp.DS_CMPST_F32: _DSOp_DS_CMPST_F32, + DSOp.DS_MIN_F32: _DSOp_DS_MIN_F32, + DSOp.DS_MAX_F32: _DSOp_DS_MAX_F32, + DSOp.DS_ADD_F32: _DSOp_DS_ADD_F32, + DSOp.DS_PK_ADD_F16: _DSOp_DS_PK_ADD_F16, + DSOp.DS_PK_ADD_BF16: _DSOp_DS_PK_ADD_BF16, + DSOp.DS_WRITE_ADDTID_B32: _DSOp_DS_WRITE_ADDTID_B32, + DSOp.DS_WRITE_B8: _DSOp_DS_WRITE_B8, + DSOp.DS_WRITE_B16: _DSOp_DS_WRITE_B16, + DSOp.DS_ADD_RTN_U32: _DSOp_DS_ADD_RTN_U32, + DSOp.DS_SUB_RTN_U32: _DSOp_DS_SUB_RTN_U32, + DSOp.DS_RSUB_RTN_U32: _DSOp_DS_RSUB_RTN_U32, + DSOp.DS_INC_RTN_U32: _DSOp_DS_INC_RTN_U32, + DSOp.DS_DEC_RTN_U32: _DSOp_DS_DEC_RTN_U32, + DSOp.DS_MIN_RTN_I32: _DSOp_DS_MIN_RTN_I32, + DSOp.DS_MAX_RTN_I32: _DSOp_DS_MAX_RTN_I32, + DSOp.DS_MIN_RTN_U32: _DSOp_DS_MIN_RTN_U32, + DSOp.DS_MAX_RTN_U32: _DSOp_DS_MAX_RTN_U32, + DSOp.DS_AND_RTN_B32: _DSOp_DS_AND_RTN_B32, + DSOp.DS_OR_RTN_B32: _DSOp_DS_OR_RTN_B32, + DSOp.DS_XOR_RTN_B32: _DSOp_DS_XOR_RTN_B32, + DSOp.DS_MSKOR_RTN_B32: _DSOp_DS_MSKOR_RTN_B32, + DSOp.DS_WRXCHG_RTN_B32: _DSOp_DS_WRXCHG_RTN_B32, + DSOp.DS_WRXCHG2_RTN_B32: _DSOp_DS_WRXCHG2_RTN_B32, + DSOp.DS_WRXCHG2ST64_RTN_B32: _DSOp_DS_WRXCHG2ST64_RTN_B32, + DSOp.DS_CMPST_RTN_B32: _DSOp_DS_CMPST_RTN_B32, + DSOp.DS_CMPST_RTN_F32: _DSOp_DS_CMPST_RTN_F32, + DSOp.DS_MIN_RTN_F32: _DSOp_DS_MIN_RTN_F32, + DSOp.DS_MAX_RTN_F32: _DSOp_DS_MAX_RTN_F32, + DSOp.DS_WRAP_RTN_B32: _DSOp_DS_WRAP_RTN_B32, + DSOp.DS_ADD_RTN_F32: _DSOp_DS_ADD_RTN_F32, + DSOp.DS_READ_B32: _DSOp_DS_READ_B32, + DSOp.DS_READ2_B32: _DSOp_DS_READ2_B32, + DSOp.DS_READ2ST64_B32: _DSOp_DS_READ2ST64_B32, + DSOp.DS_READ_I8: _DSOp_DS_READ_I8, + DSOp.DS_READ_U8: _DSOp_DS_READ_U8, + DSOp.DS_READ_I16: _DSOp_DS_READ_I16, + DSOp.DS_READ_U16: _DSOp_DS_READ_U16, + DSOp.DS_PERMUTE_B32: _DSOp_DS_PERMUTE_B32, + DSOp.DS_BPERMUTE_B32: _DSOp_DS_BPERMUTE_B32, + DSOp.DS_ADD_U64: _DSOp_DS_ADD_U64, + DSOp.DS_SUB_U64: _DSOp_DS_SUB_U64, + DSOp.DS_RSUB_U64: _DSOp_DS_RSUB_U64, + DSOp.DS_INC_U64: _DSOp_DS_INC_U64, + DSOp.DS_DEC_U64: _DSOp_DS_DEC_U64, + DSOp.DS_MIN_I64: _DSOp_DS_MIN_I64, + DSOp.DS_MAX_I64: _DSOp_DS_MAX_I64, + DSOp.DS_MIN_U64: _DSOp_DS_MIN_U64, + DSOp.DS_MAX_U64: _DSOp_DS_MAX_U64, + DSOp.DS_AND_B64: _DSOp_DS_AND_B64, + DSOp.DS_OR_B64: _DSOp_DS_OR_B64, + DSOp.DS_XOR_B64: _DSOp_DS_XOR_B64, + DSOp.DS_MSKOR_B64: _DSOp_DS_MSKOR_B64, + DSOp.DS_WRITE_B64: _DSOp_DS_WRITE_B64, + DSOp.DS_WRITE2_B64: _DSOp_DS_WRITE2_B64, + DSOp.DS_WRITE2ST64_B64: _DSOp_DS_WRITE2ST64_B64, + DSOp.DS_CMPST_B64: _DSOp_DS_CMPST_B64, + DSOp.DS_CMPST_F64: _DSOp_DS_CMPST_F64, + DSOp.DS_MIN_F64: _DSOp_DS_MIN_F64, + DSOp.DS_MAX_F64: _DSOp_DS_MAX_F64, + DSOp.DS_WRITE_B8_D16_HI: _DSOp_DS_WRITE_B8_D16_HI, + DSOp.DS_WRITE_B16_D16_HI: _DSOp_DS_WRITE_B16_D16_HI, + DSOp.DS_READ_U8_D16: _DSOp_DS_READ_U8_D16, + DSOp.DS_READ_U8_D16_HI: _DSOp_DS_READ_U8_D16_HI, + DSOp.DS_READ_I8_D16: _DSOp_DS_READ_I8_D16, + DSOp.DS_READ_I8_D16_HI: _DSOp_DS_READ_I8_D16_HI, + DSOp.DS_READ_U16_D16: _DSOp_DS_READ_U16_D16, + DSOp.DS_READ_U16_D16_HI: _DSOp_DS_READ_U16_D16_HI, + DSOp.DS_ADD_F64: _DSOp_DS_ADD_F64, + DSOp.DS_ADD_RTN_U64: _DSOp_DS_ADD_RTN_U64, + DSOp.DS_SUB_RTN_U64: _DSOp_DS_SUB_RTN_U64, + DSOp.DS_RSUB_RTN_U64: _DSOp_DS_RSUB_RTN_U64, + DSOp.DS_INC_RTN_U64: _DSOp_DS_INC_RTN_U64, + DSOp.DS_DEC_RTN_U64: _DSOp_DS_DEC_RTN_U64, + DSOp.DS_MIN_RTN_I64: _DSOp_DS_MIN_RTN_I64, + DSOp.DS_MAX_RTN_I64: _DSOp_DS_MAX_RTN_I64, + DSOp.DS_MIN_RTN_U64: _DSOp_DS_MIN_RTN_U64, + DSOp.DS_MAX_RTN_U64: _DSOp_DS_MAX_RTN_U64, + DSOp.DS_AND_RTN_B64: _DSOp_DS_AND_RTN_B64, + DSOp.DS_OR_RTN_B64: _DSOp_DS_OR_RTN_B64, + DSOp.DS_XOR_RTN_B64: _DSOp_DS_XOR_RTN_B64, + DSOp.DS_MSKOR_RTN_B64: _DSOp_DS_MSKOR_RTN_B64, + DSOp.DS_WRXCHG_RTN_B64: _DSOp_DS_WRXCHG_RTN_B64, + DSOp.DS_WRXCHG2_RTN_B64: _DSOp_DS_WRXCHG2_RTN_B64, + DSOp.DS_WRXCHG2ST64_RTN_B64: _DSOp_DS_WRXCHG2ST64_RTN_B64, + DSOp.DS_CMPST_RTN_B64: _DSOp_DS_CMPST_RTN_B64, + DSOp.DS_CMPST_RTN_F64: _DSOp_DS_CMPST_RTN_F64, + DSOp.DS_MIN_RTN_F64: _DSOp_DS_MIN_RTN_F64, + DSOp.DS_MAX_RTN_F64: _DSOp_DS_MAX_RTN_F64, + DSOp.DS_READ_B64: _DSOp_DS_READ_B64, + DSOp.DS_READ2_B64: _DSOp_DS_READ2_B64, + DSOp.DS_READ2ST64_B64: _DSOp_DS_READ2ST64_B64, + DSOp.DS_ADD_RTN_F64: _DSOp_DS_ADD_RTN_F64, + DSOp.DS_CONDXCHG32_RTN_B64: _DSOp_DS_CONDXCHG32_RTN_B64, + DSOp.DS_READ_ADDTID_B32: _DSOp_DS_READ_ADDTID_B32, + DSOp.DS_PK_ADD_RTN_F16: _DSOp_DS_PK_ADD_RTN_F16, + DSOp.DS_PK_ADD_RTN_BF16: _DSOp_DS_PK_ADD_RTN_BF16, + DSOp.DS_WRITE_B96: _DSOp_DS_WRITE_B96, + DSOp.DS_WRITE_B128: _DSOp_DS_WRITE_B128, + DSOp.DS_READ_B96: _DSOp_DS_READ_B96, + DSOp.DS_READ_B128: _DSOp_DS_READ_B128, +} + COMPILED_FUNCTIONS = { SOP1Op: SOP1Op_FUNCTIONS, SOP2Op: SOP2Op_FUNCTIONS, @@ -6282,6 +7996,7 @@ COMPILED_FUNCTIONS = { VOPCOp: VOPCOp_FUNCTIONS, VOP3AOp: VOP3AOp_FUNCTIONS, VOP3BOp: VOP3BOp_FUNCTIONS, + DSOp: DSOp_FUNCTIONS, } def get_compiled_functions(): return COMPILED_FUNCTIONS \ No newline at end of file diff --git a/extra/assembly/amd/autogen/rdna3/gen_pcode.py b/extra/assembly/amd/autogen/rdna3/gen_pcode.py index fa9392de7a..cb1e3f9cfa 100644 --- a/extra/assembly/amd/autogen/rdna3/gen_pcode.py +++ b/extra/assembly/amd/autogen/rdna3/gen_pcode.py @@ -2,7 +2,7 @@ # to regenerate: python -m extra.assembly.amd.pdf --arch rdna3 # ruff: noqa: E501,F405,F403 # mypy: ignore-errors -from extra.assembly.amd.autogen.rdna3.enum import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp +from extra.assembly.amd.autogen.rdna3.enum import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, DSOp from extra.assembly.amd.pcode import * def _SOP1Op_S_MOV_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None): @@ -6254,6 +6254,1337 @@ VOPCOp_FUNCTIONS = { VOPCOp.V_CMPX_CLASS_F64: _VOPCOp_V_CMPX_CLASS_F64, } +def _DSOp_DS_ADD_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 += DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 -= DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 = DATA.u32 - MEM[ADDR].u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i32) + src = DATA.i32 + MEM[ADDR].i32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i32) + src = DATA.i32 + MEM[ADDR].i32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = (tmp & DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = (tmp | DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = (tmp ^ DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = ((tmp & ~DATA.b32) | DATA2.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET.u32].b32 = DATA[31 : 0] + return {} + +def _DSOp_DS_STORE_2ADDR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET0.u32 * 4].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET1.u32 * 4].b32 = DATA2[31 : 0] + return {} + +def _DSOp_DS_STORE_2ADDR_STRIDE64_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET0.u32 * 256].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET1.u32 * 256].b32 = DATA2[31 : 0] + return {} + +def _DSOp_DS_CMPSTORE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + src = DATA.b32 + cmp = DATA2.b32 + MEM[ADDR].b32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + src = DATA.f32 + cmp = DATA2.f32 + MEM[ADDR].f32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + src = DATA.f32 + MEM[ADDR].f32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + src = DATA.f32 + MEM[ADDR].f32 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + MEM[ADDR].f32 += DATA.f32 + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b8 = DATA[7 : 0] + return {} + +def _DSOp_DS_STORE_B16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b16 = DATA[15 : 0] + return {} + +def _DSOp_DS_ADD_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 += DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 -= DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 = DATA.u32 - MEM[ADDR].u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i32) + src = DATA.i32 + MEM[ADDR].i32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i32) + src = DATA.i32 + MEM[ADDR].i32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = (tmp & DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = (tmp | DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = (tmp ^ DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = ((tmp & ~DATA.b32) | DATA2.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + MEM[ADDR].b32 = DATA.b32 + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b32 + tmp2 = MEM[addr2].b32 + MEM[addr1].b32 = DATA.b32 + MEM[addr2].b32 = DATA2.b32 + RETURN_DATA[31 : 0] = tmp1 + RETURN_DATA[63 : 32] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b32 + tmp2 = MEM[addr2].b32 + MEM[addr1].b32 = DATA.b32 + MEM[addr2].b32 = DATA2.b32 + RETURN_DATA[31 : 0] = tmp1 + RETURN_DATA[63 : 32] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + src = DATA.b32 + cmp = DATA2.b32 + MEM[ADDR].b32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + src = DATA.f32 + cmp = DATA2.f32 + MEM[ADDR].f32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + src = DATA.f32 + MEM[ADDR].f32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + src = DATA.f32 + MEM[ADDR].f32 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_WRAP_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u32) + MEM[ADDR].u32 = ((tmp - DATA.u32) if (tmp >= DATA.u32) else (tmp + DATA2.u32)) + RETURN_DATA = tmp + return {} + +def _DSOp_DS_LOAD_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET.u32].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET0.u32 * 4].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET1.u32 * 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_STRIDE64_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET0.u32 * 256].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET1.u32 * 256].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.i32 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.i32 = (signext(MEM[ADDR].i16)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = (_pack(0, MEM[ADDR].u16)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + MEM[ADDR].u64 += DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + MEM[ADDR].u64 -= DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + MEM[ADDR].u64 = DATA.u64 - MEM[ADDR].u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i64) + src = DATA.i64 + MEM[ADDR].i64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i64) + src = DATA.i64 + MEM[ADDR].i64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = (tmp & DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = (tmp | DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = (tmp ^ DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = ((tmp & ~DATA.b64) | DATA2.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET.u32].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET.u32 + 4].b32 = DATA[63 : 32] + return {} + +def _DSOp_DS_STORE_2ADDR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET0.u32 * 8].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET0.u32 * 8 + 4].b32 = DATA[63 : 32] + MEM[ADDR + OFFSET1.u32 * 8].b32 = DATA2[31 : 0] + MEM[ADDR + OFFSET1.u32 * 8 + 4].b32 = DATA2[63 : 32] + return {} + +def _DSOp_DS_STORE_2ADDR_STRIDE64_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET0.u32 * 512].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET0.u32 * 512 + 4].b32 = DATA[63 : 32] + MEM[ADDR + OFFSET1.u32 * 512].b32 = DATA2[31 : 0] + MEM[ADDR + OFFSET1.u32 * 512 + 4].b32 = DATA2[63 : 32] + return {} + +def _DSOp_DS_CMPSTORE_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + src = DATA.b64 + cmp = DATA2.b64 + MEM[ADDR].b64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + src = DATA.f64 + cmp = DATA2.f64 + MEM[ADDR].f64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + src = DATA.f64 + MEM[ADDR].f64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + src = DATA.f64 + MEM[ADDR].f64 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + MEM[ADDR].u64 += DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + MEM[ADDR].u64 -= DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + MEM[ADDR].u64 = DATA.u64 - MEM[ADDR].u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i64) + src = DATA.i64 + MEM[ADDR].i64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].i64) + src = DATA.i64 + MEM[ADDR].i64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].u64) + src = DATA.u64 + MEM[ADDR].u64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = (tmp & DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = (tmp | DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = (tmp ^ DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = ((tmp & ~DATA.b64) | DATA2.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + MEM[ADDR].b64 = DATA.b64 + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b64 + tmp2 = MEM[addr2].b64 + MEM[addr1].b64 = DATA.b64 + MEM[addr2].b64 = DATA2.b64 + RETURN_DATA[63 : 0] = tmp1 + RETURN_DATA[127 : 64] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b64 + tmp2 = MEM[addr2].b64 + MEM[addr1].b64 = DATA.b64 + MEM[addr2].b64 = DATA2.b64 + RETURN_DATA[63 : 0] = tmp1 + RETURN_DATA[127 : 64] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b64) + src = DATA.b64 + cmp = DATA2.b64 + MEM[ADDR].b64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + src = DATA.f64 + cmp = DATA2.f64 + MEM[ADDR].f64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + src = DATA.f64 + MEM[ADDR].f64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_F64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f64) + src = DATA.f64 + MEM[ADDR].f64 = ((src) if (src > tmp) else (tmp)) + RETURN_DATA.f64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET.u32 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET0.u32 * 8].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET0.u32 * 8 + 4].b32 + RETURN_DATA[95 : 64] = MEM[ADDR + OFFSET1.u32 * 8].b32 + RETURN_DATA[127 : 96] = MEM[ADDR + OFFSET1.u32 * 8 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_STRIDE64_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET0.u32 * 512].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET0.u32 * 512 + 4].b32 + RETURN_DATA[95 : 64] = MEM[ADDR + OFFSET1.u32 * 512].b32 + RETURN_DATA[127 : 96] = MEM[ADDR + OFFSET1.u32 * 512 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].f32) + MEM[ADDR].f32 += DATA.f32 + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CONDXCHG32_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + ADDR = S0.u32 + DATA = S1.u64 + offset = _pack(OFFSET1, OFFSET0) + RETURN_DATA[0] = LDS[ADDR0].u32 + if DATA[31]: + LDS[ADDR0] = _pack(0, DATA[30 : 0]) + RETURN_DATA[1] = LDS[ADDR1].u32 + if DATA[63]: + LDS[ADDR1] = _pack(0, DATA[62 : 32]) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b8 = DATA[23 : 16] + return {} + +def _DSOp_DS_STORE_B16_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b16 = DATA[31 : 16] + return {} + +def _DSOp_DS_LOAD_U8_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].u16 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].u16 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I8_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].i16 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].i16 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U16_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].u16 = MEM[ADDR].u16 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U16_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].u16 = MEM[ADDR].u16 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_ADDTID_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[(_pack(OFFSET1, OFFSET0) + M0[15 : 0]) + laneID.i32 * 4].u32 = DATA0.u32 + return {} + +def _DSOp_DS_LOAD_ADDTID_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = MEM[(_pack(OFFSET1, OFFSET0) + M0[15 : 0]) + laneID.i32 * 4].u32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PERMUTE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + VDST = Reg(vdst_idx) + ADDR = S0._val + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + for i in range(0, int(((63) if (WAVE64) else (31)))+1): + tmp[i] = 0x0 + for i in range(0, int(((63) if (WAVE64) else (31)))+1): + if EXEC[i].u1: + dst_lane = (VGPR[i][ADDR] + OFFSET.b32) / 4 % 32 + tmp[dst_lane] = VGPR[i][DATA0] + for i in range(0, int(((63) if (WAVE64) else (31)))+1): + if EXEC[i].u1: + VGPR[i][VDST] = tmp[i] + return {} + +def _DSOp_DS_BPERMUTE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + VDST = Reg(vdst_idx) + ADDR = S0._val + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + for i in range(0, int(((63) if (WAVE64) else (31)))+1): + tmp[i] = 0x0 + for i in range(0, int(((63) if (WAVE64) else (31)))+1): + src_lane = (VGPR[i][ADDR] + OFFSET.b32) / 4 % 32 + if EXEC[src_lane].u1: + tmp[i] = VGPR[src_lane][DATA0] + for i in range(0, int(((63) if (WAVE64) else (31)))+1): + if EXEC[i].u1: + VGPR[i][VDST] = tmp[i] + return {} + +def _DSOp_DS_STORE_B96(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET.u32].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET.u32 + 4].b32 = DATA[63 : 32] + MEM[ADDR + OFFSET.u32 + 8].b32 = DATA[95 : 64] + return {} + +def _DSOp_DS_STORE_B128(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + MEM[ADDR + OFFSET.u32].b32 = DATA[31 : 0] + MEM[ADDR + OFFSET.u32 + 4].b32 = DATA[63 : 32] + MEM[ADDR + OFFSET.u32 + 8].b32 = DATA[95 : 64] + MEM[ADDR + OFFSET.u32 + 12].b32 = DATA[127 : 96] + return {} + +def _DSOp_DS_LOAD_B96(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET.u32 + 4].b32 + RETURN_DATA[95 : 64] = MEM[ADDR + OFFSET.u32 + 8].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_B128(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 0] = MEM[ADDR + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[ADDR + OFFSET.u32 + 4].b32 + RETURN_DATA[95 : 64] = MEM[ADDR + OFFSET.u32 + 8].b32 + RETURN_DATA[127 : 96] = MEM[ADDR + OFFSET.u32 + 12].b32 + return {'RETURN_DATA': RETURN_DATA} + +DSOp_FUNCTIONS = { + DSOp.DS_ADD_U32: _DSOp_DS_ADD_U32, + DSOp.DS_SUB_U32: _DSOp_DS_SUB_U32, + DSOp.DS_RSUB_U32: _DSOp_DS_RSUB_U32, + DSOp.DS_INC_U32: _DSOp_DS_INC_U32, + DSOp.DS_DEC_U32: _DSOp_DS_DEC_U32, + DSOp.DS_MIN_I32: _DSOp_DS_MIN_I32, + DSOp.DS_MAX_I32: _DSOp_DS_MAX_I32, + DSOp.DS_MIN_U32: _DSOp_DS_MIN_U32, + DSOp.DS_MAX_U32: _DSOp_DS_MAX_U32, + DSOp.DS_AND_B32: _DSOp_DS_AND_B32, + DSOp.DS_OR_B32: _DSOp_DS_OR_B32, + DSOp.DS_XOR_B32: _DSOp_DS_XOR_B32, + DSOp.DS_MSKOR_B32: _DSOp_DS_MSKOR_B32, + DSOp.DS_STORE_B32: _DSOp_DS_STORE_B32, + DSOp.DS_STORE_2ADDR_B32: _DSOp_DS_STORE_2ADDR_B32, + DSOp.DS_STORE_2ADDR_STRIDE64_B32: _DSOp_DS_STORE_2ADDR_STRIDE64_B32, + DSOp.DS_CMPSTORE_B32: _DSOp_DS_CMPSTORE_B32, + DSOp.DS_CMPSTORE_F32: _DSOp_DS_CMPSTORE_F32, + DSOp.DS_MIN_F32: _DSOp_DS_MIN_F32, + DSOp.DS_MAX_F32: _DSOp_DS_MAX_F32, + DSOp.DS_ADD_F32: _DSOp_DS_ADD_F32, + DSOp.DS_STORE_B8: _DSOp_DS_STORE_B8, + DSOp.DS_STORE_B16: _DSOp_DS_STORE_B16, + DSOp.DS_ADD_RTN_U32: _DSOp_DS_ADD_RTN_U32, + DSOp.DS_SUB_RTN_U32: _DSOp_DS_SUB_RTN_U32, + DSOp.DS_RSUB_RTN_U32: _DSOp_DS_RSUB_RTN_U32, + DSOp.DS_INC_RTN_U32: _DSOp_DS_INC_RTN_U32, + DSOp.DS_DEC_RTN_U32: _DSOp_DS_DEC_RTN_U32, + DSOp.DS_MIN_RTN_I32: _DSOp_DS_MIN_RTN_I32, + DSOp.DS_MAX_RTN_I32: _DSOp_DS_MAX_RTN_I32, + DSOp.DS_MIN_RTN_U32: _DSOp_DS_MIN_RTN_U32, + DSOp.DS_MAX_RTN_U32: _DSOp_DS_MAX_RTN_U32, + DSOp.DS_AND_RTN_B32: _DSOp_DS_AND_RTN_B32, + DSOp.DS_OR_RTN_B32: _DSOp_DS_OR_RTN_B32, + DSOp.DS_XOR_RTN_B32: _DSOp_DS_XOR_RTN_B32, + DSOp.DS_MSKOR_RTN_B32: _DSOp_DS_MSKOR_RTN_B32, + DSOp.DS_STOREXCHG_RTN_B32: _DSOp_DS_STOREXCHG_RTN_B32, + DSOp.DS_STOREXCHG_2ADDR_RTN_B32: _DSOp_DS_STOREXCHG_2ADDR_RTN_B32, + DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32: _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32, + DSOp.DS_CMPSTORE_RTN_B32: _DSOp_DS_CMPSTORE_RTN_B32, + DSOp.DS_CMPSTORE_RTN_F32: _DSOp_DS_CMPSTORE_RTN_F32, + DSOp.DS_MIN_RTN_F32: _DSOp_DS_MIN_RTN_F32, + DSOp.DS_MAX_RTN_F32: _DSOp_DS_MAX_RTN_F32, + DSOp.DS_WRAP_RTN_B32: _DSOp_DS_WRAP_RTN_B32, + DSOp.DS_LOAD_B32: _DSOp_DS_LOAD_B32, + DSOp.DS_LOAD_2ADDR_B32: _DSOp_DS_LOAD_2ADDR_B32, + DSOp.DS_LOAD_2ADDR_STRIDE64_B32: _DSOp_DS_LOAD_2ADDR_STRIDE64_B32, + DSOp.DS_LOAD_I8: _DSOp_DS_LOAD_I8, + DSOp.DS_LOAD_U8: _DSOp_DS_LOAD_U8, + DSOp.DS_LOAD_I16: _DSOp_DS_LOAD_I16, + DSOp.DS_LOAD_U16: _DSOp_DS_LOAD_U16, + DSOp.DS_ADD_U64: _DSOp_DS_ADD_U64, + DSOp.DS_SUB_U64: _DSOp_DS_SUB_U64, + DSOp.DS_RSUB_U64: _DSOp_DS_RSUB_U64, + DSOp.DS_INC_U64: _DSOp_DS_INC_U64, + DSOp.DS_DEC_U64: _DSOp_DS_DEC_U64, + DSOp.DS_MIN_I64: _DSOp_DS_MIN_I64, + DSOp.DS_MAX_I64: _DSOp_DS_MAX_I64, + DSOp.DS_MIN_U64: _DSOp_DS_MIN_U64, + DSOp.DS_MAX_U64: _DSOp_DS_MAX_U64, + DSOp.DS_AND_B64: _DSOp_DS_AND_B64, + DSOp.DS_OR_B64: _DSOp_DS_OR_B64, + DSOp.DS_XOR_B64: _DSOp_DS_XOR_B64, + DSOp.DS_MSKOR_B64: _DSOp_DS_MSKOR_B64, + DSOp.DS_STORE_B64: _DSOp_DS_STORE_B64, + DSOp.DS_STORE_2ADDR_B64: _DSOp_DS_STORE_2ADDR_B64, + DSOp.DS_STORE_2ADDR_STRIDE64_B64: _DSOp_DS_STORE_2ADDR_STRIDE64_B64, + DSOp.DS_CMPSTORE_B64: _DSOp_DS_CMPSTORE_B64, + DSOp.DS_CMPSTORE_F64: _DSOp_DS_CMPSTORE_F64, + DSOp.DS_MIN_F64: _DSOp_DS_MIN_F64, + DSOp.DS_MAX_F64: _DSOp_DS_MAX_F64, + DSOp.DS_ADD_RTN_U64: _DSOp_DS_ADD_RTN_U64, + DSOp.DS_SUB_RTN_U64: _DSOp_DS_SUB_RTN_U64, + DSOp.DS_RSUB_RTN_U64: _DSOp_DS_RSUB_RTN_U64, + DSOp.DS_INC_RTN_U64: _DSOp_DS_INC_RTN_U64, + DSOp.DS_DEC_RTN_U64: _DSOp_DS_DEC_RTN_U64, + DSOp.DS_MIN_RTN_I64: _DSOp_DS_MIN_RTN_I64, + DSOp.DS_MAX_RTN_I64: _DSOp_DS_MAX_RTN_I64, + DSOp.DS_MIN_RTN_U64: _DSOp_DS_MIN_RTN_U64, + DSOp.DS_MAX_RTN_U64: _DSOp_DS_MAX_RTN_U64, + DSOp.DS_AND_RTN_B64: _DSOp_DS_AND_RTN_B64, + DSOp.DS_OR_RTN_B64: _DSOp_DS_OR_RTN_B64, + DSOp.DS_XOR_RTN_B64: _DSOp_DS_XOR_RTN_B64, + DSOp.DS_MSKOR_RTN_B64: _DSOp_DS_MSKOR_RTN_B64, + DSOp.DS_STOREXCHG_RTN_B64: _DSOp_DS_STOREXCHG_RTN_B64, + DSOp.DS_STOREXCHG_2ADDR_RTN_B64: _DSOp_DS_STOREXCHG_2ADDR_RTN_B64, + DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64: _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64, + DSOp.DS_CMPSTORE_RTN_B64: _DSOp_DS_CMPSTORE_RTN_B64, + DSOp.DS_CMPSTORE_RTN_F64: _DSOp_DS_CMPSTORE_RTN_F64, + DSOp.DS_MIN_RTN_F64: _DSOp_DS_MIN_RTN_F64, + DSOp.DS_MAX_RTN_F64: _DSOp_DS_MAX_RTN_F64, + DSOp.DS_LOAD_B64: _DSOp_DS_LOAD_B64, + DSOp.DS_LOAD_2ADDR_B64: _DSOp_DS_LOAD_2ADDR_B64, + DSOp.DS_LOAD_2ADDR_STRIDE64_B64: _DSOp_DS_LOAD_2ADDR_STRIDE64_B64, + DSOp.DS_ADD_RTN_F32: _DSOp_DS_ADD_RTN_F32, + DSOp.DS_CONDXCHG32_RTN_B64: _DSOp_DS_CONDXCHG32_RTN_B64, + DSOp.DS_STORE_B8_D16_HI: _DSOp_DS_STORE_B8_D16_HI, + DSOp.DS_STORE_B16_D16_HI: _DSOp_DS_STORE_B16_D16_HI, + DSOp.DS_LOAD_U8_D16: _DSOp_DS_LOAD_U8_D16, + DSOp.DS_LOAD_U8_D16_HI: _DSOp_DS_LOAD_U8_D16_HI, + DSOp.DS_LOAD_I8_D16: _DSOp_DS_LOAD_I8_D16, + DSOp.DS_LOAD_I8_D16_HI: _DSOp_DS_LOAD_I8_D16_HI, + DSOp.DS_LOAD_U16_D16: _DSOp_DS_LOAD_U16_D16, + DSOp.DS_LOAD_U16_D16_HI: _DSOp_DS_LOAD_U16_D16_HI, + DSOp.DS_STORE_ADDTID_B32: _DSOp_DS_STORE_ADDTID_B32, + DSOp.DS_LOAD_ADDTID_B32: _DSOp_DS_LOAD_ADDTID_B32, + DSOp.DS_PERMUTE_B32: _DSOp_DS_PERMUTE_B32, + DSOp.DS_BPERMUTE_B32: _DSOp_DS_BPERMUTE_B32, + DSOp.DS_STORE_B96: _DSOp_DS_STORE_B96, + DSOp.DS_STORE_B128: _DSOp_DS_STORE_B128, + DSOp.DS_LOAD_B96: _DSOp_DS_LOAD_B96, + DSOp.DS_LOAD_B128: _DSOp_DS_LOAD_B128, +} + # V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode) def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0): @@ -6273,6 +7604,7 @@ COMPILED_FUNCTIONS = { VOP3SDOp: VOP3SDOp_FUNCTIONS, VOP3POp: VOP3POp_FUNCTIONS, VOPCOp: VOPCOp_FUNCTIONS, + DSOp: DSOp_FUNCTIONS, } def get_compiled_functions(): return COMPILED_FUNCTIONS \ No newline at end of file diff --git a/extra/assembly/amd/autogen/rdna4/gen_pcode.py b/extra/assembly/amd/autogen/rdna4/gen_pcode.py index c7331ddd59..7eac59f9d0 100644 --- a/extra/assembly/amd/autogen/rdna4/gen_pcode.py +++ b/extra/assembly/amd/autogen/rdna4/gen_pcode.py @@ -2,7 +2,7 @@ # to regenerate: python -m extra.assembly.amd.pdf --arch rdna4 # ruff: noqa: E501,F405,F403 # mypy: ignore-errors -from extra.assembly.amd.autogen.rdna4.enum import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp +from extra.assembly.amd.autogen.rdna4.enum import SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, DSOp from extra.assembly.amd.pcode import * def _SOP1Op_S_MOV_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None): @@ -6179,6 +6179,1386 @@ VOPCOp_FUNCTIONS = { VOPCOp.V_CMPX_CLASS_F64: _VOPCOp_V_CMPX_CLASS_F64, } +def _DSOp_DS_ADD_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 += DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 -= DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 = DATA.u32 - MEM[addr].u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp & DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp | DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp ^ DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + return {} + +def _DSOp_DS_STORE_2ADDR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET0.u32 * 4].b32 = DATA[31 : 0] + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET1.u32 * 4].b32 = DATA2[31 : 0] + return {} + +def _DSOp_DS_STORE_2ADDR_STRIDE64_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET0.u32 * 256].b32 = DATA[31 : 0] + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET1.u32 * 256].b32 = DATA2[31 : 0] + return {} + +def _DSOp_DS_CMPSTORE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + src = DATA.b32 + cmp = DATA2.b32 + MEM[addr].b32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].f32) + MEM[addr].f32 += DATA.f32 + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b8 = DATA[7 : 0] + return {} + +def _DSOp_DS_STORE_B16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b16 = DATA[15 : 0] + return {} + +def _DSOp_DS_ADD_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 += DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 -= DATA.u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + MEM[addr].u32 = DATA.u32 - MEM[addr].u32 + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_I32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i32) + src = DATA.i32 + MEM[addr].i32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[addr].u32 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp & DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp | DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = (tmp ^ DATA.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = ((tmp & ~DATA.b32) | DATA2.b32) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + MEM[addr].b32 = DATA.b32 + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b32 + tmp2 = MEM[addr2].b32 + MEM[addr1].b32 = DATA.b32 + MEM[addr2].b32 = DATA2.b32 + RETURN_DATA[31 : 0] = tmp1 + RETURN_DATA[63 : 32] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b32 + tmp2 = MEM[addr2].b32 + MEM[addr1].b32 = DATA.b32 + MEM[addr2].b32 = DATA2.b32 + RETURN_DATA[31 : 0] = tmp1 + RETURN_DATA[63 : 32] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b32) + src = DATA.b32 + cmp = DATA2.b32 + MEM[addr].b32 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 4].b32 + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_STRIDE64_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 256].b32 + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 256].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.i32 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U8(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.i32 = (signext(MEM[ADDR].i16)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = (_pack(0, MEM[ADDR].u16)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CONSUME(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + addr = offset + rtnval = LDS(addr) + return {} + +def _DSOp_DS_APPEND(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + addr = offset + rtnval = LDS(addr) + return {} + +def _DSOp_DS_ADD_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 += DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 -= DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 = DATA.u64 - MEM[addr].u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp & DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp | DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp ^ DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + MEM[addr + OFFSET.u32 + 4].b32 = DATA[63 : 32] + return {} + +def _DSOp_DS_STORE_2ADDR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET0.u32 * 8].b32 = DATA[31 : 0] + MEM[addr + OFFSET0.u32 * 8 + 4].b32 = DATA[63 : 32] + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET1.u32 * 8].b32 = DATA2[31 : 0] + MEM[addr + OFFSET1.u32 * 8 + 4].b32 = DATA2[63 : 32] + return {} + +def _DSOp_DS_STORE_2ADDR_STRIDE64_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET0.u32 * 512].b32 = DATA[31 : 0] + MEM[addr + OFFSET0.u32 * 512 + 4].b32 = DATA[63 : 32] + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET1.u32 * 512].b32 = DATA2[31 : 0] + MEM[addr + OFFSET1.u32 * 512 + 4].b32 = DATA2[63 : 32] + return {} + +def _DSOp_DS_CMPSTORE_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + src = DATA.b64 + cmp = DATA2.b64 + MEM[addr].b64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 += DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 -= DATA.u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_RSUB_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + MEM[addr].u64 = DATA.u64 - MEM[addr].u64 + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_INC_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((0) if (tmp >= src) else (tmp + 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_DEC_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (((tmp == 0) or (tmp > src))) else (tmp - 1)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_I64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].i64) + src = DATA.i64 + MEM[addr].i64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.i64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MIN_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src < tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MAX_RTN_U64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u64) + src = DATA.u64 + MEM[addr].u64 = ((src) if (src >= tmp) else (tmp)) + RETURN_DATA.u64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_AND_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp & DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_OR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp | DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_XOR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = (tmp ^ DATA.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_MSKOR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = ((tmp & ~DATA.b64) | DATA2.b64) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + MEM[addr].b64 = DATA.b64 + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b64 + tmp2 = MEM[addr2].b64 + MEM[addr1].b64 = DATA.b64 + MEM[addr2].b64 = DATA2.b64 + RETURN_DATA[63 : 0] = tmp1 + RETURN_DATA[127 : 64] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp1 = MEM[addr1].b64 + tmp2 = MEM[addr2].b64 + MEM[addr1].b64 = DATA.b64 + MEM[addr2].b64 = DATA2.b64 + RETURN_DATA[63 : 0] = tmp1 + RETURN_DATA[127 : 64] = tmp2 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CMPSTORE_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA2 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].b64) + src = DATA.b64 + cmp = DATA2.b64 + MEM[addr].b64 = ((src) if (tmp == cmp) else (tmp)) + RETURN_DATA.b64 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 8].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 8 + 4].b32 + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 8].b32 + RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 8 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_2ADDR_STRIDE64_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 512].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 512 + 4].b32 + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 512].b32 + RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 512 + 4].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_ADD_RTN_F32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].f32) + MEM[addr].f32 += DATA.f32 + RETURN_DATA.f32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_CONDXCHG32_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + ADDR = S0.u32 + DATA = S1.u64 + offset = _pack(OFFSET1, OFFSET0) + RETURN_DATA[0] = LDS[ADDR0].u32 + if DATA[31]: + LDS[ADDR0] = _pack(0, DATA[30 : 0]) + RETURN_DATA[1] = LDS[ADDR1].u32 + if DATA[63]: + LDS[ADDR1] = _pack(0, DATA[62 : 32]) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_COND_SUB_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((tmp - src) if (tmp >= src) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_CLAMP_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + old_value = MEM[ADDR].u32 + if old_value < DATA.u32: + new_value = 0 + else: + new_value = old_value - DATA.u32 + MEM[ADDR].u32 = new_value + RETURN_DATA.u32 = old_value + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PK_ADD_F16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + src = DATA.b32 + dst[15 : 0].f16 = src[15 : 0].f16 + tmp[15 : 0].f16 + dst[31 : 16].f16 = src[31 : 16].f16 + tmp[31 : 16].f16 + MEM[ADDR].b32 = dst.b32 + RETURN_DATA.b32 = tmp.b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PK_ADD_BF16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + src = DATA.b32 + dst[15 : 0].bf16 = src[15 : 0].bf16 + tmp[15 : 0].bf16 + dst[31 : 16].bf16 = src[31 : 16].bf16 + tmp[31 : 16].bf16 + MEM[ADDR].b32 = dst.b32 + RETURN_DATA.b32 = tmp.b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_B8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b8 = DATA[23 : 16] + return {} + +def _DSOp_DS_STORE_B16_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + # --- compiled pseudocode --- + MEM[ADDR].b16 = DATA[31 : 16] + return {} + +def _DSOp_DS_LOAD_U8_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].u16 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].u16 = (_pack(0, MEM[ADDR].u8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I8_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].i16 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_I8_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].i16 = (signext(MEM[ADDR].i8)) + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U16_D16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[15 : 0].u16 = MEM[ADDR].u16 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_U16_D16_HI(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA[31 : 16].u16 = MEM[ADDR].u16 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_COND_SUB_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, offset.b32) + tmp = Reg(MEM[addr].u32) + src = DATA.u32 + MEM[ADDR].u32 = ((tmp - src) if (tmp >= src) else (tmp)) + RETURN_DATA.u32 = tmp + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_SUB_CLAMP_RTN_U32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + old_value = MEM[ADDR].u32 + if old_value < DATA.u32: + new_value = 0 + else: + new_value = old_value - DATA.u32 + MEM[ADDR].u32 = new_value + RETURN_DATA.u32 = old_value + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PK_ADD_RTN_F16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + src = DATA.b32 + dst[15 : 0].f16 = src[15 : 0].f16 + tmp[15 : 0].f16 + dst[31 : 16].f16 = src[31 : 16].f16 + tmp[31 : 16].f16 + MEM[ADDR].b32 = dst.b32 + RETURN_DATA.b32 = tmp.b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PK_ADD_RTN_BF16(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + ADDR = S0._val + DATA = S1 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + tmp = Reg(MEM[ADDR].b32) + src = DATA.b32 + dst[15 : 0].bf16 = src[15 : 0].bf16 + tmp[15 : 0].bf16 + dst[31 : 16].bf16 = src[31 : 16].bf16 + tmp[31 : 16].bf16 + MEM[ADDR].b32 = dst.b32 + RETURN_DATA.b32 = tmp.b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_STORE_ADDTID_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + # --- compiled pseudocode --- + MEM[(_pack(OFFSET1, OFFSET0) + M0[15 : 0]) + laneID.i32 * 4].u32 = DATA0.u32 + return {} + +def _DSOp_DS_LOAD_ADDTID_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + OFFSET0 = Reg(offset0) + OFFSET1 = Reg(offset1) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + RETURN_DATA.u32 = MEM[(_pack(OFFSET1, OFFSET0) + M0[15 : 0]) + laneID.i32 * 4].u32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_PERMUTE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + VDST = Reg(vdst_idx) + ADDR = S0._val + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + num_lanes = ((64) if (WAVE64) else (32)) + for i in range(0, int(num_lanes - 1)+1): + tmp[i] = 0x0 + for i in range(0, int(num_lanes - 1)+1): + if EXEC[i].u1: + dst_lane = (VGPR[i][ADDR] + OFFSET.b32) / 4 % num_lanes + tmp[dst_lane] = VGPR[i][DATA0] + for i in range(0, int(num_lanes - 1)+1): + if EXEC[i].u1: + VGPR[i][VDST] = tmp[i] + return {} + +def _DSOp_DS_BPERMUTE_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + tmp = Reg(0) + VDST = Reg(vdst_idx) + ADDR = S0._val + DATA = S1 + DATA0 = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + num_lanes = ((64) if (WAVE64) else (32)) + for i in range(0, int(num_lanes - 1)+1): + tmp[i] = 0x0 + for i in range(0, int(num_lanes - 1)+1): + src_lane = (VGPR[i][ADDR] + OFFSET.b32) / 4 % num_lanes + if EXEC[src_lane].u1: + tmp[i] = VGPR[src_lane][DATA0] + for i in range(0, int(num_lanes - 1)+1): + if EXEC[i].u1: + VGPR[i][VDST] = tmp[i] + return {} + +def _DSOp_DS_STORE_B96(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + MEM[addr + OFFSET.u32 + 4].b32 = DATA[63 : 32] + MEM[addr + OFFSET.u32 + 8].b32 = DATA[95 : 64] + return {} + +def _DSOp_DS_STORE_B128(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + MEM[addr + OFFSET.u32].b32 = DATA[31 : 0] + MEM[addr + OFFSET.u32 + 4].b32 = DATA[63 : 32] + MEM[addr + OFFSET.u32 + 8].b32 = DATA[95 : 64] + MEM[addr + OFFSET.u32 + 12].b32 = DATA[127 : 96] + return {} + +def _DSOp_DS_BVH_STACK_PUSH4_POP1_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA0 = S1 + DATA1 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + last_node_ptr = DATA0.b32 + for i in range(0, int(2)+1): + if DATA_VALID(DATA1[i * 32 + 31 : i * 32]): + MEM[stack_base.u32 + stack_index] = DATA1[i * 32 + 31 : i * 32] + stack_index += 1 + elif DATA1[i].b32 == last_node_ptr: + pass + if DATA_VALID(DATA1[127 : 96]): + RETURN_DATA[31 : 0] = DATA1[127 : 96] + else: + RETURN_DATA[31 : 0] = MEM[stack_base.u32 + stack_index] + MEM[stack_base.u32 + stack_index] = INVALID_NODE + stack_index -= 1 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_BVH_STACK_PUSH8_POP1_RTN_B32(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA0 = S1 + DATA1 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + last_node_ptr = DATA0.b32 + for i in range(0, int(6)+1): + if DATA_VALID(DATA1[i * 32 + 31 : i * 32]): + MEM[stack_base.u32 + stack_index] = DATA1[i * 32 + 31 : i * 32] + stack_index += 1 + elif DATA1[i].b32 == last_node_ptr: + pass + if DATA_VALID(DATA1[255 : 224]): + RETURN_DATA[31 : 0] = DATA1[255 : 224] + else: + RETURN_DATA[31 : 0] = MEM[stack_base.u32 + stack_index] + MEM[stack_base.u32 + stack_index] = INVALID_NODE + stack_index -= 1 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_BVH_STACK_PUSH8_POP2_RTN_B64(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + DATA0 = S1 + DATA1 = S2 + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + last_node_ptr = DATA0.b32 + for i in range(0, int(6)+1): + if DATA_VALID(DATA1[i * 32 + 31 : i * 32]): + MEM[stack_base.u32 + stack_index] = DATA1[i * 32 + 31 : i * 32] + stack_index += 1 + elif DATA1[i].b32 == last_node_ptr: + pass + if DATA_VALID(DATA1[255 : 224]): + RETURN_DATA[31 : 0] = DATA1[255 : 224] + else: + RETURN_DATA[31 : 0] = MEM[stack_base.u32 + stack_index] + MEM[stack_base.u32 + stack_index] = INVALID_NODE + stack_index -= 1 + if DATA_VALID(MEM[stack_base.u32 + stack_index]): + RETURN_DATA[63 : 32] = MEM[stack_base.u32 + stack_index] + MEM[stack_base.u32 + stack_index] = INVALID_NODE + stack_index -= 1 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_B96(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4].b32 + RETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8].b32 + return {'RETURN_DATA': RETURN_DATA} + +def _DSOp_DS_LOAD_B128(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0): + DATA = S1 + OFFSET = Reg(offset0) + RETURN_DATA = Reg(0) + # --- compiled pseudocode --- + addr = CalcDsAddr(vgpr_a.b32, 0x0) + RETURN_DATA[31 : 0] = MEM[addr + OFFSET.u32].b32 + RETURN_DATA[63 : 32] = MEM[addr + OFFSET.u32 + 4].b32 + RETURN_DATA[95 : 64] = MEM[addr + OFFSET.u32 + 8].b32 + RETURN_DATA[127 : 96] = MEM[addr + OFFSET.u32 + 12].b32 + addr = CalcBufferAddr(vgpr_a.b64, sgpr_o.b64) + VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]) + addr = CalcBufferAddr(vgpr_a.b64, sgpr_o.b64) + VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]) + VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]) + addr = CalcBufferAddr(vgpr_a.b64, sgpr_o.b64) + VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]) + VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]) + VDATA[95 : 64].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetZ()]) + return {'RETURN_DATA': RETURN_DATA} + +DSOp_FUNCTIONS = { + DSOp.DS_ADD_U32: _DSOp_DS_ADD_U32, + DSOp.DS_SUB_U32: _DSOp_DS_SUB_U32, + DSOp.DS_RSUB_U32: _DSOp_DS_RSUB_U32, + DSOp.DS_INC_U32: _DSOp_DS_INC_U32, + DSOp.DS_DEC_U32: _DSOp_DS_DEC_U32, + DSOp.DS_MIN_I32: _DSOp_DS_MIN_I32, + DSOp.DS_MAX_I32: _DSOp_DS_MAX_I32, + DSOp.DS_MIN_U32: _DSOp_DS_MIN_U32, + DSOp.DS_MAX_U32: _DSOp_DS_MAX_U32, + DSOp.DS_AND_B32: _DSOp_DS_AND_B32, + DSOp.DS_OR_B32: _DSOp_DS_OR_B32, + DSOp.DS_XOR_B32: _DSOp_DS_XOR_B32, + DSOp.DS_MSKOR_B32: _DSOp_DS_MSKOR_B32, + DSOp.DS_STORE_B32: _DSOp_DS_STORE_B32, + DSOp.DS_STORE_2ADDR_B32: _DSOp_DS_STORE_2ADDR_B32, + DSOp.DS_STORE_2ADDR_STRIDE64_B32: _DSOp_DS_STORE_2ADDR_STRIDE64_B32, + DSOp.DS_CMPSTORE_B32: _DSOp_DS_CMPSTORE_B32, + DSOp.DS_ADD_F32: _DSOp_DS_ADD_F32, + DSOp.DS_STORE_B8: _DSOp_DS_STORE_B8, + DSOp.DS_STORE_B16: _DSOp_DS_STORE_B16, + DSOp.DS_ADD_RTN_U32: _DSOp_DS_ADD_RTN_U32, + DSOp.DS_SUB_RTN_U32: _DSOp_DS_SUB_RTN_U32, + DSOp.DS_RSUB_RTN_U32: _DSOp_DS_RSUB_RTN_U32, + DSOp.DS_INC_RTN_U32: _DSOp_DS_INC_RTN_U32, + DSOp.DS_DEC_RTN_U32: _DSOp_DS_DEC_RTN_U32, + DSOp.DS_MIN_RTN_I32: _DSOp_DS_MIN_RTN_I32, + DSOp.DS_MAX_RTN_I32: _DSOp_DS_MAX_RTN_I32, + DSOp.DS_MIN_RTN_U32: _DSOp_DS_MIN_RTN_U32, + DSOp.DS_MAX_RTN_U32: _DSOp_DS_MAX_RTN_U32, + DSOp.DS_AND_RTN_B32: _DSOp_DS_AND_RTN_B32, + DSOp.DS_OR_RTN_B32: _DSOp_DS_OR_RTN_B32, + DSOp.DS_XOR_RTN_B32: _DSOp_DS_XOR_RTN_B32, + DSOp.DS_MSKOR_RTN_B32: _DSOp_DS_MSKOR_RTN_B32, + DSOp.DS_STOREXCHG_RTN_B32: _DSOp_DS_STOREXCHG_RTN_B32, + DSOp.DS_STOREXCHG_2ADDR_RTN_B32: _DSOp_DS_STOREXCHG_2ADDR_RTN_B32, + DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32: _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32, + DSOp.DS_CMPSTORE_RTN_B32: _DSOp_DS_CMPSTORE_RTN_B32, + DSOp.DS_LOAD_B32: _DSOp_DS_LOAD_B32, + DSOp.DS_LOAD_2ADDR_B32: _DSOp_DS_LOAD_2ADDR_B32, + DSOp.DS_LOAD_2ADDR_STRIDE64_B32: _DSOp_DS_LOAD_2ADDR_STRIDE64_B32, + DSOp.DS_LOAD_I8: _DSOp_DS_LOAD_I8, + DSOp.DS_LOAD_U8: _DSOp_DS_LOAD_U8, + DSOp.DS_LOAD_I16: _DSOp_DS_LOAD_I16, + DSOp.DS_LOAD_U16: _DSOp_DS_LOAD_U16, + DSOp.DS_CONSUME: _DSOp_DS_CONSUME, + DSOp.DS_APPEND: _DSOp_DS_APPEND, + DSOp.DS_ADD_U64: _DSOp_DS_ADD_U64, + DSOp.DS_SUB_U64: _DSOp_DS_SUB_U64, + DSOp.DS_RSUB_U64: _DSOp_DS_RSUB_U64, + DSOp.DS_INC_U64: _DSOp_DS_INC_U64, + DSOp.DS_DEC_U64: _DSOp_DS_DEC_U64, + DSOp.DS_MIN_I64: _DSOp_DS_MIN_I64, + DSOp.DS_MAX_I64: _DSOp_DS_MAX_I64, + DSOp.DS_MIN_U64: _DSOp_DS_MIN_U64, + DSOp.DS_MAX_U64: _DSOp_DS_MAX_U64, + DSOp.DS_AND_B64: _DSOp_DS_AND_B64, + DSOp.DS_OR_B64: _DSOp_DS_OR_B64, + DSOp.DS_XOR_B64: _DSOp_DS_XOR_B64, + DSOp.DS_MSKOR_B64: _DSOp_DS_MSKOR_B64, + DSOp.DS_STORE_B64: _DSOp_DS_STORE_B64, + DSOp.DS_STORE_2ADDR_B64: _DSOp_DS_STORE_2ADDR_B64, + DSOp.DS_STORE_2ADDR_STRIDE64_B64: _DSOp_DS_STORE_2ADDR_STRIDE64_B64, + DSOp.DS_CMPSTORE_B64: _DSOp_DS_CMPSTORE_B64, + DSOp.DS_ADD_RTN_U64: _DSOp_DS_ADD_RTN_U64, + DSOp.DS_SUB_RTN_U64: _DSOp_DS_SUB_RTN_U64, + DSOp.DS_RSUB_RTN_U64: _DSOp_DS_RSUB_RTN_U64, + DSOp.DS_INC_RTN_U64: _DSOp_DS_INC_RTN_U64, + DSOp.DS_DEC_RTN_U64: _DSOp_DS_DEC_RTN_U64, + DSOp.DS_MIN_RTN_I64: _DSOp_DS_MIN_RTN_I64, + DSOp.DS_MAX_RTN_I64: _DSOp_DS_MAX_RTN_I64, + DSOp.DS_MIN_RTN_U64: _DSOp_DS_MIN_RTN_U64, + DSOp.DS_MAX_RTN_U64: _DSOp_DS_MAX_RTN_U64, + DSOp.DS_AND_RTN_B64: _DSOp_DS_AND_RTN_B64, + DSOp.DS_OR_RTN_B64: _DSOp_DS_OR_RTN_B64, + DSOp.DS_XOR_RTN_B64: _DSOp_DS_XOR_RTN_B64, + DSOp.DS_MSKOR_RTN_B64: _DSOp_DS_MSKOR_RTN_B64, + DSOp.DS_STOREXCHG_RTN_B64: _DSOp_DS_STOREXCHG_RTN_B64, + DSOp.DS_STOREXCHG_2ADDR_RTN_B64: _DSOp_DS_STOREXCHG_2ADDR_RTN_B64, + DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64: _DSOp_DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64, + DSOp.DS_CMPSTORE_RTN_B64: _DSOp_DS_CMPSTORE_RTN_B64, + DSOp.DS_LOAD_B64: _DSOp_DS_LOAD_B64, + DSOp.DS_LOAD_2ADDR_B64: _DSOp_DS_LOAD_2ADDR_B64, + DSOp.DS_LOAD_2ADDR_STRIDE64_B64: _DSOp_DS_LOAD_2ADDR_STRIDE64_B64, + DSOp.DS_ADD_RTN_F32: _DSOp_DS_ADD_RTN_F32, + DSOp.DS_CONDXCHG32_RTN_B64: _DSOp_DS_CONDXCHG32_RTN_B64, + DSOp.DS_COND_SUB_U32: _DSOp_DS_COND_SUB_U32, + DSOp.DS_SUB_CLAMP_U32: _DSOp_DS_SUB_CLAMP_U32, + DSOp.DS_PK_ADD_F16: _DSOp_DS_PK_ADD_F16, + DSOp.DS_PK_ADD_BF16: _DSOp_DS_PK_ADD_BF16, + DSOp.DS_STORE_B8_D16_HI: _DSOp_DS_STORE_B8_D16_HI, + DSOp.DS_STORE_B16_D16_HI: _DSOp_DS_STORE_B16_D16_HI, + DSOp.DS_LOAD_U8_D16: _DSOp_DS_LOAD_U8_D16, + DSOp.DS_LOAD_U8_D16_HI: _DSOp_DS_LOAD_U8_D16_HI, + DSOp.DS_LOAD_I8_D16: _DSOp_DS_LOAD_I8_D16, + DSOp.DS_LOAD_I8_D16_HI: _DSOp_DS_LOAD_I8_D16_HI, + DSOp.DS_LOAD_U16_D16: _DSOp_DS_LOAD_U16_D16, + DSOp.DS_LOAD_U16_D16_HI: _DSOp_DS_LOAD_U16_D16_HI, + DSOp.DS_COND_SUB_RTN_U32: _DSOp_DS_COND_SUB_RTN_U32, + DSOp.DS_SUB_CLAMP_RTN_U32: _DSOp_DS_SUB_CLAMP_RTN_U32, + DSOp.DS_PK_ADD_RTN_F16: _DSOp_DS_PK_ADD_RTN_F16, + DSOp.DS_PK_ADD_RTN_BF16: _DSOp_DS_PK_ADD_RTN_BF16, + DSOp.DS_STORE_ADDTID_B32: _DSOp_DS_STORE_ADDTID_B32, + DSOp.DS_LOAD_ADDTID_B32: _DSOp_DS_LOAD_ADDTID_B32, + DSOp.DS_PERMUTE_B32: _DSOp_DS_PERMUTE_B32, + DSOp.DS_BPERMUTE_B32: _DSOp_DS_BPERMUTE_B32, + DSOp.DS_STORE_B96: _DSOp_DS_STORE_B96, + DSOp.DS_STORE_B128: _DSOp_DS_STORE_B128, + DSOp.DS_BVH_STACK_PUSH4_POP1_RTN_B32: _DSOp_DS_BVH_STACK_PUSH4_POP1_RTN_B32, + DSOp.DS_BVH_STACK_PUSH8_POP1_RTN_B32: _DSOp_DS_BVH_STACK_PUSH8_POP1_RTN_B32, + DSOp.DS_BVH_STACK_PUSH8_POP2_RTN_B64: _DSOp_DS_BVH_STACK_PUSH8_POP2_RTN_B64, + DSOp.DS_LOAD_B96: _DSOp_DS_LOAD_B96, + DSOp.DS_LOAD_B128: _DSOp_DS_LOAD_B128, +} + # V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode) def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0): @@ -6198,6 +7578,7 @@ COMPILED_FUNCTIONS = { VOP3SDOp: VOP3SDOp_FUNCTIONS, VOP3POp: VOP3POp_FUNCTIONS, VOPCOp: VOPCOp_FUNCTIONS, + DSOp: DSOp_FUNCTIONS, } def get_compiled_functions(): return COMPILED_FUNCTIONS \ No newline at end of file diff --git a/extra/assembly/amd/emu.py b/extra/assembly/amd/emu.py index 4e916604b4..0426594647 100644 --- a/extra/assembly/amd/emu.py +++ b/extra/assembly/amd/emu.py @@ -3,7 +3,7 @@ from __future__ import annotations import ctypes from extra.assembly.amd.dsl import Inst, unwrap, FLOAT_ENC, MASK32, MASK64, _f32, _i32, _sext, _f16, _i16, _f64, _i64 -from extra.assembly.amd.pcode import Reg +from extra.assembly.amd.pcode import Reg, LDSMem from extra.assembly.amd.asm import detect_format from extra.assembly.amd.autogen.rdna3.gen_pcode import get_compiled_functions from extra.assembly.amd.autogen.rdna3.ins import (SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, DS, FLAT, VOPD, @@ -51,11 +51,6 @@ _D16_LOAD_MAP = {'LOAD_D16_U8': (1,0,0), 'LOAD_D16_I8': (1,1,0), 'LOAD_D16_B16': _D16_STORE_MAP = {'STORE_D16_HI_B8': (1,1), 'STORE_D16_HI_B16': (2,1)} # (size, hi) FLAT_D16_LOAD = _mem_ops([GLOBALOp, FLATOp], _D16_LOAD_MAP) FLAT_D16_STORE = _mem_ops([GLOBALOp, FLATOp], _D16_STORE_MAP) -DS_LOAD = {DSOp.DS_LOAD_B32: (1,4,0), DSOp.DS_LOAD_B64: (2,4,0), DSOp.DS_LOAD_B128: (4,4,0), DSOp.DS_LOAD_U8: (1,1,0), DSOp.DS_LOAD_I8: (1,1,1), DSOp.DS_LOAD_U16: (1,2,0), DSOp.DS_LOAD_I16: (1,2,1)} -DS_STORE = {DSOp.DS_STORE_B32: (1,4), DSOp.DS_STORE_B64: (2,4), DSOp.DS_STORE_B128: (4,4), DSOp.DS_STORE_B8: (1,1), DSOp.DS_STORE_B16: (1,2)} -# 2ADDR ops: load/store two values using offset0 and offset1 -DS_LOAD_2ADDR = {DSOp.DS_LOAD_2ADDR_B32: 4, DSOp.DS_LOAD_2ADDR_B64: 8} -DS_STORE_2ADDR = {DSOp.DS_STORE_2ADDR_B32: 4, DSOp.DS_STORE_2ADDR_B64: 8} SMEM_LOAD = {SMEMOp.S_LOAD_B32: 1, SMEMOp.S_LOAD_B64: 2, SMEMOp.S_LOAD_B128: 4, SMEMOp.S_LOAD_B256: 8, SMEMOp.S_LOAD_B512: 16} # VOPD op -> VOP3 op mapping (VOPD is dual-issue of VOP1/VOP2 ops, use VOP3 enums for pseudocode lookup) @@ -225,31 +220,32 @@ def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = No return if isinstance(inst, DS): - op, addr0, vdst = inst.op, (V[inst.addr] + inst.offset0) & 0xffff, inst.vdst - if op in DS_LOAD: - cnt, sz, sign = DS_LOAD[op] - for i in range(cnt): val = int.from_bytes(lds[addr0+i*sz:addr0+i*sz+sz], 'little'); V[vdst + i] = _sext(val, sz * 8) & MASK32 if sign else val - elif op in DS_STORE: - cnt, sz = DS_STORE[op] - for i in range(cnt): lds[addr0+i*sz:addr0+i*sz+sz] = (V[inst.data0 + i] & ((1 << (sz * 8)) - 1)).to_bytes(sz, 'little') - elif op in DS_LOAD_2ADDR: - # Load two values from addr+offset0*sz and addr+offset1*sz into vdst (B32: 1 dword each, B64: 2 dwords each) - # Note: offsets are scaled by data size (4 for B32, 8 for B64) per AMD ISA - sz = DS_LOAD_2ADDR[op] - addr0 = (V[inst.addr] + inst.offset0 * sz) & 0xffff - addr1 = (V[inst.addr] + inst.offset1 * sz) & 0xffff - cnt = sz // 4 # 1 for B32, 2 for B64 - for i in range(cnt): V[vdst + i] = int.from_bytes(lds[addr0+i*4:addr0+i*4+4], 'little') - for i in range(cnt): V[vdst + cnt + i] = int.from_bytes(lds[addr1+i*4:addr1+i*4+4], 'little') - elif op in DS_STORE_2ADDR: - # Store two values from data0 and data1 to addr+offset0*sz and addr+offset1*sz - # Note: offsets are scaled by data size (4 for B32, 8 for B64) per AMD ISA - sz = DS_STORE_2ADDR[op] - addr0 = (V[inst.addr] + inst.offset0 * sz) & 0xffff - addr1 = (V[inst.addr] + inst.offset1 * sz) & 0xffff - cnt = sz // 4 - for i in range(cnt): lds[addr0+i*4:addr0+i*4+4] = (V[inst.data0 + i] & MASK32).to_bytes(4, 'little') - for i in range(cnt): lds[addr1+i*4:addr1+i*4+4] = (V[inst.data1 + i] & MASK32).to_bytes(4, 'little') + op, vdst = inst.op, inst.vdst + if DSOp in compiled and op in compiled[DSOp]: + fn = compiled[DSOp][op] + # For B64 operations, DATA/DATA2 access bits [63:32] so we need to pass 64-bit values + op_name = op.name + is_b64 = '_B64' in op_name or '_U64' in op_name or '_I64' in op_name or '_F64' in op_name + is_b128 = '_B128' in op_name + if is_b128: + s1 = Reg((V[inst.data0 + 3] << 96) | (V[inst.data0 + 2] << 64) | (V[inst.data0 + 1] << 32) | V[inst.data0]) + s2 = Reg((V[inst.data1 + 3] << 96) | (V[inst.data1 + 2] << 64) | (V[inst.data1 + 1] << 32) | V[inst.data1]) if inst.data1 else Reg(0) + elif is_b64: + s1 = Reg((V[inst.data0 + 1] << 32) | V[inst.data0]) + s2 = Reg((V[inst.data1 + 1] << 32) | V[inst.data1]) if inst.data1 else Reg(0) + else: + s1, s2 = Reg(V[inst.data0]), Reg(V[inst.data1] if inst.data1 else 0) + s0, mem = Reg(V[inst.addr]), LDSMem(lds) + result = fn(s0, s1, s2, Reg(V[vdst]), Reg(st.scc), Reg(st.vcc), lane, Reg(st.exec_mask), st.literal, None, + offset0=inst.offset0, offset1=inst.offset1, MEM=mem) + if 'D0' in result: V[vdst] = result['D0']._val & MASK32 + if 'RETURN_DATA' in result: + # RETURN_DATA can be multi-dword (up to 128 bits for B128 ops) + val = result['RETURN_DATA']._val + V[vdst] = val & MASK32 + V[vdst + 1] = (val >> 32) & MASK32 + V[vdst + 2] = (val >> 64) & MASK32 + V[vdst + 3] = (val >> 96) & MASK32 else: raise NotImplementedError(f"DS op {op}") return diff --git a/extra/assembly/amd/pcode.py b/extra/assembly/amd/pcode.py index 65e1193f68..151e34846b 100644 --- a/extra/assembly/amd/pcode.py +++ b/extra/assembly/amd/pcode.py @@ -212,7 +212,7 @@ def signext_from_bit(val, bit): __all__ = [ # Classes - 'Reg', 'SliceProxy', 'TypedView', + 'Reg', 'SliceProxy', 'TypedView', 'LDSMem', # Pack functions '_pack', '_pack32', 'pack', 'pack32', # Constants @@ -341,11 +341,42 @@ class _Denorm: f64 = _DenormChecker(64) DENORM = _Denorm() -def _brev(v, bits): - """Bit-reverse a value.""" - result = 0 - for i in range(bits): result |= ((v >> i) & 1) << (bits - 1 - i) - return result +# ═══════════════════════════════════════════════════════════════════════════════ +# LDS MEMORY ACCESS (for DS instructions) +# ═══════════════════════════════════════════════════════════════════════════════ + +class _LDSAccessor: + """Accessor for LDS memory at a specific address. Supports .u32/.f32 etc.""" + __slots__ = ('_lds', '_addr') + def __init__(self, lds: bytearray, addr: int): self._lds, self._addr = lds, addr & 0xffff + + def _read(self, size: int) -> int: + return int.from_bytes(self._lds[self._addr:self._addr+size], 'little') if self._addr + size <= len(self._lds) else 0 + def _write(self, size: int, val: int): + if self._addr + size <= len(self._lds): self._lds[self._addr:self._addr+size] = (int(val) & ((1 << (size*8)) - 1)).to_bytes(size, 'little') + + # Unsigned integer access + u8 = property(lambda s: s._read(1), lambda s, v: s._write(1, v)) + u16 = property(lambda s: s._read(2), lambda s, v: s._write(2, v)) + u32 = property(lambda s: s._read(4), lambda s, v: s._write(4, v)) + u64 = property(lambda s: s._read(8), lambda s, v: s._write(8, v)) + # Signed integer access + i8 = property(lambda s: _sext(s._read(1), 8), lambda s, v: s._write(1, v)) + i16 = property(lambda s: _sext(s._read(2), 16), lambda s, v: s._write(2, v)) + i32 = property(lambda s: _sext(s._read(4), 32), lambda s, v: s._write(4, v)) + i64 = property(lambda s: _sext(s._read(8), 64), lambda s, v: s._write(8, v)) + # Float access + f16 = property(lambda s: _f16(s._read(2)), lambda s, v: s._write(2, v if isinstance(v, int) else _i16(float(v)))) + f32 = property(lambda s: _f32(s._read(4)), lambda s, v: s._write(4, _i32(float(v)))) + f64 = property(lambda s: _f64(s._read(8)), lambda s, v: s._write(8, _i64(float(v)))) + # Bit/byte aliases + b8, b16, b32, b64 = u8, u16, u32, u64 + +class LDSMem: + """LDS memory wrapper that supports MEM[addr].u32 style access.""" + __slots__ = ('_lds',) + def __init__(self, lds: bytearray): self._lds = lds + def __getitem__(self, addr) -> _LDSAccessor: return _LDSAccessor(self._lds, int(addr)) class SliceProxy: """Proxy for D0[31:16] that supports .f16/.u16 etc getters and setters.""" @@ -473,10 +504,12 @@ class TypedView: @property def u32(s): return s if s._bits == 32 and not s._signed else int(s) & MASK32 +MASK128 = (1 << 128) - 1 + class Reg: - """GPU register: D0.f32 = S0.f32 + S1.f32 just works.""" + """GPU register: D0.f32 = S0.f32 + S1.f32 just works. Supports up to 128 bits for DS_LOAD_B128.""" __slots__ = ('_val',) - def __init__(self, val=0): self._val = int(val) & MASK64 + def __init__(self, val=0): self._val = int(val) & MASK128 # Typed views u64 = property(lambda s: TypedView(s, 64), lambda s, v: setattr(s, '_val', int(v) & MASK64)) diff --git a/extra/assembly/amd/pdf.py b/extra/assembly/amd/pdf.py index abd35022cd..51d05736d0 100644 --- a/extra/assembly/amd/pdf.py +++ b/extra/assembly/amd/pdf.py @@ -36,7 +36,7 @@ FIELD_ORDER = { SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'} FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO', '4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'} -INST_PATTERN = re.compile(r'^([SV]_[A-Z0-9_]+)\s+(\d+)\s*$', re.M) +INST_PATTERN = re.compile(r'^([SVD]S?_[A-Z0-9_]+)\s+(\d+)\s*$', re.M) # Patterns that can't be handled by the DSL (require special handling in emu.py) UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS', @@ -46,7 +46,7 @@ UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS', 'if n.', 'DST.u32', 'addrd = DST', 'addr = DST', 'BARRIER_STATE', 'ReallocVgprs', 'GPR_IDX', 'VSKIP', 'specified in', 'TTBL', - 'fp6', 'bf6'] # Malformed pseudocode from PDF + 'fp6', 'bf6', 'GS_REGS', 'M0.base', 'DS_DATA', '= 0..', 'sign(src', 'if no LDS', 'gds_base', 'vector mask'] # Malformed pseudocode from PDF # ═══════════════════════════════════════════════════════════════════════════════ # COMPILER: pseudocode -> Python (minimal transforms) @@ -68,8 +68,8 @@ def compile_pseudocode(pseudocode: str) -> str: lines = [] indent, need_pass, in_first_match_loop = 0, False, False for line in joined_lines: - line = line.strip() - if not line or line.startswith('//'): continue + line = line.split('//')[0].strip() # Strip C-style comments + if not line: continue if line.startswith('if '): lines.append(' ' * indent + f"if {_expr(line[3:].rstrip(' then'))}:") indent += 1 @@ -351,8 +351,9 @@ def _extract_pseudocode(text: str) -> str | None: for line in lines: s = line.strip() if not s or re.match(r'^\d+ of \d+$', s) or re.match(r'^\d+\.\d+\..*Instructions', s): continue - if s.startswith(('Notes', 'Functional examples')): break + if s.startswith(('Notes', 'Functional examples', '•', '-')): break # Stop at notes/bullets if s.startswith(('"RDNA', 'AMD ', 'CDNA')): continue + if '•' in s or '–' in s: continue # Skip lines with bullets/dashes if '= lambda(' in s: in_lambda += 1; continue if in_lambda > 0: if s.endswith(');'): in_lambda -= 1 @@ -362,7 +363,7 @@ def _extract_pseudocode(text: str) -> str | None: if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue is_code = (any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =', - 'D0[', 'D1[', 'S0[', 'S1[', 'S2[']) or + 'D0[', 'D1[', 'S0[', 'S1[', 'S2[', 'MEM[', 'RETURN_DATA']) or s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s)) if is_code: result.append(s) @@ -448,13 +449,13 @@ def _generate_gen_pcode_py(enums, pseudocode, arch) -> str: # Get op enums for this arch (import from .ins which re-exports from .enum) import importlib autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}.ins") - OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp'] if hasattr(autogen, name)] + OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp', 'DSOp'] if hasattr(autogen, name)] # Build defined ops mapping defined_ops: dict[tuple, list] = {} for enum_cls in OP_ENUMS: for op in enum_cls: - if op.name.startswith(('S_', 'V_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op)) + if op.name.startswith(('S_', 'V_', 'DS_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op)) enum_names = [e.__name__ for e in OP_ENUMS] lines = [f'''# autogenerated by pdf.py - do not edit @@ -541,11 +542,16 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str] is_cmpx = (cls_name in ('VOPCOp', 'VOP3Op')) and 'EXEC.u64[laneId]' in pc is_div_scale = 'DIV_SCALE' in op.name has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale) + is_ds = cls_name == 'DSOp' combined = code + pc fn_name = f"_{cls_name}_{op.name}" # Function accepts Reg objects directly (uppercase names), laneId is passed directly as int - lines = [f"def {fn_name}(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None):"] + # DSOp functions get additional MEM and offset parameters + if is_ds: + lines = [f"def {fn_name}(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None, MEM=None, offset0=0, offset1=0):"] + else: + lines = [f"def {fn_name}(S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None):"] # Registers that need special handling (not passed directly) # Only init if used but not first assigned as `name = Reg(...)` in the compiled code @@ -554,6 +560,11 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str] ('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)')] if needs_init('tmp'): special_regs.insert(0, ('tmp', 'Reg(0)')) if needs_init('saveexec'): special_regs.insert(0, ('saveexec', 'Reg(EXEC._val)')) + # DS ops: add ADDR, DATA, OFFSET, RETURN_DATA variables + if is_ds: + special_regs.extend([('ADDR', 'S0._val'), ('DATA', 'S1'), ('DATA0', 'S1'), ('DATA1', 'S2'), ('DATA2', 'S2'), + ('OFFSET', 'Reg(offset0)'), ('OFFSET0', 'Reg(offset0)'), ('OFFSET1', 'Reg(offset1)'), + ('RETURN_DATA', 'Reg(0)')]) used = {name for name, _ in special_regs if name in combined} # Detect which registers are modified (not just read) - look for assignments @@ -562,6 +573,8 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str] modifies_vcc = has_sdst or bool(re.search(r'VCC\.(u32|u64|b32|b64)\s*=|VCC\.u64\[laneId\]\s*=', combined)) modifies_scc = bool(re.search(r'\bSCC\s*=', combined)) modifies_pc = bool(re.search(r'\bPC\s*=', combined)) + # DS ops: detect memory writes (MEM[...] = ...) + modifies_mem = is_ds and bool(re.search(r'MEM\[.*\]\.[a-z0-9]+\s*=', combined)) # Build init code for special registers init_lines = [] @@ -587,6 +600,9 @@ def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str] if modifies_exec: result_items.append("'EXEC': EXEC") if has_d1: result_items.append("'D1': D1") if modifies_pc: result_items.append("'PC': PC") + # DS ops: return RETURN_DATA if it was set (matches RETURN_DATA.u32 = or RETURN_DATA[...] =) + if is_ds and 'RETURN_DATA' in combined and re.search(r'RETURN_DATA[\.\[].*=', combined): + result_items.append("'RETURN_DATA': RETURN_DATA") lines.append(f" return {{{', '.join(result_items)}}}\n") return fn_name, '\n'.join(lines) diff --git a/extra/assembly/amd/test/test_emu.py b/extra/assembly/amd/test/test_emu.py index e099aca931..b19514539d 100644 --- a/extra/assembly/amd/test/test_emu.py +++ b/extra/assembly/amd/test/test_emu.py @@ -4256,3 +4256,217 @@ class TestDS2Addr(unittest.TestCase): # v6,v7 from addr 8-15: 0x33333333, 0x44444444 self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should be 0x33333333") self.assertEqual(st.vgpr[0][7], 0x44444444, "v7 should be 0x44444444") + + +class TestDSAtomic(unittest.TestCase): + """Tests for DS atomic instructions (add, max, min, and, or, xor, cmpstore, etc.).""" + + def test_ds_max_rtn_u32(self): + """DS_MAX_RTN_U32: atomically store max(mem, data) and return old value.""" + instructions = [ + v_mov_b32_e32(v[10], 0), # addr = 0 + s_mov_b32(s[2], 100), + v_mov_b32_e32(v[0], s[2]), # initial value = 100 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 200), + v_mov_b32_e32(v[1], s[2]), # data = 200 (greater than 100) + ds_max_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), # read result + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 100, "v2 should have old value (100)") + self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200") + + def test_ds_max_u32_no_rtn(self): + """DS_MAX_U32 (no RTN): atomically store max, no return value.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 100), + v_mov_b32_e32(v[0], s[2]), # initial = 100 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 200), + v_mov_b32_e32(v[1], s[2]), # data = 200 + ds_max_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200") + + def test_ds_min_rtn_u32(self): + """DS_MIN_RTN_U32: atomically store min(mem, data) and return old value.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 200), + v_mov_b32_e32(v[0], s[2]), # initial = 200 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 100), + v_mov_b32_e32(v[1], s[2]), # data = 100 + ds_min_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 200, "v2 should have old value (200)") + self.assertEqual(st.vgpr[0][3], 100, "v3 should have min(200, 100) = 100") + + def test_ds_and_rtn_b32(self): + """DS_AND_RTN_B32: atomically AND mem with data and return old value.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 0xFF00FF00), + v_mov_b32_e32(v[0], s[2]), # initial = 0xFF00FF00 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 0xFFFF0000), + v_mov_b32_e32(v[1], s[2]), # data = 0xFFFF0000 + ds_and_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 0xFF00FF00, "v2 should have old value") + self.assertEqual(st.vgpr[0][3], 0xFF000000, "v3 should have 0xFF00FF00 & 0xFFFF0000 = 0xFF000000") + + def test_ds_or_rtn_b32(self): + """DS_OR_RTN_B32: atomically OR mem with data and return old value.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 0x00FF0000), + v_mov_b32_e32(v[0], s[2]), # initial = 0x00FF0000 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 0x000000FF), + v_mov_b32_e32(v[1], s[2]), # data = 0x000000FF + ds_or_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 0x00FF0000, "v2 should have old value") + self.assertEqual(st.vgpr[0][3], 0x00FF00FF, "v3 should have 0x00FF0000 | 0x000000FF = 0x00FF00FF") + + def test_ds_xor_rtn_b32(self): + """DS_XOR_RTN_B32: atomically XOR mem with data and return old value.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 0xAAAAAAAA), + v_mov_b32_e32(v[0], s[2]), # initial = 0xAAAAAAAA + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 0xFFFFFFFF), + v_mov_b32_e32(v[1], s[2]), # data = 0xFFFFFFFF + ds_xor_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA, "v2 should have old value") + self.assertEqual(st.vgpr[0][3], 0x55555555, "v3 should have 0xAAAAAAAA ^ 0xFFFFFFFF = 0x55555555") + + def test_ds_cmpstore_b32_match(self): + """DS_CMPSTORE_B32: conditional store when compare matches.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 100), + v_mov_b32_e32(v[0], s[2]), # initial = 100 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 200), + v_mov_b32_e32(v[1], s[2]), # new value = 200 + s_mov_b32(s[2], 100), + v_mov_b32_e32(v[2], s[2]), # compare = 100 (matches current) + ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[4], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][4], 200, "mem should be updated to 200 (compare matched)") + + def test_ds_cmpstore_b32_no_match(self): + """DS_CMPSTORE_B32: no store when compare doesn't match.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 100), + v_mov_b32_e32(v[0], s[2]), # initial = 100 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 200), + v_mov_b32_e32(v[1], s[2]), # new value = 200 + s_mov_b32(s[2], 50), + v_mov_b32_e32(v[2], s[2]), # compare = 50 (doesn't match 100) + ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[4], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][4], 100, "mem should still be 100 (compare didn't match)") + + def test_ds_inc_u32(self): + """DS_INC_U32: increment with wrap.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 5), + v_mov_b32_e32(v[0], s[2]), # initial = 5 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 10), + v_mov_b32_e32(v[1], s[2]), # limit = 10 + ds_inc_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 5, "v2 should have old value (5)") + self.assertEqual(st.vgpr[0][3], 6, "v3 should have incremented value (6)") + + def test_ds_dec_u32(self): + """DS_DEC_U32: decrement with wrap.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 5), + v_mov_b32_e32(v[0], s[2]), # initial = 5 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 10), + v_mov_b32_e32(v[1], s[2]), # limit = 10 + ds_dec_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 5, "v2 should have old value (5)") + self.assertEqual(st.vgpr[0][3], 4, "v3 should have decremented value (4)") + + def test_ds_dec_u32_wrap(self): + """DS_DEC_U32: wraps to limit when value is 0 or > limit.""" + instructions = [ + v_mov_b32_e32(v[10], 0), + s_mov_b32(s[2], 0), + v_mov_b32_e32(v[0], s[2]), # initial = 0 + ds_store_b32(addr=v[10], data0=v[0], offset0=0), + s_waitcnt(lgkmcnt=0), + s_mov_b32(s[2], 10), + v_mov_b32_e32(v[1], s[2]), # limit = 10 + ds_dec_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0), + s_waitcnt(lgkmcnt=0), + ds_load_b32(addr=v[10], vdst=v[3], offset0=0), + s_waitcnt(lgkmcnt=0), + ] + st = run_program(instructions, n_lanes=1) + self.assertEqual(st.vgpr[0][2], 0, "v2 should have old value (0)") + self.assertEqual(st.vgpr[0][3], 10, "v3 should wrap to limit (10)")