diff --git a/.github/workflows/autogen.yml b/.github/workflows/autogen.yml index 5a0517b942..1558178a3c 100644 --- a/.github/workflows/autogen.yml +++ b/.github/workflows/autogen.yml @@ -48,7 +48,7 @@ jobs: python3 -c "from tinygrad.runtime.autogen import opencl" python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv_580, nv" python3 -c "from tinygrad.runtime.autogen import comgr_3, hsa, hip, amd_gpu, sqtt, rocprof, amdgpu_kd, amdgpu_drm" - python3 -c "from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v13_0_6, smu_v13_0_12, smu_v14_0_2, fw" + python3 -c "from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v13_0_6, smu_v13_0_12, smu_v14_0_2, fw, navi_offsets, vega_offsets" python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio" python3 -c "from tinygrad.runtime.autogen import llvm" python3 -c "from tinygrad.runtime.autogen import webgpu" diff --git a/tinygrad/runtime/autogen/am/__init__.py b/tinygrad/runtime/autogen/am/__init__.py index 4027db1116..4212a12a89 100644 --- a/tinygrad/runtime/autogen/am/__init__.py +++ b/tinygrad/runtime/autogen/am/__init__.py @@ -34,4 +34,6 @@ def __getattr__(nm): for f in files if (p:=pathlib.Path(f)).is_file()] + ["}"]) return load("am/fw", ["{}/amdgpu/psp_*_sos.bin", "{}/amdgpu/smu_*.bin", "{}/amdgpu/sdma_*.bin"] + [f"{{}}/amdgpu/gc_*_{x}.bin" for x in ["pfp", "me", "mec", "imu", "rlc"]], srcs=fw_src, gen=genfw) + case "navi_offsets": return load("am/navi_offsets", [f"{AMD}/include/sienna_cichlid_ip_offset.h"], srcs=am_src) + case "vega_offsets": return load("am/vega_offsets", [f"{AMD}/include/vega20_ip_offset.h"], srcs=am_src) case _: raise AttributeError(f"no such autogen: {nm}") diff --git a/tinygrad/runtime/autogen/am/navi_offsets.py b/tinygrad/runtime/autogen/am/navi_offsets.py new file mode 100644 index 0000000000..021799563f --- /dev/null +++ b/tinygrad/runtime/autogen/am/navi_offsets.py @@ -0,0 +1,823 @@ +# mypy: disable-error-code="empty-body" +from __future__ import annotations +import ctypes +from typing import Literal, TypeAlias +from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR +from tinygrad.runtime.support import c +@c.record +class struct_IP_BASE_INSTANCE(c.Struct): + SIZE = 20 + segment: c.Array[ctypes.c_uint32, Literal[5]] +struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[5]], 0)]) +@c.record +class struct_IP_BASE(c.Struct): + SIZE = 140 + instance: c.Array[struct_IP_BASE_INSTANCE, Literal[7]] +struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[7]], 0)]) +MAX_INSTANCE = 7 +MAX_SEGMENT = 5 +ATHUB_BASE__INST0_SEG0 = 0x00000C00 +ATHUB_BASE__INST0_SEG1 = 0x02408C00 +ATHUB_BASE__INST0_SEG2 = 0 +ATHUB_BASE__INST0_SEG3 = 0 +ATHUB_BASE__INST0_SEG4 = 0 +ATHUB_BASE__INST1_SEG0 = 0 +ATHUB_BASE__INST1_SEG1 = 0 +ATHUB_BASE__INST1_SEG2 = 0 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+USB0_BASE__INST3_SEG4 = 0 +USB0_BASE__INST4_SEG0 = 0 +USB0_BASE__INST4_SEG1 = 0 +USB0_BASE__INST4_SEG2 = 0 +USB0_BASE__INST4_SEG3 = 0 +USB0_BASE__INST4_SEG4 = 0 +USB0_BASE__INST5_SEG0 = 0 +USB0_BASE__INST5_SEG1 = 0 +USB0_BASE__INST5_SEG2 = 0 +USB0_BASE__INST5_SEG3 = 0 +USB0_BASE__INST5_SEG4 = 0 +USB0_BASE__INST6_SEG0 = 0 +USB0_BASE__INST6_SEG1 = 0 +USB0_BASE__INST6_SEG2 = 0 +USB0_BASE__INST6_SEG3 = 0 +USB0_BASE__INST6_SEG4 = 0 +VCN_BASE__INST0_SEG0 = 0x00007800 +VCN_BASE__INST0_SEG1 = 0x00007E00 +VCN_BASE__INST0_SEG2 = 0x02403000 +VCN_BASE__INST0_SEG3 = 0 +VCN_BASE__INST0_SEG4 = 0 +VCN_BASE__INST1_SEG0 = 0x00007B00 +VCN_BASE__INST1_SEG1 = 0x00012000 +VCN_BASE__INST1_SEG2 = 0x02445000 +VCN_BASE__INST1_SEG3 = 0 +VCN_BASE__INST1_SEG4 = 0 +VCN_BASE__INST2_SEG0 = 0 +VCN_BASE__INST2_SEG1 = 0 +VCN_BASE__INST2_SEG2 = 0 +VCN_BASE__INST2_SEG3 = 0 +VCN_BASE__INST2_SEG4 = 0 +VCN_BASE__INST3_SEG0 = 0 +VCN_BASE__INST3_SEG1 = 0 +VCN_BASE__INST3_SEG2 = 0 +VCN_BASE__INST3_SEG3 = 0 +VCN_BASE__INST3_SEG4 = 0 +VCN_BASE__INST4_SEG0 = 0 +VCN_BASE__INST4_SEG1 = 0 +VCN_BASE__INST4_SEG2 = 0 +VCN_BASE__INST4_SEG3 = 0 +VCN_BASE__INST4_SEG4 = 0 +VCN_BASE__INST5_SEG0 = 0 +VCN_BASE__INST5_SEG1 = 0 +VCN_BASE__INST5_SEG2 = 0 +VCN_BASE__INST5_SEG3 = 0 +VCN_BASE__INST5_SEG4 = 0 +VCN_BASE__INST6_SEG0 = 0 +VCN_BASE__INST6_SEG1 = 0 +VCN_BASE__INST6_SEG2 = 0 +VCN_BASE__INST6_SEG3 = 0 +VCN_BASE__INST6_SEG4 = 0 \ No newline at end of file diff --git a/tinygrad/runtime/autogen/am/vega_offsets.py b/tinygrad/runtime/autogen/am/vega_offsets.py new file mode 100644 index 0000000000..673bff8720 --- /dev/null +++ b/tinygrad/runtime/autogen/am/vega_offsets.py @@ -0,0 +1,774 @@ +# mypy: disable-error-code="empty-body" +from __future__ import annotations +import ctypes +from typing import Literal, TypeAlias +from tinygrad.runtime.support.c import _IO, _IOW, _IOR, _IOWR +from tinygrad.runtime.support import c +@c.record +class struct_IP_BASE_INSTANCE(c.Struct): + SIZE = 24 + segment: c.Array[ctypes.c_uint32, Literal[6]] +struct_IP_BASE_INSTANCE.register_fields([('segment', c.Array[ctypes.c_uint32, Literal[6]], 0)]) +@c.record +class struct_IP_BASE(c.Struct): + SIZE = 144 + instance: c.Array[struct_IP_BASE_INSTANCE, Literal[6]] +struct_IP_BASE.register_fields([('instance', c.Array[struct_IP_BASE_INSTANCE, Literal[6]], 0)]) +MAX_INSTANCE = 6 +MAX_SEGMENT = 6 +ATHUB_BASE__INST0_SEG0 = 0x00000C20 +ATHUB_BASE__INST0_SEG1 = 0 +ATHUB_BASE__INST0_SEG2 = 0 +ATHUB_BASE__INST0_SEG3 = 0 +ATHUB_BASE__INST0_SEG4 = 0 +ATHUB_BASE__INST0_SEG5 = 0 +ATHUB_BASE__INST1_SEG0 = 0 +ATHUB_BASE__INST1_SEG1 = 0 +ATHUB_BASE__INST1_SEG2 = 0 +ATHUB_BASE__INST1_SEG3 = 0 +ATHUB_BASE__INST1_SEG4 = 0 +ATHUB_BASE__INST1_SEG5 = 0 +ATHUB_BASE__INST2_SEG0 = 0 +ATHUB_BASE__INST2_SEG1 = 0 +ATHUB_BASE__INST2_SEG2 = 0 +ATHUB_BASE__INST2_SEG3 = 0 +ATHUB_BASE__INST2_SEG4 = 0 +ATHUB_BASE__INST2_SEG5 = 0 +ATHUB_BASE__INST3_SEG0 = 0 +ATHUB_BASE__INST3_SEG1 = 0 +ATHUB_BASE__INST3_SEG2 = 0 +ATHUB_BASE__INST3_SEG3 = 0 +ATHUB_BASE__INST3_SEG4 = 0 +ATHUB_BASE__INST3_SEG5 = 0 +ATHUB_BASE__INST4_SEG0 = 0 +ATHUB_BASE__INST4_SEG1 = 0 +ATHUB_BASE__INST4_SEG2 = 0 +ATHUB_BASE__INST4_SEG3 = 0 +ATHUB_BASE__INST4_SEG4 = 0 +ATHUB_BASE__INST4_SEG5 = 0 +ATHUB_BASE__INST5_SEG0 = 0 +ATHUB_BASE__INST5_SEG1 = 0 +ATHUB_BASE__INST5_SEG2 = 0 +ATHUB_BASE__INST5_SEG3 = 0 +ATHUB_BASE__INST5_SEG4 = 0 +ATHUB_BASE__INST5_SEG5 = 0 +CLK_BASE__INST0_SEG0 = 0x00016C00 +CLK_BASE__INST0_SEG1 = 0x00016E00 +CLK_BASE__INST0_SEG2 = 0x00017000 +CLK_BASE__INST0_SEG3 = 0x00017200 +CLK_BASE__INST0_SEG4 = 0x0001B000 +CLK_BASE__INST0_SEG5 = 0x0001B200 +CLK_BASE__INST1_SEG0 = 0 +CLK_BASE__INST1_SEG1 = 0 +CLK_BASE__INST1_SEG2 = 0 +CLK_BASE__INST1_SEG3 = 0 +CLK_BASE__INST1_SEG4 = 0 +CLK_BASE__INST1_SEG5 = 0 +CLK_BASE__INST2_SEG0 = 0 +CLK_BASE__INST2_SEG1 = 0 +CLK_BASE__INST2_SEG2 = 0 +CLK_BASE__INST2_SEG3 = 0 +CLK_BASE__INST2_SEG4 = 0 +CLK_BASE__INST2_SEG5 = 0 +CLK_BASE__INST3_SEG0 = 0 +CLK_BASE__INST3_SEG1 = 0 +CLK_BASE__INST3_SEG2 = 0 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