testing cache

2023-08-01 19:02:22 -04:00
parent 2cfaaf32b9
commit b4d3dbc92a
1 changed files with 1 additions and 1 deletions
@@ -34,7 +34,7 @@ class ARM64Codegen(AssemblyCodegen):
          ins.append(f"movk w15, #{(value >> 16) & 0xffff}, lsl #16")
          ins.append(f"sxtw {to}, w15")
        else: 
-          #NOTE: value comes as int when it should be float
+          #NOTE: value == 0 but reg is 's' 
          ins.append(f"mov x15, #{('0x' + float_to_hex(value)) if to[0] == 's' else value}")
          ins.append(f"{'f' if to[0] == 's' else ''}mov {to}, {'w' if to[0] == 's' else 'x'}15")