ds compiled

assembly/amd: move more instructions to pcode
2025-12-31 15:43:44 -05:00 · 2025-12-31 15:42:59 -05:00
182 changed files with 27632 additions and 21911 deletions
@@ -14,12 +14,10 @@ on:
    paths:
    - 'tinygrad/runtime/autogen/**/*'
    - 'tinygrad/runtime/support/autogen.py'
-    - '.github/workflows/autogen.yml'
  workflow_dispatch:
    paths:
    - 'tinygrad/runtime/autogen/**/*'
    - 'tinygrad/runtime/support/autogen.py'
-    - '.github/workflows/autogen.yml'

 jobs:
  autogen:
@@ -41,45 +39,102 @@ jobs:
        pydeps: 'pyyaml mako'
    - name: Install autogen support packages
      run: sudo apt-get install -y --no-install-recommends libclang-20-dev llvm-20-dev hip-dev libusb-1.0-0-dev
-    - name: Regenerate autogen files
+    - name: Verify OpenCL autogen
      run: |
-        rm tinygrad/runtime/autogen/opencl.py
+        mv tinygrad/runtime/autogen/opencl.py /tmp/opencl.py.bak
        python3 -c "from tinygrad.runtime.autogen import opencl"
-        rm tinygrad/runtime/autogen/{cuda,nvrtc,nvjitlink,nv_570,nv}.py
-        python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv"
-        rm tinygrad/runtime/autogen/{comgr,hsa,hip,amd_gpu,sqtt,rocprof}.py
-        python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof"
-        rm tinygrad/runtime/autogen/am/{am,pm4_soc15,pm4_nv,sdma_4_0_0,sdma_5_0_0,sdma_6_0_0,smu_v13_0_0,smu_v14_0_2}.py
-        python3 -c "from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v14_0_2"
-        rm tinygrad/runtime/autogen/{libc,kfd,io_uring,ib,pci,vfio}.py
-        python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio"
-        rm tinygrad/runtime/autogen/llvm.py
-        python3 -c "from tinygrad.runtime.autogen import llvm"
-        rm tinygrad/runtime/autogen/webgpu.py
-        python3 -c "from tinygrad.runtime.autogen import webgpu"
-        rm tinygrad/runtime/autogen/{kgsl,qcom_dsp}.py
-        python3 -c "from tinygrad.runtime.autogen import kgsl, qcom_dsp"
-        rm tinygrad/runtime/autogen/libusb.py
-        python3 -c "from tinygrad.runtime.autogen import libusb"
-        rm tinygrad/runtime/autogen/mesa.py
-        python3 -c "from tinygrad.runtime.autogen import mesa"
-        rm tinygrad/runtime/autogen/avcodec.py
-        python3 -c "from tinygrad.runtime.autogen import avcodec"
-        REGEN=1 python3 -c "from tinygrad.runtime.autogen import libclang"
-    - name: Check for differences
+        diff /tmp/opencl.py.bak tinygrad/runtime/autogen/opencl.py
+    - name: Verify CUDA autogen
      run: |
-        if ! git diff --quiet; then
-          git diff > autogen-ubuntu.patch
-          echo "Autogen files out of date. Apply patch from: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}#artifacts"
-          exit 1
-        fi
-    - name: Upload patch artifact
-      if: failure()
-      uses: actions/upload-artifact@v4
-      with:
-        name: autogen-ubuntu-patch
-        path: autogen-ubuntu.patch
-
+        mv tinygrad/runtime/autogen/cuda.py /tmp/cuda.py.bak
+        mv tinygrad/runtime/autogen/nvrtc.py /tmp/nvrtc.py.bak
+        mv tinygrad/runtime/autogen/nvjitlink.py /tmp/nvjitlink.py.bak
+        mv tinygrad/runtime/autogen/nv_570.py /tmp/nv_570.py.bak
+        mv tinygrad/runtime/autogen/nv.py /tmp/nv.py.bak
+        python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv"
+        diff /tmp/cuda.py.bak tinygrad/runtime/autogen/cuda.py
+        diff /tmp/nvrtc.py.bak tinygrad/runtime/autogen/nvrtc.py
+        diff /tmp/nvjitlink.py.bak tinygrad/runtime/autogen/nvjitlink.py
+        diff /tmp/nv_570.py.bak tinygrad/runtime/autogen/nv_570.py
+        diff /tmp/nv.py.bak tinygrad/runtime/autogen/nv.py
+    - name: Verify AMD autogen
+      run: |
+        mv tinygrad/runtime/autogen/comgr.py /tmp/comgr.py.bak
+        mv tinygrad/runtime/autogen/hsa.py /tmp/hsa.py.bak
+        mv tinygrad/runtime/autogen/hip.py /tmp/hip.py.bak
+        mv tinygrad/runtime/autogen/amd_gpu.py /tmp/amd_gpu.py.bak
+        mv tinygrad/runtime/autogen/sqtt.py /tmp/sqtt.py.bak
+        mv tinygrad/runtime/autogen/rocprof.py /tmp/rocprof.py.bak
+        mv tinygrad/runtime/autogen/am/am.py /tmp/am_am.py.bak
+        mv tinygrad/runtime/autogen/am/pm4_soc15.py /tmp/am_pm4_soc15.py.bak
+        mv tinygrad/runtime/autogen/am/pm4_nv.py /tmp/am_pm4_nv.py.bak
+        mv tinygrad/runtime/autogen/am/sdma_4_0_0.py /tmp/am_sdma_4_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/sdma_5_0_0.py /tmp/am_sdma_5_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/sdma_6_0_0.py /tmp/am_sdma_6_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/smu_v13_0_0.py /tmp/am_smu_v13_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/smu_v14_0_2.py /tmp/am_smu_v14_0_2.py.bak
+        python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof; from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v14_0_2"
+        diff /tmp/comgr.py.bak tinygrad/runtime/autogen/comgr.py
+        diff /tmp/hsa.py.bak tinygrad/runtime/autogen/hsa.py
+        diff /tmp/hip.py.bak tinygrad/runtime/autogen/hip.py
+        diff /tmp/amd_gpu.py.bak tinygrad/runtime/autogen/amd_gpu.py
+        diff /tmp/sqtt.py.bak tinygrad/runtime/autogen/sqtt.py
+        diff /tmp/rocprof.py.bak tinygrad/runtime/autogen/rocprof.py
+        diff /tmp/am_am.py.bak tinygrad/runtime/autogen/am/am.py
+        diff /tmp/am_pm4_soc15.py.bak tinygrad/runtime/autogen/am/pm4_soc15.py
+        diff /tmp/am_pm4_nv.py.bak tinygrad/runtime/autogen/am/pm4_nv.py
+        diff /tmp/am_sdma_4_0_0.py.bak tinygrad/runtime/autogen/am/sdma_4_0_0.py
+        diff /tmp/am_sdma_5_0_0.py.bak tinygrad/runtime/autogen/am/sdma_5_0_0.py
+        diff /tmp/am_sdma_6_0_0.py.bak tinygrad/runtime/autogen/am/sdma_6_0_0.py
+        diff /tmp/am_smu_v13_0_0.py.bak tinygrad/runtime/autogen/am/smu_v13_0_0.py
+        diff /tmp/am_smu_v14_0_2.py.bak tinygrad/runtime/autogen/am/smu_v14_0_2.py
+    - name: Verify Linux autogen
+      run: |
+        mv tinygrad/runtime/autogen/libc.py /tmp/libc.py.bak
+        mv tinygrad/runtime/autogen/kfd.py /tmp/kfd.py.bak
+        mv tinygrad/runtime/autogen/io_uring.py /tmp/io_uring.py.bak
+        mv tinygrad/runtime/autogen/ib.py /tmp/ib.py.bak
+        mv tinygrad/runtime/autogen/pci.py /tmp/pci.py.bak
+        mv tinygrad/runtime/autogen/vfio.py /tmp/vfio.py.bak
+        python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio"
+        diff /tmp/libc.py.bak tinygrad/runtime/autogen/libc.py
+        diff /tmp/kfd.py.bak tinygrad/runtime/autogen/kfd.py
+        diff /tmp/io_uring.py.bak tinygrad/runtime/autogen/io_uring.py
+        diff /tmp/ib.py.bak tinygrad/runtime/autogen/ib.py
+        diff /tmp/pci.py.bak tinygrad/runtime/autogen/pci.py
+        diff /tmp/vfio.py.bak tinygrad/runtime/autogen/vfio.py
+    - name: Verify LLVM autogen
+      run: |
+        mv tinygrad/runtime/autogen/llvm.py /tmp/llvm.py.bak
+        python3 -c "from tinygrad.runtime.autogen import llvm"
+        diff /tmp/llvm.py.bak tinygrad/runtime/autogen/llvm.py
+    - name: Verify WebGPU autogen
+      run: |
+        mv tinygrad/runtime/autogen/webgpu.py /tmp/webgpu.py.bak
+        python3 -c "from tinygrad.runtime.autogen import webgpu"
+        diff /tmp/webgpu.py.bak tinygrad/runtime/autogen/webgpu.py
+    - name: Verify Qualcomm autogen
+      run: |
+        mv tinygrad/runtime/autogen/kgsl.py /tmp/kgsl.py.bak
+        mv tinygrad/runtime/autogen/qcom_dsp.py /tmp/qcom_dsp.py.bak
+        python3 -c "from tinygrad.runtime.autogen import kgsl, qcom_dsp"
+        diff /tmp/kgsl.py.bak tinygrad/runtime/autogen/kgsl.py
+        diff /tmp/qcom_dsp.py.bak tinygrad/runtime/autogen/qcom_dsp.py
+    - name: Verify libusb autogen
+      run: |
+        mv tinygrad/runtime/autogen/libusb.py /tmp/libusb.py.bak
+        python3 -c "from tinygrad.runtime.autogen import libusb"
+        diff /tmp/libusb.py.bak tinygrad/runtime/autogen/libusb.py
+    - name: Verify mesa autogen
+      run: |
+        mv tinygrad/runtime/autogen/mesa.py /tmp/mesa.py.bak
+        python3 -c "from tinygrad.runtime.autogen import mesa"
+        diff /tmp/mesa.py.bak tinygrad/runtime/autogen/mesa.py
+    - name: Verify libclang autogen
+      run: |
+        cp tinygrad/runtime/autogen/libclang.py /tmp/libclang.py.bak
+        REGEN=1 python3 -c "from tinygrad.runtime.autogen import libclang"
+        diff /tmp/libclang.py.bak tinygrad/runtime/autogen/libclang.py
  autogen-mac:
    name: In-tree Autogen (macos)
    runs-on: macos-14
@@ -91,24 +146,11 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        llvm: 'true'
-    - name: Regenerate autogen files
+    - name: Verify macos autogen
      run: |
-        rm tinygrad/runtime/autogen/metal.py
+        mv tinygrad/runtime/autogen/metal.py /tmp/metal.py.bak
        LIBCLANG_PATH=/opt/homebrew/opt/llvm@20/lib/libclang.dylib python3 -c "from tinygrad.runtime.autogen import metal"
-    - name: Check for differences
-      run: |
-        if ! git diff --quiet; then
-          git diff > autogen-macos.patch
-          echo "Autogen files out of date. Apply patch from: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}#artifacts"
-          exit 1
-        fi
-    - name: Upload patch artifact
-      if: failure()
-      uses: actions/upload-artifact@v4
-      with:
-        name: autogen-macos-patch
-        path: autogen-macos.patch
-
+        diff /tmp/metal.py.bak tinygrad/runtime/autogen/metal.py
  autogen-comgr-3:
    name: In-tree Autogen (comgr 3)
    runs-on: ubuntu-24.04
@@ -127,20 +169,8 @@ jobs:
        echo -e 'Package: *\nPin: release o=repo.radeon.com\nPin-Priority: 600' | sudo tee /etc/apt/preferences.d/rocm-pin-600
        sudo apt -qq update || true
        sudo apt-get install -y --no-install-recommends libclang-20-dev comgr
-    - name: Regenerate autogen files
+    - name: Verify comgr (3) autogen
      run: |
-        rm tinygrad/runtime/autogen/comgr_3.py
+        mv tinygrad/runtime/autogen/comgr_3.py /tmp/comgr_3.py.bak
        python3 -c "from tinygrad.runtime.autogen import comgr_3"
-    - name: Check for differences
-      run: |
-        if ! git diff --quiet; then
-          git diff > autogen-comgr3.patch
-          echo "Autogen files out of date. Apply patch from: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}#artifacts"
-          exit 1
-        fi
-    - name: Upload patch artifact
-      if: failure()
-      uses: actions/upload-artifact@v4
-      with:
-        name: autogen-comgr3-patch
-        path: autogen-comgr3.patch
+        diff /tmp/comgr_3.py.bak tinygrad/runtime/autogen/comgr_3.py
@@ -49,19 +49,19 @@ jobs:
    - name: Print macOS version
      run: sw_vers
    - name: Run Stable Diffusion
-      run: BENCHMARK_LOG=stable_diffusion JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    - name: Run Stable Diffusion without fp16
-      run: BENCHMARK_LOG=stable_diffusion_fp32 JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_fp32 JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --seed 0 --noshow --timing | tee sd_no_fp16.txt
    - name: Run Stable Diffusion v2
      # TODO: very slow step time
-      run: BENCHMARK_LOG=stable_diffusion_v2 JIT=1 ASSERT_MIN_STEP_TIME=4500 python3.11 examples/sdv2.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_v2 JIT=1 ASSERT_MIN_STEP_TIME=4500 python3.11 examples/sdv2.py --fp16 --seed 0 --noshow --timing | tee sdv2.txt
    # process replay can't capture this, the graph is too large
    - name: Run SDXL
-      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=5000 CAPTURE_PROCESS_REPLAY=0 JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=5000 CAPTURE_PROCESS_REPLAY=0 JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run model inference benchmark
      run: METAL=1 NOCLANG=1 python3.11 test/external/external_model_benchmark.py
    - name: Test speed vs torch
-      run: BIG=2 MPS=1 python3.11 test/speed/external_test_speed_v_torch.py
+      run: BIG=2 MPS=1 python3.11 test/speed/external_test_speed_v_torch.py | tee torch_speed.txt
    - name: Test tensor cores
      run: METAL=1 python3.11 test/opt/test_tensor_cores.py
    - name: Test AMX tensor cores
@@ -71,59 +71,84 @@ jobs:
        DEBUG=2 CPU=1 CPU_LLVM=0 AMX=1 python3.11 test/opt/test_gen_float4.py TestFloat4.test_float4_multidim_amx TestFloat4.test_float4_multidim_unaligned_load_amx
        DEBUG=2 CPU=1 CPU_LLVM=1 AMX=1 python3.11 test/opt/test_gen_float4.py TestFloat4.test_float4_multidim_amx TestFloat4.test_float4_multidim_unaligned_load_amx
    - name: Run Tensor Core GEMM (float)
-      run: DEBUG=2 SHOULD_USE_TC=1 python3.11 extra/gemm/simple_matmul.py
+      run: DEBUG=2 SHOULD_USE_TC=1 python3.11 extra/gemm/simple_matmul.py | tee matmul.txt
    - name: Run Tensor Core GEMM (half)
-      run: DEBUG=2 SHOULD_USE_TC=1 HALF=1 python3.11 extra/gemm/simple_matmul.py
+      run: DEBUG=2 SHOULD_USE_TC=1 HALF=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_half.txt
    - name: Run Tensor Core GEMM (bfloat16)
-      run: DEBUG=2 SHOULD_USE_TC=1 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py
+      run: DEBUG=2 SHOULD_USE_TC=1 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
    - name: Fuzz Padded Tensor Core GEMM
      run: METAL=1 M_START=6 M_STOP=10 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=6 K_STOP=24 K_STEP=1 TC_OPT=2 DEBUG=2 python3.11 ./extra/gemm/fuzz_matmul.py
    - name: Run LLaMA
      run: |
-        BENCHMARK_LOG=llama_nojit JIT=0 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=llama JIT=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=llama_nojit JIT=0 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
+        BENCHMARK_LOG=llama JIT=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt
    - name: Run LLaMA with BEAM
-      run: BENCHMARK_LOG=llama_beam JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=llama_beam JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt
    - name: Run quantized LLaMA
      run: |
-        BENCHMARK_LOG=llama_int8 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize int8
-        BENCHMARK_LOG=llama_nf4 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize nf4
+        BENCHMARK_LOG=llama_int8 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize int8 | tee llama_int8.txt
+        BENCHMARK_LOG=llama_nf4 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize nf4 | tee llama_nf4.txt
    - name: Run quantized LLaMA3
      run: |
-        BENCHMARK_LOG=llama3_int8 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize int8
-        BENCHMARK_LOG=llama3_nf4 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize nf4
+        BENCHMARK_LOG=llama3_int8 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize int8 | tee llama3_int8.txt
+        BENCHMARK_LOG=llama3_nf4 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize nf4 | tee llama3_nf4.txt
    #- name: Run LLaMA 7B on 4 (virtual) GPUs
-    #  run: python3.11 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing
+    #  run: python3.11 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    - name: Run GPT2
      run: |
-        BENCHMARK_LOG=gpt2_nojit JIT=0 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=gpt2 JIT=1 ASSERT_MIN_STEP_TIME=13 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=gpt2_nojit JIT=0 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt
+        BENCHMARK_LOG=gpt2 JIT=1 ASSERT_MIN_STEP_TIME=13 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt
    - name: Run GPT2 w HALF
-      run: BENCHMARK_LOG=gpt2_half HALF=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half HALF=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
-      run: BENCHMARK_LOG=gpt2_half_beam HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half_beam HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
    - name: Run OLMoE
      run: BENCHMARK_LOG=olmoe python3.11 examples/olmoe.py
    - name: Train MNIST
-      run: time PYTHONPATH=. TARGET_EVAL_ACC_PCT=96.0 python3.11 examples/beautiful_mnist.py
+      run: time PYTHONPATH=. TARGET_EVAL_ACC_PCT=96.0 python3.11 examples/beautiful_mnist.py | tee beautiful_mnist.txt

    # NOTE: this is failing in CI. it is not failing on my machine and I don't really have a way to debug it
    # the error is "RuntimeError: Internal Error (0000000e:Internal Error)"
    #- name: Run 10 CIFAR training steps
-    #  run: BENCHMARK_LOG=cifar_10steps JIT=1 ASSERT_MIN_STEP_TIME=3000 STEPS=10 python3.11 examples/hlb_cifar10.py
+    #  run: BENCHMARK_LOG=cifar_10steps JIT=1 ASSERT_MIN_STEP_TIME=3000 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar.txt
    #- name: Run 10 CIFAR training steps w HALF
-    #  run: BENCHMARK_LOG=cifar_10steps_half JIT=2 ASSERT_MIN_STEP_TIME=3000 STEPS=10 DEFAULT_FLOAT=HALF python3.11 examples/hlb_cifar10.py
+    #  run: BENCHMARK_LOG=cifar_10steps_half JIT=2 ASSERT_MIN_STEP_TIME=3000 STEPS=10 DEFAULT_FLOAT=HALF python3.11 examples/hlb_cifar10.py | tee train_cifar_half.txt

    #- name: Run 10 CIFAR training steps w BF16
-    #  run: STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3.11 examples/hlb_cifar10.py
+    #  run: STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3.11 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    # TODO: too slow
    # - name: Run 10 CIFAR training steps w winograd
-    #   run: BENCHMARK_LOG=cifar_10steps_wino JIT=1 ASSERT_MIN_STEP_TIME=150 WINO=1 STEPS=10 python3.11 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_wino JIT=1 ASSERT_MIN_STEP_TIME=150 WINO=1 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar_wino.txt
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (Mac)
        path: |
          onnx_inference_speed.csv
+          torch_speed.txt
+          llama_unjitted.txt
+          llama_jitted.txt
+          llama_beam.txt
+          llama_int8.txt
+          llama_nf4.txt
+          llama3_int8.txt
+          llama3_nf4.txt
+          llama_four_gpu.txt
+          gpt2_unjitted.txt
+          gpt2_jitted.txt
+          gpt2_half.txt
+          gpt2_half_beam.txt
+          matmul.txt
+          matmul_half.txt
+          matmul_bfloat16.txt
+          sd.txt
+          sd_no_fp16.txt
+          sdv2.txt
+          sdxl.txt
+          beautiful_mnist.txt
+          train_cifar.txt
+          train_cifar_half.txt
+          train_cifar_bf16.txt
+          train_cifar_wino.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3.11 process_replay.py

@@ -190,7 +215,7 @@ jobs:
    - name: Run model inference benchmark
      run: NV=1 CAPTURE_PROCESS_REPLAY=0 NOCLANG=1 python3 test/external/external_model_benchmark.py
    - name: Test speed vs torch
-      run: NV=1 CAPTURE_PROCESS_REPLAY=0 HALF=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py
+      run: NV=1 CAPTURE_PROCESS_REPLAY=0 HALF=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py | tee torch_speed.txt
    - name: Test speed vs theoretical
      run: NV=1 IGNORE_BEAM_CACHE=1 CCACHE=0 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20
    - name: Test benchmark allreduce
@@ -201,58 +226,79 @@ jobs:
        NV=1 NV_PTX=1 ALLOW_TF32=1 python3 test/opt/test_tensor_cores.py
    - name: Run Tensor Core GEMM (CUDA)
      run: |
-        CUDA=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
-        CUDA=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
-        CUDA=1 SHOULD_USE_TC=1 ALLOW_TF32=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py
-        CUDA=1 SHOULD_USE_TC=1 FP8E4M3=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
+        CUDA=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul.txt
+        CUDA=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
+        CUDA=1 SHOULD_USE_TC=1 ALLOW_TF32=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_tf32.txt
+        CUDA=1 SHOULD_USE_TC=1 FP8E4M3=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_fp8.txt
    - name: Run Tensor Core GEMM (PTX)
-      run: NV=1 NV_PTX=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
+      run: NV=1 NV_PTX=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_ptx.txt
    - name: Run Tensor Core GEMM (NV)
-      run: NV=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
+      run: NV=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_nv.txt
    - name: Test NV=1
      run: DEBUG=2 NV=1 python -m pytest -rA test/test_tiny.py
    - name: Test CUDA=1
      run: DEBUG=2 CUDA=1 python -m pytest -rA test/test_tiny.py
    - name: Run Stable Diffusion
-      run: BENCHMARK_LOG=stable_diffusion NV=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion NV=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    # TODO: too slow
    # - name: Run SDXL
-    #   run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=2000 CAPTURE_PROCESS_REPLAY=0 NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing
+    #   run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=2000 CAPTURE_PROCESS_REPLAY=0 NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run LLaMA
      run: |
-        BENCHMARK_LOG=llama_nojit NV=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=llama NV=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=llama_nojit NV=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
+        BENCHMARK_LOG=llama NV=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt
    - name: Run LLaMA with BEAM
-      run: BENCHMARK_LOG=llama_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=llama_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt
    # - name: Run LLaMA 7B on 4 GPUs
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    # - name: Run LLaMA 7B on 6 GPUs
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_six_gpu.txt
    - name: Run LLaMA-3 8B BEAM
-      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_beam.txt
    - name: Run LLaMA-3 8B on 4 GPUs with BEAM
-      run: BENCHMARK_LOG=llama3_beam_4gpu NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam_4gpu NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_four_gpu.txt
    - name: Run quantized LLaMA3
-      run: BENCHMARK_LOG=llama3_fp8 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --temperature 0 --benchmark --quantize fp8
+      run: BENCHMARK_LOG=llama3_fp8 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --temperature 0 --benchmark --quantize fp8 | tee llama3_fp8.txt
    # - name: Run LLaMA-3 8B on 6 GPUs
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_six_gpu.txt
    # - name: Run LLaMA-2 70B
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 MAX_CONTEXT=256 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 MAX_CONTEXT=256 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_2_70B.txt
    - name: Run Mixtral 8x7B
-      run: time BENCHMARK_LOG=mixtral NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/mixtral.py --temperature 0 --count 10 --timing
+      run: time BENCHMARK_LOG=mixtral NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/mixtral.py --temperature 0 --count 10 --timing | tee mixtral.txt
    - name: Run GPT2
      run: |
-        BENCHMARK_LOG=gpt2_nojit NV=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=gpt2 NV=1 JIT=1 ASSERT_MIN_STEP_TIME=4 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=gpt2_nojit NV=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt
+        BENCHMARK_LOG=gpt2 NV=1 JIT=1 ASSERT_MIN_STEP_TIME=4 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt
    - name: Run GPT2 w HALF
-      run: BENCHMARK_LOG=gpt2_half NV=1 HALF=1 ASSERT_MIN_STEP_TIME=6 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half NV=1 HALF=1 ASSERT_MIN_STEP_TIME=6 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
-      run: BENCHMARK_LOG=gpt2_half_beam NV=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half_beam NV=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (NVIDIA)
        path: |
          onnx_inference_speed.csv
+          torch_speed.txt
+          matmul.txt
+          matmul_bfloat16.txt
+          matmul_tf32.txt
+          matmul_ptx.txt
+          matmul_nv.txt
+          sd.txt
+          sdxl.txt
+          llama_unjitted.txt
+          llama_jitted.txt
+          llama_beam.txt
+          llama3_beam.txt
+          llama3_four_gpu.txt
+          llama3_six_gpu.txt
+          llama3_fp8.txt
+          llama_2_70B.txt
+          mixtral.txt
+          gpt2_unjitted.txt
+          gpt2_jitted.txt
+          gpt2_half.txt
+          gpt2_half_beam.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -291,30 +337,44 @@ jobs:
    # - name: Fuzz Padded Tensor Core GEMM (PTX)
    #   run: NV=1 NV_PTX=1 M_START=12 M_STOP=20 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=28 K_STOP=36 K_STEP=1 HALF=1 TC_OPT=2 python3 ./extra/gemm/fuzz_matmul.py
    - name: HEVC Decode Benchmark
-      run: VALIDATE=1 MAX_FRAMES=100 JITBEAM=1 NV=1 PYTHONPATH=. python3 extra/hevc/decode.py
+      run: VALIDATE=1 MAX_FRAMES=100 NV=1 PYTHONPATH=. python3 extra/hevc/decode.py
    - name: Train MNIST
-      run: time PYTHONPATH=. NV=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py
+      run: time PYTHONPATH=. NV=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py | tee beautiful_mnist.txt
    - name: Run 10 CIFAR training steps
-      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 python3 examples/hlb_cifar10.py | tee train_cifar.txt
    - name: Run 10 CIFAR training steps w HALF
-      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=110 NV=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=110 NV=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_half.txt
    - name: Run 10 CIFAR training steps w BF16
-      run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    # - name: Run 10 CIFAR training steps w winograd
-    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=350 NV=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=350 NV=1 CAPTURE_PROCESS_REPLAY=0 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_wino.txt
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_one_gpu.txt
    - name: Run full CIFAR training steps w 6 GPUS
-      run: time BENCHMARK_LOG=cifar_6gpu CAPTURE_PROCESS_REPLAY=0 NV=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar_6gpu CAPTURE_PROCESS_REPLAY=0 NV=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu.txt
    - name: Run MLPerf resnet eval on training data
      run: time BENCHMARK_LOG=resnet_eval NV=1 MODEL=resnet python3 examples/mlperf/model_eval.py
    - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-      run: BENCHMARK_LOG=resnet_10steps NV=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps NV=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet_one_gpu.txt
    - name: Run 10 MLPerf ResNet50 training steps (6 gpu)
-      run: BENCHMARK_LOG=resnet_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt
    - name: Run 10 MLPerf Bert training steps (6 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (NVIDIA Training)
+        path: |
+          beautiful_mnist.txt
+          train_cifar.txt
+          train_cifar_half.txt
+          train_cifar_bf16.txt
+          train_cifar_wino.txt
+          train_cifar_one_gpu.txt
+          train_cifar_six_gpu.txt
+          train_resnet.txt
+          train_resnet_one_gpu.txt
+          train_bert.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -366,7 +426,7 @@ jobs:
    #- name: Test speed vs torch
    #  run: |
    #    python3 -c "import torch; print(torch.__version__)"
-    #    LD_PRELOAD="/opt/rocm/lib/libhsa-runtime64.so" HSA=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py
+    #    LD_PRELOAD="/opt/rocm/lib/libhsa-runtime64.so" HSA=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py | tee torch_speed.txt
    - name: Test speed vs theoretical
      run: AMD=1 IGNORE_BEAM_CACHE=1 CCACHE=0 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20
    - name: Test tensor cores AMD_LLVM=0
@@ -377,7 +437,7 @@ jobs:
    - name: Run Tensor Core GEMM (AMD)
      run: |
        AMD=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
-        AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py
+        AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_amd.txt
    - name: Test AMD=1
      run: DEBUG=2 AMD=1 python -m pytest -rA test/test_tiny.py
    #- name: Test HIP=1
@@ -392,39 +452,61 @@ jobs:
    - name: Test AM warm start time
      run: time AMD=1 python3 test/test_tiny.py TestTiny.test_plus
    - name: Run Stable Diffusion
-      run: BENCHMARK_LOG=stable_diffusion ASSERT_MIN_STEP_TIME=550 AMD=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion ASSERT_MIN_STEP_TIME=550 AMD=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    - name: Run SDXL
-      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=3200 CAPTURE_PROCESS_REPLAY=0 AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=3200 CAPTURE_PROCESS_REPLAY=0 AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run LLaMA 7B
      run: |
-        BENCHMARK_LOG=llama_nojit AMD=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=llama AMD=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=llama_nojit AMD=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
+        BENCHMARK_LOG=llama AMD=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt
    - name: Run LLaMA 7B with BEAM
-      run: BENCHMARK_LOG=llama_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=llama_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt
    # - name: Run LLaMA 7B on 4 GPUs
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    # - name: Run LLaMA 7B on 6 GPUs
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_six_gpu.txt
    - name: Run LLaMA-3 8B BEAM
-      run: BENCHMARK_LOG=llama3_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_beam.txt
    - name: Run LLaMA-3 8B on 4 GPUs with BEAM
-      run: BENCHMARK_LOG=llama3_beam_4gpu AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam_4gpu AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_four_gpu.txt
    # - name: Run LLaMA-3 8B on 6 GPUs
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_six_gpu.txt
    #- name: Restore amdgpu
    #  run: sudo modprobe amdgpu
    # - name: Run LLaMA-2 70B
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_2_70B.txt
    - name: Run Mixtral 8x7B
-      run: time BENCHMARK_LOG=mixtral AMD=1 python3 examples/mixtral.py --temperature 0 --count 10 --timing
+      run: time BENCHMARK_LOG=mixtral AMD=1 python3 examples/mixtral.py --temperature 0 --count 10 --timing | tee mixtral.txt
    - name: Run GPT2
      run: |
-        BENCHMARK_LOG=gpt2_nojit AMD=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=gpt2 AMD=1 JIT=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=gpt2_nojit AMD=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt
+        BENCHMARK_LOG=gpt2 AMD=1 JIT=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt
    - name: Run GPT2 w HALF
-      run: BENCHMARK_LOG=gpt2_half AMD=1 HALF=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half AMD=1 HALF=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
-      run: BENCHMARK_LOG=gpt2_half_beam AMD=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half_beam AMD=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AMD)
+        path: |
+          onnx_inference_speed.csv
+          torch_speed.txt
+          llama_unjitted.txt
+          llama_jitted.txt
+          llama_beam.txt
+          llama3_beam.txt
+          llama3_four_gpu.txt
+          llama3_six_gpu.txt
+          llama_2_70B.txt
+          gpt2_unjitted.txt
+          gpt2_jitted.txt
+          gpt2_half.txt
+          gpt2_half_beam.txt
+          matmul.txt
+          matmul_amd.txt
+          sd.txt
+          sdxl.txt
+          mixtral.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -461,20 +543,31 @@ jobs:
    - name: reset process replay
      run: test/external/process_replay/reset.py
    - name: Train MNIST
-      run: time PYTHONPATH=. AMD=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py
+      run: time PYTHONPATH=. AMD=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py | tee beautiful_mnist.txt
    - name: Run 10 CIFAR training steps
-      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 python3 examples/hlb_cifar10.py | tee train_cifar.txt
    - name: Run 10 CIFAR training steps w HALF
-      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_half.txt
    # - name: Run 10 CIFAR training steps w BF16
-    #   run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=288 AMD=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=288 AMD=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    # TODO: too slow
    # - name: Run 10 CIFAR training steps w winograd
-    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=66 AMD=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=66 AMD=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_wino.txt
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_one_gpu.txt
    - name: Run full CIFAR training steps w 6 GPUS
-      run: time BENCHMARK_LOG=cifar_6gpu AMD=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar_6gpu AMD=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AMD Training)
+        path: |
+          beautiful_mnist.txt
+          train_cifar.txt
+          train_cifar_half.txt
+          train_cifar_bf16.txt
+          train_cifar_wino.txt
+          train_cifar_one_gpu.txt
+          train_cifar_six_gpu.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -513,12 +606,19 @@ jobs:
    - name: Run MLPerf resnet eval
      run: time BENCHMARK_LOG=resnet_eval AMD=1 MODEL=resnet python3 examples/mlperf/model_eval.py
    - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-      run: BENCHMARK_LOG=resnet_10steps AMD=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps AMD=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet_one_gpu.txt
    - name: Run 10 MLPerf ResNet50 training steps (6 gpu)
-      run: BENCHMARK_LOG=resnet_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt
    - name: Run 10 MLPerf Bert training steps (6 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AMD MLPerf)
+        path: |
+          train_resnet.txt
+          train_resnet_one_gpu.txt
+          train_bert.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -548,8 +648,6 @@ jobs:
      run: PYTHONPATH="." DEBUG=2 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: DEBUG=2 IMAGE=1 openpilot compile3 0.10.1 driving_vision
      run: PYTHONPATH="." DEBUG=2 DEV=QCOM FLOAT16=1 IMAGE=1 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
-    - name: IMAGE=1 openpilot compile3 0.10.1 driving_vision
-      run: BENCHMARK_LOG=image_1_openpilot_0_10_1_vision PYTHONPATH="." DEV=QCOM FLOAT16=1 IMAGE=1 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: openpilot compile3 0.10.1 driving_vision
      run: BENCHMARK_LOG=openpilot_0_10_1_vision PYTHONPATH="." ASSERT_MIN_STEP_TIME=17 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: openpilot compile3 0.10.1 driving_policy
@@ -610,7 +708,7 @@ jobs:
    #     AMD=1 AMD_LLVM=1 python3 test/test_linearizer.py test/opt/test_tensor_cores.py
    #     AMD=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
    - name: Run Tensor Core GEMM (AMD)
-      run: AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py
+      run: AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee am_matmul_amd.txt
    - name: Test AMD=1
      run: DEBUG=2 AMD=1 python -m pytest -rA test/test_tiny.py
    - name: Test DISK copy time
@@ -620,12 +718,20 @@ jobs:
        AMD=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyDefaulttoCPUJit
        AMD=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyCPUtoDefaultJit
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee am_train_cifar_one_gpu.txt
    # - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-    #   run: BENCHMARK_LOG=resnet_10steps AMD=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+    #   run: BENCHMARK_LOG=resnet_10steps AMD=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee am_train_resnet_one_gpu.txt
    - name: Run 10 MLPerf Bert training steps (1 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee am_train_bert_one_gpu.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AM Driver)
+        path: |
+          am_matmul_amd.txt
+          am_train_cifar_one_gpu.txt
+          am_train_resnet_one_gpu.txt
+          am_train_bert_one_gpu.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -672,13 +778,21 @@ jobs:
        NV=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyDefaulttoCPUJit
        NV=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyCPUtoDefaultJit
    - name: Test LLAMA-3
-      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --benchmark --temperature 0 | tee nv_llama3_beam.txt
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee nv_train_cifar_one_gpu.txt
    - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-      run: BENCHMARK_LOG=resnet_10steps NV=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps NV=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee nv_train_resnet_one_gpu.txt
    - name: Run 10 MLPerf Bert training steps (1 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee nv_train_bert_one_gpu.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (NV Driver)
+        path: |
+          nv_llama3_beam.txt
+          nv_train_cifar_one_gpu.txt
+          nv_train_resnet_one_gpu.txt
+          nv_train_bert_one_gpu.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py
@@ -218,6 +218,7 @@ jobs:
    runs-on: ubuntu-latest
    timeout-minutes: 10

+    # TODO: run the pre-commit hook to replace a lot of this
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -232,13 +233,13 @@ jobs:
    - name: Lint with ruff
      run: |
        pip3 install --upgrade --force-reinstall ruff==0.14.10
-        pre-commit run ruff --all-files
+        python3 -m ruff check .
        python3 -m ruff check examples/mlperf/ --ignore E501
        python3 -m ruff check extra/thunder/tiny/ --ignore E501 --ignore F841 --ignore E722
        python3 -m ruff check extra/torch_backend/backend.py
    - name: Run mypy
      run: |
-        python -m mypy --lineprecision-report .
+        python -m mypy --strict-equality --lineprecision-report .
        cat lineprecision.txt
    - name: Run TYPED=1
      run: TYPED=1 python -c "import tinygrad"
@@ -257,7 +258,6 @@ jobs:
        key: unittest-12
        pydeps: "pillow numpy ftfy regex"
        deps: testing_unit
-        llvm: 'true'
    - name: Check Device.DEFAULT
      run: python -c "from tinygrad import Device; assert Device.DEFAULT == 'CPU', Device.DEFAULT"
    - name: Run unit tests
@@ -310,7 +310,7 @@ jobs:
        deps: testing_unit
        python-version: '3.14'
    - name: Test SPEC=2
-      run: SPEC=2 pytest --maxfail=10 -n auto --durations=30 --ignore=test/models --ignore test/test_custom_kernel.py --ignore test/unit/test_hashing.py --ignore test/unit/test_autogen.py --timeout 60 -k "not test_setitem_big" --splits 2 --group ${{ matrix.group }}
+      run: SPEC=2 pytest --maxfail=10 -n auto --durations=30 --ignore=test/models --ignore test/test_custom_kernel.py --ignore test/unit/test_hashing.py --timeout 60 -k "not test_setitem_big" --splits 2 --group ${{ matrix.group }}

  fuzzing:
    name: Fuzzing
@@ -605,7 +605,9 @@ jobs:
        WEBGPU=1 DEBUG=4 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
    - name: Run selected webgpu tests
      run: |
-          WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
+          WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit \
+          --ignore=test/test_copy_speed.py --ignore=test/test_rearrange_einops.py \
+          --ignore=test/test_fuzz_shape_ops.py --durations=20
    - name: Run process replay tests
      uses: ./.github/actions/process-replay

@@ -667,11 +669,6 @@ jobs:
          key: rdna3-emu
          deps: testing_minimal
          amd: 'true'
-          python-version: '3.13'
-      - name: Verify AMD autogen is up to date
-        run: |
-          python -m extra.assembly.amd.pdf
-          git diff --exit-code extra/assembly/amd/autogen/
      - name: Install LLVM 21
        run: |
          wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key | sudo tee /etc/apt/trusted.gpg.d/apt.llvm.org.asc
@@ -680,8 +677,6 @@ jobs:
          sudo apt-get install llvm-21 llvm-21-tools cloc
      - name: RDNA3 Line Count
        run: cloc --by-file extra/assembly/amd/*.py
-      - name: Install rocprof-trace-decoder
-        run: sudo PYTHONPATH="." ./extra/sqtt/install_sqtt_decoder.py
      - name: Run RDNA3 emulator tests
        run: python -m pytest -n=auto extra/assembly/amd/ --durations 20
      - name: Run RDNA3 emulator tests (AMD_LLVM=1)
@@ -690,9 +685,23 @@ jobs:
        run: AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py
      - name: Run RDNA3 dtype tests (AMD_LLVM=1)
        run: AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py
-      # TODO: run all once emulator is faster
-      - name: Run RDNA3 ops tests
-        run: SKIP_SLOW_TEST=1 AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=auto test/test_ops.py -k "test_sparse_categorical_crossentropy or test_tril"
+
+  testamdautogen:
+    name: AMD autogen
+    runs-on: ubuntu-24.04
+    timeout-minutes: 10
+    steps:
+      - name: Checkout Code
+        uses: actions/checkout@v4
+      - name: Setup Environment
+        uses: ./.github/actions/setup-tinygrad
+        with:
+          key: rdna3-autogen
+          pydeps: "pdfplumber"
+      - name: Verify AMD autogen is up to date
+        run: |
+          python -m extra.assembly.amd.pdf --arch all
+          git diff --exit-code extra/assembly/amd/autogen/

  testnvidia:
    strategy:
@@ -781,8 +790,6 @@ jobs:
        ocelot: 'true'
        llvm: 'true'
    - name: Run unit tests
-      env:
-        LIBCLANG_PATH: '/opt/homebrew/opt/llvm@20/lib/libclang.dylib'
      run: METAL=1 python -m pytest -n=auto test/unit/ --durations=20
    - name: Run ONNX
      run: METAL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
@@ -16,7 +16,7 @@ repos:
        pass_filenames: false
      - id: mypy
        name: mypy
-        entry: python3 -m mypy
+        entry: python3 -m mypy tinygrad/ --strict-equality
        language: system
        always_run: true
        pass_filenames: false
@@ -192,12 +192,9 @@ When optimizing tinygrad internals:

 9. **Avoid creating intermediate objects in hot paths** - For example, `any(x.op in ops for x in self.backward_slice)` is faster than `any(x.op in ops for x in {self:None, **self.backward_slice})` because it avoids dict creation.

-## Pattern Matching Analysis
+## Pattern Matching Profiling

-**Use the right tool:**
-
- `TRACK_MATCH_STATS=2` - **Profiling**: identify expensive patterns
- `VIZ=-1` - **Inspection**: see all transformations, what every match pattern does, the before/after diffs
+Use `TRACK_MATCH_STATS=2` to identify expensive patterns:

 ```bash
 TRACK_MATCH_STATS=2 PYTHONPATH="." python3 test/external/external_benchmark_schedule.py
@@ -212,14 +209,6 @@ Key patterns to watch (from ResNet50 benchmark):

 Patterns with 0% match rate are workload-specific overhead. They may be useful in other workloads, so don't remove them without understanding their purpose.

-```bash
-# Save the trace
-VIZ=-1 python test/test_tiny.py TestTiny.test_gemm
-
-# Explore it
-./extra/viz/cli.py --help
-```
-
 ## AMD Performance Counter Profiling

 Set VIZ to `-2` to save performance counters traces for the AMD backend.
@@ -70,7 +70,7 @@ AMD backend supports several interfaces for communicating with devices:

 * `KFD`: uses the amdgpu driver
 * `PCI`: uses the [AM driver](developer/am.md)
-* `USB`: USB3 interface for asm24xx chips.
+* `USB`: USB3 interafce for asm24xx chips.

 You can force an interface by setting `AMD_IFACE` to one of these values. In the case of `AMD_IFACE=PCI`, this may unbind your GPU from the amdgpu driver.

@@ -213,13 +213,12 @@ class InterleavedDataset:
    self.queues[queue_index].queue.extend(load_file(file))

 # Reference: https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/run_pretraining.py, Line 394
-def batch_load_train_bert(BS:int, seed:int|None=None):
+def batch_load_train_bert(BS:int):
  from extra.datasets.wikipedia import get_wiki_train_files
-  rng = random.Random(seed)
  fs = sorted(get_wiki_train_files())
  train_files = []
  while fs: # TF shuffle
-    rng.shuffle(fs)
+    random.shuffle(fs)
    train_files.append(fs.pop(0))

  cycle_length = min(getenv("NUM_CPU_THREADS", min(os.cpu_count(), 8)), len(train_files))
@@ -219,18 +219,7 @@ def get_mlperf_bert_model():
  config = get_mlperf_bert_config()
  if getenv("DISABLE_DROPOUT", 0):
    config["hidden_dropout_prob"] = config["attention_probs_dropout_prob"] = 0.0
-  model = BertForPretraining(**config)
-  if getenv("FP8_TRAIN"):
-    from extra.fp8.fp8_linear import convert_to_float8_training
-    def module_filter_fn(mod, fqn):
-      if isinstance(mod, LinearBert):
-        skip_layers = [] if (ln:=config["num_hidden_layers"]) <= 2 else ["bert.encoder.layer.0.", f"bert.encoder.layer.{ln-1}"]
-        if mod.weight.shape[-1] >= 1024 and "encoder" in fqn and not any(name in fqn for name in skip_layers):
-          print(f"replacing linear with fp8: {fqn} {mod.weight.shape}")
-          return True
-      return False
-    convert_to_float8_training(model, module_filter_fn)
-  return model
+  return BertForPretraining(**config)

 def get_fake_data_bert(BS:int):
  return {
@@ -1008,7 +1008,6 @@ def train_bert():
  config["DISABLE_DROPOUT"] = getenv("DISABLE_DROPOUT", 0)
  config["TRAIN_BEAM"]    = TRAIN_BEAM = getenv("TRAIN_BEAM", BEAM.value)
  config["EVAL_BEAM"]     = EVAL_BEAM  = getenv("EVAL_BEAM", BEAM.value)
-  config["FP8_TRAIN"]     = getenv("FP8_TRAIN", 0)

  Tensor.manual_seed(seed)  # seed for weight initialization

@@ -1086,7 +1085,7 @@ def train_bert():
  if RUNMLPERF:
    # only load real data with RUNMLPERF
    eval_it = iter(batch_load_val_bert(EVAL_BS))
-    train_it = iter(tqdm(batch_load_train_bert(BS, seed=seed), total=train_steps, disable=BENCHMARK))
+    train_it = iter(tqdm(batch_load_train_bert(BS), total=train_steps, disable=BENCHMARK))
    for _ in range(start_step): next(train_it) # Fast forward
  else:
    # repeat fake data
@@ -1148,7 +1147,7 @@ def train_bert():

        device_str = parameters[0].device if isinstance(parameters[0].device, str) else f"{parameters[0].device[0]} * {len(parameters[0].device)}"
        loss = loss.item()
-        if not getenv("FP8_TRAIN"): assert not math.isnan(loss)
+        assert not math.isnan(loss)
        lr = lr.item()

      cl = time.perf_counter()
@@ -1161,7 +1160,7 @@ def train_bert():
      if WANDB:
        wandb.log({"lr": lr, "train/loss": loss, "train/global_norm": global_norm.item(), "train/step_time": cl - st,
                    "train/python_time": pt - st, "train/data_time": dt - pt, "train/cl_time": cl - dt,
-                    "train/mem":GlobalCounters.mem_used / 1e9, "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": (i+1)*GBS})
+                    "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": (i+1)*GBS})

      train_data, next_data = next_data, None
      i += 1
@@ -1,24 +0,0 @@
-#!/bin/bash
-
-export PYTHONPATH="." AMD=1
-export MODEL="bert"
-export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
-
-# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54
-export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
-export TRAIN_STEPS=3900
-
-export IGNORE_OOB=1
-export REWRITE_STACK_LIMIT=5000000
-
-export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
-export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
-export BASEDIR="/raid/datasets/wiki"
-export BEAM_TIMEOUT_SEC=15
-export FP8_TRAIN=1
-# search
-IGNORE_BEAM_CACHE=1 BENCHMARK=10 BERT_LAYERS=2 RUNMLPERF=0 python3 examples/mlperf/model_train.py
-
-export WANDB=1 PARALLEL=0
-
-RUNMLPERF=1 python3 examples/mlperf/model_train.py
@@ -7,7 +7,7 @@ if __name__ == "__main__":
  with open(fetch(sys.argv[1]), "rb") as f:
    run_onnx_jit = pickle.load(f)
  input_name = run_onnx_jit.captured.expected_names[0]
-  device = run_onnx_jit.captured.expected_input_info[0][-1]
+  device = run_onnx_jit.captured.expected_st_vars_dtype_device[0][-1]
  print(f"input goes into {input_name=} on {device=}")
  hit = 0
  for i,(img,y) in enumerate(imagenet_dataloader(cnt=getenv("CNT", 100))):
@@ -153,7 +153,8 @@ class SMICtx:
    tables = {}
    for dev in self.devs:
      match dev.ip_ver[am.MP1_HWIP]:
-        case (13,0,6)|(13,0,12): table_t = dev.smu.smu_mod.MetricsTableX_t
+        case (13,0,6): table_t = dev.smu.smu_mod.MetricsTableX_t
+        case (13,0,12): table_t = dev.smu.smu_mod.MetricsTableV2_t
        case _: table_t = dev.smu.smu_mod.SmuMetricsExternal_t
      tables[dev] = dev.smu.read_table(table_t, dev.smu.smu_mod.SMU_TABLE_SMU_METRICS) if dev.pci_state == "D0" else None
    return tables
@@ -164,17 +165,17 @@ class SMICtx:

  def get_gfx_activity(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return max(0, min(100, self._smuq10_round(metrics.SocketGfxBusy)))
+      case (13,0,6): return max(0, min(100, self._smuq10_round(metrics.SocketGfxBusy)))
      case _: return metrics.SmuMetrics.AverageGfxActivity

  def get_mem_activity(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return max(0, min(100, self._smuq10_round(metrics.DramBandwidthUtilization)))
+      case (13,0,6): return max(0, min(100, self._smuq10_round(metrics.DramBandwidthUtilization)))
      case _: return metrics.SmuMetrics.AverageUclkActivity

  def get_temps(self, dev, metrics, compact=False):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12):
+      case (13,0,6):
        temps = {
          "Hotspot": self._smuq10_round(metrics.MaxSocketTemperature),
          "HBM": self._smuq10_round(metrics.MaxHbmTemperature),
@@ -190,7 +191,7 @@ class SMICtx:

  def get_voltage(self, dev, metrics, compact=False):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return {}
+      case (13,0,6): return {}
      case _:
        voltage_keys = [(k, name) for k, name in dev.smu.smu_mod.SVI_PLANE_e.items()
                        if k < dev.smu.smu_mod.SVI_PLANE_COUNT and metrics.SmuMetrics.AvgVoltage[k] != 0]
@@ -204,33 +205,33 @@ class SMICtx:
  def get_gfx_freq(self, dev, metrics):
    if metrics is None: return 0
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.GfxclkFrequency[0])
+      case (13,0,6): return self._smuq10_round(metrics.GfxclkFrequency[0])
      case _:
        return metrics.SmuMetrics.AverageGfxclkFrequencyPostDs if self.get_gfx_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
               metrics.SmuMetrics.AverageGfxclkFrequencyPreDs

  def get_mem_freq(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.UclkFrequency)
+      case (13,0,6): return self._smuq10_round(metrics.UclkFrequency)
      case _:
        return metrics.SmuMetrics.AverageMemclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
               metrics.SmuMetrics.AverageMemclkFrequencyPreDs

  def get_fckl_freq(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.FclkFrequency)
+      case (13,0,6): return self._smuq10_round(metrics.FclkFrequency)
      case _:
        return metrics.SmuMetrics.AverageFclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
               metrics.SmuMetrics.AverageFclkFrequencyPreDs

  def get_fan_rpm_pwm(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return None, None
+      case (13,0,6): return None, None
      case _: return metrics.SmuMetrics.AvgFanRpm, metrics.SmuMetrics.AvgFanPwm

  def get_power(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.SocketPower), self._smuq10_round(metrics.MaxSocketPowerLimit)
+      case (13,0,6): return self._smuq10_round(metrics.SocketPower), self._smuq10_round(metrics.MaxSocketPowerLimit)
      case _: return metrics.SmuMetrics.AverageSocketPower, metrics.SmuMetrics.dGPU_W_MAX

  def get_mem_usage(self, dev):
@@ -3,16 +3,14 @@ An integrated environment for AMD GPU assembly and emulation
 Test with `PYTHONPATH="." pytest -n12 extra/assembly/amd/`
 `AMD_LLVM=1 PYTHONPATH="." pytest -n12 extra/assembly/amd/`

-* pdf.py -- extract assembly format + instruction pseudocode from AMD PDF
+* pdf.py -- extract assembly format + instruction psuedocode from AMD PDF
 * dsl.py -- helpers for the autogen instruction classes in `__init__.py`. should be standalone with init
-* pcode.py -- pseudocode execution environment. pseudocode should be transformed as little as possible.
+* pcode.py -- psuedocode execution environment. psuedocode should be transformed as little as possible.
 * asm.py -- an asm/disasm function to transform to and from AMD assembly syntax
 * emu.py -- an emulator for RDNA that runs in tinygrad with `AMD=1 MOCKGPU=1 PYTHON_REMU=1`

 The code should be as readable and deduplicated as possible. asm and emu shouldn't be required for dsl.

-The autogen folder is autogenerated from the AMD PDFs with `python3 -m extra.assembly.amd.pdf --arch all`
-
 test_emu.py has a good set of instruction tests for the emulation, with USE_HW=1 it will compare to real hardware.
 Whenever an instruction is fixed, regression tests should be added here and confirmed with real hardware.

@@ -28,12 +26,6 @@ The ops tests also pass, but they are very slow, so you should run them one at a
 `SKIP_SLOW_TEST=1 PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=12 test/test_ops.py`
 `SKIP_SLOW_TEST=1 PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=12 test/test_ops.py`

-When something is caught by main tinygrad tests, a local regression test should be added to `extra/assembly/amd/test`.
-While working with tinygrad, you can dump the assembly with `DEBUG=7`. These tests all pass on real hardware
-If a test is failing with `AMD=1 PYTHON_REMU=1 MOCKGPU=1` it's because an instruction is emulated incorrectly.
-You can test without `MOCKGPU=1` to test on real hardware, if it works on real hardware there's a bug in the emulator.
-IMPORTANT: if a test is failing in the emulator, it's an instruction bug. Use DEBUG=7, get the instructions, and debug.
-
-Currently, only RDNA3 is well supported, but when finished, this will support RDNA3+RDNA4+CDNA in ~2000 lines.
-Get line count with `cloc --by-file extra/assembly/amd/*.py`
+When something is caught by main tinygrad tests, a local regression test should be added to `extra/assembly/amd/test`. While working with tinygrad, you can dump the assembly with `DEBUG=7`. These tests all pass on real hardware, so if a test is failing with `AMD=1 PYTHON_REMU=1 MOCKGPU=1` it's likely because an instruction is emulated incorrectly. You can test without `MOCKGPU=1` to test on real hardware, if it works on real hardware there's a bug in the emulator.

+Currently, only RDNA3 is well supported, but when finished, this will support RDNA3+RDNA4+CDNA in ~2000 lines. Count lines with `cloc --by-file extra/assembly/amd/*.py`
@@ -1,32 +1,384 @@
-# RDNA3/RDNA4/CDNA assembler
+# RDNA3 assembler and disassembler
 from __future__ import annotations
 import re
-from extra.assembly.amd.dsl import RawImm, SrcMod, SGPR, VGPR, TTMP, s, v, ttmp, _RegFactory
+from extra.assembly.amd.dsl import Inst, RawImm, Reg, SrcMod, SGPR, VGPR, TTMP, s, v, ttmp, _RegFactory
 from extra.assembly.amd.dsl import VCC_LO, VCC_HI, VCC, EXEC_LO, EXEC_HI, EXEC, SCC, M0, NULL, OFF
-from extra.assembly.amd.dsl import FLOAT_ENC
+from extra.assembly.amd.dsl import SPECIAL_GPRS, SPECIAL_PAIRS, FLOAT_DEC, FLOAT_ENC, decode_src
 from extra.assembly.amd.autogen.rdna3 import ins
-from extra.assembly.amd.autogen.rdna3.ins import VOP2Op, VOPDOp, SOPKOp
-from extra.assembly.amd.autogen.rdna3.enum import BufFmt
-from extra.assembly.amd.autogen.rdna4 import ins as rdna4_ins
+from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, VOPD, VINTERP, SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, DS, FLAT, MUBUF, MTBUF, MIMG, EXP,
+  VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOPDOp, SOP1Op, SOPKOp, SOPPOp, SMEMOp, DSOp, MUBUFOp)

-# Re-export disasm for backwards compatibility
-from extra.assembly.amd.disasm import disasm, HWREG, HWREG_RDNA4
+def _matches_encoding(word: int, cls: type[Inst]) -> bool:
+  """Check if word matches the encoding pattern of an instruction class."""
+  if cls._encoding is None: return False
+  bf, val = cls._encoding
+  return ((word >> bf.lo) & bf.mask()) == val
+
+# Order matters: more specific encodings first, VOP2 last (it's a catch-all for bit31=0)
+_FORMATS_64 = [VOPD, VOP3P, VINTERP, VOP3, DS, FLAT, MUBUF, MTBUF, MIMG, SMEM, EXP]
+_FORMATS_32 = [SOP1, SOPC, SOPP, SOPK, VOPC, VOP1, SOP2, VOP2]  # SOP2/VOP2 are catch-alls
+
+def detect_format(data: bytes) -> type[Inst]:
+  """Detect instruction format from machine code bytes."""
+  assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}"
+  word = int.from_bytes(data[:4], 'little')
+  # Check 64-bit formats first (bits[31:30] == 0b11)
+  if (word >> 30) == 0b11:
+    for cls in _FORMATS_64:
+      if _matches_encoding(word, cls):
+        return VOP3SD if cls is VOP3 and ((word >> 16) & 0x3ff) in Inst._VOP3SD_OPS else cls
+    raise ValueError(f"unknown 64-bit format word={word:#010x}")
+  # 32-bit formats
+  for cls in _FORMATS_32:
+    if _matches_encoding(word, cls): return cls
+  raise ValueError(f"unknown 32-bit format word={word:#010x}")

 # ═══════════════════════════════════════════════════════════════════════════════
 # CONSTANTS
 # ═══════════════════════════════════════════════════════════════════════════════

-# RDNA unified buffer format
-BUF_FMT = {e.name: e.value for e in BufFmt}
-_BUF_FMT_EXT = {'BUF_FMT_32_32_32_32_SINT': 62, 'BUF_FMT_32_32_32_32_FLOAT': 63, 'BUF_FMT_8_FLOAT': 108}
-BUF_FMT.update(_BUF_FMT_EXT)
-def _parse_buf_fmt_combo(s: str) -> int:
-  parts = [p.strip().replace('BUF_DATA_FORMAT_', '').replace('BUF_NUM_FORMAT_', '') for p in s.split(',')]
-  return BUF_FMT.get(f'BUF_FMT_{parts[0]}_{parts[1]}') if len(parts) == 2 else None
+HWREG = {1: 'HW_REG_MODE', 2: 'HW_REG_STATUS', 3: 'HW_REG_TRAPSTS', 4: 'HW_REG_HW_ID', 5: 'HW_REG_GPR_ALLOC',
+         6: 'HW_REG_LDS_ALLOC', 7: 'HW_REG_IB_STS', 15: 'HW_REG_SH_MEM_BASES', 18: 'HW_REG_PERF_SNAPSHOT_PC_LO',
+         19: 'HW_REG_PERF_SNAPSHOT_PC_HI', 20: 'HW_REG_FLAT_SCR_LO', 21: 'HW_REG_FLAT_SCR_HI', 22: 'HW_REG_XNACK_MASK',
+         23: 'HW_REG_HW_ID1', 24: 'HW_REG_HW_ID2', 25: 'HW_REG_POPS_PACKER', 28: 'HW_REG_IB_STS2'}
+HWREG_IDS = {v.lower(): k for k, v in HWREG.items()}
+MSG = {128: 'MSG_RTN_GET_DOORBELL', 129: 'MSG_RTN_GET_DDID', 130: 'MSG_RTN_GET_TMA',
+       131: 'MSG_RTN_GET_REALTIME', 132: 'MSG_RTN_SAVE_WAVE', 133: 'MSG_RTN_GET_TBA'}
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# HELPERS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _reg(p: str, b: int, n: int = 1) -> str: return f"{p}{b}" if n == 1 else f"{p}[{b}:{b+n-1}]"
+def _sreg(b: int, n: int = 1) -> str: return _reg("s", b, n)
+def _vreg(b: int, n: int = 1) -> str: return _reg("v", b, n)
+def _ttmp(b: int, n: int = 1) -> str: return _reg("ttmp", b - 108, n) if 108 <= b <= 123 else None
+def _sreg_or_ttmp(b: int, n: int = 1) -> str: return _ttmp(b, n) or _sreg(b, n)
+
+def _fmt_sdst(v: int, n: int = 1) -> str:
+  if v == 124: return "null"
+  if t := _ttmp(v, n): return t
+  if n > 1: return SPECIAL_PAIRS.get(v) or _sreg(v, n)
+  return SPECIAL_GPRS.get(v, f"s{v}")
+
+def _fmt_src(v: int, n: int = 1) -> str:
+  if n == 1: return decode_src(v)
+  if v >= 256: return _vreg(v - 256, n)
+  if v <= 105: return _sreg(v, n)
+  if n == 2 and v in SPECIAL_PAIRS: return SPECIAL_PAIRS[v]
+  if t := _ttmp(v, n): return t
+  return decode_src(v)
+
+def _fmt_v16(v: int, base: int = 256, hi_thresh: int = 384) -> str:
+  return f"v{(v - base) & 0x7f}.{'h' if v >= hi_thresh else 'l'}"

 def waitcnt(vmcnt: int = 0x3f, expcnt: int = 0x7, lgkmcnt: int = 0x3f) -> int:
  return (expcnt & 0x7) | ((lgkmcnt & 0x3f) << 4) | ((vmcnt & 0x3f) << 10)

+def _has(op: str, *subs) -> bool: return any(s in op for s in subs)
+def _omod(v: int) -> str: return {1: " mul:2", 2: " mul:4", 3: " div:2"}.get(v, "")
+def _src16(inst, v: int) -> str: return _fmt_v16(v) if v >= 256 else inst.lit(v)  # format 16-bit src: vgpr.h/l or literal
+def _mods(*pairs) -> str: return " ".join(m for c, m in pairs if c)
+def _fmt_bits(label: str, val: int, count: int) -> str: return f"{label}:[{','.join(str((val >> i) & 1) for i in range(count))}]"
+
+def _vop3_src(inst, v: int, neg: int, abs_: int, hi: int, n: int, f16: bool, any_hi: bool) -> str:
+  """Format VOP3 source operand with modifiers."""
+  if n > 1: s = _fmt_src(v, n)
+  elif f16 and v >= 256: s = f"v{v - 256}.h" if hi else (f"v{v - 256}.l" if any_hi else inst.lit(v))
+  else: s = inst.lit(v)
+  if abs_: s = f"|{s}|"
+  return f"-{s}" if neg else s
+
+def _opsel_str(opsel: int, n: int, need: bool, is16_d: bool) -> str:
+  """Format op_sel modifier string."""
+  if not need: return ""
+  if is16_d and (opsel & 8): return f" op_sel:[1,1,1{',1' if n == 3 else ''}]"
+  if n == 3: return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1},{(opsel >> 3) & 1}]"
+  return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1}]"
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# DISASSEMBLER
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _disasm_vop1(inst: VOP1) -> str:
+  name = inst.op_name.lower()
+  if inst.op in (VOP1Op.V_NOP, VOP1Op.V_PIPEFLUSH): return name
+  if inst.op == VOP1Op.V_READFIRSTLANE_B32: return f"v_readfirstlane_b32 {decode_src(inst.vdst)}, v{inst.src0 - 256 if inst.src0 >= 256 else inst.src0}"
+  # 16-bit dst: uses .h/.l suffix (determined by name pattern, not dtype - e.g. sat_pk_u8_i16 outputs 8-bit but uses 16-bit encoding)
+  parts = name.split('_')
+  is_16d = any(p in ('f16','i16','u16','b16') for p in parts[-2:-1]) or (len(parts) >= 2 and parts[-1] in ('f16','i16','u16','b16') and 'cvt' not in name)
+  dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else _fmt_v16(inst.vdst, 0, 128) if is_16d else f"v{inst.vdst}"
+  src = _fmt_src(inst.src0, inst.src_regs(0)) if inst.src_regs(0) > 1 else _src16(inst, inst.src0) if inst.is_src_16(0) and 'sat_pk' not in name else inst.lit(inst.src0)
+  return f"{name}_e32 {dst}, {src}"
+
+def _disasm_vop2(inst: VOP2) -> str:
+  name = inst.op_name.lower()
+  suf = "" if inst.op == VOP2Op.V_DOT2ACC_F32_F16 else "_e32"
+  # fmaak: dst = src0 * vsrc1 + K, fmamk: dst = src0 * K + vsrc1
+  if inst.op in (VOP2Op.V_FMAAK_F32, VOP2Op.V_FMAAK_F16): return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}, 0x{inst._literal:x}"
+  if inst.op in (VOP2Op.V_FMAMK_F32, VOP2Op.V_FMAMK_F16): return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, 0x{inst._literal:x}, v{inst.vsrc1}"
+  if inst.is_16bit(): return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1, 0, 128)}"
+  return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}" + (", vcc_lo" if inst.op == VOP2Op.V_CNDMASK_B32 else "")
+
+def _disasm_vopc(inst: VOPC) -> str:
+  name = inst.op_name.lower()
+  s0 = _fmt_src(inst.src0, inst.src_regs(0)) if inst.src_regs(0) > 1 else _src16(inst, inst.src0) if inst.is_16bit() else inst.lit(inst.src0)
+  s1 = _vreg(inst.vsrc1, inst.src_regs(1)) if inst.src_regs(1) > 1 else _fmt_v16(inst.vsrc1, 0, 128) if inst.is_16bit() else f"v{inst.vsrc1}"
+  return f"{name}_e32 {s0}, {s1}" if inst.op.value >= 128 else f"{name}_e32 vcc_lo, {s0}, {s1}"
+
+NO_ARG_SOPP = {SOPPOp.S_ENDPGM, SOPPOp.S_BARRIER, SOPPOp.S_WAKEUP, SOPPOp.S_ICACHE_INV,
+               SOPPOp.S_WAIT_IDLE, SOPPOp.S_ENDPGM_SAVED, SOPPOp.S_CODE_END, SOPPOp.S_ENDPGM_ORDERED_PS_DONE}
+
+def _disasm_sopp(inst: SOPP) -> str:
+  name = inst.op_name.lower()
+  if inst.op in NO_ARG_SOPP: return name
+  if inst.op == SOPPOp.S_WAITCNT:
+    vm, exp, lgkm = (inst.simm16 >> 10) & 0x3f, inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x3f
+    p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0x3f else ""]
+    return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
+  if inst.op == SOPPOp.S_DELAY_ALU:
+    deps, skips = ['VALU_DEP_1','VALU_DEP_2','VALU_DEP_3','VALU_DEP_4','TRANS32_DEP_1','TRANS32_DEP_2','TRANS32_DEP_3','FMA_ACCUM_CYCLE_1','SALU_CYCLE_1','SALU_CYCLE_2','SALU_CYCLE_3'], ['SAME','NEXT','SKIP_1','SKIP_2','SKIP_3','SKIP_4']
+    id0, skip, id1 = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 7) & 0xf
+    dep = lambda v: deps[v-1] if 0 < v <= len(deps) else str(v)
+    p = [f"instid0({dep(id0)})" if id0 else "", f"instskip({skips[skip]})" if skip else "", f"instid1({dep(id1)})" if id1 else ""]
+    return f"s_delay_alu {' | '.join(x for x in p if x) or '0'}"
+  return f"{name} {inst.simm16}" if name.startswith(('s_cbranch', 's_branch')) else f"{name} 0x{inst.simm16:x}"
+
+def _disasm_smem(inst: SMEM) -> str:
+  name = inst.op_name.lower()
+  if inst.op in (SMEMOp.S_GL1_INV, SMEMOp.S_DCACHE_INV): return name
+  off_s = f"{decode_src(inst.soffset)} offset:0x{inst.offset:x}" if inst.offset and inst.soffset != 124 else f"0x{inst.offset:x}" if inst.offset else decode_src(inst.soffset)
+  sbase_idx, sbase_count = inst.sbase * 2, 4 if (8 <= inst.op.value <= 12 or name == 's_atc_probe_buffer') else 2
+  sbase_str = _fmt_src(sbase_idx, sbase_count) if sbase_count == 2 else _sreg(sbase_idx, sbase_count) if sbase_idx <= 105 else _reg("ttmp", sbase_idx - 108, sbase_count)
+  if name in ('s_atc_probe', 's_atc_probe_buffer'): return f"{name} {inst.sdata}, {sbase_str}, {off_s}"
+  return f"{name} {_fmt_sdst(inst.sdata, inst.dst_regs())}, {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (inst.dlc, " dlc"))
+
+def _disasm_flat(inst: FLAT) -> str:
+  name = inst.op_name.lower()
+  seg = ['flat', 'scratch', 'global'][inst.seg] if inst.seg < 3 else 'flat'
+  instr = f"{seg}_{name.split('_', 1)[1] if '_' in name else name}"
+  off_val = inst.offset if seg == 'flat' else (inst.offset if inst.offset < 4096 else inst.offset - 8192)
+  w = inst.dst_regs() * (2 if 'cmpswap' in name else 1)
+  mods = f"{f' offset:{off_val}' if off_val else ''}{' glc' if inst.glc else ''}{' slc' if inst.slc else ''}{' dlc' if inst.dlc else ''}"
+  # saddr
+  if seg == 'flat' or inst.saddr == 0x7F: saddr_s = ""
+  elif inst.saddr == 124: saddr_s = ", off"
+  elif seg == 'scratch': saddr_s = f", {decode_src(inst.saddr)}"
+  elif inst.saddr in SPECIAL_PAIRS: saddr_s = f", {SPECIAL_PAIRS[inst.saddr]}"
+  elif t := _ttmp(inst.saddr, 2): saddr_s = f", {t}"
+  else: saddr_s = f", {_sreg(inst.saddr, 2) if inst.saddr < 106 else decode_src(inst.saddr)}"
+  # addtid: no addr
+  if 'addtid' in name: return f"{instr} v{inst.data if 'store' in name else inst.vdst}{saddr_s}{mods}"
+  # addr width
+  addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(inst.addr, 1 if seg == 'scratch' or (inst.saddr not in (0x7F, 124)) else 2)
+  data_s, vdst_s = _vreg(inst.data, w), _vreg(inst.vdst, w // 2 if 'cmpswap' in name else w)
+  if 'atomic' in name:
+    return f"{instr} {vdst_s}, {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}" if inst.glc else f"{instr} {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}"
+  if 'store' in name: return f"{instr} {addr_s}, {data_s}{saddr_s}{mods}"
+  return f"{instr} {_vreg(inst.vdst, w)}, {addr_s}{saddr_s}{mods}"
+
+def _disasm_ds(inst: DS) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  gds = " gds" if inst.gds else ""
+  off = f" offset:{inst.offset0 | (inst.offset1 << 8)}" if inst.offset0 or inst.offset1 else ""
+  off2 = f" offset0:{inst.offset0} offset1:{inst.offset1}" if inst.offset0 or inst.offset1 else ""
+  w = inst.dst_regs()
+  d0, d1, dst, addr = _vreg(inst.data0, w), _vreg(inst.data1, w), _vreg(inst.vdst, w), f"v{inst.addr}"
+
+  if op == DSOp.DS_NOP: return name
+  if op == DSOp.DS_BVH_STACK_RTN_B32: return f"{name} v{inst.vdst}, {addr}, v{inst.data0}, {_vreg(inst.data1, 4)}{off}{gds}"
+  if 'gws_sema' in name and op != DSOp.DS_GWS_SEMA_BR: return f"{name}{off}{gds}"
+  if 'gws_' in name: return f"{name} {addr}{off}{gds}"
+  if op in (DSOp.DS_CONSUME, DSOp.DS_APPEND): return f"{name} v{inst.vdst}{off}{gds}"
+  if 'gs_reg' in name: return f"{name} {_vreg(inst.vdst, 2)}, v{inst.data0}{off}{gds}"
+  if '2addr' in name:
+    if 'load' in name: return f"{name} {_vreg(inst.vdst, w*2)}, {addr}{off2}{gds}"
+    if 'store' in name and 'xchg' not in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
+    return f"{name} {_vreg(inst.vdst, w*2)}, {addr}, {d0}, {d1}{off2}{gds}"
+  if 'load' in name: return f"{name} v{inst.vdst}{off}{gds}" if 'addtid' in name else f"{name} {dst}, {addr}{off}{gds}"
+  if 'store' in name and not _has(name, 'cmp', 'xchg'):
+    return f"{name} v{inst.data0}{off}{gds}" if 'addtid' in name else f"{name} {addr}, {d0}{off}{gds}"
+  if 'swizzle' in name or op == DSOp.DS_ORDERED_COUNT: return f"{name} v{inst.vdst}, {addr}{off}{gds}"
+  if 'permute' in name: return f"{name} v{inst.vdst}, {addr}, v{inst.data0}{off}{gds}"
+  if 'condxchg' in name: return f"{name} {_vreg(inst.vdst, 2)}, {addr}, {_vreg(inst.data0, 2)}{off}{gds}"
+  if _has(name, 'cmpstore', 'mskor', 'wrap'):
+    return f"{name} {dst}, {addr}, {d0}, {d1}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}, {d1}{off}{gds}"
+  return f"{name} {dst}, {addr}, {d0}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}{off}{gds}"
+
+def _disasm_vop3(inst: VOP3) -> str:
+  op, name = inst.op, inst.op_name.lower()
+
+  # VOP3SD (shared encoding)
+  if isinstance(op, VOP3SDOp):
+    sdst = (inst.clmp << 7) | (inst.opsel << 3) | inst.abs
+    def src(v, neg, n): s = _fmt_src(v, n) if n > 1 else inst.lit(v); return f"-{s}" if neg else s
+    s0, s1, s2 = src(inst.src0, inst.neg & 1, inst.src_regs(0)), src(inst.src1, inst.neg & 2, inst.src_regs(1)), src(inst.src2, inst.neg & 4, inst.src_regs(2))
+    dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else f"v{inst.vdst}"
+    srcs = f"{s0}, {s1}, {s2}" if inst.num_srcs() == 3 else f"{s0}, {s1}"
+    return f"{name} {dst}, {_fmt_sdst(sdst, 1)}, {srcs}" + _omod(inst.omod)
+
+  # Detect 16-bit operand sizes (for .h/.l suffix handling)
+  is16_d = is16_s = is16_s2 = False
+  if 'cvt_pk' in name: is16_s = name.endswith('16')
+  elif m := re.match(r'v_(?:cvt|frexp_exp)_([a-z0-9_]+)_([a-z0-9]+)', name):
+    is16_d, is16_s = _has(m.group(1), 'f16','i16','u16','b16'), _has(m.group(2), 'f16','i16','u16','b16')
+    is16_s2 = is16_s
+  elif re.match(r'v_mad_[iu]32_[iu]16', name): is16_s = True
+  elif 'pack_b32' in name: is16_s = is16_s2 = True
+  else: is16_d = is16_s = is16_s2 = inst.is_16bit()
+
+  any_hi = inst.opsel != 0
+  s0 = _vop3_src(inst, inst.src0, inst.neg&1, inst.abs&1, inst.opsel&1, inst.src_regs(0), is16_s, any_hi)
+  s1 = _vop3_src(inst, inst.src1, inst.neg&2, inst.abs&2, inst.opsel&2, inst.src_regs(1), is16_s, any_hi)
+  s2 = _vop3_src(inst, inst.src2, inst.neg&4, inst.abs&4, inst.opsel&4, inst.src_regs(2), is16_s2, any_hi)
+
+  # Destination
+  dn = inst.dst_regs()
+  if op == VOP3Op.V_READLANE_B32: dst = _fmt_sdst(inst.vdst, 1)
+  elif dn > 1: dst = _vreg(inst.vdst, dn)
+  elif is16_d: dst = f"v{inst.vdst}.h" if (inst.opsel & 8) else f"v{inst.vdst}.l" if any_hi else f"v{inst.vdst}"
+  else: dst = f"v{inst.vdst}"
+
+  cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
+  nonvgpr_opsel = (inst.src0 < 256 and (inst.opsel & 1)) or (inst.src1 < 256 and (inst.opsel & 2)) or (inst.src2 < 256 and (inst.opsel & 4))
+  need_opsel = nonvgpr_opsel or (inst.opsel and not is16_s)
+
+  if inst.op < 256:  # VOPC
+    return f"{name}_e64 {s0}, {s1}" if name.startswith('v_cmpx') else f"{name}_e64 {_fmt_sdst(inst.vdst, 1)}, {s0}, {s1}"
+  if inst.op < 384:  # VOP2
+    n = inst.num_srcs()
+    os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
+    return f"{name}_e64 {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name}_e64 {dst}, {s0}, {s1}{os}{cl}{om}"
+  if inst.op < 512:  # VOP1
+    return f"{name}_e64" if op in (VOP3Op.V_NOP, VOP3Op.V_PIPEFLUSH) else f"{name}_e64 {dst}, {s0}{_opsel_str(inst.opsel, 1, need_opsel, is16_d)}{cl}{om}"
+  # Native VOP3
+  n = inst.num_srcs()
+  os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
+  return f"{name} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{os}{cl}{om}"
+
+def _disasm_vop3sd(inst: VOP3SD) -> str:
+  name = inst.op_name.lower()
+  def src(v, neg, n): s = _fmt_src(v, n) if n > 1 else inst.lit(v); return f"-{s}" if neg else s
+  s0, s1, s2 = src(inst.src0, inst.neg & 1, inst.src_regs(0)), src(inst.src1, inst.neg & 2, inst.src_regs(1)), src(inst.src2, inst.neg & 4, inst.src_regs(2))
+  dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else f"v{inst.vdst}"
+  srcs = f"{s0}, {s1}, {s2}" if inst.num_srcs() == 3 else f"{s0}, {s1}"
+  suffix = "_e64" if name.startswith('v_') and 'co_' in name else ""
+  return f"{name}{suffix} {dst}, {_fmt_sdst(inst.sdst, 1)}, {srcs}{' clamp' if inst.clmp else ''}{_omod(inst.omod)}"
+
+def _disasm_vopd(inst: VOPD) -> str:
+  lit = inst._literal or inst.literal
+  vdst_y, nx, ny = (inst.vdsty << 1) | ((inst.vdstx & 1) ^ 1), VOPDOp(inst.opx).name.lower(), VOPDOp(inst.opy).name.lower()
+  def half(n, vd, s0, vs1): return f"{n} v{vd}, {inst.lit(s0)}{f', 0x{lit:x}' if lit and _has(n, 'fmaak', 'fmamk') else ''}" if 'mov' in n else f"{n} v{vd}, {inst.lit(s0)}, v{vs1}{f', 0x{lit:x}' if lit and _has(n, 'fmaak', 'fmamk') else ''}"
+  return f"{half(nx, inst.vdstx, inst.srcx0, inst.vsrcx1)} :: {half(ny, vdst_y, inst.srcy0, inst.vsrcy1)}"
+
+def _disasm_vop3p(inst: VOP3P) -> str:
+  name = inst.op_name.lower()
+  is_wmma, n, is_fma_mix = 'wmma' in name, inst.num_srcs(), 'fma_mix' in name
+  if is_wmma:
+    sc = 2 if 'iu4' in name else 4 if 'iu8' in name else 8
+    src0, src1, src2, dst = _fmt_src(inst.src0, sc), _fmt_src(inst.src1, sc), _fmt_src(inst.src2, 8), _vreg(inst.vdst, 8)
+  else: src0, src1, src2, dst = _fmt_src(inst.src0, 1), _fmt_src(inst.src1, 1), _fmt_src(inst.src2, 1), f"v{inst.vdst}"
+  opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
+  if is_fma_mix:
+    def m(s, neg, abs_): return f"-{f'|{s}|' if abs_ else s}" if neg else (f"|{s}|" if abs_ else s)
+    src0, src1, src2 = m(src0, inst.neg & 1, inst.neg_hi & 1), m(src1, inst.neg & 2, inst.neg_hi & 2), m(src2, inst.neg & 4, inst.neg_hi & 4)
+    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi else []) + (["clamp"] if inst.clmp else [])
+  else:
+    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != (7 if n == 3 else 3) else []) + \
+           ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if inst.clmp else [])
+  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
+
+def _disasm_buf(inst: MUBUF | MTBUF) -> str:
+  name = inst.op_name.lower()
+  if inst.op in (MUBUFOp.BUFFER_GL0_INV, MUBUFOp.BUFFER_GL1_INV): return name
+  w = (2 if _has(name, 'xyz', 'xyzw') else 1) if 'd16' in name else \
+      ((2 if _has(name, 'b64', 'u64', 'i64') else 1) * (2 if 'cmpswap' in name else 1)) if 'atomic' in name else \
+      {'b32':1,'b64':2,'b96':3,'b128':4,'b16':1,'x':1,'xy':2,'xyz':3,'xyzw':4}.get(name.split('_')[-1], 1)
+  if inst.tfe: w += 1
+  vaddr = _vreg(inst.vaddr, 2) if inst.offen and inst.idxen else f"v{inst.vaddr}" if inst.offen or inst.idxen else "off"
+  srsrc = _sreg_or_ttmp(inst.srsrc*4, 4)
+  mods = ([f"format:{inst.format}"] if isinstance(inst, MTBUF) else []) + [m for c, m in [(inst.idxen,"idxen"),(inst.offen,"offen"),(inst.offset,f"offset:{inst.offset}"),(inst.glc,"glc"),(inst.dlc,"dlc"),(inst.slc,"slc"),(inst.tfe,"tfe")] if c]
+  return f"{name} {_vreg(inst.vdata, w)}, {vaddr}, {srsrc}, {decode_src(inst.soffset)}{' ' + ' '.join(mods) if mods else ''}"
+
+def _mimg_vaddr_width(name: str, dim: int, a16: bool) -> int:
+  """Calculate vaddr register count for MIMG sample/gather operations."""
+  #                    1d,2d,3d,cube,1d_arr,2d_arr,2d_msaa,2d_msaa_arr
+  base =              [1, 2, 3, 3,   2,     3,     3,      4][dim]  # address coords
+  grad =              [1, 2, 3, 2,   1,     2,     2,      2][dim]  # gradient coords (for derivatives)
+  if 'get_resinfo' in name: return 1  # only mip level
+  packed, unpacked = 0, 0
+  if '_mip' in name: packed += 1
+  elif 'sample' in name or 'gather' in name:
+    if '_o' in name: unpacked += 1                                              # offset
+    if re.search(r'_c(_|$)', name): unpacked += 1                               # compare (not _cl)
+    if '_d' in name: unpacked += (grad + 1) & ~1 if '_g16' in name else grad*2  # derivatives
+    if '_b' in name: unpacked += 1                                              # bias
+    if '_l' in name and '_cl' not in name and '_lz' not in name: packed += 1    # LOD
+    if '_cl' in name: packed += 1                                               # clamp
+  return (base + packed + 1) // 2 + unpacked if a16 else base + packed + unpacked
+
+def _disasm_mimg(inst: MIMG) -> str:
+  name = inst.op_name.lower()
+  srsrc_base = inst.srsrc * 4
+  srsrc_str = _sreg_or_ttmp(srsrc_base, 8)
+  # BVH intersect ray: special case with 4 SGPR srsrc
+  if 'bvh' in name:
+    vaddr = (9 if '64' in name else 8) if inst.a16 else (12 if '64' in name else 11)
+    return f"{name} {_vreg(inst.vdata, 4)}, {_vreg(inst.vaddr, vaddr)}, {_sreg_or_ttmp(srsrc_base, 4)}{' a16' if inst.a16 else ''}"
+  # vdata width from dmask (gather4/msaa_load always 4), d16 packs, tfe adds 1
+  vdata = 4 if 'gather4' in name or 'msaa_load' in name else (bin(inst.dmask).count('1') or 1)
+  if inst.d16: vdata = (vdata + 1) // 2
+  if inst.tfe: vdata += 1
+  # vaddr width
+  dim_names = ['1d', '2d', '3d', 'cube', '1d_array', '2d_array', '2d_msaa', '2d_msaa_array']
+  dim = dim_names[inst.dim] if inst.dim < len(dim_names) else f"dim_{inst.dim}"
+  vaddr = _mimg_vaddr_width(name, inst.dim, inst.a16)
+  vaddr_str = f"v{inst.vaddr}" if vaddr == 1 else _vreg(inst.vaddr, vaddr)
+  # modifiers
+  mods = [f"dmask:0x{inst.dmask:x}"] if inst.dmask and (inst.dmask != 15 or 'atomic' in name) else []
+  mods.append(f"dim:SQ_RSRC_IMG_{dim.upper()}")
+  for flag, mod in [(inst.unrm,"unorm"),(inst.glc,"glc"),(inst.slc,"slc"),(inst.dlc,"dlc"),(inst.r128,"r128"),
+                    (inst.a16,"a16"),(inst.tfe,"tfe"),(inst.lwe,"lwe"),(inst.d16,"d16")]:
+    if flag: mods.append(mod)
+  # ssamp for sample/gather/get_lod
+  ssamp_str = ""
+  if 'sample' in name or 'gather' in name or 'get_lod' in name:
+    ssamp_str = ", " + _sreg_or_ttmp(inst.ssamp * 4, 4)
+  return f"{name} {_vreg(inst.vdata, vdata)}, {vaddr_str}, {srsrc_str}{ssamp_str} {' '.join(mods)}"
+
+def _disasm_sop1(inst: SOP1) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  if op == SOP1Op.S_GETPC_B64: return f"{name} {_fmt_sdst(inst.sdst, 2)}"
+  if op in (SOP1Op.S_SETPC_B64, SOP1Op.S_RFE_B64): return f"{name} {_fmt_src(inst.ssrc0, 2)}"
+  if op == SOP1Op.S_SWAPPC_B64: return f"{name} {_fmt_sdst(inst.sdst, 2)}, {_fmt_src(inst.ssrc0, 2)}"
+  if op in (SOP1Op.S_SENDMSG_RTN_B32, SOP1Op.S_SENDMSG_RTN_B64): return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, sendmsg({MSG.get(inst.ssrc0, str(inst.ssrc0))})"
+  return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, {inst.lit(inst.ssrc0) if inst.src_regs(0) == 1 else _fmt_src(inst.ssrc0, inst.src_regs(0))}"
+
+def _disasm_sop2(inst: SOP2) -> str:
+  return f"{inst.op_name.lower()} {_fmt_sdst(inst.sdst, inst.dst_regs())}, {inst.lit(inst.ssrc0) if inst.ssrc0 == 255 else _fmt_src(inst.ssrc0, inst.src_regs(0))}, {inst.lit(inst.ssrc1) if inst.ssrc1 == 255 else _fmt_src(inst.ssrc1, inst.src_regs(1))}"
+
+def _disasm_sopc(inst: SOPC) -> str:
+  return f"{inst.op_name.lower()} {_fmt_src(inst.ssrc0, inst.src_regs(0))}, {_fmt_src(inst.ssrc1, inst.src_regs(1))}"
+
+def _disasm_sopk(inst: SOPK) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  if op == SOPKOp.S_VERSION: return f"{name} 0x{inst.simm16:x}"
+  if op in (SOPKOp.S_SETREG_B32, SOPKOp.S_GETREG_B32):
+    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
+    hs = f"0x{inst.simm16:x}" if hid in (16, 17) else f"hwreg({HWREG.get(hid, str(hid))}, {hoff}, {hsz})"
+    return f"{name} {hs}, {_fmt_sdst(inst.sdst, 1)}" if op == SOPKOp.S_SETREG_B32 else f"{name} {_fmt_sdst(inst.sdst, 1)}, {hs}"
+  return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, 0x{inst.simm16:x}"
+
+def _disasm_vinterp(inst: VINTERP) -> str:
+  mods = _mods((inst.waitexp, f"wait_exp:{inst.waitexp}"), (inst.clmp, "clamp"))
+  return f"{inst.op_name.lower()} v{inst.vdst}, {inst.lit(inst.src0, inst.neg & 1)}, {inst.lit(inst.src1, inst.neg & 2)}, {inst.lit(inst.src2, inst.neg & 4)}" + (" " + mods if mods else "")
+
+DISASM_HANDLERS = {VOP1: _disasm_vop1, VOP2: _disasm_vop2, VOPC: _disasm_vopc, VOP3: _disasm_vop3, VOP3SD: _disasm_vop3sd, VOPD: _disasm_vopd, VOP3P: _disasm_vop3p,
+                   VINTERP: _disasm_vinterp, SOPP: _disasm_sopp, SMEM: _disasm_smem, DS: _disasm_ds, FLAT: _disasm_flat, MUBUF: _disasm_buf, MTBUF: _disasm_buf,
+                   MIMG: _disasm_mimg, SOP1: _disasm_sop1, SOP2: _disasm_sop2, SOPC: _disasm_sopc, SOPK: _disasm_sopk}
+
+def disasm(inst: Inst) -> str: return DISASM_HANDLERS[type(inst)](inst)
+
 # ═══════════════════════════════════════════════════════════════════════════════
 # ASSEMBLER
 # ═══════════════════════════════════════════════════════════════════════════════
@@ -35,11 +387,8 @@ SPEC_REGS = {'vcc_lo': RawImm(106), 'vcc_hi': RawImm(107), 'vcc': RawImm(106), '
             'exec_lo': RawImm(126), 'exec_hi': RawImm(127), 'exec': RawImm(126), 'scc': RawImm(253), 'src_scc': RawImm(253)}
 FLOATS = {str(k): k for k in FLOAT_ENC}  # Valid float literal strings: '0.5', '-0.5', '1.0', etc.
 REG_MAP: dict[str, _RegFactory] = {'s': s, 'v': v, 't': ttmp, 'ttmp': ttmp}
-SMEM_OPS = {'s_load_b32', 's_load_b64', 's_load_b96', 's_load_b128', 's_load_b256', 's_load_b512',
-            's_load_i8', 's_load_u8', 's_load_i16', 's_load_u16',
-            's_buffer_load_b32', 's_buffer_load_b64', 's_buffer_load_b96', 's_buffer_load_b128', 's_buffer_load_b256', 's_buffer_load_b512',
-            's_buffer_load_i8', 's_buffer_load_u8', 's_buffer_load_i16', 's_buffer_load_u16',
-            's_atc_probe', 's_atc_probe_buffer'}
+SMEM_OPS = {'s_load_b32', 's_load_b64', 's_load_b128', 's_load_b256', 's_load_b512',
+            's_buffer_load_b32', 's_buffer_load_b64', 's_buffer_load_b128', 's_buffer_load_b256', 's_buffer_load_b512'}
 SPEC_DSL = {'vcc_lo': 'VCC_LO', 'vcc_hi': 'VCC_HI', 'vcc': 'VCC_LO', 'null': 'NULL', 'off': 'OFF', 'm0': 'M0',
            'exec_lo': 'EXEC_LO', 'exec_hi': 'EXEC_HI', 'exec': 'EXEC_LO', 'scc': 'SCC', 'src_scc': 'SCC'}

@@ -47,7 +396,6 @@ def _op2dsl(op: str) -> str:
  op = op.strip()
  neg = op.startswith('-') and not (op[1:2].isdigit() or (len(op) > 2 and op[1] == '0' and op[2] in 'xX'))
  if neg: op = op[1:]
-  if op.startswith('neg(') and op.endswith(')'): neg = True; op = op[4:-1]
  abs_ = (op.startswith('|') and op.endswith('|')) or (op.startswith('abs(') and op.endswith(')'))
  if abs_: op = op[1:-1] if op.startswith('|') else op[4:-1]
  hi = ".h" if op.endswith('.h') else ".l" if op.endswith('.l') else ""
@@ -74,99 +422,29 @@ def _parse_ops(s: str) -> list[str]:
  return ops

 def _extract(text: str, pat: str, flags=re.I):
-  if m := re.search(pat, text, flags): return m, text[:m.start()] + ' ' + text[m.end():]
+  if m := re.search(pat, text, flags): return m, text[:m.start()] + text[m.end():]
  return None, text

-# Instruction aliases: LLVM uses different names for some instructions
-_ALIASES = {
-  'v_cmp_tru_f16': 'v_cmp_t_f16', 'v_cmp_tru_f32': 'v_cmp_t_f32', 'v_cmp_tru_f64': 'v_cmp_t_f64',
-  'v_cmpx_tru_f16': 'v_cmpx_t_f16', 'v_cmpx_tru_f32': 'v_cmpx_t_f32', 'v_cmpx_tru_f64': 'v_cmpx_t_f64',
-  'v_cvt_flr_i32_f32': 'v_cvt_floor_i32_f32', 'v_cvt_rpi_i32_f32': 'v_cvt_nearest_i32_f32',
-  'v_ffbh_i32': 'v_cls_i32', 'v_ffbh_u32': 'v_clz_i32_u32', 'v_ffbl_b32': 'v_ctz_i32_b32',
-  'v_cvt_pkrtz_f16_f32': 'v_cvt_pk_rtz_f16_f32', 'v_fmac_legacy_f32': 'v_fmac_dx9_zero_f32', 'v_mul_legacy_f32': 'v_mul_dx9_zero_f32',
-  's_load_dword': 's_load_b32', 's_load_dwordx2': 's_load_b64', 's_load_dwordx4': 's_load_b128',
-  's_load_dwordx8': 's_load_b256', 's_load_dwordx16': 's_load_b512',
-  's_buffer_load_dword': 's_buffer_load_b32', 's_buffer_load_dwordx2': 's_buffer_load_b64',
-  's_buffer_load_dwordx4': 's_buffer_load_b128', 's_buffer_load_dwordx8': 's_buffer_load_b256',
-  's_buffer_load_dwordx16': 's_buffer_load_b512',
-  'v_cvt_pknorm_i16_f16': 'v_cvt_pk_norm_i16_f16', 'v_cvt_pknorm_u16_f16': 'v_cvt_pk_norm_u16_f16',
-  'v_add3_nc_u32': 'v_add3_u32', 'v_xor_add_u32': 'v_xad_u32',
-  'v_interp_p2_new_f32': 'v_interp_p2_f32',
-  's_ff1_i32_b32': 's_ctz_i32_b32', 's_ff1_i32_b64': 's_ctz_i32_b64',
-  's_flbit_i32_b32': 's_clz_i32_u32', 's_flbit_i32_b64': 's_clz_i32_u64', 's_flbit_i32': 's_cls_i32', 's_flbit_i32_i64': 's_cls_i32_i64',
-  's_andn1_saveexec_b32': 's_and_not0_saveexec_b32', 's_andn1_saveexec_b64': 's_and_not0_saveexec_b64',
-  's_andn1_wrexec_b32': 's_and_not0_wrexec_b32', 's_andn1_wrexec_b64': 's_and_not0_wrexec_b64',
-  's_andn2_saveexec_b32': 's_and_not1_saveexec_b32', 's_andn2_saveexec_b64': 's_and_not1_saveexec_b64',
-  's_andn2_wrexec_b32': 's_and_not1_wrexec_b32', 's_andn2_wrexec_b64': 's_and_not1_wrexec_b64',
-  's_orn1_saveexec_b32': 's_or_not0_saveexec_b32', 's_orn1_saveexec_b64': 's_or_not0_saveexec_b64',
-  's_orn2_saveexec_b32': 's_or_not1_saveexec_b32', 's_orn2_saveexec_b64': 's_or_not1_saveexec_b64',
-  's_andn2_b32': 's_and_not1_b32', 's_andn2_b64': 's_and_not1_b64',
-  's_orn2_b32': 's_or_not1_b32', 's_orn2_b64': 's_or_not1_b64',
-  'v_dot2c_f32_f16': 'v_dot2acc_f32_f16',
-  'v_fma_legacy_f32': 'v_fma_dx9_zero_f32',
-  'ds_read_b32': 'ds_load_b32', 'ds_read_b64': 'ds_load_b64', 'ds_read_b96': 'ds_load_b96', 'ds_read_b128': 'ds_load_b128',
-  'ds_read_i8': 'ds_load_i8', 'ds_read_u8': 'ds_load_u8', 'ds_read_i16': 'ds_load_i16', 'ds_read_u16': 'ds_load_u16',
-  'ds_read_i8_d16': 'ds_load_i8_d16', 'ds_read_u8_d16': 'ds_load_u8_d16', 'ds_read_i8_d16_hi': 'ds_load_i8_d16_hi', 'ds_read_u8_d16_hi': 'ds_load_u8_d16_hi',
-  'ds_read_u16_d16': 'ds_load_u16_d16', 'ds_read_u16_d16_hi': 'ds_load_u16_d16_hi',
-  'ds_read2_b32': 'ds_load_2addr_b32', 'ds_read2_b64': 'ds_load_2addr_b64',
-  'ds_read2st64_b32': 'ds_load_2addr_stride64_b32', 'ds_read2st64_b64': 'ds_load_2addr_stride64_b64',
-  'ds_read_addtid_b32': 'ds_load_addtid_b32', 'ds_write_addtid_b32': 'ds_store_addtid_b32',
-  'ds_write_b32': 'ds_store_b32', 'ds_write_b64': 'ds_store_b64', 'ds_write_b96': 'ds_store_b96', 'ds_write_b128': 'ds_store_b128',
-  'ds_write_b8': 'ds_store_b8', 'ds_write_b16': 'ds_store_b16',
-  'ds_write_b8_d16_hi': 'ds_store_b8_d16_hi', 'ds_write_b16_d16_hi': 'ds_store_b16_d16_hi',
-  'ds_write2_b32': 'ds_store_2addr_b32', 'ds_write2_b64': 'ds_store_2addr_b64',
-  'ds_write2st64_b32': 'ds_store_2addr_stride64_b32', 'ds_write2st64_b64': 'ds_store_2addr_stride64_b64',
-  'ds_wrxchg_rtn_b32': 'ds_storexchg_rtn_b32', 'ds_wrxchg_rtn_b64': 'ds_storexchg_rtn_b64',
-  'ds_wrxchg2_rtn_b32': 'ds_storexchg_2addr_rtn_b32', 'ds_wrxchg2_rtn_b64': 'ds_storexchg_2addr_rtn_b64',
-  'ds_wrxchg2st64_rtn_b32': 'ds_storexchg_2addr_stride64_rtn_b32', 'ds_wrxchg2st64_rtn_b64': 'ds_storexchg_2addr_stride64_rtn_b64',
-}
-
-def _apply_alias(text: str) -> str:
-  mn = text.split()[0].lower() if ' ' in text else text.lower().rstrip('_')
-  for m in (mn, mn.removesuffix('_e32'), mn.removesuffix('_e64')):
-    if m in _ALIASES: return _ALIASES[m] + text[len(m):]
-  return text
-
-def _has(op: str, *subs) -> bool: return any(s in op for s in subs)
-
-def get_dsl(text: str, arch: str = "rdna3") -> str:
-  text, kw = _apply_alias(text.strip()), []
+def get_dsl(text: str) -> str:
+  text, kw = text.strip(), []
  # Extract modifiers
  for pat, val in [(r'\s+mul:2(?:\s|$)', 1), (r'\s+mul:4(?:\s|$)', 2), (r'\s+div:2(?:\s|$)', 3)]:
    if (m := _extract(text, pat))[0]: kw.append(f'omod={val}'); text = m[1]; break
-  clamp_found = False
-  if (m := _extract(text, r'\s+clamp(?:\s|$)'))[0]: clamp_found = True; text = m[1]
+  if (m := _extract(text, r'\s+clamp(?:\s|$)'))[0]: kw.append('clmp=1'); text = m[1]
  opsel, m, text = None, *_extract(text, r'\s+op_sel:\[([^\]]+)\]')
  if m:
    bits, mn = [int(x.strip()) for x in m.group(1).split(',')], text.split()[0].lower()
-    is3p = mn.startswith(('v_pk_', 'v_wmma_', 'v_dot', 'v_fma_mix'))
+    is3p = mn.startswith(('v_pk_', 'v_wmma_', 'v_dot'))
    opsel = (bits[0] | (bits[1] << 1) | (bits[2] << 2)) if len(bits) == 3 and is3p else \
            (bits[0] | (bits[1] << 1) | (bits[2] << 3)) if len(bits) == 3 else sum(b << i for i, b in enumerate(bits))
-  opsel_hi_val, m, text = None, *_extract(text, r'\s+op_sel_hi:\[([^\]]+)\]')
-  if m: opsel_hi_val = [int(x.strip()) for x in m.group(1).split(',')]
  m, text = _extract(text, r'\s+wait_exp:(\d+)'); waitexp = m.group(1) if m else None
  m, text = _extract(text, r'\s+offset:(0x[0-9a-fA-F]+|-?\d+)'); off_val = m.group(1) if m else None
  m, text = _extract(text, r'\s+dlc(?:\s|$)'); dlc = 1 if m else None
  m, text = _extract(text, r'\s+glc(?:\s|$)'); glc = 1 if m else None
  m, text = _extract(text, r'\s+slc(?:\s|$)'); slc = 1 if m else None
-  m, text = _extract(text, r'\s+tfe(?:\s|$)'); tfe = 1 if m else None
-  m, text = _extract(text, r'\s+offen(?:\s|$)'); offen = 1 if m else None
-  m, text = _extract(text, r'\s+idxen(?:\s|$)'); idxen = 1 if m else None
-  m, text = _extract(text, r'\s+format:\[([^\]]+)\]'); fmt_val = m.group(1) if m else None
-  m, text = _extract(text, r'\s+format:(\d+)'); fmt_val = m.group(1) if m and not fmt_val else fmt_val
  m, text = _extract(text, r'\s+neg_lo:\[([^\]]+)\]'); neg_lo = sum(int(x.strip()) << i for i, x in enumerate(m.group(1).split(','))) if m else None
  m, text = _extract(text, r'\s+neg_hi:\[([^\]]+)\]'); neg_hi = sum(int(x.strip()) << i for i, x in enumerate(m.group(1).split(','))) if m else None
-  m, text = _extract(text, r'\s+byte_sel:(\d+)'); byte_sel = int(m.group(1)) if m else None
-  m, text = _extract(text, r'\s+offset0:(\d+)'); ds_off0 = int(m.group(1)) if m else None
-  m, text = _extract(text, r'\s+offset1:(\d+)'); ds_off1 = int(m.group(1)) if m else None
-  m, text = _extract(text, r'\s+index_key:(\d+)'); index_key = int(m.group(1)) if m else None
  if waitexp: kw.append(f'waitexp={waitexp}')
-  if byte_sel is not None:
-    if opsel is None: opsel = 0
-    opsel |= (byte_sel << 2)
-  if ds_off0 is not None: kw.append(f'offset0={ds_off0}')
-  if ds_off1 is not None: kw.append(f'offset1={ds_off1}')
-  if index_key is not None: kw.append(f'opsel={index_key}')

  parts = text.replace(',', ' ').split()
  if not parts: raise ValueError("empty instruction")
@@ -197,103 +475,24 @@ def get_dsl(text: str, arch: str = "rdna3") -> str:

  # Special instructions
  if mn == 's_setreg_imm32_b32': raise ValueError(f"unsupported: {mn}")
-  sop1_no_dest = ('s_alloc_vgpr', 's_barrier_init', 's_barrier_join', 's_barrier_signal', 's_barrier_signal_isfirst', 's_sleep_var')
-  if mn in sop1_no_dest:
-    return f"{mn}(sdst=RawImm(128), ssrc0={args[0]})"
  if mn in ('s_setpc_b64', 's_rfe_b64'): return f"{mn}(ssrc0={args[0]})"
  if mn in ('s_sendmsg_rtn_b32', 's_sendmsg_rtn_b64'): return f"{mn}(sdst={args[0]}, ssrc0=RawImm({args[1].strip()}))"
  if mn == 's_version': return f"{mn}(simm16={args[0]})"
  if mn == 's_setreg_b32': return f"{mn}(simm16={args[0]}, sdst={args[1]})"

-  # Export instructions (RDNA4 VEXPORT)
-  if mn == 'export':
-    target_map = {**{f'mrt{i}': i for i in range(8)}, 'mrtz': 8, **{f'pos{i}': 12+i for i in range(4)}}
-    m, exp_str = _extract(op_str, r'\s+done(?:\s|$)')
-    done_val = 1 if m else 0
-    exp_parts = exp_str.replace(',', ' ').split()
-    target_name = exp_parts[0].lower().strip()
-    target = target_map.get(target_name, 0)
-    vsrcs, en = [], 0
-    for i, o in enumerate(exp_parts[1:5]):
-      o = o.strip().lower()
-      if o == 'off': vsrcs.append('v[0]')
-      else: vsrcs.append(_op2dsl(o)); en |= (1 << i)
-    return f"VEXPORT(target={target}, en={en}, vsrc0={vsrcs[0]}, vsrc1={vsrcs[1]}, vsrc2={vsrcs[2]}, vsrc3={vsrcs[3]}, done={done_val})"
-
  # SMEM
  if mn in SMEM_OPS:
    gs, ds = ", glc=1" if glc else "", ", dlc=1" if dlc else ""
-    off_field = "ioffset" if arch == "rdna4" else "offset"
-    th_s, scope_s, smem_str = "", "", op_str
-    if arch == "rdna4":
-      m, smem_str = _extract(op_str, r'\s+th:TH_(\w+)')
-      th_val = {'LOAD_RT': 0, 'LOAD_NT': 1, 'LOAD_HT': 2, 'LOAD_LU': 3, 'STORE_RT': 0, 'STORE_NT': 1, 'STORE_HT': 2, 'STORE_LU': 3}.get(m.group(1), 0) if m else None
-      m, smem_str = _extract(smem_str, r'\s+scope:SCOPE_(\w+)')
-      scope_val = {'CU': 0, 'SE': 1, 'DEV': 2, 'SYS': 3}.get(m.group(1), 0) if m else None
-      if scope_val is None:
-        m, smem_str = _extract(smem_str, r'\s+scope:(0?x?[0-9a-fA-F]+)')
-        scope_val = int(m.group(1), 0) if m else None
-      th_s = f", th={th_val}" if th_val else ""
-      scope_s = f", scope={scope_val}" if scope_val else ""
-    smem_ops = _parse_ops(smem_str)
-    smem_args = [_op2dsl(o) for o in smem_ops]
-    if len(smem_ops) >= 3 and re.match(r'^-?[0-9]|^-?0x', smem_ops[2].strip().lower()):
-      return f"{mn}(sdata={smem_args[0]}, sbase={smem_args[1]}, {off_field}={smem_ops[2].strip()}, soffset=RawImm(124){gs}{ds}{th_s}{scope_s})"
-    if off_val and len(smem_ops) >= 3: return f"{mn}(sdata={smem_args[0]}, sbase={smem_args[1]}, {off_field}={off_val}, soffset={smem_args[2]}{gs}{ds}{th_s}{scope_s})"
-    if len(smem_ops) >= 3: return f"{mn}(sdata={smem_args[0]}, sbase={smem_args[1]}, soffset={smem_args[2]}{gs}{ds}{th_s}{scope_s})"
+    if len(ops) >= 3 and re.match(r'^-?[0-9]|^-?0x', ops[2].strip().lower()):
+      return f"{mn}(sdata={args[0]}, sbase={args[1]}, offset={args[2]}, soffset=RawImm(124){gs}{ds})"
+    if off_val and len(ops) >= 3: return f"{mn}(sdata={args[0]}, sbase={args[1]}, offset={off_val}, soffset={args[2]}{gs}{ds})"
+    if len(ops) >= 3: return f"{mn}(sdata={args[0]}, sbase={args[1]}, soffset={args[2]}{gs}{ds})"

-  # Buffer (MUBUF/MTBUF/VBUFFER) instructions
-  if mn.startswith(('buffer_', 'tbuffer_')):
-    is_tbuf = mn.startswith('tbuffer_')
-    fmt_num = None
-    if fmt_val is not None:
-      if fmt_val.isdigit(): fmt_num = int(fmt_val)
-      else: fmt_num = BUF_FMT.get(fmt_val.replace(' ', '')) or _parse_buf_fmt_combo(fmt_val)
-    if mn in ('buffer_gl0_inv', 'buffer_gl1_inv', 'buffer_wbl2', 'buffer_inv'): return f"{mn}()"
-    if arch == "rdna4":
-      m, buf_text = _extract(op_str, r'\s+th:TH_(\w+)')
-      th_val = {'LOAD_RT': 0, 'LOAD_NT': 1, 'LOAD_HT': 2, 'LOAD_BYPASS': 3, 'LOAD_LU': 4, 'LOAD_RT_NT': 5, 'LOAD_NT_HT': 6, 'LOAD_RT_WB': 7,
-                'STORE_RT': 0, 'STORE_NT': 1, 'STORE_HT': 2, 'STORE_BYPASS': 3, 'STORE_LU': 4, 'STORE_RT_NT': 5, 'STORE_NT_HT': 6,
-                'ATOMIC_RT': 0, 'ATOMIC_NT': 1, 'ATOMIC_RETURN': 1, 'ATOMIC_RT_RETURN': 1, 'ATOMIC_NT_RETURN': 3, 'ATOMIC_CASCADE_RT': 6, 'ATOMIC_CASCADE_NT': 6}.get(m.group(1), 0) if m else 0
-      m, buf_text = _extract(buf_text, r'\s+scope:SCOPE_(\w+)')
-      scope_val = {'CU': 0, 'SE': 1, 'DEV': 2, 'SYS': 3}.get(m.group(1), 0) if m else 0
-      buf_ops = _parse_ops(buf_text)
-      buf_args = [_op2dsl(o) for o in buf_ops]
-      vbuf_mods = "".join([f", ioffset={off_val}" if off_val else "", ", offen=1" if offen else "", ", idxen=1" if idxen else "",
-                          f", th={th_val}" if th_val else "", f", scope={scope_val}" if scope_val else "",
-                          ", tfe=1" if tfe else ""])
-      if is_tbuf and fmt_num is not None: vbuf_mods = f", format={fmt_num}" + vbuf_mods
-      elif is_tbuf: vbuf_mods = ", format=1" + vbuf_mods
-      else: vbuf_mods = ", format=1" + vbuf_mods
-      vaddr_idx = 1
-      if len(buf_ops) > vaddr_idx and buf_ops[vaddr_idx].strip().lower() == 'off': vaddr_val = "v[0]"
-      else: vaddr_val = buf_args[vaddr_idx] if len(buf_args) > vaddr_idx else "v[0]"
-      rsrc_idx, soff_idx = (2, 3) if len(buf_ops) > 1 else (1, 2)
-      rsrc_raw = buf_ops[rsrc_idx].strip() if len(buf_ops) > rsrc_idx else "s[0:3]"
-      if m := re.match(r's\[(\d+):\d+\]', rsrc_raw.lower()): rsrc_val = m.group(1)
-      elif m := re.match(r's(\d+)', rsrc_raw.lower()): rsrc_val = m.group(1)
-      elif m := re.match(r'ttmp\[(\d+):\d+\]', rsrc_raw.lower()): rsrc_val = str(108 + int(m.group(1)))
-      elif m := re.match(r'ttmp(\d+)', rsrc_raw.lower()): rsrc_val = str(108 + int(m.group(1)))
-      else: rsrc_val = "0"
-      soff_raw = buf_ops[soff_idx].strip() if len(buf_ops) > soff_idx else "0"
-      soff_lower = soff_raw.lower()
-      if soff_lower == 'm0': soff_val = "RawImm(125)"
-      elif soff_lower in ('null', 'off'): soff_val = "RawImm(124)"
-      elif m := re.match(r's(\d+)', soff_lower): soff_val = f"RawImm({m.group(1)})"
-      else: soff_val = f"RawImm({soff_raw})"
-      return f"{mn}(vdata={buf_args[0]}, vaddr={vaddr_val}, rsrc={rsrc_val}, soffset={soff_val}{vbuf_mods})"
-    buf_mods = "".join([f", offset={off_val}" if off_val else "", ", glc=1" if glc else "", ", dlc=1" if dlc else "",
-                        ", slc=1" if slc else "", ", tfe=1" if tfe else "", ", offen=1" if offen else "", ", idxen=1" if idxen else ""])
-    if is_tbuf and fmt_num is not None: buf_mods = f", format={fmt_num}" + buf_mods
-    vaddr_idx = 1
-    if len(ops) > vaddr_idx and ops[vaddr_idx].strip().lower() == 'off': vaddr_val = "v[0]"
-    else: vaddr_val = args[vaddr_idx] if len(args) > vaddr_idx else "v[0]"
-    srsrc_idx, soff_idx = (2, 3) if len(ops) > 1 else (1, 2)
-    srsrc_val = args[srsrc_idx] if len(args) > srsrc_idx else "s[0:3]"
-    soff_val = args[soff_idx] if len(args) > soff_idx else "0"
-    return f"{mn}(vdata={args[0]}, vaddr={vaddr_val}, srsrc={srsrc_val}, soffset={soff_val}{buf_mods})"
+  # Buffer
+  if mn.startswith('buffer_') and len(ops) >= 2 and ops[1].strip().lower() == 'off':
+    return f"{mn}(vdata={args[0]}, vaddr=0, srsrc={args[2]}, soffset={f'RawImm({args[3].strip()})' if len(args) > 3 else 'RawImm(0)'})"

-  # FLAT/GLOBAL/SCRATCH load/store/atomic
+  # FLAT/GLOBAL/SCRATCH load/store/atomic - saddr needs RawImm(124) for off/null
  def _saddr(a): return 'RawImm(124)' if a in ('OFF', 'NULL') else a
  flat_mods = f"{f', offset={off_val}' if off_val else ''}{', glc=1' if glc else ''}{', slc=1' if slc else ''}{', dlc=1' if dlc else ''}"
  for pre, flds in [('flat_load','vdst,addr,saddr'), ('global_load','vdst,addr,saddr'), ('scratch_load','vdst,addr,saddr'),
@@ -308,12 +507,7 @@ def get_dsl(text: str, arch: str = "rdna3") -> str:

  # DS instructions
  if mn.startswith('ds_'):
-    if ds_off0 is not None or ds_off1 is not None:
-      off0, off1 = str(ds_off0 or 0), str(ds_off1 or 0)
-    elif off_val:
-      off0, off1 = str(int(off_val, 0) & 0xff), str((int(off_val, 0) >> 8) & 0xff)
-    else:
-      off0, off1 = "0", "0"
+    off0, off1 = (str(int(off_val, 0) & 0xff), str((int(off_val, 0) >> 8) & 0xff)) if off_val else ("0", "0")
    gds_s = ", gds=1" if 'gds' in text.lower().split()[-1:] else ""
    off_kw = f", offset0={off0}, offset1={off1}{gds_s}"
    if mn == 'ds_nop' or mn in ('ds_gws_sema_v', 'ds_gws_sema_p', 'ds_gws_sema_release_all'): return f"{mn}({off_kw.lstrip(', ')})"
@@ -339,33 +533,13 @@ def get_dsl(text: str, arch: str = "rdna3") -> str:
  lit_s = ""
  if mn in ('v_fmaak_f32', 'v_fmaak_f16') and len(args) == 4: lit_s, args = f", literal={args[3].strip()}", args[:3]
  elif mn in ('v_fmamk_f32', 'v_fmamk_f16') and len(args) == 4: lit_s, args = f", literal={args[2].strip()}", [args[0], args[1], args[3]]
-  elif mn in ('s_fmaak_f32',) and len(args) == 4: lit_s, args = f", literal={args[3].strip()}", args[:3]
-  elif mn in ('s_fmamk_f32',) and len(args) == 4: lit_s, args = f", literal={args[2].strip()}", [args[0], args[1], args[3]]
-  elif mn in ('v_cndmask_b32', 'v_cndmask_b32_e32') and len(args) == 4 and ops[3].strip().lower() in ('vcc_lo', 'vcc'):
-    mn, args = 'v_cndmask_b32_e32', args[:3]

-  _SGPR_NAMES = {'vcc_lo': 106, 'vcc_hi': 107, 'vcc': 106, 'null': 124, 'm0': 125, 'exec_lo': 126, 'exec_hi': 127}
+  # VCC ops cleanup
  vcc_ops = {'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'}
-  if mn.replace('_e32', '') in vcc_ops and len(args) >= 5:
-    carry_in = ops[4].strip().lower() if len(ops) > 4 else 'vcc_lo'
-    carry_out = ops[1].strip().lower() if len(ops) > 1 else 'vcc_lo'
-    if carry_in in ('vcc_lo', 'vcc') and carry_out in ('vcc_lo', 'vcc'):
-      mn, args = mn.replace('_e32', '') + '_e32', [args[0], args[2], args[3]]
-    else:
-      mn_base = mn.replace('_e32', '').replace('_e64', '')
-      sdst = _SGPR_NAMES.get(carry_out, 124) if carry_out in _SGPR_NAMES else (int(carry_out[1:]) if carry_out.startswith('s') and carry_out[1:].isdigit() else 124)
-      src2 = _SGPR_NAMES.get(carry_in, 0) if carry_in in _SGPR_NAMES else (int(carry_in[1:]) if carry_in.startswith('s') and carry_in[1:].isdigit() else 0)
-      return f"{mn_base}(vdst={args[0]}, sdst=RawImm({sdst}), src0={args[2]}, src1={args[3]}, src2=RawImm({src2}))"
+  if mn.replace('_e32', '') in vcc_ops and len(args) >= 5: mn, args = mn.replace('_e32', '') + '_e32', [args[0], args[2], args[3]]
  if mn.replace('_e64', '') in vcc_ops and mn.endswith('_e64'): mn = mn.replace('_e64', '')
  if mn.startswith('v_cmp') and not mn.endswith('_e64') and len(args) >= 3 and ops[0].strip().lower() in ('vcc_lo', 'vcc_hi', 'vcc'): args = args[1:]
  if 'cmpx' in mn and mn.endswith('_e64') and len(args) == 2: args = ['RawImm(126)'] + args
-  if ((mn.startswith('v_cmp') and 'cmpx' not in mn and mn.endswith('_e64')) or mn.startswith('v_s_') or mn in ('v_readlane_b32', 'v_readfirstlane_b32')) and len(args) >= 1:
-    dst = ops[0].strip().lower()
-    if dst.startswith('s') and dst[1:].isdigit(): args[0] = f'RawImm({int(dst[1:])})'
-    elif dst.startswith('s[') and ':' in dst: args[0] = f'RawImm({int(dst[2:].split(":")[0])})'
-    elif dst.startswith('ttmp') and dst[4:].isdigit(): args[0] = f'RawImm({108 + int(dst[4:])})'
-    elif dst.startswith('ttmp[') and ':' in dst: args[0] = f'RawImm({108 + int(dst[5:].split(":")[0])})'
-    elif dst in _SGPR_NAMES: args[0] = f'RawImm({_SGPR_NAMES[dst]})'

  fn = mn.replace('.', '_')
  if opsel is not None: args = [re.sub(r'\.[hl]$', '', a) for a in args]
@@ -392,52 +566,15 @@ def get_dsl(text: str, arch: str = "rdna3") -> str:
  if neg_lo is not None: all_kw.append(f'neg={neg_lo}')
  if neg_hi is not None: all_kw.append(f'neg_hi={neg_hi}')
  if 'bvh' in mn and 'intersect_ray' in mn: all_kw.extend(['dmask=15', 'unrm=1', 'r128=1'])
-  vop3p_ops = {'v_pk_', 'v_dot2', 'v_dot4', 'v_dot8', 'v_wmma', 'v_swmmac'}
-  is_vop3p = any(mn.startswith(p) for p in vop3p_ops)
-  is_fma_mix = 'fma_mix' in mn
-  if opsel_hi_val is not None:
-    opsel_hi_enc = opsel_hi_val[0] | (opsel_hi_val[1] << 1) if len(opsel_hi_val) >= 2 else opsel_hi_val[0]
-    opsel_hi2_enc = opsel_hi_val[2] if len(opsel_hi_val) >= 3 else (0 if is_fma_mix else 1)
-    all_kw.extend([f'opsel_hi={opsel_hi_enc}', f'opsel_hi2={opsel_hi2_enc}'])
-  elif is_vop3p and not is_fma_mix:
-    all_kw.extend(['opsel_hi=3', 'opsel_hi2=1'])
-  if clamp_found:
-    if arch == 'rdna4': all_kw.append('cm=1')
-    else: all_kw.append('clmp=1')

  a_str, kw_str = ', '.join(args), ', '.join(all_kw)
  return f"{fn}({a_str}, {kw_str})" if kw_str and a_str else f"{fn}({kw_str})" if kw_str else f"{fn}({a_str})"

-def _hwreg(id_, offset=0, size=32): return id_ | (offset << 6) | ((size - 1) << 11)
-def _sendmsg(id_, op=0, stream=0): return id_ | (op << 4) | (stream << 8)
-
-_HWREG_NAMES = {'HW_REG_MODE': 1, 'HW_REG_STATUS': 2, 'HW_REG_TRAPSTS': 3, 'HW_REG_HW_ID': 4, 'HW_REG_GPR_ALLOC': 5,
-  'HW_REG_LDS_ALLOC': 6, 'HW_REG_IB_STS': 7, 'HW_REG_PC_LO': 8, 'HW_REG_PC_HI': 9, 'HW_REG_INST_DW0': 10, 'HW_REG_INST_DW1': 11,
-  'HW_REG_IB_DBG0': 12, 'HW_REG_IB_DBG1': 13, 'HW_REG_FLUSH_IB': 14, 'HW_REG_SH_MEM_BASES': 15, 'HW_REG_SQ_SHADER_TBA_LO': 16,
-  'HW_REG_SQ_SHADER_TBA_HI': 17, 'HW_REG_SQ_SHADER_TMA_LO': 18, 'HW_REG_SQ_SHADER_TMA_HI': 19, 'HW_REG_FLAT_SCR_LO': 20,
-  'HW_REG_FLAT_SCR_HI': 21, 'HW_REG_XNACK_MASK': 22, 'HW_REG_HW_ID1': 23, 'HW_REG_HW_ID2': 24, 'HW_REG_POPS_PACKER': 25,
-  'HW_REG_PERF_SNAPSHOT_DATA': 26, 'HW_REG_PERF_SNAPSHOT_PC_LO': 27, 'HW_REG_PERF_SNAPSHOT_PC_HI': 28, 'HW_REG_SHADER_CYCLES': 29,
-  'HW_REG_SHADER_CYCLES_HI': 30, 'HW_REG_WAVE_MODE': 31, 'HW_REG_WAVE_SCRATCH_BASE': 32}
-_HWREG_NAMES_RDNA4 = {v: k for k, v in HWREG_RDNA4.items()}
-_SENDMSG_NAMES = {'MSG_INTERRUPT': 1, 'MSG_GS': 2, 'MSG_GS_DONE': 3, 'MSG_SAVEWAVE': 4, 'MSG_STALL_WAVE_GEN': 5,
-  'MSG_HALT_WAVES': 6, 'MSG_ORDERED_PS_DONE': 7, 'MSG_EARLY_PRIM_DEALLOC': 8, 'MSG_GS_ALLOC_REQ': 9, 'MSG_GET_DOORBELL': 10,
-  'MSG_GET_DDID': 11, 'MSG_HS_TESSFACTOR': 2, 'MSG_DEALLOC_VGPRS': 10, 'MSG_RTN_GET_DOORBELL': 128, 'MSG_RTN_GET_DDID': 129,
-  'MSG_RTN_GET_TMA': 130, 'MSG_RTN_GET_REALTIME': 131, 'MSG_RTN_SAVE_WAVE': 132, 'MSG_RTN_GET_TBA': 133,
-  'MSG_RTN_GET_TBA_TO_PC': 134, 'MSG_RTN_GET_SE_AID_ID': 135}
-
-def asm(text: str, arch: str = "rdna3") -> Inst:
-  dsl = get_dsl(text, arch)
-  if arch == "rdna4":
-    ns = {n: getattr(rdna4_ins, n) for n in dir(rdna4_ins) if not n.startswith('_')}
-    hwreg_names = _HWREG_NAMES_RDNA4
-  else:
-    ns = {n: getattr(ins, n) for n in dir(ins) if not n.startswith('_')}
-    hwreg_names = _HWREG_NAMES
-  def hwreg(id_, offset=0, size=32): return _hwreg(hwreg_names.get(id_, id_) if isinstance(id_, str) else id_, offset, size)
-  def sendmsg(id_, op=0, stream=0): return _sendmsg(_SENDMSG_NAMES.get(id_, id_) if isinstance(id_, str) else id_, op, stream)
+def asm(text: str) -> Inst:
+  dsl = get_dsl(text)
+  ns = {n: getattr(ins, n) for n in dir(ins) if not n.startswith('_')}
  ns.update({'s': s, 'v': v, 'ttmp': ttmp, 'abs': abs, 'RawImm': RawImm, 'SrcMod': SrcMod, 'VGPR': VGPR, 'SGPR': SGPR, 'TTMP': TTMP,
-             'VCC_LO': VCC_LO, 'VCC_HI': VCC_HI, 'VCC': VCC, 'EXEC_LO': EXEC_LO, 'EXEC_HI': EXEC_HI, 'EXEC': EXEC, 'SCC': SCC, 'M0': M0, 'NULL': NULL, 'OFF': OFF,
-             'hwreg': hwreg, 'sendmsg': sendmsg, **{k: k for k in hwreg_names}, **{k: k for k in _SENDMSG_NAMES}})
+             'VCC_LO': VCC_LO, 'VCC_HI': VCC_HI, 'VCC': VCC, 'EXEC_LO': EXEC_LO, 'EXEC_HI': EXEC_HI, 'EXEC': EXEC, 'SCC': SCC, 'M0': M0, 'NULL': NULL, 'OFF': OFF})
  try: return eval(dsl, ns)
  except NameError:
    if m := re.match(r'^(v_\w+)(\(.*\))$', dsl): return eval(f"{m.group(1)}_e32{m.group(2)}", ns)
@@ -1,6 +1,46 @@
-# autogenerated from AMD ISA PDF by pdf.py - do not edit
+# autogenerated from AMD CDNA3+CDNA4 ISA PDF by pdf.py - do not edit
 from enum import IntEnum

+class SrcEnum(IntEnum):
+  S_ADD_U32 = 0
+  S_SUB_U32 = 1
+  S_ADD_I32 = 2
+  S_SUB_I32 = 3
+  S_ADDC_U32 = 4
+  S_SUBB_U32 = 5
+  S_MIN_I32 = 6
+  FLAT_SCRATCH_LO = 102
+  FLAT_SCRATCH_HI = 103
+  XNACK_MASK_LO = 104
+  XNACK_MASK_HI = 105
+  VCC_LO = 106
+  VCC_HI = 107
+  M0 = 124
+  EXEC_LO = 126
+  EXEC_HI = 127
+  ZERO = 128
+  DPP8 = 233
+  DPP8FI = 234
+  SHARED_BASE = 235
+  SHARED_LIMIT = 236
+  PRIVATE_BASE = 237
+  PRIVATE_LIMIT = 238
+  RESERVED = 239
+  POS_HALF = 240
+  NEG_HALF = 241
+  POS_ONE = 242
+  NEG_ONE = 243
+  POS_TWO = 244
+  NEG_TWO = 245
+  POS_FOUR = 246
+  NEG_FOUR = 247
+  INV_2PI = 248
+  DPP16 = 250
+  VCCZ = 251
+  EXECZ = 252
+  SCC = 253
+  LDS_DIRECT = 254
+
 class DSOp(IntEnum):
  DS_ADD_U32 = 0
  DS_SUB_U32 = 1
@@ -115,6 +155,12 @@ class DSOp(IntEnum):
  DS_READ2ST64_B64 = 120
  DS_ADD_RTN_F64 = 124
  DS_CONDXCHG32_RTN_B64 = 126
+  DS_GWS_SEMA_RELEASE_ALL = 152
+  DS_GWS_INIT = 153
+  DS_GWS_SEMA_V = 154
+  DS_GWS_SEMA_BR = 155
+  DS_GWS_SEMA_P = 156
+  DS_GWS_BARRIER = 157
  DS_READ_ADDTID_B32 = 182
  DS_PK_ADD_RTN_F16 = 183
  DS_PK_ADD_RTN_BF16 = 184
@@ -128,6 +174,7 @@ class DSOp(IntEnum):
  DS_READ_B64_TR_B16 = 227
  DS_READ_B96 = 254
  DS_READ_B128 = 255
+  CDNA4 = 600

 class FLATOp(IntEnum):
  FLAT_LOAD_UBYTE = 16
@@ -184,6 +231,7 @@ class FLATOp(IntEnum):
  FLAT_ATOMIC_XOR_X2 = 106
  FLAT_ATOMIC_INC_X2 = 107
  FLAT_ATOMIC_DEC_X2 = 108
+  CDNA4 = 600

 class GLOBALOp(IntEnum):
  GLOBAL_LOAD_UBYTE = 16
@@ -247,6 +295,7 @@ class GLOBALOp(IntEnum):
  GLOBAL_ATOMIC_DEC_X2 = 108
  GLOBAL_LOAD_LDS_DWORDX4 = 125
  GLOBAL_LOAD_LDS_DWORDX3 = 126
+  CDNA4 = 600

 class MTBUFOp(IntEnum):
  TBUFFER_LOAD_FORMAT_X = 0
@@ -341,6 +390,7 @@ class MUBUFOp(IntEnum):
  BUFFER_ATOMIC_XOR_X2 = 106
  BUFFER_ATOMIC_INC_X2 = 107
  BUFFER_ATOMIC_DEC_X2 = 108
+  CDNA4 = 600

 class SCRATCHOp(IntEnum):
  SCRATCH_LOAD_UBYTE = 16
@@ -454,6 +504,7 @@ class SMEMOp(IntEnum):
  S_ATOMIC_XOR_X2 = 170
  S_ATOMIC_INC_X2 = 171
  S_ATOMIC_DEC_X2 = 172
+  CDNA4 = 600

 class SOP1Op(IntEnum):
  S_MOV_B32 = 0
@@ -510,6 +561,7 @@ class SOP1Op(IntEnum):
  S_ANDN1_WREXEC_B64 = 53
  S_ANDN2_WREXEC_B64 = 54
  S_BITREPLICATE_B64_B32 = 55
+  CDNA4 = 600

 class SOP2Op(IntEnum):
  S_ADD_U32 = 0
@@ -564,6 +616,7 @@ class SOP2Op(IntEnum):
  S_PACK_LL_B32_B16 = 50
  S_PACK_LH_B32_B16 = 51
  S_PACK_HH_B32_B16 = 52
+  CDNA4 = 600

 class SOPCOp(IntEnum):
  S_CMP_EQ_I32 = 0
@@ -586,6 +639,7 @@ class SOPCOp(IntEnum):
  S_SET_GPR_IDX_ON = 17
  S_CMP_EQ_U64 = 18
  S_CMP_LG_U64 = 19
+  CDNA4 = 600

 class SOPKOp(IntEnum):
  S_MOVK_I32 = 0
@@ -641,6 +695,7 @@ class SOPPOp(IntEnum):
  S_ENDPGM_SAVED = 27
  S_SET_GPR_IDX_OFF = 28
  S_SET_GPR_IDX_MODE = 29
+  CDNA4 = 600

 class VOP1Op(IntEnum):
  V_NOP = 0
@@ -728,6 +783,7 @@ class VOP1Op(IntEnum):
  V_PERMLANE16_SWAP_B32 = 89
  V_PERMLANE32_SWAP_B32 = 90
  V_CVT_F32_BF16 = 91
+  CDNA4 = 600

 class VOP2Op(IntEnum):
  V_CNDMASK_B32 = 0
@@ -792,6 +848,7 @@ class VOP2Op(IntEnum):
  V_FMAC_F32 = 59
  V_PK_FMAC_F16 = 60
  V_XNOR_B32 = 61
+  CDNA4 = 600

 class VOP3AOp(IntEnum):
  V_CMP_CLASS_F32 = 16
@@ -1211,7 +1268,7 @@ class VOP3AOp(IntEnum):
  V_CVT_SCALEF32_SR_PK32_BF6_F32 = 597
  V_CVT_SCALEF32_PK32_F32_FP6 = 598
  V_CVT_SCALEF32_PK32_F32_BF6 = 599
-  V_CVT_SCALEF32_PK32_FP6_F16 = 600
+  CDNA4 = 600
  V_CVT_SCALEF32_PK32_FP6_BF16 = 601
  V_CVT_SCALEF32_PK32_BF6_F16 = 602
  V_CVT_SCALEF32_PK32_BF6_BF16 = 603
@@ -1281,6 +1338,7 @@ class VOP3BOp(IntEnum):
  V_DIV_SCALE_F64 = 481
  V_MAD_U64_U32 = 488
  V_MAD_I64_I32 = 489
+  CDNA4 = 600

 class VOP3POp(IntEnum):
  V_PK_MAD_I16 = 0
@@ -1330,6 +1388,8 @@ class VOP3POp(IntEnum):
  V_SMFMAC_F32_16X16X128_BF8_BF8 = 59
  V_SMFMAC_F32_16X16X128_BF8_FP8 = 60
  V_SMFMAC_F32_16X16X128_FP8_BF8 = 61
+  V_MFMA_F32_16X16X8_XF32 = 62
+  V_MFMA_F32_32X32X4_XF32 = 63
  V_MFMA_F32_32X32X1_2B_F32 = 64
  V_MFMA_F32_16X16X1_4B_F32 = 65
  V_MFMA_F32_4X4X1_16B_F32 = 66
@@ -1387,6 +1447,7 @@ class VOP3POp(IntEnum):
  V_SMFMAC_F32_32X32X32_BF8_FP8 = 125
  V_SMFMAC_F32_32X32X32_FP8_BF8 = 126
  V_SMFMAC_F32_32X32X32_FP8_FP8 = 127
+  CDNA4 = 600

 class VOPCOp(IntEnum):
  V_CMP_CLASS_F32 = 16
@@ -1587,3 +1648,4 @@ class VOPCOp(IntEnum):
  V_CMPX_NE_U64 = 253
  V_CMPX_GE_U64 = 254
  V_CMPX_T_U64 = 255
+  CDNA4 = 600
@@ -1,26 +1,29 @@
-# autogenerated from AMD ISA PDF by pdf.py - do not edit
+# autogenerated from AMD CDNA3+CDNA4 ISA PDF by pdf.py - do not edit
 # ruff: noqa: F401,F403
 from typing import Annotated
-from extra.assembly.amd.dsl import *
+from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField
 from extra.assembly.amd.autogen.cdna.enum import *
 import functools

-class DPP(Inst):
-  encoding = bits[8:0] == 0b11111010
-  vdst:VGPRField = bits[24:17]
-  src0:Src = bits[39:32]
-  vop_op = bits[16:9]
-  vop2_op = bits[31:25]
-  dpp_ctrl = bits[48:40]
-  bc = bits[51]
-  src0_neg = bits[52]
-  src0_abs = bits[53]
-  src1_neg = bits[54]
-  src1_abs = bits[55]
-  bank_mask = bits[59:56]
+# instruction formats
+class DPP(Inst64):
+  encoding = bits[31:26] == 0b110110
+  src1_sel = bits[58:56]
+  src1_sext = bits[59]
+  src1_neg = bits[60]
+  src1_abs = bits[61]
+  s1 = bits[63]
+  offset0 = bits[7:0]
+  offset1 = bits[15:8]
+  op = bits[24:17]
+  acc = bits[25]
+  addr:VGPRField = bits[39:32]
+  data0:VGPRField = bits[47:40]
+  data1:VGPRField = bits[55:48]
+  vdst:VGPRField = bits[63:56]
  row_mask = bits[63:60]

-class DS(Inst):
+class DS(Inst64):
  encoding = bits[31:26] == 0b110110
  op:Annotated[BitField, DSOp] = bits[24:17]
  vdst:VGPRField = bits[63:56]
@@ -32,7 +35,7 @@ class DS(Inst):
  gds = bits[16]
  acc = bits[25]

-class FLAT(Inst):
+class FLAT(Inst64):
  encoding = bits[31:26] == 0b110111
  op:Annotated[BitField, FLATOp] = bits[24:18]
  vdst:VGPRField = bits[63:56]
@@ -47,7 +50,7 @@ class FLAT(Inst):
  sc1 = bits[25]
  acc = bits[55]

-class MTBUF(Inst):
+class MTBUF(Inst64):
  encoding = bits[31:26] == 0b111010
  op:Annotated[BitField, MTBUFOp] = bits[18:15]
  vdata:VGPRField = bits[47:40]
@@ -57,14 +60,12 @@ class MTBUF(Inst):
  offset:Imm = bits[11:0]
  offen = bits[12]
  idxen = bits[13]
-  sc0 = bits[14]
-  dfmt = bits[22:19]
-  nfmt = bits[25:23]
  sc1 = bits[53]
  nt = bits[54]
  acc = bits[55]
+  sc0 = bits[14]

-class MUBUF(Inst):
+class MUBUF(Inst64):
  encoding = bits[31:26] == 0b111000
  op:Annotated[BitField, MUBUFOp] = bits[24:18]
  vdata:VGPRField = bits[47:40]
@@ -80,16 +81,12 @@ class MUBUF(Inst):
  nt = bits[17]
  acc = bits[55]

-class SDWA(Inst):
-  encoding = bits[8:0] == 0b11111001
-  vdst:VGPRField = bits[24:17]
+class SDWA(Inst64):
  src0:Src = bits[39:32]
-  omod = bits[47:46]
-  clmp = bits[45]
-  vop_op = bits[16:9]
-  vop2_op = bits[31:25]
  dst_sel = bits[42:40]
  dst_u = bits[44:43]
+  clmp = bits[45]
+  omod = bits[47:46]
  src0_sel = bits[50:48]
  src0_sext = bits[51]
  src0_neg = bits[52]
@@ -100,11 +97,16 @@ class SDWA(Inst):
  src1_neg = bits[60]
  src1_abs = bits[61]
  s1 = bits[63]
-
-class SDWAB(Inst):
  sdst:SGPRField = bits[46:40]
-  src0:Src = bits[39:32]
  sd = bits[47]
+  row_mask = bits[63:60]
+
+class SDWAB(Inst64):
+  src0:Src = bits[39:32]
+  dst_sel = bits[42:40]
+  dst_u = bits[44:43]
+  clmp = bits[45]
+  omod = bits[47:46]
  src0_sel = bits[50:48]
  src0_sext = bits[51]
  src0_neg = bits[52]
@@ -116,88 +118,89 @@ class SDWAB(Inst):
  src1_abs = bits[61]
  s1 = bits[63]

-class SMEM(Inst):
+class SMEM(Inst64):
  encoding = bits[31:26] == 0b110000
  op:Annotated[BitField, SMEMOp] = bits[25:18]
  sdata:SGPRField = bits[12:6]
  sbase:SGPRField = bits[5:0]
  soffset:SSrc = bits[63:57]
  offset:Imm = bits[52:32]
-  glc = bits[16]
+  glc = bits[14]
  soe = bits[14]
  nv = bits[15]
-  imm:Imm = bits[17]
+  imm = bits[17]

-class SOP1(Inst):
+class SOP1(Inst32):
  encoding = bits[31:23] == 0b101111101
  op:Annotated[BitField, SOP1Op] = bits[15:8]
  sdst:SGPRField = bits[22:16]
  ssrc0:SSrc = bits[7:0]

-class SOP2(Inst):
+class SOP2(Inst32):
  encoding = bits[31:30] == 0b10
  op:Annotated[BitField, SOP2Op] = bits[29:23]
  sdst:SGPRField = bits[22:16]
  ssrc0:SSrc = bits[7:0]
  ssrc1:SSrc = bits[15:8]

-class SOPC(Inst):
+class SOPC(Inst32):
  encoding = bits[31:23] == 0b101111110
  op:Annotated[BitField, SOPCOp] = bits[22:16]
  ssrc0:SSrc = bits[7:0]
  ssrc1:SSrc = bits[15:8]

-class SOPK(Inst):
+class SOPK(Inst32):
  encoding = bits[31:28] == 0b1011
  op:Annotated[BitField, SOPKOp] = bits[27:23]
  sdst:SGPRField = bits[22:16]
  simm16:SImm = bits[15:0]

-class SOPP(Inst):
+class SOPP(Inst32):
  encoding = bits[31:23] == 0b101111111
  op:Annotated[BitField, SOPPOp] = bits[22:16]
  simm16:SImm = bits[15:0]

-class VOP1(Inst):
-  encoding = bits[31:25] == 0b0111111
+class VOP1(Inst32):
+  encoding = bits[31:25] == 0b111111
  op:Annotated[BitField, VOP1Op] = bits[16:9]
  vdst:VGPRField = bits[24:17]
  src0:Src = bits[8:0]

-class VOP2(Inst):
-  encoding = bits[31] == 0b0
+class VOP2(Inst32):
+  encoding = bits[31] == 0
  op:Annotated[BitField, VOP2Op] = bits[30:25]
  vdst:VGPRField = bits[24:17]
  src0:Src = bits[8:0]
  vsrc1:VGPRField = bits[16:9]

-class VOP3A(Inst):
+class VOP3A(Inst64):
  encoding = bits[31:26] == 0b110100
-  op:Annotated[BitField, VOP3AOp] = bits[25:16]
  vdst:VGPRField = bits[7:0]
+  abs = bits[10:8]
+  opsel = bits[14:11]
+  clmp = bits[15]
+  op:Annotated[BitField, VOP3AOp] = bits[25:16]
  src0:Src = bits[40:32]
  src1:Src = bits[49:41]
  src2:Src = bits[58:50]
  omod = bits[60:59]
  neg = bits[63:61]
-  abs = bits[10:8]
-  clmp = bits[15]
-  opsel = bits[14:11]

-class VOP3B(Inst):
+class VOP3B(Inst64):
  encoding = bits[31:26] == 0b110100
-  op:Annotated[BitField, VOP3BOp] = bits[25:16]
  vdst:VGPRField = bits[7:0]
  sdst:SGPRField = bits[14:8]
+  clmp = bits[15]
+  op:Annotated[BitField, VOP3BOp] = bits[25:16]
  src0:Src = bits[40:32]
  src1:Src = bits[49:41]
  src2:Src = bits[58:50]
  omod = bits[60:59]
  neg = bits[63:61]
-  clmp = bits[15]

-class VOP3P(Inst):
+class VOP3P(Inst64):
  encoding = bits[31:23] == 0b110100111
+  _defaults = {'opsel_hi': 3, 'opsel_hi2': 1}
  op:Annotated[BitField, VOP3POp] = bits[22:16]
  vdst:VGPRField = bits[7:0]
  src0:Src = bits[40:32]
@@ -205,13 +208,13 @@ class VOP3P(Inst):
  src2:Src = bits[58:50]
  neg = bits[63:61]
  neg_hi = bits[10:8]
-  clmp = bits[15]
  opsel = bits[13:11]
  opsel_hi = bits[60:59]
+  clmp = bits[15]
  opsel_hi2 = bits[14]

-class VOPC(Inst):
-  encoding = bits[31:25] == 0b0111110
+class VOPC(Inst32):
+  encoding = bits[31:25] == 0b111110
  op:Annotated[BitField, VOPCOp] = bits[24:17]
  src0:Src = bits[8:0]
  vsrc1:VGPRField = bits[16:9]
@@ -330,6 +333,12 @@ ds_read2_b64 = functools.partial(DS, DSOp.DS_READ2_B64)
 ds_read2st64_b64 = functools.partial(DS, DSOp.DS_READ2ST64_B64)
 ds_add_rtn_f64 = functools.partial(DS, DSOp.DS_ADD_RTN_F64)
 ds_condxchg32_rtn_b64 = functools.partial(DS, DSOp.DS_CONDXCHG32_RTN_B64)
+ds_gws_sema_release_all = functools.partial(DS, DSOp.DS_GWS_SEMA_RELEASE_ALL)
+ds_gws_init = functools.partial(DS, DSOp.DS_GWS_INIT)
+ds_gws_sema_v = functools.partial(DS, DSOp.DS_GWS_SEMA_V)
+ds_gws_sema_br = functools.partial(DS, DSOp.DS_GWS_SEMA_BR)
+ds_gws_sema_p = functools.partial(DS, DSOp.DS_GWS_SEMA_P)
+ds_gws_barrier = functools.partial(DS, DSOp.DS_GWS_BARRIER)
 ds_read_addtid_b32 = functools.partial(DS, DSOp.DS_READ_ADDTID_B32)
 ds_pk_add_rtn_f16 = functools.partial(DS, DSOp.DS_PK_ADD_RTN_F16)
 ds_pk_add_rtn_bf16 = functools.partial(DS, DSOp.DS_PK_ADD_RTN_BF16)
@@ -343,6 +352,7 @@ ds_read_b64_tr_b8 = functools.partial(DS, DSOp.DS_READ_B64_TR_B8)
 ds_read_b64_tr_b16 = functools.partial(DS, DSOp.DS_READ_B64_TR_B16)
 ds_read_b96 = functools.partial(DS, DSOp.DS_READ_B96)
 ds_read_b128 = functools.partial(DS, DSOp.DS_READ_B128)
+cdna4 = functools.partial(DS, DSOp.CDNA4)
 flat_load_ubyte = functools.partial(FLAT, FLATOp.FLAT_LOAD_UBYTE)
 flat_load_sbyte = functools.partial(FLAT, FLATOp.FLAT_LOAD_SBYTE)
 flat_load_ushort = functools.partial(FLAT, FLATOp.FLAT_LOAD_USHORT)
@@ -397,6 +407,7 @@ flat_atomic_or_x2 = functools.partial(FLAT, FLATOp.FLAT_ATOMIC_OR_X2)
 flat_atomic_xor_x2 = functools.partial(FLAT, FLATOp.FLAT_ATOMIC_XOR_X2)
 flat_atomic_inc_x2 = functools.partial(FLAT, FLATOp.FLAT_ATOMIC_INC_X2)
 flat_atomic_dec_x2 = functools.partial(FLAT, FLATOp.FLAT_ATOMIC_DEC_X2)
+cdna4 = functools.partial(FLAT, FLATOp.CDNA4)
 global_load_ubyte = functools.partial(FLAT, GLOBALOp.GLOBAL_LOAD_UBYTE, seg=2)
 global_load_sbyte = functools.partial(FLAT, GLOBALOp.GLOBAL_LOAD_SBYTE, seg=2)
 global_load_ushort = functools.partial(FLAT, GLOBALOp.GLOBAL_LOAD_USHORT, seg=2)
@@ -458,6 +469,7 @@ global_atomic_inc_x2 = functools.partial(FLAT, GLOBALOp.GLOBAL_ATOMIC_INC_X2, se
 global_atomic_dec_x2 = functools.partial(FLAT, GLOBALOp.GLOBAL_ATOMIC_DEC_X2, seg=2)
 global_load_lds_dwordx4 = functools.partial(FLAT, GLOBALOp.GLOBAL_LOAD_LDS_DWORDX4, seg=2)
 global_load_lds_dwordx3 = functools.partial(FLAT, GLOBALOp.GLOBAL_LOAD_LDS_DWORDX3, seg=2)
+cdna4 = functools.partial(FLAT, GLOBALOp.CDNA4, seg=2)
 tbuffer_load_format_x = functools.partial(MTBUF, MTBUFOp.TBUFFER_LOAD_FORMAT_X)
 tbuffer_load_format_xy = functools.partial(MTBUF, MTBUFOp.TBUFFER_LOAD_FORMAT_XY)
 tbuffer_load_format_xyz = functools.partial(MTBUF, MTBUFOp.TBUFFER_LOAD_FORMAT_XYZ)
@@ -548,6 +560,7 @@ buffer_atomic_or_x2 = functools.partial(MUBUF, MUBUFOp.BUFFER_ATOMIC_OR_X2)
 buffer_atomic_xor_x2 = functools.partial(MUBUF, MUBUFOp.BUFFER_ATOMIC_XOR_X2)
 buffer_atomic_inc_x2 = functools.partial(MUBUF, MUBUFOp.BUFFER_ATOMIC_INC_X2)
 buffer_atomic_dec_x2 = functools.partial(MUBUF, MUBUFOp.BUFFER_ATOMIC_DEC_X2)
+cdna4 = functools.partial(MUBUF, MUBUFOp.CDNA4)
 scratch_load_ubyte = functools.partial(FLAT, SCRATCHOp.SCRATCH_LOAD_UBYTE, seg=1)
 scratch_load_sbyte = functools.partial(FLAT, SCRATCHOp.SCRATCH_LOAD_SBYTE, seg=1)
 scratch_load_ushort = functools.partial(FLAT, SCRATCHOp.SCRATCH_LOAD_USHORT, seg=1)
@@ -657,6 +670,7 @@ s_atomic_or_x2 = functools.partial(SMEM, SMEMOp.S_ATOMIC_OR_X2)
 s_atomic_xor_x2 = functools.partial(SMEM, SMEMOp.S_ATOMIC_XOR_X2)
 s_atomic_inc_x2 = functools.partial(SMEM, SMEMOp.S_ATOMIC_INC_X2)
 s_atomic_dec_x2 = functools.partial(SMEM, SMEMOp.S_ATOMIC_DEC_X2)
+cdna4 = functools.partial(SMEM, SMEMOp.CDNA4)
 s_mov_b32 = functools.partial(SOP1, SOP1Op.S_MOV_B32)
 s_mov_b64 = functools.partial(SOP1, SOP1Op.S_MOV_B64)
 s_cmov_b32 = functools.partial(SOP1, SOP1Op.S_CMOV_B32)
@@ -711,6 +725,7 @@ s_orn1_saveexec_b64 = functools.partial(SOP1, SOP1Op.S_ORN1_SAVEEXEC_B64)
 s_andn1_wrexec_b64 = functools.partial(SOP1, SOP1Op.S_ANDN1_WREXEC_B64)
 s_andn2_wrexec_b64 = functools.partial(SOP1, SOP1Op.S_ANDN2_WREXEC_B64)
 s_bitreplicate_b64_b32 = functools.partial(SOP1, SOP1Op.S_BITREPLICATE_B64_B32)
+cdna4 = functools.partial(SOP1, SOP1Op.CDNA4)
 s_add_u32 = functools.partial(SOP2, SOP2Op.S_ADD_U32)
 s_sub_u32 = functools.partial(SOP2, SOP2Op.S_SUB_U32)
 s_add_i32 = functools.partial(SOP2, SOP2Op.S_ADD_I32)
@@ -763,6 +778,7 @@ s_lshl4_add_u32 = functools.partial(SOP2, SOP2Op.S_LSHL4_ADD_U32)
 s_pack_ll_b32_b16 = functools.partial(SOP2, SOP2Op.S_PACK_LL_B32_B16)
 s_pack_lh_b32_b16 = functools.partial(SOP2, SOP2Op.S_PACK_LH_B32_B16)
 s_pack_hh_b32_b16 = functools.partial(SOP2, SOP2Op.S_PACK_HH_B32_B16)
+cdna4 = functools.partial(SOP2, SOP2Op.CDNA4)
 s_cmp_eq_i32 = functools.partial(SOPC, SOPCOp.S_CMP_EQ_I32)
 s_cmp_lg_i32 = functools.partial(SOPC, SOPCOp.S_CMP_LG_I32)
 s_cmp_gt_i32 = functools.partial(SOPC, SOPCOp.S_CMP_GT_I32)
@@ -783,6 +799,7 @@ s_setvskip = functools.partial(SOPC, SOPCOp.S_SETVSKIP)
 s_set_gpr_idx_on = functools.partial(SOPC, SOPCOp.S_SET_GPR_IDX_ON)
 s_cmp_eq_u64 = functools.partial(SOPC, SOPCOp.S_CMP_EQ_U64)
 s_cmp_lg_u64 = functools.partial(SOPC, SOPCOp.S_CMP_LG_U64)
+cdna4 = functools.partial(SOPC, SOPCOp.CDNA4)
 s_movk_i32 = functools.partial(SOPK, SOPKOp.S_MOVK_I32)
 s_cmovk_i32 = functools.partial(SOPK, SOPKOp.S_CMOVK_I32)
 s_cmpk_eq_i32 = functools.partial(SOPK, SOPKOp.S_CMPK_EQ_I32)
@@ -834,6 +851,7 @@ s_cbranch_cdbgsys_and_user = functools.partial(SOPP, SOPPOp.S_CBRANCH_CDBGSYS_AN
 s_endpgm_saved = functools.partial(SOPP, SOPPOp.S_ENDPGM_SAVED)
 s_set_gpr_idx_off = functools.partial(SOPP, SOPPOp.S_SET_GPR_IDX_OFF)
 s_set_gpr_idx_mode = functools.partial(SOPP, SOPPOp.S_SET_GPR_IDX_MODE)
+cdna4 = functools.partial(SOPP, SOPPOp.CDNA4)
 v_nop_e32 = functools.partial(VOP1, VOP1Op.V_NOP)
 v_mov_b32_e32 = functools.partial(VOP1, VOP1Op.V_MOV_B32)
 v_readfirstlane_b32_e32 = functools.partial(VOP1, VOP1Op.V_READFIRSTLANE_B32)
@@ -919,6 +937,7 @@ v_prng_b32_e32 = functools.partial(VOP1, VOP1Op.V_PRNG_B32)
 v_permlane16_swap_b32_e32 = functools.partial(VOP1, VOP1Op.V_PERMLANE16_SWAP_B32)
 v_permlane32_swap_b32_e32 = functools.partial(VOP1, VOP1Op.V_PERMLANE32_SWAP_B32)
 v_cvt_f32_bf16_e32 = functools.partial(VOP1, VOP1Op.V_CVT_F32_BF16)
+cdna4_e32 = functools.partial(VOP1, VOP1Op.CDNA4)
 v_cndmask_b32_e32 = functools.partial(VOP2, VOP2Op.V_CNDMASK_B32)
 v_add_f32_e32 = functools.partial(VOP2, VOP2Op.V_ADD_F32)
 v_sub_f32_e32 = functools.partial(VOP2, VOP2Op.V_SUB_F32)
@@ -942,8 +961,8 @@ v_and_b32_e32 = functools.partial(VOP2, VOP2Op.V_AND_B32)
 v_or_b32_e32 = functools.partial(VOP2, VOP2Op.V_OR_B32)
 v_xor_b32_e32 = functools.partial(VOP2, VOP2Op.V_XOR_B32)
 v_dot2c_f32_bf16_e32 = functools.partial(VOP2, VOP2Op.V_DOT2C_F32_BF16)
-v_fmamk_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAMK_F32)
-v_fmaak_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAAK_F32)
+def v_fmamk_f32_e32(vdst, src0, K, vsrc1): return VOP2(VOP2Op.V_FMAMK_F32, vdst, src0, vsrc1, literal=K)
+def v_fmaak_f32_e32(vdst, src0, vsrc1, K): return VOP2(VOP2Op.V_FMAAK_F32, vdst, src0, vsrc1, literal=K)
 v_add_co_u32_e32 = functools.partial(VOP2, VOP2Op.V_ADD_CO_U32)
 v_sub_co_u32_e32 = functools.partial(VOP2, VOP2Op.V_SUB_CO_U32)
 v_subrev_co_u32_e32 = functools.partial(VOP2, VOP2Op.V_SUBREV_CO_U32)
@@ -981,6 +1000,7 @@ v_dot8c_i32_i4_e32 = functools.partial(VOP2, VOP2Op.V_DOT8C_I32_I4)
 v_fmac_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAC_F32)
 v_pk_fmac_f16_e32 = functools.partial(VOP2, VOP2Op.V_PK_FMAC_F16)
 v_xnor_b32_e32 = functools.partial(VOP2, VOP2Op.V_XNOR_B32)
+cdna4_e32 = functools.partial(VOP2, VOP2Op.CDNA4)
 v_cmp_class_f32 = functools.partial(VOP3A, VOP3AOp.V_CMP_CLASS_F32)
 v_cmpx_class_f32 = functools.partial(VOP3A, VOP3AOp.V_CMPX_CLASS_F32)
 v_cmp_class_f64 = functools.partial(VOP3A, VOP3AOp.V_CMP_CLASS_F64)
@@ -1398,7 +1418,7 @@ v_cvt_scalef32_sr_pk32_fp6_f32 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32
 v_cvt_scalef32_sr_pk32_bf6_f32 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_SR_PK32_BF6_F32)
 v_cvt_scalef32_pk32_f32_fp6 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_PK32_F32_FP6)
 v_cvt_scalef32_pk32_f32_bf6 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_PK32_F32_BF6)
-v_cvt_scalef32_pk32_fp6_f16 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_PK32_FP6_F16)
+cdna4 = functools.partial(VOP3A, VOP3AOp.CDNA4)
 v_cvt_scalef32_pk32_fp6_bf16 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_PK32_FP6_BF16)
 v_cvt_scalef32_pk32_bf6_f16 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_PK32_BF6_F16)
 v_cvt_scalef32_pk32_bf6_bf16 = functools.partial(VOP3A, VOP3AOp.V_CVT_SCALEF32_PK32_BF6_BF16)
@@ -1466,6 +1486,7 @@ v_div_scale_f32 = functools.partial(VOP3B, VOP3BOp.V_DIV_SCALE_F32)
 v_div_scale_f64 = functools.partial(VOP3B, VOP3BOp.V_DIV_SCALE_F64)
 v_mad_u64_u32 = functools.partial(VOP3B, VOP3BOp.V_MAD_U64_U32)
 v_mad_i64_i32 = functools.partial(VOP3B, VOP3BOp.V_MAD_I64_I32)
+cdna4 = functools.partial(VOP3B, VOP3BOp.CDNA4)
 v_pk_mad_i16 = functools.partial(VOP3P, VOP3POp.V_PK_MAD_I16)
 v_pk_mul_lo_u16 = functools.partial(VOP3P, VOP3POp.V_PK_MUL_LO_U16)
 v_pk_add_i16 = functools.partial(VOP3P, VOP3POp.V_PK_ADD_I16)
@@ -1513,6 +1534,8 @@ v_smfmac_i32_16x16x128_i8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_I32_16X16X
 v_smfmac_f32_16x16x128_bf8_bf8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_16X16X128_BF8_BF8)
 v_smfmac_f32_16x16x128_bf8_fp8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_16X16X128_BF8_FP8)
 v_smfmac_f32_16x16x128_fp8_bf8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_16X16X128_FP8_BF8)
+v_mfma_f32_16x16x8_xf32 = functools.partial(VOP3P, VOP3POp.V_MFMA_F32_16X16X8_XF32)
+v_mfma_f32_32x32x4_xf32 = functools.partial(VOP3P, VOP3POp.V_MFMA_F32_32X32X4_XF32)
 v_mfma_f32_32x32x1_2b_f32 = functools.partial(VOP3P, VOP3POp.V_MFMA_F32_32X32X1_2B_F32)
 v_mfma_f32_16x16x1_4b_f32 = functools.partial(VOP3P, VOP3POp.V_MFMA_F32_16X16X1_4B_F32)
 v_mfma_f32_4x4x1_16b_f32 = functools.partial(VOP3P, VOP3POp.V_MFMA_F32_4X4X1_16B_F32)
@@ -1570,6 +1593,7 @@ v_smfmac_f32_32x32x32_bf8_bf8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_32
 v_smfmac_f32_32x32x32_bf8_fp8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_32X32X32_BF8_FP8)
 v_smfmac_f32_32x32x32_fp8_bf8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_32X32X32_FP8_BF8)
 v_smfmac_f32_32x32x32_fp8_fp8 = functools.partial(VOP3P, VOP3POp.V_SMFMAC_F32_32X32X32_FP8_FP8)
+cdna4 = functools.partial(VOP3P, VOP3POp.CDNA4)
 v_cmp_class_f32_e32 = functools.partial(VOPC, VOPCOp.V_CMP_CLASS_F32)
 v_cmpx_class_f32_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_CLASS_F32)
 v_cmp_class_f64_e32 = functools.partial(VOPC, VOPCOp.V_CMP_CLASS_F64)
@@ -1767,4 +1791,42 @@ v_cmpx_le_u64_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_LE_U64)
 v_cmpx_gt_u64_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_GT_U64)
 v_cmpx_ne_u64_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_NE_U64)
 v_cmpx_ge_u64_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_GE_U64)
-v_cmpx_t_u64_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_T_U64)
+v_cmpx_t_u64_e32 = functools.partial(VOPC, VOPCOp.V_CMPX_T_U64)
+cdna4_e32 = functools.partial(VOPC, VOPCOp.CDNA4)
+
+S_ADD_U32 = SrcEnum.S_ADD_U32
+S_SUB_U32 = SrcEnum.S_SUB_U32
+S_ADD_I32 = SrcEnum.S_ADD_I32
+S_SUB_I32 = SrcEnum.S_SUB_I32
+S_ADDC_U32 = SrcEnum.S_ADDC_U32
+S_SUBB_U32 = SrcEnum.S_SUBB_U32
+S_MIN_I32 = SrcEnum.S_MIN_I32
+FLAT_SCRATCH_LO = SrcEnum.FLAT_SCRATCH_LO
+FLAT_SCRATCH_HI = SrcEnum.FLAT_SCRATCH_HI
+XNACK_MASK_LO = SrcEnum.XNACK_MASK_LO
+XNACK_MASK_HI = SrcEnum.XNACK_MASK_HI
+VCC_LO = SrcEnum.VCC_LO
+VCC_HI = SrcEnum.VCC_HI
+M0 = SrcEnum.M0
+EXEC_LO = SrcEnum.EXEC_LO
+EXEC_HI = SrcEnum.EXEC_HI
+ZERO = SrcEnum.ZERO
+DPP8FI = SrcEnum.DPP8FI
+SHARED_BASE = SrcEnum.SHARED_BASE
+SHARED_LIMIT = SrcEnum.SHARED_LIMIT
+PRIVATE_BASE = SrcEnum.PRIVATE_BASE
+PRIVATE_LIMIT = SrcEnum.PRIVATE_LIMIT
+RESERVED = SrcEnum.RESERVED
+POS_HALF = SrcEnum.POS_HALF
+NEG_HALF = SrcEnum.NEG_HALF
+POS_ONE = SrcEnum.POS_ONE
+NEG_ONE = SrcEnum.NEG_ONE
+POS_TWO = SrcEnum.POS_TWO
+NEG_TWO = SrcEnum.NEG_TWO
+POS_FOUR = SrcEnum.POS_FOUR
+NEG_FOUR = SrcEnum.NEG_FOUR
+INV_2PI = SrcEnum.INV_2PI
+VCCZ = SrcEnum.VCCZ
+EXECZ = SrcEnum.EXECZ
+SCC = SrcEnum.SCC
+LDS_DIRECT = SrcEnum.LDS_DIRECT
@@ -1,97 +1,34 @@
-# autogenerated from AMD ISA PDF by pdf.py - do not edit
+# autogenerated from AMD RDNA3.5 ISA PDF by pdf.py - do not edit
 from enum import IntEnum

-class BufFmt(IntEnum):
-  BUF_FMT_8_UNORM = 1
-  BUF_FMT_8_SNORM = 2
-  BUF_FMT_8_USCALED = 3
-  BUF_FMT_8_SSCALED = 4
-  BUF_FMT_8_UINT = 5
-  BUF_FMT_8_SINT = 6
-  BUF_FMT_16_UNORM = 7
-  BUF_FMT_16_SNORM = 8
-  BUF_FMT_16_USCALED = 9
-  BUF_FMT_16_SSCALED = 10
-  BUF_FMT_16_UINT = 11
-  BUF_FMT_16_SINT = 12
-  BUF_FMT_16_FLOAT = 13
-  BUF_FMT_8_8_UNORM = 14
-  BUF_FMT_8_8_SNORM = 15
-  BUF_FMT_8_8_USCALED = 16
-  BUF_FMT_8_8_SSCALED = 17
-  BUF_FMT_8_8_UINT = 18
-  BUF_FMT_8_8_SINT = 19
-  BUF_FMT_32_UINT = 20
-  BUF_FMT_32_SINT = 21
-  BUF_FMT_32_FLOAT = 22
-  BUF_FMT_16_16_UNORM = 23
-  BUF_FMT_16_16_SNORM = 24
-  BUF_FMT_16_16_USCALED = 25
-  BUF_FMT_16_16_SSCALED = 26
-  BUF_FMT_16_16_UINT = 27
-  BUF_FMT_16_16_SINT = 28
-  BUF_FMT_16_16_FLOAT = 29
-  BUF_FMT_10_11_11_FLOAT = 30
-  BUF_FMT_11_11_10_FLOAT = 31
-  BUF_FMT_10_10_10_2_UNORM = 32
-  BUF_FMT_10_10_10_2_SNORM = 33
-  BUF_FMT_10_10_10_2_UINT = 34
-  BUF_FMT_10_10_10_2_SINT = 35
-  BUF_FMT_2_10_10_10_UNORM = 36
-  BUF_FMT_2_10_10_10_SNORM = 37
-  BUF_FMT_2_10_10_10_USCALED = 38
-  BUF_FMT_2_10_10_10_SSCALED = 39
-  BUF_FMT_2_10_10_10_UINT = 40
-  BUF_FMT_2_10_10_10_SINT = 41
-  BUF_FMT_8_8_8_8_UNORM = 42
-  BUF_FMT_8_8_8_8_SNORM = 43
-  BUF_FMT_8_8_8_8_USCALED = 44
-  BUF_FMT_8_8_8_8_SSCALED = 45
-  BUF_FMT_8_8_8_8_UINT = 46
-  BUF_FMT_8_8_8_8_SINT = 47
-  BUF_FMT_32_32_UINT = 48
-  BUF_FMT_32_32_SINT = 49
-  BUF_FMT_32_32_FLOAT = 50
-  BUF_FMT_16_16_16_16_UNORM = 51
-  BUF_FMT_16_16_16_16_SNORM = 52
-  BUF_FMT_16_16_16_16_USCALED = 53
-  BUF_FMT_16_16_16_16_SSCALED = 54
-  BUF_FMT_16_16_16_16_UINT = 55
-  BUF_FMT_16_16_16_16_SINT = 56
-  BUF_FMT_16_16_16_16_FLOAT = 57
-  BUF_FMT_32_32_32_UINT = 58
-  BUF_FMT_32_32_32_SINT = 59
-  BUF_FMT_32_32_32_FLOAT = 60
-  BUF_FMT_32_32_32_32_UINT = 61
-  BUF_FMT_8_SRGB = 64
-  BUF_FMT_8_8_SRGB = 65
-  BUF_FMT_8_8_8_8_SRGB = 66
-  BUF_FMT_5_9_9_9_FLOAT = 67
-  BUF_FMT_5_6_5_UNORM = 68
-  BUF_FMT_1_5_5_5_UNORM = 69
-  BUF_FMT_5_5_5_1_UNORM = 70
-  BUF_FMT_4_4_4_4_UNORM = 71
-  BUF_FMT_4_4_UNORM = 72
-  BUF_FMT_1_UNORM = 73
-  BUF_FMT_1_REVERSED_UNORM = 74
-  BUF_FMT_32_FLOAT_CLAMP = 75
-  BUF_FMT_8_24_UNORM = 76
-  BUF_FMT_8_24_UINT = 77
-  BUF_FMT_24_8_UNORM = 78
-  BUF_FMT_24_8_UINT = 79
-  BUF_FMT_X24_8_32_UINT = 80
-  BUF_FMT_X24_8_32_FLOAT = 81
-  BUF_FMT_GB_GR_UNORM = 82
-  BUF_FMT_GB_GR_SNORM = 83
-  BUF_FMT_GB_GR_UINT = 84
-  BUF_FMT_GB_GR_SRGB = 85
-  BUF_FMT_BG_RG_UNORM = 86
-  BUF_FMT_BG_RG_SNORM = 87
-  BUF_FMT_BG_RG_UINT = 88
-  BUF_FMT_BG_RG_SRGB = 89
-  BUF_FMT_BC1_UNORM = 109
-  BUF_FMT_BC1_SRGB = 110
-  BUF_FMT_BC2_UNORM = 111
+class SrcEnum(IntEnum):
+  VCC_LO = 106
+  VCC_HI = 107
+  NULL = 124
+  M0 = 125
+  EXEC_LO = 126
+  EXEC_HI = 127
+  ZERO = 128
+  DPP8 = 233
+  DPP8FI = 234
+  SHARED_BASE = 235
+  SHARED_LIMIT = 236
+  PRIVATE_BASE = 237
+  PRIVATE_LIMIT = 238
+  POS_HALF = 240
+  NEG_HALF = 241
+  POS_ONE = 242
+  NEG_ONE = 243
+  POS_TWO = 244
+  NEG_TWO = 245
+  POS_FOUR = 246
+  NEG_FOUR = 247
+  INV_2PI = 248
+  DPP16 = 250
+  VCCZ = 251
+  EXECZ = 252
+  SCC = 253
+  LDS_DIRECT = 254

 class DSOp(IntEnum):
  DS_ADD_U32 = 0
@@ -551,8 +488,6 @@ class SMEMOp(IntEnum):
  S_BUFFER_LOAD_B512 = 12
  S_GL1_INV = 32
  S_DCACHE_INV = 33
-  S_ATC_PROBE = 34
-  S_ATC_PROBE_BUFFER = 35

 class SOP1Op(IntEnum):
  S_MOV_B32 = 0
@@ -775,8 +710,6 @@ class SOPKOp(IntEnum):
  S_SETREG_B32 = 18
  S_SETREG_IMM32_B32 = 19
  S_CALL_B64 = 20
-  S_SUBVECTOR_LOOP_BEGIN = 22
-  S_SUBVECTOR_LOOP_END = 23
  S_WAITCNT_VSCNT = 24
  S_WAITCNT_VMCNT = 25
  S_WAITCNT_EXPCNT = 26
@@ -818,8 +751,6 @@ class SOPPOp(IntEnum):
  S_SENDMSGHALT = 55
  S_INCPERFLEVEL = 56
  S_DECPERFLEVEL = 57
-  S_TTRACEDATA = 58
-  S_TTRACEDATA_IMM = 59
  S_ICACHE_INV = 60
  S_BARRIER = 61

@@ -1435,6 +1366,7 @@ class VOP3POp(IntEnum):
  V_WMMA_I32_16X16X16_IU4 = 69

 class VOP3SDOp(IntEnum):
+  DWORD = 1
  V_ADD_CO_CI_U32 = 288
  V_SUB_CO_CI_U32 = 289
  V_SUBREV_CO_CI_U32 = 290
@@ -1,11 +1,12 @@
-# autogenerated from AMD ISA PDF by pdf.py - do not edit
+# autogenerated from AMD RDNA3.5 ISA PDF by pdf.py - do not edit
 # ruff: noqa: F401,F403
 from typing import Annotated
-from extra.assembly.amd.dsl import *
+from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField
 from extra.assembly.amd.autogen.rdna3.enum import *
 import functools

-class DPP16(Inst):
+# instruction formats
+class DPP16(Inst64):
  src0:Src = bits[39:32]
  dpp_ctrl = bits[48:40]
  fi = bits[50]
@@ -17,7 +18,7 @@ class DPP16(Inst):
  bank_mask = bits[59:56]
  row_mask = bits[63:60]

-class DPP8(Inst):
+class DPP8(Inst64):
  src0:Src = bits[39:32]
  lane_sel0 = bits[42:40]
  lane_sel1 = bits[45:43]
@@ -28,7 +29,7 @@ class DPP8(Inst):
  lane_sel6 = bits[60:58]
  lane_sel7 = bits[63:61]

-class DS(Inst):
+class DS(Inst64):
  encoding = bits[31:26] == 0b110110
  op:Annotated[BitField, DSOp] = bits[25:18]
  vdst:VGPRField = bits[63:56]
@@ -39,18 +40,18 @@ class DS(Inst):
  offset1 = bits[15:8]
  gds = bits[17]

-class EXP(Inst):
+class EXP(Inst64):
  encoding = bits[31:26] == 0b111110
-  vsrc0:VGPRField = bits[39:32]
-  vsrc1:VGPRField = bits[47:40]
-  vsrc2:VGPRField = bits[55:48]
-  vsrc3:VGPRField = bits[63:56]
  en = bits[3:0]
  target = bits[9:4]
+  vsrc0 = bits[39:32]
+  vsrc1:VGPRField = bits[47:40]
+  vsrc2 = bits[55:48]
+  vsrc3 = bits[63:56]
  done = bits[11]
  row = bits[13]

-class FLAT(Inst):
+class FLAT(Inst64):
  encoding = bits[31:26] == 0b110111
  op:Annotated[BitField, FLATOp] = bits[24:18]
  vdst:VGPRField = bits[63:56]
@@ -59,12 +60,12 @@ class FLAT(Inst):
  saddr:SSrc = bits[54:48]
  offset:Imm = bits[12:0]
  seg = bits[17:16]
-  glc = bits[14]
  dlc = bits[13]
+  glc = bits[14]
  slc = bits[15]
  sve = bits[55]

-class LDSDIR(Inst):
+class LDSDIR(Inst32):
  encoding = bits[31:24] == 0b11001110
  op = bits[21:20]
  vdst:VGPRField = bits[7:0]
@@ -72,29 +73,29 @@ class LDSDIR(Inst):
  attr_chan = bits[9:8]
  wait_va = bits[19:16]

-class MIMG(Inst):
+class MIMG(Inst64):
  encoding = bits[31:26] == 0b111100
  op:Annotated[BitField, MIMGOp] = bits[25:18]
  vdata:VGPRField = bits[47:40]
  vaddr:VGPRField = bits[39:32]
  srsrc:SGPRField = bits[52:48]
-  ssamp:SGPRField = bits[62:58]
+  ssamp = bits[62:58]
  dmask = bits[11:8]
  dim = bits[4:2]
-  glc = bits[14]
-  dlc = bits[13]
-  slc = bits[12]
-  tfe = bits[53]
  unrm = bits[7]
+  dlc = bits[13]
+  glc = bits[14]
+  slc = bits[12]
  nsa = bits[0]
  r128 = bits[15]
  a16 = bits[16]
  d16 = bits[17]
+  tfe = bits[53]
  lwe = bits[54]
  addr1 = bits[71:64]
  addr2 = bits[79:72]

-class MTBUF(Inst):
+class MTBUF(Inst64):
  encoding = bits[31:26] == 0b111010
  op:Annotated[BitField, MTBUFOp] = bits[18:15]
  vdata:VGPRField = bits[47:40]
@@ -110,7 +111,7 @@ class MTBUF(Inst):
  slc = bits[12]
  tfe = bits[53]

-class MUBUF(Inst):
+class MUBUF(Inst64):
  encoding = bits[31:26] == 0b111000
  op:Annotated[BitField, MUBUFOp] = bits[25:18]
  vdata:VGPRField = bits[47:40]
@@ -125,7 +126,7 @@ class MUBUF(Inst):
  slc = bits[12]
  tfe = bits[53]

-class SMEM(Inst):
+class SMEM(Inst64):
  encoding = bits[31:26] == 0b111101
  op:Annotated[BitField, SMEMOp] = bits[25:18]
  sdata:SGPRField = bits[12:6]
@@ -135,63 +136,62 @@ class SMEM(Inst):
  glc = bits[14]
  dlc = bits[13]

-class SOP1(Inst):
+class SOP1(Inst32):
  encoding = bits[31:23] == 0b101111101
  op:Annotated[BitField, SOP1Op] = bits[15:8]
  sdst:SGPRField = bits[22:16]
  ssrc0:SSrc = bits[7:0]

-class SOP2(Inst):
+class SOP2(Inst32):
  encoding = bits[31:30] == 0b10
  op:Annotated[BitField, SOP2Op] = bits[29:23]
  sdst:SGPRField = bits[22:16]
  ssrc0:SSrc = bits[7:0]
  ssrc1:SSrc = bits[15:8]

-class SOPC(Inst):
+class SOPC(Inst32):
  encoding = bits[31:23] == 0b101111110
  op:Annotated[BitField, SOPCOp] = bits[22:16]
  ssrc0:SSrc = bits[7:0]
  ssrc1:SSrc = bits[15:8]

-class SOPK(Inst):
+class SOPK(Inst32):
  encoding = bits[31:28] == 0b1011
  op:Annotated[BitField, SOPKOp] = bits[27:23]
  sdst:SGPRField = bits[22:16]
  simm16:SImm = bits[15:0]

-class SOPP(Inst):
+class SOPP(Inst32):
  encoding = bits[31:23] == 0b101111111
  op:Annotated[BitField, SOPPOp] = bits[22:16]
  simm16:SImm = bits[15:0]

-class VINTERP(Inst):
+class VINTERP(Inst64):
  encoding = bits[31:24] == 0b11001101
  op:Annotated[BitField, VINTERPOp] = bits[22:16]
  vdst:VGPRField = bits[7:0]
  src0:Src = bits[40:32]
-  src0:Src = bits[40:32]
  src1:Src = bits[49:41]
  src2:Src = bits[58:50]
-  neg = bits[63:61]
+  waitexp = bits[10:8]
  clmp = bits[15]
  opsel = bits[14:11]
-  waitexp = bits[10:8]
+  neg = bits[63:61]

-class VOP1(Inst):
-  encoding = bits[31:25] == 0b0111111
+class VOP1(Inst32):
+  encoding = bits[31:25] == 0b111111
  op:Annotated[BitField, VOP1Op] = bits[16:9]
  vdst:VGPRField = bits[24:17]
  src0:Src = bits[8:0]

-class VOP2(Inst):
-  encoding = bits[31] == 0b0
+class VOP2(Inst32):
+  encoding = bits[31] == 0
  op:Annotated[BitField, VOP2Op] = bits[30:25]
  vdst:VGPRField = bits[24:17]
  src0:Src = bits[8:0]
  vsrc1:VGPRField = bits[16:9]

-class VOP3(Inst):
+class VOP3(Inst64):
  encoding = bits[31:26] == 0b110101
  op:Annotated[BitField, VOP3Op] = bits[25:16]
  vdst:VGPRField = bits[7:0]
@@ -204,8 +204,9 @@ class VOP3(Inst):
  clmp = bits[15]
  opsel = bits[14:11]

-class VOP3P(Inst):
+class VOP3P(Inst64):
  encoding = bits[31:24] == 0b11001100
+  _defaults = {'opsel_hi': 3, 'opsel_hi2': 1}
  op:Annotated[BitField, VOP3POp] = bits[22:16]
  vdst:VGPRField = bits[7:0]
  src0:Src = bits[40:32]
@@ -213,12 +214,12 @@ class VOP3P(Inst):
  src2:Src = bits[58:50]
  neg = bits[63:61]
  neg_hi = bits[10:8]
-  clmp = bits[15]
  opsel = bits[13:11]
  opsel_hi = bits[60:59]
+  clmp = bits[15]
  opsel_hi2 = bits[14]

-class VOP3SD(Inst):
+class VOP3SD(Inst64):
  encoding = bits[31:26] == 0b110101
  op:Annotated[BitField, VOP3SDOp] = bits[25:16]
  vdst:VGPRField = bits[7:0]
@@ -226,26 +227,26 @@ class VOP3SD(Inst):
  src0:Src = bits[40:32]
  src1:Src = bits[49:41]
  src2:Src = bits[58:50]
+  clmp = bits[15]
  omod = bits[60:59]
  neg = bits[63:61]
-  clmp = bits[15]

-class VOPC(Inst):
-  encoding = bits[31:25] == 0b0111110
+class VOPC(Inst32):
+  encoding = bits[31:25] == 0b111110
  op:Annotated[BitField, VOPCOp] = bits[24:17]
  src0:Src = bits[8:0]
  vsrc1:VGPRField = bits[16:9]

-class VOPD(Inst):
+class VOPD(Inst64):
  encoding = bits[31:26] == 0b110010
  opx:Annotated[BitField, VOPDOp] = bits[25:22]
  opy:Annotated[BitField, VOPDOp] = bits[21:17]
-  vdstx = bits[63:56]
+  vdstx:VGPRField = bits[63:56]
  vdsty:VDSTYEnc = bits[55:49]
  srcx0:Src = bits[8:0]
+  vsrcx1:VGPRField = bits[16:9]
  srcy0:Src = bits[40:32]
-  vsrcx1 = bits[16:9]
-  vsrcy1 = bits[48:41]
+  vsrcy1:VGPRField = bits[48:41]

 # instruction helpers
 ds_add_u32 = functools.partial(DS, DSOp.DS_ADD_U32)
@@ -691,8 +692,6 @@ s_buffer_load_b256 = functools.partial(SMEM, SMEMOp.S_BUFFER_LOAD_B256)
 s_buffer_load_b512 = functools.partial(SMEM, SMEMOp.S_BUFFER_LOAD_B512)
 s_gl1_inv = functools.partial(SMEM, SMEMOp.S_GL1_INV)
 s_dcache_inv = functools.partial(SMEM, SMEMOp.S_DCACHE_INV)
-s_atc_probe = functools.partial(SMEM, SMEMOp.S_ATC_PROBE)
-s_atc_probe_buffer = functools.partial(SMEM, SMEMOp.S_ATC_PROBE_BUFFER)
 s_mov_b32 = functools.partial(SOP1, SOP1Op.S_MOV_B32)
 s_mov_b64 = functools.partial(SOP1, SOP1Op.S_MOV_B64)
 s_cmov_b32 = functools.partial(SOP1, SOP1Op.S_CMOV_B32)
@@ -907,8 +906,6 @@ s_getreg_b32 = functools.partial(SOPK, SOPKOp.S_GETREG_B32)
 s_setreg_b32 = functools.partial(SOPK, SOPKOp.S_SETREG_B32)
 s_setreg_imm32_b32 = functools.partial(SOPK, SOPKOp.S_SETREG_IMM32_B32)
 s_call_b64 = functools.partial(SOPK, SOPKOp.S_CALL_B64)
-s_subvector_loop_begin = functools.partial(SOPK, SOPKOp.S_SUBVECTOR_LOOP_BEGIN)
-s_subvector_loop_end = functools.partial(SOPK, SOPKOp.S_SUBVECTOR_LOOP_END)
 s_waitcnt_vscnt = functools.partial(SOPK, SOPKOp.S_WAITCNT_VSCNT)
 s_waitcnt_vmcnt = functools.partial(SOPK, SOPKOp.S_WAITCNT_VMCNT)
 s_waitcnt_expcnt = functools.partial(SOPK, SOPKOp.S_WAITCNT_EXPCNT)
@@ -948,8 +945,6 @@ s_sendmsg = functools.partial(SOPP, SOPPOp.S_SENDMSG)
 s_sendmsghalt = functools.partial(SOPP, SOPPOp.S_SENDMSGHALT)
 s_incperflevel = functools.partial(SOPP, SOPPOp.S_INCPERFLEVEL)
 s_decperflevel = functools.partial(SOPP, SOPPOp.S_DECPERFLEVEL)
-s_ttracedata = functools.partial(SOPP, SOPPOp.S_TTRACEDATA)
-s_ttracedata_imm = functools.partial(SOPP, SOPPOp.S_TTRACEDATA_IMM)
 s_icache_inv = functools.partial(SOPP, SOPPOp.S_ICACHE_INV)
 s_barrier = functools.partial(SOPP, SOPPOp.S_BARRIER)
 v_interp_p10_f32 = functools.partial(VINTERP, VINTERPOp.V_INTERP_P10_F32)
@@ -1076,16 +1071,16 @@ v_add_nc_u32_e32 = functools.partial(VOP2, VOP2Op.V_ADD_NC_U32)
 v_sub_nc_u32_e32 = functools.partial(VOP2, VOP2Op.V_SUB_NC_U32)
 v_subrev_nc_u32_e32 = functools.partial(VOP2, VOP2Op.V_SUBREV_NC_U32)
 v_fmac_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAC_F32)
-v_fmamk_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAMK_F32)
-v_fmaak_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAAK_F32)
+def v_fmamk_f32_e32(vdst, src0, K, vsrc1): return VOP2(VOP2Op.V_FMAMK_F32, vdst, src0, vsrc1, literal=K)
+def v_fmaak_f32_e32(vdst, src0, vsrc1, K): return VOP2(VOP2Op.V_FMAAK_F32, vdst, src0, vsrc1, literal=K)
 v_cvt_pk_rtz_f16_f32_e32 = functools.partial(VOP2, VOP2Op.V_CVT_PK_RTZ_F16_F32)
 v_add_f16_e32 = functools.partial(VOP2, VOP2Op.V_ADD_F16)
 v_sub_f16_e32 = functools.partial(VOP2, VOP2Op.V_SUB_F16)
 v_subrev_f16_e32 = functools.partial(VOP2, VOP2Op.V_SUBREV_F16)
 v_mul_f16_e32 = functools.partial(VOP2, VOP2Op.V_MUL_F16)
 v_fmac_f16_e32 = functools.partial(VOP2, VOP2Op.V_FMAC_F16)
-v_fmamk_f16_e32 = functools.partial(VOP2, VOP2Op.V_FMAMK_F16)
-v_fmaak_f16_e32 = functools.partial(VOP2, VOP2Op.V_FMAAK_F16)
+def v_fmamk_f16_e32(vdst, src0, K, vsrc1): return VOP2(VOP2Op.V_FMAMK_F16, vdst, src0, vsrc1, literal=K)
+def v_fmaak_f16_e32(vdst, src0, vsrc1, K): return VOP2(VOP2Op.V_FMAAK_F16, vdst, src0, vsrc1, literal=K)
 v_max_f16_e32 = functools.partial(VOP2, VOP2Op.V_MAX_F16)
 v_min_f16_e32 = functools.partial(VOP2, VOP2Op.V_MIN_F16)
 v_ldexp_f16_e32 = functools.partial(VOP2, VOP2Op.V_LDEXP_F16)
@@ -1553,6 +1548,7 @@ v_wmma_f16_16x16x16_f16 = functools.partial(VOP3P, VOP3POp.V_WMMA_F16_16X16X16_F
 v_wmma_bf16_16x16x16_bf16 = functools.partial(VOP3P, VOP3POp.V_WMMA_BF16_16X16X16_BF16)
 v_wmma_i32_16x16x16_iu8 = functools.partial(VOP3P, VOP3POp.V_WMMA_I32_16X16X16_IU8)
 v_wmma_i32_16x16x16_iu4 = functools.partial(VOP3P, VOP3POp.V_WMMA_I32_16X16X16_IU4)
+dword = functools.partial(VOP3SD, VOP3SDOp.DWORD)
 v_add_co_ci_u32 = functools.partial(VOP3SD, VOP3SDOp.V_ADD_CO_CI_U32)
 v_sub_co_ci_u32 = functools.partial(VOP3SD, VOP3SDOp.V_SUB_CO_CI_U32)
 v_subrev_co_ci_u32 = functools.partial(VOP3SD, VOP3SDOp.V_SUBREV_CO_CI_U32)
@@ -1769,4 +1765,31 @@ v_dual_dot2acc_f32_f16 = functools.partial(VOPD, VOPDOp.V_DUAL_DOT2ACC_F32_F16)
 v_dual_dot2acc_f32_bf16 = functools.partial(VOPD, VOPDOp.V_DUAL_DOT2ACC_F32_BF16)
 v_dual_add_nc_u32 = functools.partial(VOPD, VOPDOp.V_DUAL_ADD_NC_U32)
 v_dual_lshlrev_b32 = functools.partial(VOPD, VOPDOp.V_DUAL_LSHLREV_B32)
-v_dual_and_b32 = functools.partial(VOPD, VOPDOp.V_DUAL_AND_B32)
+v_dual_and_b32 = functools.partial(VOPD, VOPDOp.V_DUAL_AND_B32)
+
+VCC_LO = SrcEnum.VCC_LO
+VCC_HI = SrcEnum.VCC_HI
+NULL = SrcEnum.NULL
+M0 = SrcEnum.M0
+EXEC_LO = SrcEnum.EXEC_LO
+EXEC_HI = SrcEnum.EXEC_HI
+ZERO = SrcEnum.ZERO
+DPP8FI = SrcEnum.DPP8FI
+SHARED_BASE = SrcEnum.SHARED_BASE
+SHARED_LIMIT = SrcEnum.SHARED_LIMIT
+PRIVATE_BASE = SrcEnum.PRIVATE_BASE
+PRIVATE_LIMIT = SrcEnum.PRIVATE_LIMIT
+POS_HALF = SrcEnum.POS_HALF
+NEG_HALF = SrcEnum.NEG_HALF
+POS_ONE = SrcEnum.POS_ONE
+NEG_ONE = SrcEnum.NEG_ONE
+POS_TWO = SrcEnum.POS_TWO
+NEG_TWO = SrcEnum.NEG_TWO
+POS_FOUR = SrcEnum.POS_FOUR
+NEG_FOUR = SrcEnum.NEG_FOUR
+INV_2PI = SrcEnum.INV_2PI
+VCCZ = SrcEnum.VCCZ
+EXECZ = SrcEnum.EXECZ
+SCC = SrcEnum.SCC
+LDS_DIRECT = SrcEnum.LDS_DIRECT
+OFF = NULL
@@ -1,100 +1,34 @@
-# autogenerated from AMD ISA PDF by pdf.py - do not edit
+# autogenerated from AMD RDNA4 ISA PDF by pdf.py - do not edit
 from enum import IntEnum

-class BufFmt(IntEnum):
-  BUF_FMT_8_UNORM = 1
-  BUF_FMT_8_SNORM = 2
-  BUF_FMT_8_USCALED = 3
-  BUF_FMT_8_SSCALED = 4
-  BUF_FMT_8_UINT = 5
-  BUF_FMT_8_SINT = 6
-  BUF_FMT_16_UNORM = 7
-  BUF_FMT_16_SNORM = 8
-  BUF_FMT_16_USCALED = 9
-  BUF_FMT_16_SSCALED = 10
-  BUF_FMT_16_UINT = 11
-  BUF_FMT_16_SINT = 12
-  BUF_FMT_16_FLOAT = 13
-  BUF_FMT_8_8_UNORM = 14
-  BUF_FMT_8_8_SNORM = 15
-  BUF_FMT_8_8_USCALED = 16
-  BUF_FMT_8_8_SSCALED = 17
-  BUF_FMT_8_8_UINT = 18
-  BUF_FMT_8_8_SINT = 19
-  BUF_FMT_32_UINT = 20
-  BUF_FMT_32_SINT = 21
-  BUF_FMT_32_FLOAT = 22
-  BUF_FMT_16_16_UNORM = 23
-  BUF_FMT_16_16_SNORM = 24
-  BUF_FMT_16_16_USCALED = 25
-  BUF_FMT_16_16_SSCALED = 26
-  BUF_FMT_16_16_UINT = 27
-  BUF_FMT_16_16_SINT = 28
-  BUF_FMT_16_16_FLOAT = 29
-  BUF_FMT_10_11_11_FLOAT = 30
-  BUF_FMT_11_11_10_FLOAT = 31
-  BUF_FMT_10_10_10_2_UNORM = 32
-  BUF_FMT_10_10_10_2_SNORM = 33
-  BUF_FMT_10_10_10_2_UINT = 34
-  BUF_FMT_10_10_10_2_SINT = 35
-  BUF_FMT_2_10_10_10_UNORM = 36
-  BUF_FMT_2_10_10_10_SNORM = 37
-  BUF_FMT_2_10_10_10_USCALED = 38
-  BUF_FMT_2_10_10_10_SSCALED = 39
-  BUF_FMT_2_10_10_10_UINT = 40
-  BUF_FMT_2_10_10_10_SINT = 41
-  BUF_FMT_8_8_8_8_UNORM = 42
-  BUF_FMT_8_8_8_8_SNORM = 43
-  BUF_FMT_8_8_8_8_USCALED = 44
-  BUF_FMT_8_8_8_8_SSCALED = 45
-  BUF_FMT_8_8_8_8_UINT = 46
-  BUF_FMT_8_8_8_8_SINT = 47
-  BUF_FMT_32_32_UINT = 48
-  BUF_FMT_32_32_SINT = 49
-  BUF_FMT_32_32_FLOAT = 50
-  BUF_FMT_16_16_16_16_UNORM = 51
-  BUF_FMT_16_16_16_16_SNORM = 52
-  BUF_FMT_16_16_16_16_USCALED = 53
-  BUF_FMT_16_16_16_16_SSCALED = 54
-  BUF_FMT_16_16_16_16_UINT = 55
-  BUF_FMT_16_16_16_16_SINT = 56
-  BUF_FMT_16_16_16_16_FLOAT = 57
-  BUF_FMT_32_32_32_UINT = 58
-  BUF_FMT_32_32_32_SINT = 59
-  BUF_FMT_32_32_32_FLOAT = 60
-  BUF_FMT_32_32_32_32_UINT = 61
-  BUF_FMT_32_32_32_32_SINT = 62
-  BUF_FMT_32_32_32_32_FLOAT = 63
-  BUF_FMT_8_SRGB = 64
-  BUF_FMT_8_8_SRGB = 65
-  BUF_FMT_8_8_8_8_SRGB = 66
-  BUF_FMT_5_9_9_9_FLOAT = 67
-  BUF_FMT_5_6_5_UNORM = 68
-  BUF_FMT_1_5_5_5_UNORM = 69
-  BUF_FMT_5_5_5_1_UNORM = 70
-  BUF_FMT_4_4_4_4_UNORM = 71
-  BUF_FMT_4_4_UNORM = 72
-  BUF_FMT_1_UNORM = 73
-  BUF_FMT_1_REVERSED_UNORM = 74
-  BUF_FMT_32_FLOAT_CLAMP = 75
-  BUF_FMT_8_24_UNORM = 76
-  BUF_FMT_8_24_UINT = 77
-  BUF_FMT_24_8_UNORM = 78
-  BUF_FMT_24_8_UINT = 79
-  BUF_FMT_X24_8_32_UINT = 80
-  BUF_FMT_X24_8_32_FLOAT = 81
-  BUF_FMT_GB_GR_UNORM = 82
-  BUF_FMT_GB_GR_SNORM = 83
-  BUF_FMT_GB_GR_UINT = 84
-  BUF_FMT_GB_GR_SRGB = 85
-  BUF_FMT_BG_RG_UNORM = 86
-  BUF_FMT_BG_RG_SNORM = 87
-  BUF_FMT_BG_RG_UINT = 88
-  BUF_FMT_BG_RG_SRGB = 89
-  BUF_FMT_BC1_UNORM = 109
-  BUF_FMT_BC1_SRGB = 110
-  BUF_FMT_BC2_UNORM = 111
-  BUF_FMT_BC2_SRGB = 112
+class SrcEnum(IntEnum):
+  VCC_LO = 106
+  VCC_HI = 107
+  NULL = 124
+  M0 = 125
+  EXEC_LO = 126
+  EXEC_HI = 127
+  ZERO = 128
+  DPP8 = 233
+  DPP8FI = 234
+  SHARED_BASE = 235
+  SHARED_LIMIT = 236
+  PRIVATE_BASE = 237
+  PRIVATE_LIMIT = 238
+  POS_HALF = 240
+  NEG_HALF = 241
+  POS_ONE = 242
+  NEG_ONE = 243
+  POS_TWO = 244
+  NEG_TWO = 245
+  POS_FOUR = 246
+  NEG_FOUR = 247
+  INV_2PI = 248
+  DPP16 = 250
+  VCCZ = 251
+  EXECZ = 252
+  SCC = 253
+  LDS_DIRECT = 254

 class DSOp(IntEnum):
  DS_ADD_U32 = 0
@@ -243,8 +177,6 @@ class SMEMOp(IntEnum):
  S_BUFFER_LOAD_I16 = 26
  S_BUFFER_LOAD_U16 = 27
  S_DCACHE_INV = 33
-  S_ATC_PROBE = 34
-  S_ATC_PROBE_BUFFER = 35
  S_PREFETCH_INST = 36
  S_PREFETCH_INST_PC_REL = 37
  S_PREFETCH_DATA = 38
@@ -320,8 +252,6 @@ class SOP1Op(IntEnum):
  S_BARRIER_SIGNAL = 78
  S_BARRIER_SIGNAL_ISFIRST = 79
  S_GET_BARRIER_STATE = 80
-  S_BARRIER_INIT = 81
-  S_BARRIER_JOIN = 82
  S_ALLOC_VGPR = 83
  S_SLEEP_VAR = 88
  S_CEIL_F32 = 96
@@ -490,7 +420,6 @@ class SOPPOp(IntEnum):
  S_ROUND_MODE = 17
  S_DENORM_MODE = 18
  S_BARRIER_WAIT = 20
-  S_BARRIER_LEAVE = 21
  S_CODE_END = 31
  S_BRANCH = 32
  S_CBRANCH_SCC0 = 33
@@ -507,8 +436,6 @@ class SOPPOp(IntEnum):
  S_SENDMSGHALT = 55
  S_INCPERFLEVEL = 56
  S_DECPERFLEVEL = 57
-  S_TTRACEDATA = 58
-  S_TTRACEDATA_IMM = 59
  S_ICACHE_INV = 60
  S_WAIT_LOADCNT = 64
  S_WAIT_STORECNT = 65
@@ -1420,6 +1347,7 @@ class VOP3POp(IntEnum):
  V_SWMMAC_F32_16X16X32_BF8_BF8 = 90

 class VOP3SDOp(IntEnum):
+  DWORD = 1
  V_ADD_CO_CI_U32 = 288
  V_SUB_CO_CI_U32 = 289
  V_SUBREV_CO_CI_U32 = 290
@@ -1,11 +1,12 @@
-# autogenerated from AMD ISA PDF by pdf.py - do not edit
+# autogenerated from AMD RDNA4 ISA PDF by pdf.py - do not edit
 # ruff: noqa: F401,F403
 from typing import Annotated
-from extra.assembly.amd.dsl import *
+from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField
 from extra.assembly.amd.autogen.rdna4.enum import *
 import functools

-class DPP16(Inst):
+# instruction formats
+class DPP16(Inst64):
  src0:Src = bits[39:32]
  dpp_ctrl = bits[48:40]
  fi = bits[50]
@@ -17,7 +18,7 @@ class DPP16(Inst):
  bank_mask = bits[59:56]
  row_mask = bits[63:60]

-class DPP8(Inst):
+class DPP8(Inst64):
  src0:Src = bits[39:32]
  lane_sel0 = bits[42:40]
  lane_sel1 = bits[45:43]
@@ -28,17 +29,7 @@ class DPP8(Inst):
  lane_sel6 = bits[60:58]
  lane_sel7 = bits[63:61]

-class DS(Inst):
-  encoding = bits[31:26] == 0b110110
-  op:Annotated[BitField, DSOp] = bits[25:18]
-  vdst:VGPRField = bits[63:56]
-  addr:VGPRField = bits[39:32]
-  data0:VGPRField = bits[47:40]
-  data1:VGPRField = bits[55:48]
-  offset0 = bits[7:0]
-  offset1 = bits[15:8]
-
-class SMEM(Inst):
+class SMEM(Inst64):
  encoding = bits[31:26] == 0b111101
  op:Annotated[BitField, SMEMOp] = bits[18:13]
  sdata:SGPRField = bits[12:6]
@@ -48,116 +39,110 @@ class SMEM(Inst):
  th = bits[24:23]
  ioffset = bits[55:32]

-class SOP1(Inst):
+class SOP1(Inst32):
  encoding = bits[31:23] == 0b101111101
  op:Annotated[BitField, SOP1Op] = bits[15:8]
  sdst:SGPRField = bits[22:16]
  ssrc0:SSrc = bits[7:0]

-class SOP2(Inst):
+class SOP2(Inst32):
  encoding = bits[31:30] == 0b10
  op:Annotated[BitField, SOP2Op] = bits[29:23]
  sdst:SGPRField = bits[22:16]
  ssrc0:SSrc = bits[7:0]
  ssrc1:SSrc = bits[15:8]

-class SOPC(Inst):
+class SOPC(Inst32):
  encoding = bits[31:23] == 0b101111110
  op:Annotated[BitField, SOPCOp] = bits[22:16]
  ssrc0:SSrc = bits[7:0]
  ssrc1:SSrc = bits[15:8]

-class SOPK(Inst):
+class SOPK(Inst32):
  encoding = bits[31:28] == 0b1011
  op:Annotated[BitField, SOPKOp] = bits[27:23]
  sdst:SGPRField = bits[22:16]
  simm16:SImm = bits[15:0]

-class SOPP(Inst):
+class SOPP(Inst32):
  encoding = bits[31:23] == 0b101111111
  op:Annotated[BitField, SOPPOp] = bits[22:16]
  simm16:SImm = bits[15:0]

-class VBUFFER(Inst):
+class VBUFFER(Inst64):
  encoding = bits[31:26] == 0b110001
-  op:Annotated[BitField, VBUFFEROp] = bits[21:14]
-  vdata:VGPRField = bits[39:32]
-  vaddr:VGPRField = bits[71:64]
  soffset:SSrc = bits[6:0]
-  format = bits[61:55]
-  offen = bits[62]
-  idxen = bits[63]
+  op:Annotated[BitField, VBUFFEROp] = bits[21:14]
  tfe = bits[22]
+  vdata:VGPRField = bits[39:32]
  rsrc = bits[49:41]
  scope = bits[51:50]
  th = bits[54:52]
+  format = bits[61:55]
+  offen = bits[62]
+  idxen = bits[63]
+  vaddr:VGPRField = bits[71:64]
  ioffset = bits[95:72]

-class VDSDIR(Inst):
-  encoding = bits[31:24] == 0b11001110
-  op:Annotated[BitField, VDSDIROp] = bits[21:20]
-  vdst:VGPRField = bits[7:0]
-  attr = bits[15:10]
-  attr_chan = bits[9:8]
-  wait_va = bits[19:16]
-  wait_vmvsrc = bits[23]
+class VDS(Inst64):
+  encoding = bits[31:26] == 0b110110
+  offset0 = bits[7:0]
+  offset1 = bits[15:8]
+  op = bits[25:18]
+  addr:VGPRField = bits[39:32]
+  data0:VGPRField = bits[47:40]
+  data1:VGPRField = bits[55:48]
+  vdst:VGPRField = bits[63:56]

-class VEXPORT(Inst):
+class VDSDIR(Inst64):
+  encoding = bits[31:24] == 0b11001101
+  vdst:VGPRField = bits[7:0]
+  waitexp = bits[10:8]
+  opsel = bits[14:11]
+  cm = bits[15]
+  op:Annotated[BitField, VDSDIROp] = bits[20:16]
+  src0:Src = bits[40:32]
+  src1:Src = bits[49:41]
+  src2:Src = bits[58:50]
+  neg = bits[63:61]
+
+class VEXPORT(Inst64):
  encoding = bits[31:26] == 0b111110
-  vsrc0:VGPRField = bits[39:32]
-  vsrc1:VGPRField = bits[47:40]
-  vsrc2:VGPRField = bits[55:48]
-  vsrc3:VGPRField = bits[63:56]
  en = bits[3:0]
  target = bits[9:4]
  done = bits[11]
  row = bits[13]
+  vsrc0 = bits[39:32]
+  vsrc1:VGPRField = bits[47:40]
+  vsrc2 = bits[55:48]
+  vsrc3 = bits[63:56]

-class VIMAGE(Inst):
-  encoding = bits[31:26] == 0b110100
-  op:Annotated[BitField, VIMAGEOp] = bits[21:14]
-  vdata:VGPRField = bits[39:32]
-  dmask = bits[25:22]
-  dim = bits[2:0]
-  tfe = bits[55]
-  r128 = bits[4]
-  d16 = bits[5]
-  a16 = bits[6]
-  rsrc = bits[49:41]
-  scope = bits[51:50]
-  th = bits[54:52]
-  vaddr4 = bits[56:63]
-  vaddr0 = bits[71:64]
-  vaddr1 = bits[79:72]
-  vaddr2 = bits[87:80]
-  vaddr3 = bits[95:88]
-
-class VINTERP(Inst):
+class VINTERP(Inst64):
  encoding = bits[31:24] == 0b11001101
  op:Annotated[BitField, VINTERPOp] = bits[20:16]
  vdst:VGPRField = bits[7:0]
  src0:Src = bits[40:32]
  src1:Src = bits[49:41]
  src2:Src = bits[58:50]
-  neg = bits[63:61]
-  opsel = bits[14:11]
  waitexp = bits[10:8]
+  opsel = bits[14:11]
+  neg = bits[63:61]
  cm = bits[15]

-class VOP1(Inst):
-  encoding = bits[31:25] == 0b0111111
+class VOP1(Inst32):
+  encoding = bits[31:25] == 0b111111
  op:Annotated[BitField, VOP1Op] = bits[15:9]
  vdst:VGPRField = bits[24:17]
  src0:Src = bits[8:0]

-class VOP2(Inst):
-  encoding = bits[31] == 0b0
+class VOP2(Inst32):
+  encoding = bits[31] == 0
  op:Annotated[BitField, VOP2Op] = bits[30:25]
  vdst:VGPRField = bits[24:17]
  src0:Src = bits[8:0]
  vsrc1:VGPRField = bits[16:9]

-class VOP3(Inst):
+class VOP3(Inst64):
  encoding = bits[31:26] == 0b110101
  op:Annotated[BitField, VOP3Op] = bits[25:16]
  vdst:VGPRField = bits[7:0]
@@ -170,8 +155,9 @@ class VOP3(Inst):
  opsel = bits[14:11]
  cm = bits[15]

-class VOP3P(Inst):
+class VOP3P(Inst64):
  encoding = bits[31:24] == 0b11001100
+  _defaults = {'opsel_hi': 3, 'opsel_hi2': 1}
  op:Annotated[BitField, VOP3POp] = bits[22:16]
  vdst:VGPRField = bits[7:0]
  src0:Src = bits[40:32]
@@ -184,7 +170,7 @@ class VOP3P(Inst):
  opsel_hi2 = bits[14]
  cm = bits[15]

-class VOP3SD(Inst):
+class VOP3SD(Inst64):
  encoding = bits[31:26] == 0b110101
  op:Annotated[BitField, VOP3SDOp] = bits[25:16]
  vdst:VGPRField = bits[7:0]
@@ -192,172 +178,28 @@ class VOP3SD(Inst):
  src0:Src = bits[40:32]
  src1:Src = bits[49:41]
  src2:Src = bits[58:50]
+  cm = bits[15]
  omod = bits[60:59]
  neg = bits[63:61]
-  cm = bits[15]

-class VOPC(Inst):
-  encoding = bits[31:25] == 0b0111110
+class VOPC(Inst32):
+  encoding = bits[31:25] == 0b111110
  op:Annotated[BitField, VOPCOp] = bits[24:17]
  src0:Src = bits[8:0]
  vsrc1:VGPRField = bits[16:9]

-class VOPD(Inst):
+class VOPD(Inst64):
  encoding = bits[31:26] == 0b110010
  opx:Annotated[BitField, VOPDOp] = bits[25:22]
  opy:Annotated[BitField, VOPDOp] = bits[21:17]
-  vdstx = bits[63:56]
+  vdstx:VGPRField = bits[63:56]
  vdsty:VDSTYEnc = bits[55:49]
  srcx0:Src = bits[8:0]
+  vsrcx1:VGPRField = bits[16:9]
  srcy0:Src = bits[40:32]
-  vsrcx1 = bits[16:9]
-  vsrcy1 = bits[48:41]
-
-class VSAMPLE(Inst):
-  encoding = bits[31:26] == 0b111001
-  op:Annotated[BitField, VSAMPLEOp] = bits[21:14]
-  vdata:VGPRField = bits[39:32]
-  dmask = bits[25:22]
-  dim = bits[2:0]
-  tfe = bits[3]
-  unrm = bits[13]
-  r128 = bits[4]
-  d16 = bits[5]
-  a16 = bits[6]
-  lwe = bits[40]
-  rsrc = bits[49:41]
-  scope = bits[51:50]
-  th = bits[54:52]
-  samp = bits[63:55]
-  vaddr0 = bits[71:64]
-  vaddr1 = bits[79:72]
-  vaddr2 = bits[87:80]
-  vaddr3 = bits[95:88]
+  vsrcy1:VGPRField = bits[48:41]

 # instruction helpers
-ds_add_u32 = functools.partial(DS, DSOp.DS_ADD_U32)
-ds_sub_u32 = functools.partial(DS, DSOp.DS_SUB_U32)
-ds_rsub_u32 = functools.partial(DS, DSOp.DS_RSUB_U32)
-ds_inc_u32 = functools.partial(DS, DSOp.DS_INC_U32)
-ds_dec_u32 = functools.partial(DS, DSOp.DS_DEC_U32)
-ds_min_i32 = functools.partial(DS, DSOp.DS_MIN_I32)
-ds_max_i32 = functools.partial(DS, DSOp.DS_MAX_I32)
-ds_min_u32 = functools.partial(DS, DSOp.DS_MIN_U32)
-ds_max_u32 = functools.partial(DS, DSOp.DS_MAX_U32)
-ds_and_b32 = functools.partial(DS, DSOp.DS_AND_B32)
-ds_or_b32 = functools.partial(DS, DSOp.DS_OR_B32)
-ds_xor_b32 = functools.partial(DS, DSOp.DS_XOR_B32)
-ds_mskor_b32 = functools.partial(DS, DSOp.DS_MSKOR_B32)
-ds_store_b32 = functools.partial(DS, DSOp.DS_STORE_B32)
-ds_store_2addr_b32 = functools.partial(DS, DSOp.DS_STORE_2ADDR_B32)
-ds_store_2addr_stride64_b32 = functools.partial(DS, DSOp.DS_STORE_2ADDR_STRIDE64_B32)
-ds_cmpstore_b32 = functools.partial(DS, DSOp.DS_CMPSTORE_B32)
-ds_min_num_f32 = functools.partial(DS, DSOp.DS_MIN_NUM_F32)
-ds_max_num_f32 = functools.partial(DS, DSOp.DS_MAX_NUM_F32)
-ds_nop = functools.partial(DS, DSOp.DS_NOP)
-ds_add_f32 = functools.partial(DS, DSOp.DS_ADD_F32)
-ds_store_b8 = functools.partial(DS, DSOp.DS_STORE_B8)
-ds_store_b16 = functools.partial(DS, DSOp.DS_STORE_B16)
-ds_add_rtn_u32 = functools.partial(DS, DSOp.DS_ADD_RTN_U32)
-ds_sub_rtn_u32 = functools.partial(DS, DSOp.DS_SUB_RTN_U32)
-ds_rsub_rtn_u32 = functools.partial(DS, DSOp.DS_RSUB_RTN_U32)
-ds_inc_rtn_u32 = functools.partial(DS, DSOp.DS_INC_RTN_U32)
-ds_dec_rtn_u32 = functools.partial(DS, DSOp.DS_DEC_RTN_U32)
-ds_min_rtn_i32 = functools.partial(DS, DSOp.DS_MIN_RTN_I32)
-ds_max_rtn_i32 = functools.partial(DS, DSOp.DS_MAX_RTN_I32)
-ds_min_rtn_u32 = functools.partial(DS, DSOp.DS_MIN_RTN_U32)
-ds_max_rtn_u32 = functools.partial(DS, DSOp.DS_MAX_RTN_U32)
-ds_and_rtn_b32 = functools.partial(DS, DSOp.DS_AND_RTN_B32)
-ds_or_rtn_b32 = functools.partial(DS, DSOp.DS_OR_RTN_B32)
-ds_xor_rtn_b32 = functools.partial(DS, DSOp.DS_XOR_RTN_B32)
-ds_mskor_rtn_b32 = functools.partial(DS, DSOp.DS_MSKOR_RTN_B32)
-ds_storexchg_rtn_b32 = functools.partial(DS, DSOp.DS_STOREXCHG_RTN_B32)
-ds_storexchg_2addr_rtn_b32 = functools.partial(DS, DSOp.DS_STOREXCHG_2ADDR_RTN_B32)
-ds_storexchg_2addr_stride64_rtn_b32 = functools.partial(DS, DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32)
-ds_cmpstore_rtn_b32 = functools.partial(DS, DSOp.DS_CMPSTORE_RTN_B32)
-ds_min_num_rtn_f32 = functools.partial(DS, DSOp.DS_MIN_NUM_RTN_F32)
-ds_max_num_rtn_f32 = functools.partial(DS, DSOp.DS_MAX_NUM_RTN_F32)
-ds_swizzle_b32 = functools.partial(DS, DSOp.DS_SWIZZLE_B32)
-ds_load_b32 = functools.partial(DS, DSOp.DS_LOAD_B32)
-ds_load_2addr_b32 = functools.partial(DS, DSOp.DS_LOAD_2ADDR_B32)
-ds_load_2addr_stride64_b32 = functools.partial(DS, DSOp.DS_LOAD_2ADDR_STRIDE64_B32)
-ds_load_i8 = functools.partial(DS, DSOp.DS_LOAD_I8)
-ds_load_u8 = functools.partial(DS, DSOp.DS_LOAD_U8)
-ds_load_i16 = functools.partial(DS, DSOp.DS_LOAD_I16)
-ds_load_u16 = functools.partial(DS, DSOp.DS_LOAD_U16)
-ds_consume = functools.partial(DS, DSOp.DS_CONSUME)
-ds_append = functools.partial(DS, DSOp.DS_APPEND)
-ds_add_u64 = functools.partial(DS, DSOp.DS_ADD_U64)
-ds_sub_u64 = functools.partial(DS, DSOp.DS_SUB_U64)
-ds_rsub_u64 = functools.partial(DS, DSOp.DS_RSUB_U64)
-ds_inc_u64 = functools.partial(DS, DSOp.DS_INC_U64)
-ds_dec_u64 = functools.partial(DS, DSOp.DS_DEC_U64)
-ds_min_i64 = functools.partial(DS, DSOp.DS_MIN_I64)
-ds_max_i64 = functools.partial(DS, DSOp.DS_MAX_I64)
-ds_min_u64 = functools.partial(DS, DSOp.DS_MIN_U64)
-ds_max_u64 = functools.partial(DS, DSOp.DS_MAX_U64)
-ds_and_b64 = functools.partial(DS, DSOp.DS_AND_B64)
-ds_or_b64 = functools.partial(DS, DSOp.DS_OR_B64)
-ds_xor_b64 = functools.partial(DS, DSOp.DS_XOR_B64)
-ds_mskor_b64 = functools.partial(DS, DSOp.DS_MSKOR_B64)
-ds_store_b64 = functools.partial(DS, DSOp.DS_STORE_B64)
-ds_store_2addr_b64 = functools.partial(DS, DSOp.DS_STORE_2ADDR_B64)
-ds_store_2addr_stride64_b64 = functools.partial(DS, DSOp.DS_STORE_2ADDR_STRIDE64_B64)
-ds_cmpstore_b64 = functools.partial(DS, DSOp.DS_CMPSTORE_B64)
-ds_min_num_f64 = functools.partial(DS, DSOp.DS_MIN_NUM_F64)
-ds_max_num_f64 = functools.partial(DS, DSOp.DS_MAX_NUM_F64)
-ds_add_rtn_u64 = functools.partial(DS, DSOp.DS_ADD_RTN_U64)
-ds_sub_rtn_u64 = functools.partial(DS, DSOp.DS_SUB_RTN_U64)
-ds_rsub_rtn_u64 = functools.partial(DS, DSOp.DS_RSUB_RTN_U64)
-ds_inc_rtn_u64 = functools.partial(DS, DSOp.DS_INC_RTN_U64)
-ds_dec_rtn_u64 = functools.partial(DS, DSOp.DS_DEC_RTN_U64)
-ds_min_rtn_i64 = functools.partial(DS, DSOp.DS_MIN_RTN_I64)
-ds_max_rtn_i64 = functools.partial(DS, DSOp.DS_MAX_RTN_I64)
-ds_min_rtn_u64 = functools.partial(DS, DSOp.DS_MIN_RTN_U64)
-ds_max_rtn_u64 = functools.partial(DS, DSOp.DS_MAX_RTN_U64)
-ds_and_rtn_b64 = functools.partial(DS, DSOp.DS_AND_RTN_B64)
-ds_or_rtn_b64 = functools.partial(DS, DSOp.DS_OR_RTN_B64)
-ds_xor_rtn_b64 = functools.partial(DS, DSOp.DS_XOR_RTN_B64)
-ds_mskor_rtn_b64 = functools.partial(DS, DSOp.DS_MSKOR_RTN_B64)
-ds_storexchg_rtn_b64 = functools.partial(DS, DSOp.DS_STOREXCHG_RTN_B64)
-ds_storexchg_2addr_rtn_b64 = functools.partial(DS, DSOp.DS_STOREXCHG_2ADDR_RTN_B64)
-ds_storexchg_2addr_stride64_rtn_b64 = functools.partial(DS, DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64)
-ds_cmpstore_rtn_b64 = functools.partial(DS, DSOp.DS_CMPSTORE_RTN_B64)
-ds_min_num_rtn_f64 = functools.partial(DS, DSOp.DS_MIN_NUM_RTN_F64)
-ds_max_num_rtn_f64 = functools.partial(DS, DSOp.DS_MAX_NUM_RTN_F64)
-ds_load_b64 = functools.partial(DS, DSOp.DS_LOAD_B64)
-ds_load_2addr_b64 = functools.partial(DS, DSOp.DS_LOAD_2ADDR_B64)
-ds_load_2addr_stride64_b64 = functools.partial(DS, DSOp.DS_LOAD_2ADDR_STRIDE64_B64)
-ds_add_rtn_f32 = functools.partial(DS, DSOp.DS_ADD_RTN_F32)
-ds_condxchg32_rtn_b64 = functools.partial(DS, DSOp.DS_CONDXCHG32_RTN_B64)
-ds_cond_sub_u32 = functools.partial(DS, DSOp.DS_COND_SUB_U32)
-ds_sub_clamp_u32 = functools.partial(DS, DSOp.DS_SUB_CLAMP_U32)
-ds_pk_add_f16 = functools.partial(DS, DSOp.DS_PK_ADD_F16)
-ds_pk_add_bf16 = functools.partial(DS, DSOp.DS_PK_ADD_BF16)
-ds_store_b8_d16_hi = functools.partial(DS, DSOp.DS_STORE_B8_D16_HI)
-ds_store_b16_d16_hi = functools.partial(DS, DSOp.DS_STORE_B16_D16_HI)
-ds_load_u8_d16 = functools.partial(DS, DSOp.DS_LOAD_U8_D16)
-ds_load_u8_d16_hi = functools.partial(DS, DSOp.DS_LOAD_U8_D16_HI)
-ds_load_i8_d16 = functools.partial(DS, DSOp.DS_LOAD_I8_D16)
-ds_load_i8_d16_hi = functools.partial(DS, DSOp.DS_LOAD_I8_D16_HI)
-ds_load_u16_d16 = functools.partial(DS, DSOp.DS_LOAD_U16_D16)
-ds_load_u16_d16_hi = functools.partial(DS, DSOp.DS_LOAD_U16_D16_HI)
-ds_cond_sub_rtn_u32 = functools.partial(DS, DSOp.DS_COND_SUB_RTN_U32)
-ds_sub_clamp_rtn_u32 = functools.partial(DS, DSOp.DS_SUB_CLAMP_RTN_U32)
-ds_pk_add_rtn_f16 = functools.partial(DS, DSOp.DS_PK_ADD_RTN_F16)
-ds_pk_add_rtn_bf16 = functools.partial(DS, DSOp.DS_PK_ADD_RTN_BF16)
-ds_store_addtid_b32 = functools.partial(DS, DSOp.DS_STORE_ADDTID_B32)
-ds_load_addtid_b32 = functools.partial(DS, DSOp.DS_LOAD_ADDTID_B32)
-ds_permute_b32 = functools.partial(DS, DSOp.DS_PERMUTE_B32)
-ds_bpermute_b32 = functools.partial(DS, DSOp.DS_BPERMUTE_B32)
-ds_bpermute_fi_b32 = functools.partial(DS, DSOp.DS_BPERMUTE_FI_B32)
-ds_store_b96 = functools.partial(DS, DSOp.DS_STORE_B96)
-ds_store_b128 = functools.partial(DS, DSOp.DS_STORE_B128)
-ds_bvh_stack_push4_pop1_rtn_b32 = functools.partial(DS, DSOp.DS_BVH_STACK_PUSH4_POP1_RTN_B32)
-ds_bvh_stack_push8_pop1_rtn_b32 = functools.partial(DS, DSOp.DS_BVH_STACK_PUSH8_POP1_RTN_B32)
-ds_bvh_stack_push8_pop2_rtn_b64 = functools.partial(DS, DSOp.DS_BVH_STACK_PUSH8_POP2_RTN_B64)
-ds_load_b96 = functools.partial(DS, DSOp.DS_LOAD_B96)
-ds_load_b128 = functools.partial(DS, DSOp.DS_LOAD_B128)
 s_load_b32 = functools.partial(SMEM, SMEMOp.S_LOAD_B32)
 s_load_b64 = functools.partial(SMEM, SMEMOp.S_LOAD_B64)
 s_load_b128 = functools.partial(SMEM, SMEMOp.S_LOAD_B128)
@@ -379,8 +221,6 @@ s_buffer_load_u8 = functools.partial(SMEM, SMEMOp.S_BUFFER_LOAD_U8)
 s_buffer_load_i16 = functools.partial(SMEM, SMEMOp.S_BUFFER_LOAD_I16)
 s_buffer_load_u16 = functools.partial(SMEM, SMEMOp.S_BUFFER_LOAD_U16)
 s_dcache_inv = functools.partial(SMEM, SMEMOp.S_DCACHE_INV)
-s_atc_probe = functools.partial(SMEM, SMEMOp.S_ATC_PROBE)
-s_atc_probe_buffer = functools.partial(SMEM, SMEMOp.S_ATC_PROBE_BUFFER)
 s_prefetch_inst = functools.partial(SMEM, SMEMOp.S_PREFETCH_INST)
 s_prefetch_inst_pc_rel = functools.partial(SMEM, SMEMOp.S_PREFETCH_INST_PC_REL)
 s_prefetch_data = functools.partial(SMEM, SMEMOp.S_PREFETCH_DATA)
@@ -454,8 +294,6 @@ s_sendmsg_rtn_b64 = functools.partial(SOP1, SOP1Op.S_SENDMSG_RTN_B64)
 s_barrier_signal = functools.partial(SOP1, SOP1Op.S_BARRIER_SIGNAL)
 s_barrier_signal_isfirst = functools.partial(SOP1, SOP1Op.S_BARRIER_SIGNAL_ISFIRST)
 s_get_barrier_state = functools.partial(SOP1, SOP1Op.S_GET_BARRIER_STATE)
-s_barrier_init = functools.partial(SOP1, SOP1Op.S_BARRIER_INIT)
-s_barrier_join = functools.partial(SOP1, SOP1Op.S_BARRIER_JOIN)
 s_alloc_vgpr = functools.partial(SOP1, SOP1Op.S_ALLOC_VGPR)
 s_sleep_var = functools.partial(SOP1, SOP1Op.S_SLEEP_VAR)
 s_ceil_f32 = functools.partial(SOP1, SOP1Op.S_CEIL_F32)
@@ -616,7 +454,6 @@ s_trap = functools.partial(SOPP, SOPPOp.S_TRAP)
 s_round_mode = functools.partial(SOPP, SOPPOp.S_ROUND_MODE)
 s_denorm_mode = functools.partial(SOPP, SOPPOp.S_DENORM_MODE)
 s_barrier_wait = functools.partial(SOPP, SOPPOp.S_BARRIER_WAIT)
-s_barrier_leave = functools.partial(SOPP, SOPPOp.S_BARRIER_LEAVE)
 s_code_end = functools.partial(SOPP, SOPPOp.S_CODE_END)
 s_branch = functools.partial(SOPP, SOPPOp.S_BRANCH)
 s_cbranch_scc0 = functools.partial(SOPP, SOPPOp.S_CBRANCH_SCC0)
@@ -633,8 +470,6 @@ s_sendmsg = functools.partial(SOPP, SOPPOp.S_SENDMSG)
 s_sendmsghalt = functools.partial(SOPP, SOPPOp.S_SENDMSGHALT)
 s_incperflevel = functools.partial(SOPP, SOPPOp.S_INCPERFLEVEL)
 s_decperflevel = functools.partial(SOPP, SOPPOp.S_DECPERFLEVEL)
-s_ttracedata = functools.partial(SOPP, SOPPOp.S_TTRACEDATA)
-s_ttracedata_imm = functools.partial(SOPP, SOPPOp.S_TTRACEDATA_IMM)
 s_icache_inv = functools.partial(SOPP, SOPPOp.S_ICACHE_INV)
 s_wait_loadcnt = functools.partial(SOPP, SOPPOp.S_WAIT_LOADCNT)
 s_wait_storecnt = functools.partial(SOPP, SOPPOp.S_WAIT_STORECNT)
@@ -736,39 +571,6 @@ tbuffer_store_d16_format_xyz = functools.partial(VBUFFER, VBUFFEROp.TBUFFER_STOR
 tbuffer_store_d16_format_xyzw = functools.partial(VBUFFER, VBUFFEROp.TBUFFER_STORE_D16_FORMAT_XYZW)
 ds_param_load = functools.partial(VDSDIR, VDSDIROp.DS_PARAM_LOAD)
 ds_direct_load = functools.partial(VDSDIR, VDSDIROp.DS_DIRECT_LOAD)
-image_load = functools.partial(VIMAGE, VIMAGEOp.IMAGE_LOAD)
-image_load_mip = functools.partial(VIMAGE, VIMAGEOp.IMAGE_LOAD_MIP)
-image_load_pck = functools.partial(VIMAGE, VIMAGEOp.IMAGE_LOAD_PCK)
-image_load_pck_sgn = functools.partial(VIMAGE, VIMAGEOp.IMAGE_LOAD_PCK_SGN)
-image_load_mip_pck = functools.partial(VIMAGE, VIMAGEOp.IMAGE_LOAD_MIP_PCK)
-image_load_mip_pck_sgn = functools.partial(VIMAGE, VIMAGEOp.IMAGE_LOAD_MIP_PCK_SGN)
-image_store = functools.partial(VIMAGE, VIMAGEOp.IMAGE_STORE)
-image_store_mip = functools.partial(VIMAGE, VIMAGEOp.IMAGE_STORE_MIP)
-image_store_pck = functools.partial(VIMAGE, VIMAGEOp.IMAGE_STORE_PCK)
-image_store_mip_pck = functools.partial(VIMAGE, VIMAGEOp.IMAGE_STORE_MIP_PCK)
-image_atomic_swap = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_SWAP)
-image_atomic_cmpswap = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_CMPSWAP)
-image_atomic_add_uint = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_ADD_UINT)
-image_atomic_sub_uint = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_SUB_UINT)
-image_atomic_min_int = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_MIN_INT)
-image_atomic_min_uint = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_MIN_UINT)
-image_atomic_max_int = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_MAX_INT)
-image_atomic_max_uint = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_MAX_UINT)
-image_atomic_and = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_AND)
-image_atomic_or = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_OR)
-image_atomic_xor = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_XOR)
-image_atomic_inc_uint = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_INC_UINT)
-image_atomic_dec_uint = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_DEC_UINT)
-image_get_resinfo = functools.partial(VIMAGE, VIMAGEOp.IMAGE_GET_RESINFO)
-image_bvh_intersect_ray = functools.partial(VIMAGE, VIMAGEOp.IMAGE_BVH_INTERSECT_RAY)
-image_bvh64_intersect_ray = functools.partial(VIMAGE, VIMAGEOp.IMAGE_BVH64_INTERSECT_RAY)
-image_bvh_dual_intersect_ray = functools.partial(VIMAGE, VIMAGEOp.IMAGE_BVH_DUAL_INTERSECT_RAY)
-image_bvh8_intersect_ray = functools.partial(VIMAGE, VIMAGEOp.IMAGE_BVH8_INTERSECT_RAY)
-image_atomic_add_flt = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_ADD_FLT)
-image_atomic_min_flt = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_MIN_FLT)
-image_atomic_max_flt = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_MAX_FLT)
-image_atomic_pk_add_f16 = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_PK_ADD_F16)
-image_atomic_pk_add_bf16 = functools.partial(VIMAGE, VIMAGEOp.IMAGE_ATOMIC_PK_ADD_BF16)
 v_interp_p10_f32 = functools.partial(VINTERP, VINTERPOp.V_INTERP_P10_F32)
 v_interp_p2_f32 = functools.partial(VINTERP, VINTERPOp.V_INTERP_P2_F32)
 v_interp_p10_f16_f32 = functools.partial(VINTERP, VINTERPOp.V_INTERP_P10_F16_F32)
@@ -900,8 +702,8 @@ v_add_nc_u32_e32 = functools.partial(VOP2, VOP2Op.V_ADD_NC_U32)
 v_sub_nc_u32_e32 = functools.partial(VOP2, VOP2Op.V_SUB_NC_U32)
 v_subrev_nc_u32_e32 = functools.partial(VOP2, VOP2Op.V_SUBREV_NC_U32)
 v_fmac_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAC_F32)
-v_fmamk_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAMK_F32)
-v_fmaak_f32_e32 = functools.partial(VOP2, VOP2Op.V_FMAAK_F32)
+def v_fmamk_f32_e32(vdst, src0, K, vsrc1): return VOP2(VOP2Op.V_FMAMK_F32, vdst, src0, vsrc1, literal=K)
+def v_fmaak_f32_e32(vdst, src0, vsrc1, K): return VOP2(VOP2Op.V_FMAAK_F32, vdst, src0, vsrc1, literal=K)
 v_cvt_pk_rtz_f16_f32_e32 = functools.partial(VOP2, VOP2Op.V_CVT_PK_RTZ_F16_F32)
 v_min_num_f16_e32 = functools.partial(VOP2, VOP2Op.V_MIN_NUM_F16)
 v_max_num_f16_e32 = functools.partial(VOP2, VOP2Op.V_MAX_NUM_F16)
@@ -910,8 +712,8 @@ v_sub_f16_e32 = functools.partial(VOP2, VOP2Op.V_SUB_F16)
 v_subrev_f16_e32 = functools.partial(VOP2, VOP2Op.V_SUBREV_F16)
 v_mul_f16_e32 = functools.partial(VOP2, VOP2Op.V_MUL_F16)
 v_fmac_f16_e32 = functools.partial(VOP2, VOP2Op.V_FMAC_F16)
-v_fmamk_f16_e32 = functools.partial(VOP2, VOP2Op.V_FMAMK_F16)
-v_fmaak_f16_e32 = functools.partial(VOP2, VOP2Op.V_FMAAK_F16)
+def v_fmamk_f16_e32(vdst, src0, K, vsrc1): return VOP2(VOP2Op.V_FMAMK_F16, vdst, src0, vsrc1, literal=K)
+def v_fmaak_f16_e32(vdst, src0, vsrc1, K): return VOP2(VOP2Op.V_FMAAK_F16, vdst, src0, vsrc1, literal=K)
 v_ldexp_f16_e32 = functools.partial(VOP2, VOP2Op.V_LDEXP_F16)
 v_pk_fmac_f16_e32 = functools.partial(VOP2, VOP2Op.V_PK_FMAC_F16)
 v_cmp_lt_f16_e64 = functools.partial(VOP3, VOP3Op.V_CMP_LT_F16)
@@ -1404,6 +1206,7 @@ v_swmmac_f32_16x16x32_fp8_fp8 = functools.partial(VOP3P, VOP3POp.V_SWMMAC_F32_16
 v_swmmac_f32_16x16x32_fp8_bf8 = functools.partial(VOP3P, VOP3POp.V_SWMMAC_F32_16X16X32_FP8_BF8)
 v_swmmac_f32_16x16x32_bf8_fp8 = functools.partial(VOP3P, VOP3POp.V_SWMMAC_F32_16X16X32_BF8_FP8)
 v_swmmac_f32_16x16x32_bf8_bf8 = functools.partial(VOP3P, VOP3POp.V_SWMMAC_F32_16X16X32_BF8_BF8)
+dword = functools.partial(VOP3SD, VOP3SDOp.DWORD)
 v_add_co_ci_u32 = functools.partial(VOP3SD, VOP3SDOp.V_ADD_CO_CI_U32)
 v_sub_co_ci_u32 = functools.partial(VOP3SD, VOP3SDOp.V_SUB_CO_CI_U32)
 v_subrev_co_ci_u32 = functools.partial(VOP3SD, VOP3SDOp.V_SUBREV_CO_CI_U32)
@@ -1593,61 +1396,30 @@ v_dual_dot2acc_f32_bf16 = functools.partial(VOPD, VOPDOp.V_DUAL_DOT2ACC_F32_BF16
 v_dual_add_nc_u32 = functools.partial(VOPD, VOPDOp.V_DUAL_ADD_NC_U32)
 v_dual_lshlrev_b32 = functools.partial(VOPD, VOPDOp.V_DUAL_LSHLREV_B32)
 v_dual_and_b32 = functools.partial(VOPD, VOPDOp.V_DUAL_AND_B32)
-image_msaa_load = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_MSAA_LOAD)
-image_sample = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE)
-image_sample_d = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D)
-image_sample_l = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_L)
-image_sample_b = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_B)
-image_sample_lz = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_LZ)
-image_sample_c = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C)
-image_sample_c_d = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D)
-image_sample_c_l = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_L)
-image_sample_c_b = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_B)
-image_sample_c_lz = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_LZ)
-image_sample_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_O)
-image_sample_d_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_O)
-image_sample_l_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_L_O)
-image_sample_b_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_B_O)
-image_sample_lz_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_LZ_O)
-image_sample_c_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_O)
-image_sample_c_d_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_O)
-image_sample_c_l_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_L_O)
-image_sample_c_b_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_B_O)
-image_sample_c_lz_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_LZ_O)
-image_gather4 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4)
-image_gather4_l = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_L)
-image_gather4_b = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_B)
-image_gather4_lz = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_LZ)
-image_gather4_c = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C)
-image_gather4_c_lz = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C_LZ)
-image_gather4_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_O)
-image_gather4_lz_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_LZ_O)
-image_gather4_c_lz_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C_LZ_O)
-image_get_lod = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GET_LOD)
-image_sample_d_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_G16)
-image_sample_c_d_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_G16)
-image_sample_d_o_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_O_G16)
-image_sample_c_d_o_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_O_G16)
-image_sample_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_CL)
-image_sample_d_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_CL)
-image_sample_b_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_B_CL)
-image_sample_c_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_CL)
-image_sample_c_d_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_CL)
-image_sample_c_b_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_B_CL)
-image_sample_cl_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_CL_O)
-image_sample_d_cl_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_CL_O)
-image_sample_b_cl_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_B_CL_O)
-image_sample_c_cl_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_CL_O)
-image_sample_c_d_cl_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_CL_O)
-image_sample_c_b_cl_o = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_B_CL_O)
-image_sample_c_d_cl_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_CL_G16)
-image_sample_d_cl_o_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_CL_O_G16)
-image_sample_c_d_cl_o_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_C_D_CL_O_G16)
-image_sample_d_cl_g16 = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_SAMPLE_D_CL_G16)
-image_gather4_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_CL)
-image_gather4_b_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_B_CL)
-image_gather4_c_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C_CL)
-image_gather4_c_l = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C_L)
-image_gather4_c_b = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C_B)
-image_gather4_c_b_cl = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4_C_B_CL)
-image_gather4h = functools.partial(VSAMPLE, VSAMPLEOp.IMAGE_GATHER4H)
+
+VCC_LO = SrcEnum.VCC_LO
+VCC_HI = SrcEnum.VCC_HI
+NULL = SrcEnum.NULL
+M0 = SrcEnum.M0
+EXEC_LO = SrcEnum.EXEC_LO
+EXEC_HI = SrcEnum.EXEC_HI
+ZERO = SrcEnum.ZERO
+DPP8FI = SrcEnum.DPP8FI
+SHARED_BASE = SrcEnum.SHARED_BASE
+SHARED_LIMIT = SrcEnum.SHARED_LIMIT
+PRIVATE_BASE = SrcEnum.PRIVATE_BASE
+PRIVATE_LIMIT = SrcEnum.PRIVATE_LIMIT
+POS_HALF = SrcEnum.POS_HALF
+NEG_HALF = SrcEnum.NEG_HALF
+POS_ONE = SrcEnum.POS_ONE
+NEG_ONE = SrcEnum.NEG_ONE
+POS_TWO = SrcEnum.POS_TWO
+NEG_TWO = SrcEnum.NEG_TWO
+POS_FOUR = SrcEnum.POS_FOUR
+NEG_FOUR = SrcEnum.NEG_FOUR
+INV_2PI = SrcEnum.INV_2PI
+VCCZ = SrcEnum.VCCZ
+EXECZ = SrcEnum.EXECZ
+SCC = SrcEnum.SCC
+LDS_DIRECT = SrcEnum.LDS_DIRECT
+OFF = NULL
@@ -1,62 +0,0 @@
-# Instruction format detection and decoding
-from __future__ import annotations
-from extra.assembly.amd.dsl import Inst
-from extra.assembly.amd.autogen.rdna3.ins import VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, VOPD, VINTERP, SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, DS, FLAT, MUBUF, MTBUF, MIMG, EXP
-from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP2 as R4_VOP2, VOP3 as R4_VOP3, VOP3SD as R4_VOP3SD, VOP3P as R4_VOP3P,
-  VOPC as R4_VOPC, VOPD as R4_VOPD, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP2 as R4_SOP2, SOPC as R4_SOPC, SOPK as R4_SOPK, SOPP as R4_SOPP,
-  SMEM as R4_SMEM, DS as R4_DS, VBUFFER as R4_VBUFFER, VEXPORT as R4_VEXPORT)
-from extra.assembly.amd.autogen.cdna.ins import (VOP1 as C_VOP1, VOP2 as C_VOP2, VOPC as C_VOPC, VOP3A, VOP3B, VOP3P as C_VOP3P,
-  SOP1 as C_SOP1, SOP2 as C_SOP2, SOPC as C_SOPC, SOPK as C_SOPK, SOPP as C_SOPP, SMEM as C_SMEM, DS as C_DS,
-  FLAT as C_FLAT, MUBUF as C_MUBUF, MTBUF as C_MTBUF, SDWA, DPP)
-
-def _matches_encoding(word: int, cls: type[Inst]) -> bool:
-  """Check if word matches the encoding pattern of an instruction class."""
-  if cls._encoding is None: return False
-  bf, val = cls._encoding
-  return ((word >> bf.lo) & bf.mask()) == val
-
-# Order matters: more specific encodings first, VOP2 last (it's a catch-all for bit31=0)
-_RDNA_FORMATS_64 = [VOPD, VOP3P, VINTERP, VOP3, DS, FLAT, MUBUF, MTBUF, MIMG, SMEM, EXP]
-_RDNA_FORMATS_32 = [SOP1, SOPC, SOPP, SOPK, VOPC, VOP1, SOP2, VOP2]  # SOP2/VOP2 are catch-alls
-_CDNA_FORMATS_64 = [C_VOP3P, VOP3A, C_DS, C_FLAT, C_MUBUF, C_MTBUF, C_SMEM]
-_CDNA_FORMATS_32 = [SDWA, DPP, C_SOP1, C_SOPC, C_SOPP, C_SOPK, C_VOPC, C_VOP1, C_SOP2, C_VOP2]
-_CDNA_VOP3B_OPS = {281, 282, 283, 284, 285, 286, 480, 481, 488, 489}  # VOP3B opcodes
-_RDNA4_FORMATS_64 = [R4_VOPD, R4_VOP3P, R4_VINTERP, R4_VOP3, R4_DS, R4_VBUFFER, R4_SMEM, R4_VEXPORT]
-_RDNA4_FORMATS_32 = [R4_SOP1, R4_SOPC, R4_SOPP, R4_SOPK, R4_VOPC, R4_VOP1, R4_SOP2, R4_VOP2]
-_RDNA4_VOP3SD_OPS = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770}
-
-def detect_format(data: bytes, arch: str = "rdna3") -> type[Inst]:
-  """Detect instruction format from machine code bytes."""
-  assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}"
-  word = int.from_bytes(data[:4], 'little')
-  if arch == "cdna":
-    if (word >> 30) == 0b11:
-      for cls in _CDNA_FORMATS_64:
-        if _matches_encoding(word, cls):
-          return VOP3B if cls is VOP3A and ((word >> 16) & 0x3ff) in _CDNA_VOP3B_OPS else cls
-      raise ValueError(f"unknown CDNA 64-bit format word={word:#010x}")
-    for cls in _CDNA_FORMATS_32:
-      if _matches_encoding(word, cls): return cls
-    raise ValueError(f"unknown CDNA 32-bit format word={word:#010x}")
-  if arch == "rdna4":
-    if (word >> 30) == 0b11:
-      for cls in _RDNA4_FORMATS_64:
-        if _matches_encoding(word, cls):
-          return R4_VOP3SD if cls is R4_VOP3 and ((word >> 16) & 0x3ff) in _RDNA4_VOP3SD_OPS else cls
-      raise ValueError(f"unknown RDNA4 64-bit format word={word:#010x}")
-    for cls in _RDNA4_FORMATS_32:
-      if _matches_encoding(word, cls): return cls
-    raise ValueError(f"unknown RDNA4 32-bit format word={word:#010x}")
-  # RDNA3 (default)
-  if (word >> 30) == 0b11:
-    for cls in _RDNA_FORMATS_64:
-      if _matches_encoding(word, cls):
-        return VOP3SD if cls is VOP3 and ((word >> 16) & 0x3ff) in Inst._VOP3SD_OPS else cls
-    raise ValueError(f"unknown 64-bit format word={word:#010x}")
-  for cls in _RDNA_FORMATS_32:
-    if _matches_encoding(word, cls): return cls
-  raise ValueError(f"unknown 32-bit format word={word:#010x}")
-
-def decode_inst(data: bytes, arch: str = "rdna3") -> Inst:
-  """Decode machine code bytes into an instruction."""
-  return detect_format(data, arch).from_bytes(data)
@@ -1,745 +0,0 @@
-# RDNA3/RDNA4/CDNA disassembler
-from __future__ import annotations
-import re
-from extra.assembly.amd.dsl import Inst, decode_src, SPECIAL_GPRS, SPECIAL_GPRS_CDNA, SPECIAL_PAIRS, SPECIAL_PAIRS_CDNA
-from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, VOPD, VINTERP, SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, DS, FLAT, MUBUF, MTBUF, MIMG, EXP,
-  VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOPDOp, SOP1Op, SOPKOp, SOPPOp, SMEMOp, DSOp, MUBUFOp)
-from extra.assembly.amd.autogen.rdna3.enum import BufFmt
-from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP2 as R4_VOP2, VOP3 as R4_VOP3, VOP3SD as R4_VOP3SD, VOP3P as R4_VOP3P,
-  VOPC as R4_VOPC, VOPD as R4_VOPD, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP2 as R4_SOP2, SOPC as R4_SOPC, SOPK as R4_SOPK, SOPP as R4_SOPP,
-  SMEM as R4_SMEM, DS as R4_DS, VBUFFER as R4_VBUFFER, VEXPORT as R4_VEXPORT, VOPDOp as R4_VOPDOp)
-from extra.assembly.amd.autogen.cdna.ins import FLAT as C_FLAT, MUBUF as C_MUBUF, MTBUF as C_MTBUF
-
-def _is_cdna(inst: Inst) -> bool: return 'cdna' in inst.__class__.__module__
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# CONSTANTS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-HWREG = {1: 'HW_REG_MODE', 2: 'HW_REG_STATUS', 3: 'HW_REG_TRAPSTS', 4: 'HW_REG_HW_ID', 5: 'HW_REG_GPR_ALLOC',
-         6: 'HW_REG_LDS_ALLOC', 7: 'HW_REG_IB_STS', 15: 'HW_REG_SH_MEM_BASES', 18: 'HW_REG_PERF_SNAPSHOT_PC_LO',
-         19: 'HW_REG_PERF_SNAPSHOT_PC_HI', 20: 'HW_REG_FLAT_SCR_LO', 21: 'HW_REG_FLAT_SCR_HI', 22: 'HW_REG_XNACK_MASK',
-         23: 'HW_REG_HW_ID1', 24: 'HW_REG_HW_ID2', 25: 'HW_REG_POPS_PACKER', 28: 'HW_REG_IB_STS2'}
-HWREG_RDNA4 = {1: 'HW_REG_WAVE_MODE', 2: 'HW_REG_WAVE_STATUS', 4: 'HW_REG_WAVE_STATE_PRIV', 5: 'HW_REG_WAVE_GPR_ALLOC',
-               6: 'HW_REG_WAVE_LDS_ALLOC', 7: 'HW_REG_IB_STS', 10: 'HW_REG_PERF_SNAPSHOT_DATA', 11: 'HW_REG_PERF_SNAPSHOT_PC_LO',
-               12: 'HW_REG_PERF_SNAPSHOT_PC_HI', 15: 'HW_REG_PERF_SNAPSHOT_DATA1', 16: 'HW_REG_PERF_SNAPSHOT_DATA2',
-               17: 'HW_REG_WAVE_EXCP_FLAG_PRIV', 18: 'HW_REG_WAVE_EXCP_FLAG_USER', 19: 'HW_REG_WAVE_TRAP_CTRL',
-               20: 'HW_REG_WAVE_SCRATCH_BASE_LO', 21: 'HW_REG_WAVE_SCRATCH_BASE_HI', 23: 'HW_REG_WAVE_HW_ID1',
-               24: 'HW_REG_WAVE_HW_ID2', 26: 'HW_REG_WAVE_SCHED_MODE', 29: 'HW_REG_SHADER_CYCLES_LO',
-               30: 'HW_REG_SHADER_CYCLES_HI', 31: 'HW_REG_WAVE_DVGPR_ALLOC_LO', 32: 'HW_REG_WAVE_DVGPR_ALLOC_HI'}
-MSG = {128: 'MSG_RTN_GET_DOORBELL', 129: 'MSG_RTN_GET_DDID', 130: 'MSG_RTN_GET_TMA',
-       131: 'MSG_RTN_GET_REALTIME', 132: 'MSG_RTN_SAVE_WAVE', 133: 'MSG_RTN_GET_TBA',
-       134: 'MSG_RTN_GET_TBA_TO_PC', 135: 'MSG_RTN_GET_SE_AID_ID'}
-# CDNA opcode name aliases for disasm (new name -> old name expected by tests)
-_CDNA_DISASM_ALIASES = {'v_fmac_f64': 'v_mul_legacy_f32', 'v_dot2c_f32_bf16': 'v_mac_f32', 'v_fmamk_f32': 'v_madmk_f32', 'v_fmaak_f32': 'v_madak_f32'}
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# HELPERS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def _reg(p: str, b: int, n: int = 1) -> str: return f"{p}{b}" if n == 1 else f"{p}[{b}:{b+n-1}]"
-def _sreg(b: int, n: int = 1) -> str: return _reg("s", b, n)
-def _vreg(b: int, n: int = 1) -> str: return _reg("v", b, n)
-def _areg(b: int, n: int = 1) -> str: return _reg("a", b, n)  # accumulator registers for GFX90a
-def _ttmp(b: int, n: int = 1) -> str: return _reg("ttmp", b - 108, n) if 108 <= b <= 123 else None
-def _sreg_or_ttmp(b: int, n: int = 1) -> str: return _ttmp(b, n) or _sreg(b, n)
-
-def _fmt_sdst(v: int, n: int = 1, cdna: bool = False) -> str:
-  if t := _ttmp(v, n): return t
-  pairs = SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS
-  gprs = SPECIAL_GPRS_CDNA if cdna else SPECIAL_GPRS
-  if n > 1: return pairs.get(v) or gprs.get(v) or _sreg(v, n)  # also check gprs for null/m0
-  return gprs.get(v, f"s{v}")
-
-def _fmt_src(v: int, n: int = 1, cdna: bool = False) -> str:
-  if n == 1: return decode_src(v, cdna)
-  if v >= 256: return _vreg(v - 256, n)
-  if v <= 101: return _sreg(v, n)  # s0-s101 can be pairs, but 102+ are special on CDNA
-  pairs = SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS
-  if n == 2 and v in pairs: return pairs[v]
-  if v <= 105: return _sreg(v, n)  # s102-s105 regular pairs for RDNA
-  if t := _ttmp(v, n): return t
-  return decode_src(v, cdna)
-
-def _fmt_v16(v: int, base: int = 256, hi_thresh: int = 384) -> str:
-  return f"v{(v - base) & 0x7f}.{'h' if v >= hi_thresh else 'l'}"
-
-def _has(op: str, *subs) -> bool: return any(s in op for s in subs)
-def _omod(v: int) -> str: return {1: " mul:2", 2: " mul:4", 3: " div:2"}.get(v, "")
-def _src16(inst, v: int) -> str: return _fmt_v16(v) if v >= 256 else inst.lit(v)  # format 16-bit src: vgpr.h/l or literal
-def _mods(*pairs) -> str: return " ".join(m for c, m in pairs if c)
-def _fmt_bits(label: str, val: int, count: int) -> str: return f"{label}:[{','.join(str((val >> i) & 1) for i in range(count))}]"
-
-def _vop3_src(inst, v: int, neg: int, abs_: int, hi: int, n: int, f16: bool) -> str:
-  """Format VOP3 source operand with modifiers."""
-  if v == 255: s = inst.lit(v)  # literal constant takes priority
-  elif n > 1: s = _fmt_src(v, n)
-  elif f16 and v >= 256: s = f"v{v - 256}.h" if hi else f"v{v - 256}.l"
-  elif v == 253: s = "src_scc"  # VOP3 sources use src_scc not scc
-  else: s = inst.lit(v)
-  if abs_: s = f"|{s}|"
-  return f"-{s}" if neg else s
-
-def _opsel_str(opsel: int, n: int, need: bool, is16_d: bool) -> str:
-  """Format op_sel modifier string."""
-  if not need: return ""
-  dst_hi = (opsel >> 3) & 1
-  if n == 1: return f" op_sel:[{opsel & 1},{dst_hi}]"
-  if n == 2: return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{dst_hi}]"
-  return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1},{dst_hi}]"
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# DISASSEMBLER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def _disasm_vop1(inst: VOP1) -> str:
-  name, cdna = inst.op_name.lower() or f'vop1_op_{inst.op}', _is_cdna(inst)
-  suf = "" if cdna else "_e32"
-  if name in ('v_nop', 'v_pipeflush', 'v_clrexcp'): return name  # no operands
-  if 'readfirstlane' in name:
-    src = f"v{inst.src0 - 256}" if inst.src0 >= 256 else decode_src(inst.src0, cdna)
-    return f"{name} {_fmt_sdst(inst.vdst, 1, cdna)}, {src}"
-  # 16-bit dst: uses .h/.l suffix for RDNA (CDNA uses plain vN)
-  parts = name.split('_')
-  is_16d = not cdna and (any(p in ('f16','i16','u16','b16') for p in parts[-2:-1]) or (len(parts) >= 2 and parts[-1] in ('f16','i16','u16','b16') and 'cvt' not in name))
-  # v_cvt_pk_f32_fp8 and v_cvt_pk_f32_bf8 output to 2 VGPRs, and take 16-bit src
-  is_pk_fp8 = 'cvt_pk_f32_fp8' in name or 'cvt_pk_f32_bf8' in name
-  dregs = 2 if is_pk_fp8 else inst.dst_regs()
-  dst = _vreg(inst.vdst, dregs) if dregs > 1 else _fmt_v16(inst.vdst, 0, 128) if is_16d else f"v{inst.vdst}"
-  src = inst.lit(inst.src0) if inst.src0 == 255 else _fmt_src(inst.src0, inst.src_regs(0), cdna) if inst.src_regs(0) > 1 else _src16(inst, inst.src0) if not cdna and (inst.is_src_16(0) or is_pk_fp8) and 'sat_pk' not in name else inst.lit(inst.src0)
-  return f"{name}{suf} {dst}, {src}"
-
-_VOP2_CARRY_OUT = {'v_add_co_u32', 'v_sub_co_u32', 'v_subrev_co_u32'}  # carry out only
-_VOP2_CARRY_INOUT = {'v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'}  # carry in and out (CDNA)
-_VOP2_CARRY_INOUT_RDNA = {'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'}  # carry in and out (RDNA)
-def _disasm_vop2(inst: VOP2) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  if cdna: name = _CDNA_DISASM_ALIASES.get(name, name)  # apply CDNA aliases
-  suf = "" if cdna or (not cdna and inst.op == VOP2Op.V_DOT2ACC_F32_F16) else "_e32"
-  lit = getattr(inst, '_literal', None)
-  is16 = not cdna and inst.is_16bit()
-  # fmaak/madak: dst = src0 * vsrc1 + K, fmamk/madmk: dst = src0 * K + vsrc1
-  if 'fmaak' in name or 'madak' in name or (not cdna and inst.op in (VOP2Op.V_FMAAK_F32, VOP2Op.V_FMAAK_F16)):
-    if is16: return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1, 0, 128)}, 0x{lit:x}"
-    return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}, 0x{lit:x}"
-  if 'fmamk' in name or 'madmk' in name or (not cdna and inst.op in (VOP2Op.V_FMAMK_F32, VOP2Op.V_FMAMK_F16)):
-    if is16: return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_src16(inst, inst.src0)}, 0x{lit:x}, {_fmt_v16(inst.vsrc1, 0, 128)}"
-    return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, 0x{lit:x}, v{inst.vsrc1}"
-  if is16: return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1, 0, 128)}"
-  vcc = "vcc" if cdna else "vcc_lo"
-  # CDNA carry ops output vcc after vdst
-  if cdna and name in _VOP2_CARRY_OUT: return f"{name}{suf} v{inst.vdst}, {vcc}, {inst.lit(inst.src0)}, v{inst.vsrc1}"
-  if cdna and name in _VOP2_CARRY_INOUT: return f"{name}{suf} v{inst.vdst}, {vcc}, {inst.lit(inst.src0)}, v{inst.vsrc1}, {vcc}"
-  # RDNA carry-in/out ops: v_add_co_ci_u32, etc. - format: vdst, vcc_lo, src0, vsrc1, vcc_lo
-  if not cdna and name in _VOP2_CARRY_INOUT_RDNA: return f"{name}{suf} v{inst.vdst}, {vcc}, {inst.lit(inst.src0)}, v{inst.vsrc1}, {vcc}"
-  # Handle 64-bit register operands (v_add_f64, v_mul_f64, etc.)
-  dn, sn0, sn1 = inst.dst_regs(), inst.src_regs(0), inst.src_regs(1)
-  if dn > 1 or sn0 > 1 or sn1 > 1:
-    dst = _vreg(inst.vdst, dn) if dn > 1 else f"v{inst.vdst}"
-    src0 = inst.lit(inst.src0) if inst.src0 == 255 else _fmt_src(inst.src0, sn0, cdna)
-    src1 = _vreg(inst.vsrc1, sn1) if sn1 > 1 else f"v{inst.vsrc1}"
-    return f"{name} {dst}, {src0}, {src1}"
-  return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}" + (f", {vcc}" if name == 'v_cndmask_b32' else "")
-
-def _disasm_vopc(inst: VOPC) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  if cdna:
-    s0 = inst.lit(inst.src0) if inst.src0 == 255 else _fmt_src(inst.src0, inst.src_regs(0), cdna)
-    s1 = _vreg(inst.vsrc1, inst.src_regs(1)) if inst.src_regs(1) > 1 else f"v{inst.vsrc1}"
-    return f"{name} vcc, {s0}, {s1}"  # CDNA VOPC always outputs vcc
-  # RDNA: v_cmpx_* writes to exec (no vcc), v_cmp_* writes to vcc_lo
-  has_vcc = 'cmpx' not in name
-  s0 = inst.lit(inst.src0) if inst.src0 == 255 else _fmt_src(inst.src0, inst.src_regs(0)) if inst.src_regs(0) > 1 else _src16(inst, inst.src0) if inst.is_16bit() else inst.lit(inst.src0)
-  s1 = _vreg(inst.vsrc1, inst.src_regs(1)) if inst.src_regs(1) > 1 else _fmt_v16(inst.vsrc1, 0, 128) if inst.is_16bit() else f"v{inst.vsrc1}"
-  return f"{name}_e32 vcc_lo, {s0}, {s1}" if has_vcc else f"{name}_e32 {s0}, {s1}"
-
-NO_ARG_SOPP = {SOPPOp.S_BARRIER, SOPPOp.S_WAKEUP, SOPPOp.S_ICACHE_INV,
-               SOPPOp.S_WAIT_IDLE, SOPPOp.S_ENDPGM_SAVED, SOPPOp.S_CODE_END, SOPPOp.S_ENDPGM_ORDERED_PS_DONE, SOPPOp.S_TTRACEDATA}
-_CDNA_NO_ARG_SOPP = {'s_endpgm', 's_barrier', 's_wakeup', 's_icache_inv', 's_ttracedata', 's_nop', 's_sethalt', 's_sleep',
-                     's_setprio', 's_trap', 's_incperflevel', 's_decperflevel', 's_sendmsg', 's_sendmsghalt'}
-
-def _disasm_sopp(inst: SOPP) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  if cdna:
-    if name == 's_endpgm': return name if inst.simm16 == 0 else f"{name} {inst.simm16}"
-    if name in ('s_barrier', 's_wakeup', 's_icache_inv', 's_ttracedata'): return name
-    if name == 's_waitcnt':
-      vm, lgkm, exp = inst.simm16 & 0xf, (inst.simm16 >> 8) & 0x3f, (inst.simm16 >> 4) & 0x7
-      p = [f"vmcnt({vm})" if vm != 0xf else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0x3f else ""]
-      return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
-    if name.startswith(('s_cbranch', 's_branch')): return f"{name} {inst.simm16}"
-    return f"{name} 0x{inst.simm16:x}" if inst.simm16 else name
-  # RDNA
-  if inst.op in NO_ARG_SOPP: return name
-  if inst.op == SOPPOp.S_ENDPGM: return name if inst.simm16 == 0 else f"{name} {inst.simm16}"
-  if inst.op == SOPPOp.S_WAITCNT:
-    vm, exp, lgkm = (inst.simm16 >> 10) & 0x3f, inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x3f
-    p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0x3f else ""]
-    return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
-  if inst.op == SOPPOp.S_DELAY_ALU:
-    deps, skips = ['VALU_DEP_1','VALU_DEP_2','VALU_DEP_3','VALU_DEP_4','TRANS32_DEP_1','TRANS32_DEP_2','TRANS32_DEP_3','FMA_ACCUM_CYCLE_1','SALU_CYCLE_1','SALU_CYCLE_2','SALU_CYCLE_3'], ['SAME','NEXT','SKIP_1','SKIP_2','SKIP_3','SKIP_4']
-    id0, skip, id1 = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 7) & 0xf
-    dep = lambda v: deps[v-1] if 0 < v <= len(deps) else str(v)
-    p = [f"instid0({dep(id0)})" if id0 else "", f"instskip({skips[skip]})" if skip else "", f"instid1({dep(id1)})" if id1 else ""]
-    return f"s_delay_alu {' | '.join(x for x in p if x) or '0'}"
-  return f"{name} {inst.simm16}" if name.startswith(('s_cbranch', 's_branch')) else f"{name} 0x{inst.simm16:x}"
-
-def _disasm_smem(inst: SMEM) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  if inst.op in (SMEMOp.S_GL1_INV, SMEMOp.S_DCACHE_INV): return name
-  soe, imm = getattr(inst, 'soe', 0), getattr(inst, 'imm', 1)
-  is_rdna4 = 'rdna4' in inst.__class__.__module__
-  offset = inst.ioffset if is_rdna4 else getattr(inst, 'offset', 0)
-  if cdna:
-    if soe and imm: off_s = f"{decode_src(inst.soffset, cdna)} offset:0x{offset:x}"
-    elif imm: off_s = f"0x{offset:x}"
-    elif offset < 256: off_s = decode_src(offset, cdna)
-    else: off_s = decode_src(inst.soffset, cdna)
-  elif offset and inst.soffset != 124: off_s = f"{decode_src(inst.soffset, cdna)} offset:0x{offset:x}"
-  elif offset: off_s = f"0x{offset:x}"
-  else: off_s = decode_src(inst.soffset, cdna)
-  is_buffer = 'buffer' in name or 's_atc_probe_buffer' == name
-  sbase_idx, sbase_count = inst.sbase * 2, 4 if is_buffer else 2
-  sbase_str = _fmt_src(sbase_idx, sbase_count, cdna) if sbase_count == 2 else _sreg(sbase_idx, sbase_count) if sbase_idx <= 105 else _reg("ttmp", sbase_idx - 108, sbase_count)
-  if name in ('s_atc_probe', 's_atc_probe_buffer'): return f"{name} {inst.sdata}, {sbase_str}, {off_s}"
-  if 'prefetch' in name:
-    off = getattr(inst, 'ioffset', inst.offset)
-    if off >= 0x800000: off = off - 0x1000000
-    off_s = f"0x{off:x}" if off > 255 else str(off)
-    soff_s = decode_src(inst.soffset, cdna) if inst.soffset != 124 else "null"
-    if 'pc_rel' in name: return f"{name} {off_s}, {soff_s}, {inst.sdata}"
-    return f"{name} {sbase_str}, {off_s}, {soff_s}, {inst.sdata}"
-  th, scope = getattr(inst, 'th', 0), getattr(inst, 'scope', 0)
-  if th or scope:
-    th_names = ['TH_LOAD_RT', 'TH_LOAD_NT', 'TH_LOAD_HT', 'TH_LOAD_LU']
-    scope_names = ['SCOPE_CU', 'SCOPE_SE', 'SCOPE_DEV', 'SCOPE_SYS']
-    mods = (f" th:{th_names[th]}" if th else "") + (f" scope:{scope_names[scope]}" if scope else "")
-    return f"{name} {_fmt_sdst(inst.sdata, inst.dst_regs(), cdna)}, {sbase_str}, {off_s}{mods}"
-  return f"{name} {_fmt_sdst(inst.sdata, inst.dst_regs(), cdna)}, {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (getattr(inst, 'dlc', 0), " dlc"))
-
-def _disasm_flat(inst: FLAT) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  acc = getattr(inst, 'acc', 0)
-  reg_fn = _areg if acc else _vreg
-  seg = ['flat', 'scratch', 'global'][inst.seg] if inst.seg < 3 else 'flat'
-  instr = f"{seg}_{name.split('_', 1)[1] if '_' in name else name}"
-  off_val = inst.offset if seg == 'flat' else (inst.offset if inst.offset < 4096 else inst.offset - 8192)
-  w = inst.dst_regs() * (2 if '_x2' in name else 1) * (2 if 'cmpswap' in name else 1)
-  off_s = f" offset:{off_val}" if off_val else ""
-  if cdna: mods = f"{off_s}{' glc' if inst.sc0 else ''}{' slc' if inst.nt else ''}"
-  else: mods = f"{off_s}{' glc' if inst.glc else ''}{' slc' if inst.slc else ''}{' dlc' if inst.dlc else ''}"
-  if seg == 'flat' or inst.saddr == 0x7F: saddr_s = ""
-  elif inst.saddr == 124: saddr_s = ", off"
-  elif seg == 'scratch': saddr_s = f", {decode_src(inst.saddr, cdna)}"
-  elif inst.saddr in (SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS): saddr_s = f", {(SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS)[inst.saddr]}"
-  elif t := _ttmp(inst.saddr, 2): saddr_s = f", {t}"
-  else: saddr_s = f", {_sreg(inst.saddr, 2) if inst.saddr < 106 else decode_src(inst.saddr, cdna)}"
-  if 'addtid' in name: return f"{instr} {'a' if acc else 'v'}{inst.data if 'store' in name else inst.vdst}{saddr_s}{mods}"
-  if cdna: addr_w = 1 if seg == 'scratch' else 2
-  else: addr_w = 1 if seg == 'scratch' or (inst.saddr not in (0x7F, 124)) else 2
-  addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(inst.addr, addr_w)
-  data_s, vdst_s = reg_fn(inst.data, w), reg_fn(inst.vdst, w // 2 if 'cmpswap' in name else w)
-  glc_or_sc0 = inst.sc0 if cdna else inst.glc
-  if 'atomic' in name:
-    return f"{instr} {vdst_s}, {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}" if glc_or_sc0 else f"{instr} {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}"
-  if 'store' in name: return f"{instr} {addr_s}, {data_s}{saddr_s}{mods}"
-  return f"{instr} {reg_fn(inst.vdst, w)}, {addr_s}{saddr_s}{mods}"
-
-def _disasm_ds(inst: DS) -> str:
-  op, name = inst.op, inst.op_name.lower()
-  acc = getattr(inst, 'acc', 0)
-  reg_fn = _areg if acc else _vreg
-  rp = 'a' if acc else 'v'
-  gds = " gds" if inst.gds else ""
-  off = f" offset:{inst.offset0 | (inst.offset1 << 8)}" if inst.offset0 or inst.offset1 else ""
-  off2 = (" offset0:" + str(inst.offset0) if inst.offset0 else "") + (" offset1:" + str(inst.offset1) if inst.offset1 else "")
-  w = inst.dst_regs()
-  d0, d1, dst, addr = reg_fn(inst.data0, w), reg_fn(inst.data1, w), reg_fn(inst.vdst, w), f"v{inst.addr}"
-
-  if op == DSOp.DS_NOP: return name
-  if op == DSOp.DS_BVH_STACK_RTN_B32: return f"{name} v{inst.vdst}, {addr}, v{inst.data0}, {_vreg(inst.data1, 4)}{off}{gds}"
-  if 'bvh_stack_push' in name:
-    d1_regs = 8 if 'push8' in name else 4
-    vdst_regs = 2 if 'pop2' in name else 1
-    vdst_s = _vreg(inst.vdst, vdst_regs) if vdst_regs > 1 else f"v{inst.vdst}"
-    return f"{name} {vdst_s}, {addr}, v{inst.data0}, {_vreg(inst.data1, d1_regs)}{off}{gds}"
-  if 'gws_sema' in name and op != DSOp.DS_GWS_SEMA_BR: return f"{name}{off}{gds}"
-  if 'gws_' in name: return f"{name} {addr}{off}{gds}"
-  if op in (DSOp.DS_CONSUME, DSOp.DS_APPEND): return f"{name} {rp}{inst.vdst}{off}{gds}"
-  if 'gs_reg' in name: return f"{name} {reg_fn(inst.vdst, 2)}, {rp}{inst.data0}{off}{gds}"
-  if '2addr' in name:
-    if 'load' in name: return f"{name} {reg_fn(inst.vdst, w*2)}, {addr}{off2}{gds}"
-    if 'store' in name and 'xchg' not in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
-    return f"{name} {reg_fn(inst.vdst, w*2)}, {addr}, {d0}, {d1}{off2}{gds}"
-  if 'write2' in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
-  if 'read2' in name: return f"{name} {reg_fn(inst.vdst, w*2)}, {addr}{off2}{gds}"
-  if 'load' in name: return f"{name} {rp}{inst.vdst}{off}{gds}" if 'addtid' in name else f"{name} {dst}, {addr}{off}{gds}"
-  if 'store' in name and not _has(name, 'cmp', 'xchg'):
-    return f"{name} {rp}{inst.data0}{off}{gds}" if 'addtid' in name else f"{name} {addr}, {d0}{off}{gds}"
-  if 'swizzle' in name or op == DSOp.DS_ORDERED_COUNT: return f"{name} {rp}{inst.vdst}, {addr}{off}{gds}"
-  if 'permute' in name: return f"{name} {rp}{inst.vdst}, {addr}, {rp}{inst.data0}{off}{gds}"
-  if 'condxchg' in name: return f"{name} {reg_fn(inst.vdst, 2)}, {addr}, {reg_fn(inst.data0, 2)}{off}{gds}"
-  if _has(name, 'cmpstore', 'mskor', 'wrap'):
-    return f"{name} {dst}, {addr}, {d0}, {d1}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}, {d1}{off}{gds}"
-  return f"{name} {dst}, {addr}, {d0}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}{off}{gds}"
-
-def _disasm_vop3(inst: VOP3) -> str:
-  op, name = inst.op, inst.op_name.lower()
-
-  # RDNA4 v_s_* scalar VOP3 instructions
-  if name.startswith('v_s_'):
-    src = inst.lit(inst.src0) if inst.src0 == 255 else ("src_scc" if inst.src0 == 253 else _fmt_src(inst.src0, inst.src_regs(0)))
-    if inst.neg & 1: src = f"-{src}"
-    if inst.abs & 1: src = f"|{src}|"
-    clamp = inst.cm if 'cm' in inst._fields else getattr(inst, 'clmp', 0)
-    return f"{name} s{inst.vdst}, {src}" + (" clamp" if clamp else "") + _omod(inst.omod)
-
-  # VOP3SD (shared encoding)
-  if isinstance(op, VOP3SDOp):
-    sdst = (inst.clmp << 7) | (inst.opsel << 3) | inst.abs
-    def src(v, neg, n):
-      s = inst.lit(v) if v == 255 else ("src_scc" if v == 253 else (_fmt_src(v, n) if n > 1 else inst.lit(v)))
-      return f"neg({s})" if neg and v == 255 else (f"-{s}" if neg else s)
-    s0, s1, s2 = src(inst.src0, inst.neg & 1, inst.src_regs(0)), src(inst.src1, inst.neg & 2, inst.src_regs(1)), src(inst.src2, inst.neg & 4, inst.src_regs(2))
-    dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else f"v{inst.vdst}"
-    srcs = f"{s0}, {s1}, {s2}" if inst.num_srcs() == 3 else f"{s0}, {s1}"
-    return f"{name} {dst}, {_fmt_sdst(sdst, 1)}, {srcs}" + _omod(inst.omod)
-
-  # Detect 16-bit operand sizes
-  is16_d = is16_s = is16_s2 = False
-  if 'cvt_pk' in name: is16_s = name.endswith('16')
-  elif m := re.match(r'v_(?:cvt|frexp_exp)_([a-z0-9_]+)_([a-z0-9]+)', name):
-    is16_d, is16_s = _has(m.group(1), 'f16','i16','u16','b16'), _has(m.group(2), 'f16','i16','u16','b16')
-    is16_s2 = is16_s
-  elif re.match(r'v_mad_[iu]32_[iu]16', name): is16_s = True
-  elif 'pack_b32' in name: is16_s = is16_s2 = True
-  elif 'sat_pk' in name: is16_d = True
-  else: is16_d = is16_s = is16_s2 = inst.is_16bit()
-
-  s0 = _vop3_src(inst, inst.src0, inst.neg&1, inst.abs&1, inst.opsel&1, inst.src_regs(0), is16_s)
-  s1 = _vop3_src(inst, inst.src1, inst.neg&2, inst.abs&2, inst.opsel&2, inst.src_regs(1), is16_s)
-  s2 = _vop3_src(inst, inst.src2, inst.neg&4, inst.abs&4, inst.opsel&4, inst.src_regs(2), is16_s2)
-
-  # Destination
-  dn = inst.dst_regs()
-  if op == VOP3Op.V_READLANE_B32: dst = _fmt_sdst(inst.vdst, 1)
-  elif dn > 1: dst = _vreg(inst.vdst, dn)
-  elif is16_d: dst = f"v{inst.vdst}.h" if (inst.opsel & 8) else f"v{inst.vdst}.l"
-  else: dst = f"v{inst.vdst}"
-
-  clamp = inst.cm if 'cm' in inst._fields else getattr(inst, 'clmp', 0)
-  cl, om = " clamp" if clamp else "", _omod(inst.omod)
-  nonvgpr_opsel = (inst.src0 < 256 and (inst.opsel & 1)) or (inst.src1 < 256 and (inst.opsel & 2)) or (inst.src2 < 256 and (inst.opsel & 4))
-  need_opsel = nonvgpr_opsel or (inst.opsel and not is16_s)
-
-  if inst.op < 256:  # VOPC
-    return f"{name}_e64 {s0}, {s1}{cl}" if name.startswith('v_cmpx') else f"{name}_e64 {_fmt_sdst(inst.vdst, 1)}, {s0}, {s1}{cl}"
-  if inst.op < 384:  # VOP2
-    n = inst.num_srcs()
-    os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
-    return f"{name}_e64 {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name}_e64 {dst}, {s0}, {s1}{os}{cl}{om}"
-  if inst.op < 512:  # VOP1
-    if re.match(r'v_cvt_f32_(bf|fp)8', name) and inst.opsel:
-      os = f" byte_sel:{((inst.opsel & 1) << 1) | ((inst.opsel >> 1) & 1)}"
-    else:
-      os = _opsel_str(inst.opsel, 1, need_opsel, is16_d)
-    return f"{name}_e64" if op in (VOP3Op.V_NOP, VOP3Op.V_PIPEFLUSH) else f"{name}_e64 {dst}, {s0}{os}{cl}{om}"
-  # Native VOP3
-  n = inst.num_srcs()
-  if 'cvt_sr' in name and inst.opsel:
-    os = f" byte_sel:{inst.opsel >> 2}"
-  else:
-    os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
-  return f"{name} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{os}{cl}{om}"
-
-def _disasm_vop3sd(inst: VOP3SD) -> str:
-  name = inst.op_name.lower()
-  src2_n = 2 if '_co_' in name and '64' in name else inst.src_regs(2)
-  def src(v, neg, n):
-    s = inst.lit(v) if v == 255 else ("src_scc" if v == 253 else (_fmt_src(v, n) if n > 1 else inst.lit(v)))
-    return f"neg({s})" if neg and v == 255 else (f"-{s}" if neg else s)
-  s0, s1, s2 = src(inst.src0, inst.neg & 1, inst.src_regs(0)), src(inst.src1, inst.neg & 2, inst.src_regs(1)), src(inst.src2, inst.neg & 4, src2_n)
-  dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else f"v{inst.vdst}"
-  srcs = f"{s0}, {s1}, {s2}" if inst.num_srcs() == 3 else f"{s0}, {s1}"
-  clamp = inst.cm if 'cm' in inst._fields else getattr(inst, 'clmp', 0)
-  return f"{name} {dst}, {_fmt_sdst(inst.sdst, 1)}, {srcs}{' clamp' if clamp else ''}{_omod(inst.omod)}"
-
-def _disasm_vopd(inst: VOPD) -> str:
-  lit = inst._literal or inst.literal
-  is_rdna4 = 'rdna4' in inst.__class__.__module__
-  op_enum = R4_VOPDOp if is_rdna4 else VOPDOp
-  vdst_y, nx, ny = (inst.vdsty << 1) | ((inst.vdstx & 1) ^ 1), op_enum(inst.opx).name.lower(), op_enum(inst.opy).name.lower()
-  def half(n, vd, s0, vs1):
-    if 'mov' in n: return f"{n} v{vd}, {inst.lit(s0)}"
-    if 'fmamk' in n and lit: return f"{n} v{vd}, {inst.lit(s0)}, 0x{lit:x}, v{vs1}"
-    if 'fmaak' in n and lit: return f"{n} v{vd}, {inst.lit(s0)}, v{vs1}, 0x{lit:x}"
-    return f"{n} v{vd}, {inst.lit(s0)}, v{vs1}"
-  return f"{half(nx, inst.vdstx, inst.srcx0, inst.vsrcx1)} :: {half(ny, vdst_y, inst.srcy0, inst.vsrcy1)}"
-
-def _swmmac_regs(name: str) -> tuple[int, int, int, int]:
-  """Return (dst, src0, src1, src2) register counts for SWMMAC instructions."""
-  if 'f16_16x16x32' in name or 'bf16_16x16x32' in name: return (4, 4, 8, 1)
-  if 'f32_16x16x32_f16' in name or 'f32_16x16x32_bf16' in name: return (8, 4, 8, 1)
-  if 'i32_16x16x32_iu4' in name: return (8, 1, 2, 1)
-  if 'i32_16x16x64_iu4' in name: return (8, 2, 4, 1)
-  if 'i32_16x16x32_iu8' in name or 'f32_16x16x32_fp8' in name or 'f32_16x16x32_bf8' in name: return (8, 2, 4, 1)
-  return (8, 8, 8, 8)
-
-def _disasm_vop3p(inst: VOP3P) -> str:
-  name = inst.op_name.lower()
-  is_wmma, is_swmmac, n, is_fma_mix = 'wmma' in name, 'swmmac' in name, inst.num_srcs(), 'fma_mix' in name
-  def get_src(v, sc): return inst.lit(v) if v == 255 else _fmt_src(v, sc)
-  if is_swmmac:
-    dn, s0n, s1n, s2n = _swmmac_regs(name)
-    src0, src1, src2, dst = get_src(inst.src0, s0n), get_src(inst.src1, s1n), get_src(inst.src2, s2n), _vreg(inst.vdst, dn)
-  elif is_wmma:
-    is_rdna4_wmma = 'rdna4' in inst.__class__.__module__
-    sc = 1 if '16x16x16_iu4' in name else 2 if ('iu4' in name or 'iu8' in name or 'fp8' in name or 'bf8' in name) else 4
-    if not is_rdna4_wmma: sc *= 2
-    dc = 8 if not is_rdna4_wmma else (4 if ('f16_16x16' in name or 'bf16_16x16' in name) and 'f32' not in name else 8)
-    src0, src1, src2, dst = get_src(inst.src0, sc), get_src(inst.src1, sc), get_src(inst.src2, dc), _vreg(inst.vdst, dc)
-  else: src0, src1, src2, dst = get_src(inst.src0, 1), get_src(inst.src1, 1), get_src(inst.src2, 1), f"v{inst.vdst}"
-  opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
-  clamp = inst.cm if 'cm' in inst._fields else getattr(inst, 'clmp', 0)
-  if is_fma_mix:
-    def m(s, neg, abs_): return f"-{f'|{s}|' if abs_ else s}" if neg else (f"|{s}|" if abs_ else s)
-    src0, src1, src2 = m(src0, inst.neg & 1, inst.neg_hi & 1), m(src1, inst.neg & 2, inst.neg_hi & 2), m(src2, inst.neg & 4, inst.neg_hi & 4)
-    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi else []) + (["clamp"] if clamp else [])
-  elif is_swmmac:
-    mods = ([f"index_key:{inst.opsel}"] if inst.opsel else []) + ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + \
-           ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if clamp else [])
-  else:
-    opsel_hi_default = 7 if n == 3 else 3
-    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != opsel_hi_default else []) + \
-           ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if clamp else [])
-  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
-
-def _disasm_buf(inst: MUBUF | MTBUF) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  acc = getattr(inst, 'acc', 0)
-  reg_fn = _areg if acc else _vreg
-  if cdna and name in ('buffer_wbl2', 'buffer_inv'): return name
-  if not cdna and inst.op in (MUBUFOp.BUFFER_GL0_INV, MUBUFOp.BUFFER_GL1_INV): return name
-  w = (2 if _has(name, 'xyz', 'xyzw') else 1) if 'd16' in name else \
-      ((2 if _has(name, 'b64', 'u64', 'i64') else 1) * (2 if 'cmpswap' in name else 1)) if 'atomic' in name else \
-      {'b32':1,'b64':2,'b96':3,'b128':4,'b16':1,'x':1,'xy':2,'xyz':3,'xyzw':4}.get(name.split('_')[-1], 1)
-  if hasattr(inst, 'tfe') and inst.tfe: w += 1
-  vaddr = _vreg(inst.vaddr, 2) if inst.offen and inst.idxen else f"v{inst.vaddr}" if inst.offen or inst.idxen else "off"
-  srsrc = _sreg_or_ttmp(inst.srsrc*4, 4)
-  is_mtbuf = isinstance(inst, MTBUF) or isinstance(inst, C_MTBUF)
-  if is_mtbuf:
-    dfmt, nfmt = inst.format & 0xf, (inst.format >> 4) & 0x7
-    if acc: fmt_s = f"  dfmt:{dfmt}, nfmt:{nfmt},"
-    elif not cdna: fmt_s = f" format:{inst.format}" if inst.format else ""
-    else:
-      dfmt_names = ['INVALID', '8', '16', '8_8', '32', '16_16', '10_11_11', '11_11_10', '10_10_10_2', '2_10_10_10', '8_8_8_8', '32_32', '16_16_16_16', '32_32_32', '32_32_32_32', 'RESERVED_15']
-      nfmt_names = ['UNORM', 'SNORM', 'USCALED', 'SSCALED', 'UINT', 'SINT', 'RESERVED_6', 'FLOAT']
-      if dfmt == 1 and nfmt == 0: fmt_s = ""
-      elif nfmt == 0: fmt_s = f" format:[BUF_DATA_FORMAT_{dfmt_names[dfmt]}]"
-      elif dfmt == 1: fmt_s = f" format:[BUF_NUM_FORMAT_{nfmt_names[nfmt]}]"
-      else: fmt_s = f" format:[BUF_DATA_FORMAT_{dfmt_names[dfmt]},BUF_NUM_FORMAT_{nfmt_names[nfmt]}]"
-  else: fmt_s = ""
-  if cdna: mods = [m for c, m in [(inst.idxen,"idxen"),(inst.offen,"offen"),(inst.offset,f"offset:{inst.offset}"),(inst.sc0,"glc"),(inst.nt,"slc"),(inst.sc1,"sc1")] if c]
-  else: mods = [m for c, m in [(inst.idxen,"idxen"),(inst.offen,"offen"),(inst.offset,f"offset:{inst.offset}"),(inst.glc,"glc"),(inst.dlc,"dlc"),(inst.slc,"slc"),(inst.tfe,"tfe")] if c]
-  soffset_s = decode_src(inst.soffset, cdna)
-  if cdna and not acc and is_mtbuf: return f"{name} {reg_fn(inst.vdata, w)}, {vaddr}, {srsrc}, {soffset_s}{fmt_s}{' ' + ' '.join(mods) if mods else ''}"
-  return f"{name} {reg_fn(inst.vdata, w)}, {vaddr}, {srsrc},{fmt_s} {soffset_s}{' ' + ' '.join(mods) if mods else ''}"
-
-def _mimg_vaddr_width(name: str, dim: int, a16: bool) -> int:
-  base =              [1, 2, 3, 3,   2,     3,     3,      4][dim]
-  grad =              [1, 2, 3, 2,   1,     2,     2,      2][dim]
-  if 'get_resinfo' in name: return 1
-  packed, unpacked = 0, 0
-  if '_mip' in name: packed += 1
-  elif 'sample' in name or 'gather' in name:
-    if '_o' in name: unpacked += 1
-    if re.search(r'_c(_|$)', name): unpacked += 1
-    if '_d' in name: unpacked += (grad + 1) & ~1 if '_g16' in name else grad*2
-    if '_b' in name: unpacked += 1
-    if '_l' in name and '_cl' not in name and '_lz' not in name: packed += 1
-    if '_cl' in name: packed += 1
-  return (base + packed + 1) // 2 + unpacked if a16 else base + packed + unpacked
-
-def _disasm_mimg(inst: MIMG) -> str:
-  name = inst.op_name.lower()
-  srsrc_base = inst.srsrc * 4
-  srsrc_str = _sreg_or_ttmp(srsrc_base, 8)
-  if 'bvh' in name:
-    vaddr = (9 if '64' in name else 8) if inst.a16 else (12 if '64' in name else 11)
-    return f"{name} {_vreg(inst.vdata, 4)}, {_vreg(inst.vaddr, vaddr)}, {_sreg_or_ttmp(srsrc_base, 4)}{' a16' if inst.a16 else ''}"
-  vdata = 4 if 'gather4' in name or 'msaa_load' in name else (bin(inst.dmask).count('1') or 1)
-  if inst.d16: vdata = (vdata + 1) // 2
-  if inst.tfe: vdata += 1
-  dim_names = ['1d', '2d', '3d', 'cube', '1d_array', '2d_array', '2d_msaa', '2d_msaa_array']
-  dim = dim_names[inst.dim] if inst.dim < len(dim_names) else f"dim_{inst.dim}"
-  vaddr = _mimg_vaddr_width(name, inst.dim, inst.a16)
-  vaddr_str = f"v{inst.vaddr}" if vaddr == 1 else _vreg(inst.vaddr, vaddr)
-  mods = [f"dmask:0x{inst.dmask:x}"] if inst.dmask and (inst.dmask != 15 or 'atomic' in name) else []
-  mods.append(f"dim:SQ_RSRC_IMG_{dim.upper()}")
-  for flag, mod in [(inst.unrm,"unorm"),(inst.glc,"glc"),(inst.slc,"slc"),(inst.dlc,"dlc"),(inst.r128,"r128"),
-                    (inst.a16,"a16"),(inst.tfe,"tfe"),(inst.lwe,"lwe"),(inst.d16,"d16")]:
-    if flag: mods.append(mod)
-  ssamp_str = ""
-  if 'sample' in name or 'gather' in name or 'get_lod' in name:
-    ssamp_str = ", " + _sreg_or_ttmp(inst.ssamp * 4, 4)
-  return f"{name} {_vreg(inst.vdata, vdata)}, {vaddr_str}, {srsrc_str}{ssamp_str} {' '.join(mods)}"
-
-def _disasm_sop1(inst: SOP1) -> str:
-  op, name, cdna = inst.op, inst.op_name.lower(), _is_cdna(inst)
-  src = inst.lit(inst.ssrc0) if inst.ssrc0 == 255 else _fmt_src(inst.ssrc0, inst.src_regs(0), cdna)
-  if not cdna:
-    if op == SOP1Op.S_GETPC_B64: return f"{name} {_fmt_sdst(inst.sdst, 2)}"
-    if op in (SOP1Op.S_SETPC_B64, SOP1Op.S_RFE_B64): return f"{name} {src}"
-    if op == SOP1Op.S_SWAPPC_B64: return f"{name} {_fmt_sdst(inst.sdst, 2)}, {src}"
-    if op in (SOP1Op.S_SENDMSG_RTN_B32, SOP1Op.S_SENDMSG_RTN_B64): return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, sendmsg({MSG.get(inst.ssrc0, str(inst.ssrc0))})"
-  sop1_src_only = ('S_ALLOC_VGPR', 'S_SLEEP_VAR', 'S_BARRIER_SIGNAL', 'S_BARRIER_SIGNAL_ISFIRST', 'S_BARRIER_INIT', 'S_BARRIER_JOIN')
-  if inst.op_name in sop1_src_only: return f"{name} {src}"
-  return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs(), cdna)}, {src}"
-
-def _disasm_sop2(inst: SOP2) -> str:
-  cdna, name = _is_cdna(inst), inst.op_name.lower()
-  lit = getattr(inst, '_literal', None)
-  s0 = inst.lit(inst.ssrc0) if inst.ssrc0 == 255 else _fmt_src(inst.ssrc0, inst.src_regs(0), cdna)
-  s1 = inst.lit(inst.ssrc1) if inst.ssrc1 == 255 else _fmt_src(inst.ssrc1, inst.src_regs(1), cdna)
-  dst = _fmt_sdst(inst.sdst, inst.dst_regs(), cdna)
-  if 'fmamk' in name and lit is not None: return f"{name} {dst}, {s0}, 0x{lit:x}, {s1}"
-  if 'fmaak' in name and lit is not None: return f"{name} {dst}, {s0}, {s1}, 0x{lit:x}"
-  return f"{name} {dst}, {s0}, {s1}"
-
-def _disasm_sopc(inst: SOPC) -> str:
-  cdna = _is_cdna(inst)
-  s0 = inst.lit(inst.ssrc0) if inst.ssrc0 == 255 else _fmt_src(inst.ssrc0, inst.src_regs(0), cdna)
-  s1 = inst.lit(inst.ssrc1) if inst.ssrc1 == 255 else _fmt_src(inst.ssrc1, inst.src_regs(1), cdna)
-  return f"{inst.op_name.lower()} {s0}, {s1}"
-
-def _disasm_sopk(inst: SOPK) -> str:
-  op, name, cdna = inst.op, inst.op_name.lower(), _is_cdna(inst)
-  is_rdna4 = 'rdna4' in inst.__class__.__module__
-  hw = HWREG
-  def fmt_hwreg(hid, hoff, hsz):
-    if hid not in hw: return f"0x{inst.simm16:x}"
-    hr_name = str(hid) if is_rdna4 else hw[hid]
-    return f"hwreg({hr_name})" if hoff == 0 and hsz == 32 else f"hwreg({hr_name}, {hoff}, {hsz})"
-  if name == 's_setreg_imm32_b32' or (not cdna and op == SOPKOp.S_SETREG_IMM32_B32):
-    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
-    return f"{name} {fmt_hwreg(hid, hoff, hsz)}, 0x{inst._literal:x}"
-  if not cdna and op == SOPKOp.S_VERSION: return f"{name} 0x{inst.simm16:x}"
-  if (not cdna and op in (SOPKOp.S_SETREG_B32, SOPKOp.S_GETREG_B32)) or (cdna and name in ('s_setreg_b32', 's_getreg_b32')):
-    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
-    hs = fmt_hwreg(hid, hoff, hsz)
-    return f"{name} {hs}, {_fmt_sdst(inst.sdst, 1, cdna)}" if 'setreg' in name else f"{name} {_fmt_sdst(inst.sdst, 1, cdna)}, {hs}"
-  if not cdna and op in (SOPKOp.S_SUBVECTOR_LOOP_BEGIN, SOPKOp.S_SUBVECTOR_LOOP_END):
-    return f"{name} {_fmt_sdst(inst.sdst, 1)}, 0x{inst.simm16:x}"
-  return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs(), cdna)}, 0x{inst.simm16:x}"
-
-def _disasm_vinterp(inst: VINTERP) -> str:
-  mods = _mods((inst.waitexp, f"wait_exp:{inst.waitexp}"), (inst.clmp, "clamp"))
-  return f"{inst.op_name.lower()} v{inst.vdst}, {inst.lit(inst.src0, inst.neg & 1)}, {inst.lit(inst.src1, inst.neg & 2)}, {inst.lit(inst.src2, inst.neg & 4)}" + (" " + mods if mods else "")
-
-EXP_TARGETS = {0: 'mrt0', 1: 'mrt1', 2: 'mrt2', 3: 'mrt3', 4: 'mrt4', 5: 'mrt5', 6: 'mrt6', 7: 'mrt7',
-               8: 'mrtz', 9: 'null', 12: 'pos0', 13: 'pos1', 14: 'pos2', 15: 'pos3', 16: 'pos4',
-               32: 'param0', 33: 'param1', 34: 'param2', 35: 'param3', 36: 'param4', 37: 'param5'}
-def _disasm_vexport(inst) -> str:
-  tgt = EXP_TARGETS.get(inst.target, f'{inst.target}')
-  srcs = [f'v{getattr(inst, f"vsrc{i}")}' if inst.en & (1 << i) else 'off' for i in range(4)]
-  mods = _mods((inst.done, "done"), (inst.row, "row_en"))
-  return f"export {tgt} {', '.join(srcs)}" + (" " + mods if mods else "")
-
-def _disasm_vbuffer(inst) -> str:
-  name = inst.op_name.lower().replace('buffer_', 'buffer_').replace('tbuffer_', 'tbuffer_')
-  w = (2 if _has(name, 'xyz', 'xyzw') else 1) if 'd16' in name else \
-      ((2 if _has(name, 'b64', 'u64', 'i64') else 1) * (2 if 'cmpswap' in name else 1)) if 'atomic' in name else \
-      {'b32':1,'b64':2,'b96':3,'b128':4,'b16':1,'x':1,'xy':2,'xyz':3,'xyzw':4}.get(name.split('_')[-1], inst.dst_regs())
-  if getattr(inst, 'tfe', 0): w += 1
-  vdata = _vreg(inst.vdata, w) if w else f'v{inst.vdata}'
-  vaddr = _vreg(inst.vaddr, 2) if inst.offen and inst.idxen else (f'v{inst.vaddr}' if inst.offen or inst.idxen else 'off')
-  srsrc = f'ttmp[{inst.rsrc - 108}:{inst.rsrc - 108 + 3}]' if inst.rsrc >= 108 else f's[{inst.rsrc}:{inst.rsrc + 3}]'
-  soff = decode_src(inst.soffset) if inst.soffset >= 106 else f's{inst.soffset}'
-  fmt = getattr(inst, 'format', 0)
-  fmt_names = {e.value: e.name for e in BufFmt}
-  fmt_s = f" format:[{fmt_names[fmt]}]" if fmt > 1 and fmt in fmt_names else (f" format:{fmt}" if fmt > 1 else "")
-  if 'atomic' in name: th_names = {1: 'TH_ATOMIC_RETURN', 6: 'TH_ATOMIC_CASCADE_NT'}
-  elif 'store' in name: th_names = {3: 'TH_STORE_BYPASS', 6: 'TH_STORE_NT_HT'}
-  else: th_names = {3: 'TH_LOAD_BYPASS', 6: 'TH_LOAD_NT_HT'}
-  scope_names = {1: 'SCOPE_SE', 2: 'SCOPE_DEV', 3: 'SCOPE_SYS'}
-  mods = _mods((inst.idxen, "idxen"), (inst.offen, "offen"), (inst.ioffset, f"offset:{inst.ioffset}"),
-               (inst.th in th_names, f"th:{th_names.get(inst.th, '')}"), (inst.scope in scope_names, f"scope:{scope_names.get(inst.scope, '')}"))
-  return f"{name} {vdata}, {vaddr}, {srsrc}, {soff}{fmt_s}" + (" " + mods if mods else "")
-
-DISASM_HANDLERS: dict[type, callable] = {
-  VOP1: _disasm_vop1, VOP2: _disasm_vop2, VOPC: _disasm_vopc, VOP3: _disasm_vop3, VOP3SD: _disasm_vop3sd, VOPD: _disasm_vopd, VOP3P: _disasm_vop3p,
-  VINTERP: _disasm_vinterp, SOPP: _disasm_sopp, SMEM: _disasm_smem, DS: _disasm_ds, FLAT: _disasm_flat, MUBUF: _disasm_buf, MTBUF: _disasm_buf,
-  MIMG: _disasm_mimg, SOP1: _disasm_sop1, SOP2: _disasm_sop2, SOPC: _disasm_sopc, SOPK: _disasm_sopk,
-  # RDNA4
-  R4_VOP1: _disasm_vop1, R4_VOP2: _disasm_vop2, R4_VOPC: _disasm_vopc, R4_VOP3: _disasm_vop3, R4_VOP3SD: _disasm_vop3sd,
-  R4_VOPD: _disasm_vopd, R4_VOP3P: _disasm_vop3p, R4_VINTERP: _disasm_vinterp, R4_SOPP: _disasm_sopp, R4_SMEM: _disasm_smem,
-  R4_DS: _disasm_ds, R4_SOP1: _disasm_sop1, R4_SOP2: _disasm_sop2, R4_SOPC: _disasm_sopc, R4_SOPK: _disasm_sopk,
-  R4_VEXPORT: _disasm_vexport, R4_VBUFFER: _disasm_vbuffer}
-
-def disasm(inst: Inst) -> str: return DISASM_HANDLERS[type(inst)](inst)
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# CDNA DISASSEMBLER SUPPORT
-# ═══════════════════════════════════════════════════════════════════════════════
-
-try:
-  from extra.assembly.amd.autogen.cdna.ins import (VOP1 as CDNA_VOP1, VOP2 as CDNA_VOP2, VOPC as CDNA_VOPC, VOP3A, VOP3B, VOP3P as CDNA_VOP3P,
-    SOP1 as CDNA_SOP1, SOP2 as CDNA_SOP2, SOPC as CDNA_SOPC, SOPK as CDNA_SOPK, SOPP as CDNA_SOPP, SMEM as CDNA_SMEM, DS as CDNA_DS,
-    FLAT as CDNA_FLAT, MUBUF as CDNA_MUBUF, MTBUF as CDNA_MTBUF, SDWA, DPP, VOP1Op as CDNA_VOP1Op, VOP2Op as CDNA_VOP2Op, VOPCOp as CDNA_VOPCOp)
-
-  def _cdna_src(inst, v, neg, abs_=0, n=1):
-    s = inst.lit(v) if v == 255 else _fmt_src(v, n, cdna=True)
-    if abs_: s = f"|{s}|"
-    return f"neg({s})" if neg and v == 255 else (f"-{s}" if neg else s)
-
-  _CDNA_VOP3_ALIASES = {'v_fmac_f64': 'v_mul_legacy_f32', 'v_dot2c_f32_bf16': 'v_mac_f32'}
-
-  def _disasm_vop3a(inst) -> str:
-    op_val = inst._values.get('op', 0)
-    if hasattr(op_val, 'value'): op_val = op_val.value
-    name = inst.op_name.lower() or f'vop3a_op_{op_val}'
-    from extra.assembly.amd.dsl import spec_num_srcs, spec_regs
-    n = spec_num_srcs(name) if name else inst.num_srcs()
-    cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
-    orig_name = name
-    name = _CDNA_VOP3_ALIASES.get(name, name)
-    if name != orig_name:
-      s0, s1 = _cdna_src(inst, inst.src0, inst.neg&1, inst.abs&1, 1), _cdna_src(inst, inst.src1, inst.neg&2, inst.abs&2, 1)
-      s2 = ""
-      dst = f"v{inst.vdst}"
-    else:
-      dregs, r0, r1, r2 = spec_regs(name) if name else (inst.dst_regs(), inst.src_regs(0), inst.src_regs(1), inst.src_regs(2))
-      s0, s1, s2 = _cdna_src(inst, inst.src0, inst.neg&1, inst.abs&1, r0), _cdna_src(inst, inst.src1, inst.neg&2, inst.abs&2, r1), _cdna_src(inst, inst.src2, inst.neg&4, inst.abs&4, r2)
-      dst = _vreg(inst.vdst, dregs) if dregs > 1 else f"v{inst.vdst}"
-    if op_val >= 512:
-      return f"{name} {dst}, {s0}, {s1}, {s2}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{cl}{om}"
-    if op_val < 256:
-      sdst = _fmt_sdst(inst.vdst, 2, cdna=True)
-      return f"{name}_e64 {sdst}, {s0}, {s1}{cl}"
-    if 320 <= op_val < 512:
-      if name in ('v_nop', 'v_clrexcp'): return f"{name}_e64"
-      return f"{name}_e64 {dst}, {s0}{cl}{om}"
-    if name == 'v_cndmask_b32':
-      s2 = _fmt_src(inst.src2, 2, cdna=True)
-      return f"{name}_e64 {dst}, {s0}, {s1}, {s2}{cl}{om}"
-    if name in ('v_mul_legacy_f32', 'v_mac_f32'):
-      return f"{name}_e64 {dst}, {s0}, {s1}{cl}{om}"
-    suf = "_e64" if op_val < 512 else ""
-    return f"{name}{suf} {dst}, {s0}, {s1}, {s2}{cl}{om}" if n == 3 else f"{name}{suf} {dst}, {s0}, {s1}{cl}{om}"
-
-  def _disasm_vop3b(inst) -> str:
-    op_val = inst._values.get('op', 0)
-    if hasattr(op_val, 'value'): op_val = op_val.value
-    name = inst.op_name.lower() or f'vop3b_op_{op_val}'
-    from extra.assembly.amd.dsl import spec_num_srcs, spec_regs
-    n = spec_num_srcs(name) if name else inst.num_srcs()
-    dregs, r0, r1, r2 = spec_regs(name) if name else (inst.dst_regs(), inst.src_regs(0), inst.src_regs(1), inst.src_regs(2))
-    s0, s1, s2 = _cdna_src(inst, inst.src0, inst.neg&1, n=r0), _cdna_src(inst, inst.src1, inst.neg&2, n=r1), _cdna_src(inst, inst.src2, inst.neg&4, n=r2)
-    dst = _vreg(inst.vdst, dregs) if dregs > 1 else f"v{inst.vdst}"
-    sdst = _fmt_sdst(inst.sdst, 2, cdna=True)
-    cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
-    if name in ('v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'):
-      s2 = _fmt_src(inst.src2, 2, cdna=True)
-      return f"{name}_e64 {dst}, {sdst}, {s0}, {s1}, {s2}{cl}{om}"
-    suf = "_e64" if 'co_' in name else ""
-    return f"{name}{suf} {dst}, {sdst}, {s0}, {s1}, {s2}{cl}{om}" if n == 3 else f"{name}{suf} {dst}, {sdst}, {s0}, {s1}{cl}{om}"
-
-  def _disasm_cdna_vop3p(inst) -> str:
-    name, n, is_mfma = inst.op_name.lower(), inst.num_srcs(), 'mfma' in inst.op_name.lower() or 'smfmac' in inst.op_name.lower()
-    get_src = lambda v, sc: inst.lit(v) if v == 255 else _fmt_src(v, sc, cdna=True)
-    if is_mfma: sc = 2 if 'iu4' in name else 4 if 'iu8' in name or 'i4' in name else 8 if 'f16' in name or 'bf16' in name else 4; src0, src1, src2, dst = get_src(inst.src0, sc), get_src(inst.src1, sc), get_src(inst.src2, 16), _vreg(inst.vdst, 16)
-    else: src0, src1, src2, dst = get_src(inst.src0, 1), get_src(inst.src1, 1), get_src(inst.src2, 1), f"v{inst.vdst}"
-    opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
-    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != (7 if n == 3 else 3) else []) + \
-           ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if inst.clmp else [])
-    return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
-
-  _SEL = {0: 'BYTE_0', 1: 'BYTE_1', 2: 'BYTE_2', 3: 'BYTE_3', 4: 'WORD_0', 5: 'WORD_1', 6: 'DWORD'}
-  _UNUSED = {0: 'UNUSED_PAD', 1: 'UNUSED_SEXT', 2: 'UNUSED_PRESERVE'}
-  _DPP = {0x130: "wave_shl:1", 0x134: "wave_rol:1", 0x138: "wave_shr:1", 0x13c: "wave_ror:1", 0x140: "row_mirror", 0x141: "row_half_mirror", 0x142: "row_bcast:15", 0x143: "row_bcast:31"}
-
-  def _sdwa_src0(v, is_sgpr, sext=0, neg=0, abs_=0):
-    s = decode_src(v, cdna=True) if is_sgpr else f"v{v}"
-    if sext: s = f"sext({s})"
-    if abs_: s = f"|{s}|"
-    return f"-{s}" if neg else s
-
-  def _sdwa_vsrc1(v, sext=0, neg=0, abs_=0):
-    s = f"v{v}"
-    if sext: s = f"sext({s})"
-    if abs_: s = f"|{s}|"
-    return f"-{s}" if neg else s
-
-  _OMOD_SDWA = {0: "", 1: " mul:2", 2: " mul:4", 3: " div:2"}
-
-  def _disasm_sdwa(inst) -> str:
-    vop2_op = inst.vop2_op
-    src0 = _sdwa_src0(inst.src0, inst.s0, inst.src0_sext, inst.src0_neg, inst.src0_abs)
-    clamp = " clamp" if inst.clmp else ""
-    omod = _OMOD_SDWA.get(inst.omod, "")
-    if vop2_op == 63:
-      try: name = CDNA_VOP1Op(inst.vop_op).name.lower()
-      except ValueError: name = f"vop1_op_{inst.vop_op}"
-      dst = f"v{inst.vdst}"
-      mods = [f"dst_sel:{_SEL[inst.dst_sel]}", f"dst_unused:{_UNUSED[inst.dst_u]}", f"src0_sel:{_SEL[inst.src0_sel]}"]
-      return f"{name}_sdwa {dst}, {src0}{clamp}{omod} " + " ".join(mods)
-    elif vop2_op == 62:
-      try: name = CDNA_VOPCOp(inst.vdst).name.lower()
-      except ValueError: name = f"vopc_op_{inst.vdst}"
-      src1 = _sdwa_vsrc1(inst.vop_op, inst.src1_sext, inst.src1_neg, inst.src1_abs)
-      sdst_enc = inst.dst_sel | (inst.dst_u << 3) | (inst.clmp << 5) | (inst.omod << 6)
-      if sdst_enc == 0: sdst = "vcc"
-      else:
-        sdst_val = sdst_enc - 128 if sdst_enc >= 128 else sdst_enc
-        sdst = _fmt_sdst(sdst_val, 2, cdna=True)
-      mods = [f"src0_sel:{_SEL[inst.src0_sel]}", f"src1_sel:{_SEL[inst.src1_sel]}"]
-      return f"{name}_sdwa {sdst}, {src0}, {src1} " + " ".join(mods)
-    else:
-      try: name = CDNA_VOP2Op(vop2_op).name.lower()
-      except ValueError: name = f"vop2_op_{vop2_op}"
-      name = _CDNA_DISASM_ALIASES.get(name, name)
-      dst = f"v{inst.vdst}"
-      src1 = _sdwa_vsrc1(inst.vop_op, inst.src1_sext, inst.src1_neg, inst.src1_abs)
-      mods = [f"dst_sel:{_SEL[inst.dst_sel]}", f"dst_unused:{_UNUSED[inst.dst_u]}", f"src0_sel:{_SEL[inst.src0_sel]}", f"src1_sel:{_SEL[inst.src1_sel]}"]
-      if name == 'v_cndmask_b32':
-        return f"{name}_sdwa {dst}, {src0}, {src1}, vcc{clamp}{omod} " + " ".join(mods)
-      if name in ('v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'):
-        return f"{name}_sdwa {dst}, vcc, {src0}, {src1}, vcc{clamp}{omod} " + " ".join(mods)
-      if '_co_' in name:
-        return f"{name}_sdwa {dst}, vcc, {src0}, {src1}{clamp}{omod} " + " ".join(mods)
-      return f"{name}_sdwa {dst}, {src0}, {src1}{clamp}{omod} " + " ".join(mods)
-
-  def _dpp_src(v, neg=0, abs_=0):
-    s = f"v{v}" if v < 256 else f"v{v - 256}"
-    if abs_: s = f"|{s}|"
-    return f"-{s}" if neg else s
-
-  def _disasm_dpp(inst) -> str:
-    vop2_op = inst.vop2_op
-    ctrl = inst.dpp_ctrl
-    dpp = f"quad_perm:[{ctrl&3},{(ctrl>>2)&3},{(ctrl>>4)&3},{(ctrl>>6)&3}]" if ctrl < 0x100 else f"row_shl:{ctrl&0xf}" if ctrl < 0x110 else f"row_shr:{ctrl&0xf}" if ctrl < 0x120 else f"row_ror:{ctrl&0xf}" if ctrl < 0x130 else _DPP.get(ctrl, f"dpp_ctrl:0x{ctrl:x}")
-    src0 = _dpp_src(inst.src0, inst.src0_neg, inst.src0_abs)
-    mods = [dpp, f"row_mask:0x{inst.row_mask:x}", f"bank_mask:0x{inst.bank_mask:x}"] + (["bound_ctrl:0"] if inst.bound_ctrl else [])
-    if vop2_op == 63:
-      try: name = CDNA_VOP1Op(inst.vop_op).name.lower()
-      except ValueError: name = f"vop1_op_{inst.vop_op}"
-      return f"{name}_dpp v{inst.vdst}, {src0} " + " ".join(mods)
-    else:
-      try: name = CDNA_VOP2Op(vop2_op).name.lower()
-      except ValueError: name = f"vop2_op_{vop2_op}"
-      name = _CDNA_DISASM_ALIASES.get(name, name)
-      src1 = _dpp_src(inst.vop_op, inst.src1_neg, inst.src1_abs)
-      if name == 'v_cndmask_b32':
-        return f"{name}_dpp v{inst.vdst}, {src0}, {src1}, vcc " + " ".join(mods)
-      if name in ('v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'):
-        return f"{name}_dpp v{inst.vdst}, vcc, {src0}, {src1}, vcc " + " ".join(mods)
-      if '_co_' in name:
-        return f"{name}_dpp v{inst.vdst}, vcc, {src0}, {src1} " + " ".join(mods)
-      return f"{name}_dpp v{inst.vdst}, {src0}, {src1} " + " ".join(mods)
-
-  DISASM_HANDLERS.update({CDNA_VOP1: _disasm_vop1, CDNA_VOP2: _disasm_vop2, CDNA_VOPC: _disasm_vopc,
-    CDNA_SOP1: _disasm_sop1, CDNA_SOP2: _disasm_sop2, CDNA_SOPC: _disasm_sopc, CDNA_SOPK: _disasm_sopk, CDNA_SOPP: _disasm_sopp,
-    CDNA_SMEM: _disasm_smem, CDNA_DS: _disasm_ds, CDNA_FLAT: _disasm_flat, CDNA_MUBUF: _disasm_buf, CDNA_MTBUF: _disasm_buf,
-    VOP3A: _disasm_vop3a, VOP3B: _disasm_vop3b, CDNA_VOP3P: _disasm_cdna_vop3p, SDWA: _disasm_sdwa, DPP: _disasm_dpp})
-except ImportError:
-  pass
@@ -1,48 +1,48 @@
 # library for RDNA3 assembly DSL
 # mypy: ignore-errors
 from __future__ import annotations
-import re, struct
+import struct, math, re
 from enum import IntEnum
-from functools import cache
+from functools import cache, cached_property
 from typing import overload, Annotated, TypeVar, Generic
 from extra.assembly.amd.autogen.rdna3.enum import (VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, VOPDOp, SOP1Op, SOP2Op,
  SOPCOp, SOPKOp, SOPPOp, SMEMOp, DSOp, FLATOp, MUBUFOp, MTBUFOp, MIMGOp, VINTERPOp)
-from extra.assembly.amd.autogen.cdna.enum import VOP1Op as CDNA_VOP1Op, VOP2Op as CDNA_VOP2Op
-from extra.assembly.amd.autogen.rdna4.enum import (VOP1Op as RDNA4_VOP1Op, VOP2Op as RDNA4_VOP2Op, VOP3Op as RDNA4_VOP3Op,
-  VOP3SDOp as RDNA4_VOP3SDOp, VOP3POp as RDNA4_VOP3POp, VOPCOp as RDNA4_VOPCOp, VOPDOp as RDNA4_VOPDOp,
-  SOP1Op as RDNA4_SOP1Op, SOP2Op as RDNA4_SOP2Op, SOPCOp as RDNA4_SOPCOp, SOPKOp as RDNA4_SOPKOp, SOPPOp as RDNA4_SOPPOp,
-  SMEMOp as RDNA4_SMEMOp, DSOp as RDNA4_DSOp, VBUFFEROp as RDNA4_VBUFFEROp, VINTERPOp as RDNA4_VINTERPOp)

-# Source operand encoding - constant across all AMD ISAs
-class SrcEnum(IntEnum):
-  VCC_LO=106; VCC_HI=107; NULL=124; M0=125; EXEC_LO=126; EXEC_HI=127; ZERO=128
-  DPP8=233; DPP8FI=234; SHARED_BASE=235; SHARED_LIMIT=236; PRIVATE_BASE=237; PRIVATE_LIMIT=238
-  POS_HALF=240; NEG_HALF=241; POS_ONE=242; NEG_ONE=243; POS_TWO=244; NEG_TWO=245
-  POS_FOUR=246; NEG_FOUR=247; INV_2PI=248; DPP16=250; VCCZ=251; EXECZ=252; SCC=253; LDS_DIRECT=254
-VCC_LO, VCC_HI, NULL, M0, EXEC_LO, EXEC_HI, ZERO = SrcEnum.VCC_LO, SrcEnum.VCC_HI, SrcEnum.NULL, SrcEnum.M0, SrcEnum.EXEC_LO, SrcEnum.EXEC_HI, SrcEnum.ZERO
-DPP8FI, SHARED_BASE, SHARED_LIMIT, PRIVATE_BASE, PRIVATE_LIMIT = SrcEnum.DPP8FI, SrcEnum.SHARED_BASE, SrcEnum.SHARED_LIMIT, SrcEnum.PRIVATE_BASE, SrcEnum.PRIVATE_LIMIT
-POS_HALF, NEG_HALF, POS_ONE, NEG_ONE, POS_TWO, NEG_TWO = SrcEnum.POS_HALF, SrcEnum.NEG_HALF, SrcEnum.POS_ONE, SrcEnum.NEG_ONE, SrcEnum.POS_TWO, SrcEnum.NEG_TWO
-POS_FOUR, NEG_FOUR, INV_2PI, VCCZ, EXECZ, SCC, LDS_DIRECT = SrcEnum.POS_FOUR, SrcEnum.NEG_FOUR, SrcEnum.INV_2PI, SrcEnum.VCCZ, SrcEnum.EXECZ, SrcEnum.SCC, SrcEnum.LDS_DIRECT
-OFF = NULL
-
-# Common masks
-MASK32, MASK64, MASK128 = 0xffffffff, 0xffffffffffffffff, (1 << 128) - 1
-
-# Float/int bit conversion (simple versions for literal encoding)
-def _i32(f: float) -> int: return struct.unpack("<I", struct.pack("<f", f))[0]
-def _i64(f: float) -> int: return struct.unpack("<Q", struct.pack("<d", f))[0]
+# Common masks and bit conversion functions
+MASK32, MASK64 = 0xffffffff, 0xffffffffffffffff
+_struct_f, _struct_I = struct.Struct("<f"), struct.Struct("<I")
+_struct_e, _struct_H = struct.Struct("<e"), struct.Struct("<H")
+_struct_d, _struct_Q = struct.Struct("<d"), struct.Struct("<Q")
+def _f32(i): return _struct_f.unpack(_struct_I.pack(i & MASK32))[0]
+def _i32(f):
+  if isinstance(f, int): f = float(f)
+  if math.isnan(f): return 0xffc00000 if math.copysign(1.0, f) < 0 else 0x7fc00000
+  if math.isinf(f): return 0x7f800000 if f > 0 else 0xff800000
+  try: return _struct_I.unpack(_struct_f.pack(f))[0]
+  except (OverflowError, struct.error): return 0x7f800000 if f > 0 else 0xff800000
+def _sext(v, b): return v - (1 << b) if v & (1 << (b - 1)) else v
+def _f16(i): return _struct_e.unpack(_struct_H.pack(i & 0xffff))[0]
+def _i16(f):
+  if math.isnan(f): return 0x7e00
+  if math.isinf(f): return 0x7c00 if f > 0 else 0xfc00
+  try: return _struct_H.unpack(_struct_e.pack(f))[0]
+  except (OverflowError, struct.error): return 0x7c00 if f > 0 else 0xfc00
+def _f64(i): return _struct_d.unpack(_struct_Q.pack(i & MASK64))[0]
+def _i64(f):
+  if math.isnan(f): return 0x7ff8000000000000
+  if math.isinf(f): return 0x7ff0000000000000 if f > 0 else 0xfff0000000000000
+  try: return _struct_Q.unpack(_struct_d.pack(f))[0]
+  except (OverflowError, struct.error): return 0x7ff0000000000000 if f > 0 else 0xfff0000000000000

 # Instruction spec - register counts and dtypes derived from instruction names
 _REGS = {'B32': 1, 'B64': 2, 'B96': 3, 'B128': 4, 'B256': 8, 'B512': 16,
         'F32': 1, 'I32': 1, 'U32': 1, 'F64': 2, 'I64': 2, 'U64': 2,
-         'F16': 1, 'I16': 1, 'U16': 1, 'B16': 1, 'I8': 1, 'U8': 1, 'B8': 1,
-         'DWORD': 1, 'DWORDX2': 2, 'DWORDX3': 3, 'DWORDX4': 4, 'DWORDX8': 8, 'DWORDX16': 16,
-         'BYTE': 1, 'SHORT': 1, 'UBYTE': 1, 'SBYTE': 1, 'USHORT': 1, 'SSHORT': 1}
+         'F16': 1, 'I16': 1, 'U16': 1, 'B16': 1, 'I8': 1, 'U8': 1, 'B8': 1}
 _CVT_RE = re.compile(r'CVT_([FIUB]\d+)_([FIUB]\d+)$')
 _MAD_MUL_RE = re.compile(r'(?:MAD|MUL)_([IU]\d+)_([IU]\d+)$')
 _PACK_RE = re.compile(r'PACK_([FIUB]\d+)_([FIUB]\d+)$')
 _DST_SRC_RE = re.compile(r'_([FIUB]\d+)_([FIUB]\d+)$')
-_SINGLE_RE = re.compile(r'_([FIUB](?:32|64|16|8|96|128|256|512)|DWORD(?:X(?:2|3|4|8|16))?|[US]?BYTE|[US]?SHORT)$')
+_SINGLE_RE = re.compile(r'_([FIUB](?:32|64|16|8|96|128|256|512))$')
@cache
 def _suffix(name: str) -> tuple[str | None, str | None]:
  name = name.upper()
@@ -64,7 +64,6 @@ _SPECIAL_REGS = {
  'V_CMP_CLASS_F16': (1, 1, 1, 1), 'V_CMPX_CLASS_F16': (1, 1, 1, 1),
  'V_MAD_U64_U32': (2, 1, 1, 2), 'V_MAD_I64_I32': (2, 1, 1, 2),
  'V_QSAD_PK_U16_U8': (2, 2, 1, 2), 'V_MQSAD_PK_U16_U8': (2, 2, 1, 2), 'V_MQSAD_U32_U8': (4, 2, 1, 4),
-  'V_CVT_PK_F32_BF8': (2, 1, 1, 1), 'V_CVT_PK_F32_FP8': (2, 1, 1, 1),
 }
 _SPECIAL_DTYPE = {
  'V_LSHLREV_B64': ('B64', 'U32', 'B64', None), 'V_LSHRREV_B64': ('B64', 'U32', 'B64', None), 'V_ASHRREV_I64': ('I64', 'U32', 'I64', None),
@@ -109,8 +108,8 @@ def spec_is_16bit(name: str) -> bool:
 def spec_is_64bit(name: str) -> bool: return bool(_F64_RE.search(name.upper()))
 _3SRC = {'FMA', 'MAD', 'MIN3', 'MAX3', 'MED3', 'DIV_FIX', 'DIV_FMAS', 'DIV_SCALE', 'SAD', 'LERP', 'ALIGN', 'CUBE', 'BFE', 'BFI',
         'PERM_B32', 'PERMLANE', 'CNDMASK', 'XOR3', 'OR3', 'ADD3', 'LSHL_OR', 'AND_OR', 'LSHL_ADD', 'ADD_LSHL', 'XAD', 'MAXMIN',
-         'MINMAX', 'MINIMUMMAXIMUM', 'MAXIMUMMINIMUM', 'MINIMUM3', 'MAXIMUM3', 'DOT2', 'DOT4', 'DOT8', 'WMMA', 'CVT_PK_U8', 'MULLIT', 'CO_CI'}
-_2SRC = {'FMAC', 'PERMLANE16_VAR', 'PERMLANEX16_VAR'}  # FMAC uses dst as implicit accumulator, _VAR permlane only 2 sources
+         'MINMAX', 'DOT2', 'DOT4', 'DOT8', 'WMMA', 'CVT_PK_U8', 'MULLIT', 'CO_CI'}
+_2SRC = {'FMAC'}  # FMAC uses dst as implicit accumulator, so only 2 explicit sources
 def spec_num_srcs(name: str) -> int:
  name = name.upper()
  if any(k in name for k in _2SRC): return 2
@@ -234,36 +233,26 @@ def unwrap(val) -> int:
 FLOAT_ENC = {0.5: 240, -0.5: 241, 1.0: 242, -1.0: 243, 2.0: 244, -2.0: 245, 4.0: 246, -4.0: 247}
 FLOAT_DEC = {v: str(k) for k, v in FLOAT_ENC.items()}
 SPECIAL_GPRS = {106: "vcc_lo", 107: "vcc_hi", 124: "null", 125: "m0", 126: "exec_lo", 127: "exec_hi", 253: "scc"}
-SPECIAL_GPRS_CDNA = {102: "flat_scratch_lo", 103: "flat_scratch_hi", 104: "xnack_mask_lo", 105: "xnack_mask_hi",
-                    106: "vcc_lo", 107: "vcc_hi", 124: "m0", 126: "exec_lo", 127: "exec_hi",
-                    251: "src_vccz", 252: "src_execz", 253: "src_scc", 254: "src_lds_direct"}
 SPECIAL_PAIRS = {106: "vcc", 126: "exec"}
-SPECIAL_PAIRS_CDNA = {102: "flat_scratch", 104: "xnack_mask", 106: "vcc", 126: "exec"}
 SRC_FIELDS = {'src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'soffset', 'srcx0', 'srcy0'}
 RAW_FIELDS = {'vdata', 'vdst', 'vaddr', 'addr', 'data', 'data0', 'data1', 'sdst', 'sdata', 'vsrc1'}

 def _encode_reg(val: Reg) -> int: return (108 if isinstance(val, TTMP) else 0) + val.idx

-def _is_encoded_src(v: int) -> bool: return 106 <= v <= 127 or 128 <= v <= 208 or 240 <= v <= 255  # Special regs (106-127) or inline const
+def _is_inline_const(v: int) -> bool: return 0 <= v <= 127 or 128 <= v <= 208 or 240 <= v <= 255

 def encode_src(val) -> int:
  if isinstance(val, VGPR): return 256 + _encode_reg(val)
  if isinstance(val, Reg): return _encode_reg(val)
-  if isinstance(val, SrcMod) and not isinstance(val, Reg):
-    v = val.val
-    if _is_encoded_src(v): return v  # Already encoded (special reg 106-127 or inline const 128-208 or float 240-255)
-    if isinstance(v, int) and 0 <= v <= 64: return 128 + v  # Encode as inline constant
-    if isinstance(v, int) and -16 <= v <= -1: return 192 - v
-    return 255  # Literal
+  if isinstance(val, SrcMod) and not isinstance(val, Reg): return val.val if _is_inline_const(val.val) else 255
  if hasattr(val, 'value'): return val.value  # IntEnum
  if isinstance(val, float): return 128 if val == 0.0 else FLOAT_ENC.get(val, 255)
  if isinstance(val, int): return 128 + val if 0 <= val <= 64 else 192 - val if -16 <= val <= -1 else 255
  return 255

-def decode_src(val: int, cdna: bool = False) -> str:
-  special = SPECIAL_GPRS_CDNA if cdna else SPECIAL_GPRS
-  if val in special: return special[val]
+def decode_src(val: int) -> str:
  if val <= 105: return f"s{val}"
+  if val in SPECIAL_GPRS: return SPECIAL_GPRS[val]
  if val in FLOAT_DEC: return FLOAT_DEC[val]
  if 108 <= val <= 123: return f"ttmp{val - 108}"
  if 128 <= val <= 192: return str(val - 128)
@@ -282,17 +271,7 @@ class Inst:

  def __init_subclass__(cls, **kwargs):
    super().__init_subclass__(**kwargs)
-    # Merge fields from parent classes
-    cls._fields = {}
-    for base in reversed(cls.__mro__):
-      if base is Inst or not hasattr(base, '_fields'): continue
-      cls._fields.update(base._fields)
-    # Add this class's own fields (overrides parents)
-    cls._fields.update({n: v[0] if isinstance(v, tuple) else v for n, v in cls.__dict__.items() if isinstance(v, BitField) or (isinstance(v, tuple) and len(v) == 2 and isinstance(v[0], BitField))})
-    # Compute size from max bit (exclude optional MIMG NSA fields: addr1/addr2 at bits 64+)
-    optional_nsa = {'addr1', 'addr2'}
-    max_bit = max((bf.hi for n, bf in cls._fields.items() if n not in optional_nsa), default=0) if cls._fields else 0
-    cls._sz = 12 if max_bit > 63 else 8 if max_bit > 31 else 4
+    cls._fields = {n: v[0] if isinstance(v, tuple) else v for n, v in cls.__dict__.items() if isinstance(v, BitField) or (isinstance(v, tuple) and len(v) == 2 and isinstance(v[0], BitField))}
    if 'encoding' in cls._fields and isinstance(cls.__dict__.get('encoding'), tuple): cls._encoding = cls.__dict__['encoding']

  def _or_field(self, name: str, bit: int):
@@ -337,49 +316,25 @@ class Inst:
  def _validate(self, orig_args: dict):
    """Format-specific validation. Override in subclass or check by class name."""
    cls_name, op = self.__class__.__name__, orig_args.get('op')
-    op_val = op.value if hasattr(op, 'value') else op
-    op_name = op.name if hasattr(op, 'name') else None
-    # SMEM: register count must match opcode (derive from name: b32=1, b64=2, b96=3, b128=4, b256=8, b512=16, i8/u8/i16/u16=1)
-    if cls_name == 'SMEM' and op_name:
-      expected = {'B32': 1, 'B64': 2, 'B96': 3, 'B128': 4, 'B256': 8, 'B512': 16, 'I8': 1, 'U8': 1, 'I16': 1, 'U16': 1}.get(op_name.split('_')[-1])
+    if hasattr(op, 'value'): op = op.value
+    # SMEM: register count must match opcode
+    if cls_name == 'SMEM' and op is not None:
+      expected = {0:1, 1:2, 2:4, 3:8, 4:16, 8:1, 9:2, 10:4, 11:8, 12:16}.get(op)
      sdata = orig_args.get('sdata')
      if expected and isinstance(sdata, Reg) and sdata.count != expected:
-        raise ValueError(f"SMEM op {op_name} expects {expected} registers, got {sdata.count}")
-    # SOP1: derive expected register sizes from op name (e.g., S_MOV_B64 -> dst=2, src=2; S_CTZ_I32_B64 -> dst=1, src=2)
+        raise ValueError(f"SMEM op {op} expects {expected} registers, got {sdata.count}")
+    # SOP1: b32=1 reg, b64=2 regs
    if cls_name == 'SOP1' and hasattr(orig_args.get('op'), 'name'):
-      op_name = orig_args['op'].name
-      # Special cases: BITSET takes bit index (1 reg) regardless of dst size
-      if 'BITSET' in op_name:
-        dst_size = 2 if op_name.endswith('_B64') else 1
-        src_size = 1  # bit index is always 1 reg
-      else:
-        # Extract sizes from name: last suffix is src type, second-to-last (if exists) is dst type
-        sizes = {'B32': 1, 'I32': 1, 'U32': 1, 'B64': 2, 'I64': 2, 'U64': 2, 'B128': 4, 'B256': 8, 'B512': 16}
-        parts = op_name.split('_')
-        src_size = sizes.get(parts[-1], 1) if parts[-1] in sizes else 1
-        dst_size = sizes.get(parts[-2], src_size) if len(parts) >= 2 and parts[-2] in sizes else src_size
-      for fld, expected in [('sdst', dst_size), ('ssrc0', src_size)]:
+      expected = 2 if orig_args['op'].name.endswith('_B64') else 1
+      for fld in ('sdst', 'ssrc0'):
        if isinstance(orig_args.get(fld), Reg) and orig_args[fld].count != expected:
-          raise ValueError(f"SOP1 {op_name} expects {expected} register(s) for {fld}, got {orig_args[fld].count}")
+          raise ValueError(f"SOP1 {orig_args['op'].name} expects {expected} register(s) for {fld}, got {orig_args[fld].count}")

  def __init__(self, *args, literal: int | None = None, **kwargs):
    self._values, self._literal = dict(self._defaults), None
    field_names = [n for n in self._fields if n != 'encoding']
-    # Map Python-friendly names to actual field names (abs_ -> abs for Python reserved word)
-    if 'abs_' in kwargs: kwargs['abs'] = kwargs.pop('abs_')
-    # If more args than fields, treat extra arg as literal (for FMAAK/FMAMK style instructions)
-    # FMAMK has K in middle (vdst, src0, K, vsrc1), FMAAK has K at end (vdst, src0, vsrc1, K)
-    args = list(args)
-    if len(args) > len(field_names) and literal is None:
-      for i, a in enumerate(args):
-        if isinstance(a, int) and not isinstance(a, SrcEnum) and i < len(field_names) and field_names[i] in ('vsrc1',):
-          literal = args.pop(i)
-          break
-      else:
-        literal = args.pop()  # fallback: last arg is literal
    orig_args = dict(zip(field_names, args)) | kwargs
    self._values.update(orig_args)
-    self._precompute()
    self._validate(orig_args)
    # Pre-shift literal for 64-bit sources (literal param is always raw 32-bit value from user)
    if literal is not None:
@@ -400,9 +355,7 @@ class Inst:
    if cls_name == 'VOP3P':
      op = orig_args.get('op')
      if hasattr(op, 'value'): op = op.value
-      # fma_mix ops (32-34) default to opsel_hi=0, WMMA ops (64-69) default to opsel_hi=7 to match LLVM
      if op in (32, 33, 34) and 'opsel_hi' not in orig_args: self._values['opsel_hi'] = self._values['opsel_hi2'] = 0
-      if op in range(64, 70) and 'opsel_hi' not in orig_args: self._values['opsel_hi'], self._values['opsel_hi2'] = 3, 1

    # Encode all fields
    for name, val in list(self._values.items()):
@@ -420,14 +373,13 @@ class Inst:
      if name in SRC_FIELDS: self._encode_src(name, val)
      elif name in RAW_FIELDS: self._encode_raw(name, val)
      elif name == 'sbase': self._values[name] = (val.idx if isinstance(val, Reg) else val.val if isinstance(val, SrcMod) else val * 2) // 2
-      elif name in {'srsrc', 'ssamp'} and isinstance(val, Reg): self._values[name] = _encode_reg(val) // 4
+      elif name in {'srsrc', 'ssamp'} and isinstance(val, Reg): self._values[name] = val.idx // 4
      elif marker is _VDSTYEnc and isinstance(val, VGPR): self._values[name] = val.idx >> 1
-    self._precompute_fields()

  def _encode_field(self, name: str, val) -> int:
    if isinstance(val, RawImm): return val.val
    if isinstance(val, SrcMod) and not isinstance(val, Reg): return val.val  # Special regs like VCC_LO
-    if name in {'srsrc', 'ssamp'}: return _encode_reg(val) // 4 if isinstance(val, Reg) else val
+    if name in {'srsrc', 'ssamp'}: return val.idx // 4 if isinstance(val, Reg) else val
    if name == 'sbase': return val.idx // 2 if isinstance(val, Reg) else val.val // 2 if isinstance(val, SrcMod) else val
    if name in RAW_FIELDS: return _encode_reg(val) if isinstance(val, Reg) else val
    if isinstance(val, Reg) or name in SRC_FIELDS: return encode_src(val)
@@ -477,7 +429,7 @@ class Inst:
    return result + (lit32 & MASK32).to_bytes(4, 'little')

  @classmethod
-  def _size(cls) -> int: return cls._sz
+  def _size(cls) -> int: return 4 if issubclass(cls, Inst32) else 8
  def size(self) -> int:
    # Literal is always 4 bytes in the binary (for 64-bit ops, it's in high 32 bits)
    return self._size() + (4 if self._literal is not None else 0)
@@ -487,22 +439,14 @@ class Inst:
    inst = object.__new__(cls)
    inst._values = {n: RawImm(v) if n in SRC_FIELDS else v for n, bf in cls._fields.items() if n != 'encoding' for v in [(word >> bf.lo) & bf.mask()]}
    inst._literal = None
-    inst._precompute()
-    inst._precompute_fields()
    return inst

  @classmethod
  def from_bytes(cls, data: bytes):
-    import typing
    inst = cls.from_int(int.from_bytes(data[:cls._size()], 'little'))
    op_val = inst._values.get('op', 0)
-    # Check for instructions that always have a literal constant (FMAMK/FMAAK/MADMK/MADAK, SETREG_IMM32)
-    op_name = ''
-    if cls.__name__ in ('VOP2', 'SOP2', 'SOPK') and 'op' in (hints := typing.get_type_hints(cls, include_extras=True)):
-      if typing.get_origin(hints['op']) is typing.Annotated:
-        try: op_name = typing.get_args(hints['op'])[1](op_val).name
-        except (ValueError, TypeError): pass
-    has_literal = any(x in op_name for x in ('FMAMK', 'FMAAK', 'MADMK', 'MADAK', 'SETREG_IMM32'))
+    has_literal = cls.__name__ == 'VOP2' and op_val in (44, 45, 55, 56)
+    has_literal = has_literal or (cls.__name__ == 'SOP2' and op_val in (69, 70))
    # VOPD fmaak/fmamk always have a literal (opx/opy value 1 or 2)
    opx, opy = inst._values.get('opx', 0), inst._values.get('opy', 0)
    has_literal = has_literal or (cls.__name__ == 'VOPD' and (opx in (1, 2) or opy in (1, 2)))
@@ -516,7 +460,7 @@ class Inst:
        lit32 = int.from_bytes(data[cls._size():cls._size()+4], 'little')
        # Find which source has literal (255) and check its register count
        lit_src_is_64 = False
-        for n, idx in [('src0', 0), ('src1', 1), ('src2', 2), ('ssrc0', 0), ('ssrc1', 1)]:
+        for n, idx in [('src0', 0), ('src1', 1), ('src2', 2)]:
          if n in inst._values and isinstance(inst._values[n], RawImm) and inst._values[n].val == 255:
            lit_src_is_64 = inst.src_regs(idx) == 2
            break
@@ -536,12 +480,7 @@ class Inst:
    return unwrap(self._values.get(name, 0))

  def lit(self, v: int, neg: bool = False) -> str:
-    if v == 255 and self._literal is not None:
-      # For 64-bit sources, literal is stored shifted - extract the 32-bit value
-      lit32 = (self._literal >> 32) if self._literal > 0xffffffff else self._literal
-      s = f"0x{lit32:x}"
-    else:
-      s = decode_src(v, 'cdna' in self.__class__.__module__)
+    s = f"0x{self._literal:x}" if v == 255 and self._literal else decode_src(v)
    return f"-{s}" if neg else s

  def __eq__(self, other):
@@ -560,45 +499,25 @@ class Inst:
               'VOPD': VOPDOp, 'VINTERP': VINTERPOp}
  _VOP3SD_OPS = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770}

-  def _precompute(self):
-    """Precompute op, op_name, _spec_regs, _spec_dtype for fast access."""
+  @property
+  def op(self):
+    """Return the op as an enum (e.g., VOP1Op.V_MOV_B32). VOP3 returns VOPCOp/VOP3SDOp for those op ranges."""
    val = self._values.get('op')
-    if val is None: self.op = None
-    elif hasattr(val, 'name'): self.op = val
-    else:
-      cls_name = self.__class__.__name__
-      is_cdna = cls_name in ('VOP3A', 'VOP3B')
-      # Try marker enum first (VOP3AOp, VOP3BOp, etc.)
-      marker = self._fields['op'].marker if 'op' in self._fields else None
-      if marker and issubclass(marker, IntEnum):
-        try: self.op = marker(val)
-        except ValueError: self.op = val
-      elif cls_name in self._enum_map:
-        try: self.op = self._enum_map[cls_name](val)
-        except ValueError: self.op = val
-      else: self.op = val
-      # Fallback for promoted instructions when marker lookup failed
-      if not hasattr(self.op, 'name') and cls_name in ('VOP3', 'VOP3A', 'VOP3B') and isinstance(val, int):
-        if val < 256:
-          try: self.op = VOPCOp(val)
-          except ValueError: pass
-        elif is_cdna and 256 <= val < 512:
-          try: self.op = (CDNA_VOP1Op(val - 320) if val >= 320 else CDNA_VOP2Op(val - 256))
-          except ValueError: pass
-        elif val in self._VOP3SD_OPS and not is_cdna:
-          try: self.op = VOP3SDOp(val)
-          except ValueError: pass
-        elif 256 <= val < 512 and not is_cdna:
-          try: self.op = VOP1Op(val - 384) if val >= 384 else VOP2Op(val - 256)
-          except ValueError: pass
-    self.op_name = self.op.name if hasattr(self.op, 'name') else ''
-    self._spec_regs = spec_regs(self.op_name)
-    self._spec_dtype = spec_dtype(self.op_name)
+    if val is None: return None
+    if hasattr(val, 'name'): return val  # already an enum
+    cls_name = self.__class__.__name__
+    assert cls_name in self._enum_map, f"no enum map for {cls_name}"
+    return self._enum_map[cls_name](val)

-  def _precompute_fields(self):
-    """Unwrap all field values as direct attributes for fast access."""
-    for name, val in self._values.items():
-      if name != 'op': setattr(self, name, unwrap(val))
+  @cached_property
+  def op_name(self) -> str:
+    op = self.op
+    return op.name if hasattr(op, 'name') else ''
+
+  @cached_property
+  def _spec_regs(self) -> tuple[int, int, int, int]: return spec_regs(self.op_name)
+  @cached_property
+  def _spec_dtype(self) -> tuple[str | None, str | None, str | None, str | None]: return spec_dtype(self.op_name)
  def dst_regs(self) -> int: return self._spec_regs[0]
  def src_regs(self, n: int) -> int: return self._spec_regs[n + 1]
  def num_srcs(self) -> int: return spec_num_srcs(self.op_name)
@@ -610,4 +529,5 @@ class Inst:
  def is_64bit(self) -> bool: return spec_is_64bit(self.op_name)
  def is_dst_16(self) -> bool: return self._spec_regs[0] == 1 and is_dtype_16(self._spec_dtype[0])

-
+class Inst32(Inst): pass
+class Inst64(Inst): pass
@@ -1,17 +1,15 @@
 # RDNA3 emulator - executes compiled pseudocode from AMD ISA PDF
 # mypy: ignore-errors
 from __future__ import annotations
-import ctypes, functools
-from tinygrad.runtime.autogen import hsa
-from extra.assembly.amd.dsl import Inst, unwrap, FLOAT_ENC, MASK32, MASK64
-from extra.assembly.amd.pcode import _f32, _i32, _sext, _f16, _i16, _f64, _i64
-from extra.assembly.amd.decode import decode_inst
-from extra.assembly.amd.pcode import compile_pseudocode
-from extra.assembly.amd.autogen.rdna3.str_pcode import PSEUDOCODE_STRINGS
-from extra.assembly.amd.dsl import SrcEnum
+import ctypes
+from extra.assembly.amd.dsl import Inst, unwrap, FLOAT_ENC, MASK32, MASK64, _f32, _i32, _sext, _f16, _i16, _f64, _i64
+from extra.assembly.amd.pcode import Reg
+from extra.assembly.amd.asm import detect_format
+from extra.assembly.amd.autogen.rdna3.gen_pcode import get_compiled_functions
 from extra.assembly.amd.autogen.rdna3.ins import (SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, DS, FLAT, VOPD,
-  SOP1Op, SOP2Op, SOPCOp, SOPKOp, SOPPOp, SMEMOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, DSOp, FLATOp, GLOBALOp, SCRATCHOp, VOPDOp)
+  SrcEnum, SOPPOp, SMEMOp, VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, GLOBALOp, FLATOp, DSOp, VOPDOp)

+Program = dict[int, Inst]
 WAVE_SIZE, SGPR_COUNT, VGPR_COUNT = 32, 128, 256
 VCC_LO, VCC_HI, NULL, EXEC_LO, EXEC_HI, SCC = SrcEnum.VCC_LO, SrcEnum.VCC_HI, SrcEnum.NULL, SrcEnum.EXEC_LO, SrcEnum.EXEC_HI, SrcEnum.SCC

@@ -31,102 +29,29 @@ def _dst16(cur: int, val: int, is_hi: bool) -> int: return (cur & 0x0000ffff) |
 def _vgpr_hi(src: int) -> bool: return src >= 256 and ((src - 256) & 0x80) != 0
 def _vgpr_masked(src: int) -> int: return ((src - 256) & 0x7f) + 256 if src >= 256 else src

-# VOP3 source modifier: apply abs/neg to value
-def _mod_src(val: int, idx: int, neg: int, abs_: int, is64: bool = False) -> int:
-  to_f, to_i = (_f64, _i64) if is64 else (_f32, _i32)
-  if (abs_ >> idx) & 1: val = to_i(abs(to_f(val)))
-  if (neg >> idx) & 1: val = to_i(-to_f(val))
-  return val
-
-# Read source operand with VOP3 modifiers
-def _read_src(st, inst, src, idx: int, lane: int, neg: int, abs_: int, opsel: int) -> int:
-  if src is None: return 0
-  literal, regs, is_src_16 = inst._literal, inst.src_regs(idx), inst.is_src_16(idx)
-  if regs == 2: return _mod_src(st.rsrc64(src, lane, literal), idx, neg, abs_, is64=True)
-  if isinstance(inst, VOP3P):
-    opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
-    if 'FMA_MIX' in inst.op_name:
-      raw = st.rsrc(src, lane, literal)
-      sign_bit = (15 if not (opsel & (1 << idx)) else 31) if (opsel_hi >> idx) & 1 else 31
-      if inst.neg_hi & (1 << idx): raw &= ~(1 << sign_bit)
-      if neg & (1 << idx): raw ^= (1 << sign_bit)
-      return raw
-    raw = st.rsrc_f16(src, lane, literal)
-    hi = _src16(raw, opsel_hi & (1 << idx)) ^ (0x8000 if inst.neg_hi & (1 << idx) else 0)
-    lo = _src16(raw, opsel & (1 << idx)) ^ (0x8000 if neg & (1 << idx) else 0)
-    return (hi << 16) | lo
-  if is_src_16 and isinstance(inst, VOP3):
-    raw = st.rsrc_f16(src, lane, literal) if 128 <= src < 255 else st.rsrc(src, lane, literal)
-    val = _src16(raw, bool(opsel & (1 << idx)))
-    if abs_ & (1 << idx): val &= 0x7fff
-    if neg & (1 << idx): val ^= 0x8000
-    return val
-  if is_src_16 and isinstance(inst, (VOP1, VOP2, VOPC)):
-    if src >= 256: return _src16(_mod_src(st.rsrc(_vgpr_masked(src), lane, literal), idx, neg, abs_), _vgpr_hi(src))
-    return _mod_src(st.rsrc_f16(src, lane, literal), idx, neg, abs_) & 0xffff
-  return _mod_src(st.rsrc(src, lane, literal), idx, neg, abs_)
-
-# Helper: get number of dwords from memory op name
-def _op_ndwords(name: str) -> int:
-  if '_B128' in name: return 4
-  if '_B96' in name: return 3
-  if any(s in name for s in ('_B64', '_U64', '_I64', '_F64')): return 2
-  return 1
-
-# Helper: build multi-dword int from consecutive VGPRs
-def _vgpr_read(V: list, base: int, ndwords: int) -> int: return sum(V[base + i] << (32 * i) for i in range(ndwords))
-
-# Helper: write multi-dword value to consecutive VGPRs
-def _vgpr_write(V: list, base: int, val: int, ndwords: int):
-  for i in range(ndwords): V[base + i] = (val >> (32 * i)) & MASK32
-
 # Memory access
 _valid_mem_ranges: list[tuple[int, int]] = []
 def set_valid_mem_ranges(ranges: set[tuple[int, int]]) -> None: _valid_mem_ranges.clear(); _valid_mem_ranges.extend(ranges)
 def _mem_valid(addr: int, size: int) -> bool:
  return not _valid_mem_ranges or any(s <= addr and addr + size <= s + z for s, z in _valid_mem_ranges)
-def _ctypes_at(addr: int, size: int): return (ctypes.c_uint8 if size == 1 else ctypes.c_uint16 if size == 2 else ctypes.c_uint64 if size == 8 else ctypes.c_uint32).from_address(addr)
+def _ctypes_at(addr: int, size: int): return (ctypes.c_uint8 if size == 1 else ctypes.c_uint16 if size == 2 else ctypes.c_uint32).from_address(addr)
 def mem_read(addr: int, size: int) -> int: return _ctypes_at(addr, size).value if _mem_valid(addr, size) else 0
 def mem_write(addr: int, size: int, val: int) -> None:
  if _mem_valid(addr, size): _ctypes_at(addr, size).value = val

-def _make_mem_accessor(read_fn, write_fn):
-  """Create a memory accessor class with the given read/write functions."""
-  class _MemAccessor:
-    __slots__ = ('_addr',)
-    def __init__(self, addr: int): self._addr = int(addr)
-    u8 = property(lambda s: read_fn(s._addr, 1), lambda s, v: write_fn(s._addr, 1, int(v)))
-    u16 = property(lambda s: read_fn(s._addr, 2), lambda s, v: write_fn(s._addr, 2, int(v)))
-    u32 = property(lambda s: read_fn(s._addr, 4), lambda s, v: write_fn(s._addr, 4, int(v)))
-    u64 = property(lambda s: read_fn(s._addr, 8), lambda s, v: write_fn(s._addr, 8, int(v)))
-    i8 = property(lambda s: _sext(read_fn(s._addr, 1), 8), lambda s, v: write_fn(s._addr, 1, int(v)))
-    i16 = property(lambda s: _sext(read_fn(s._addr, 2), 16), lambda s, v: write_fn(s._addr, 2, int(v)))
-    i32 = property(lambda s: _sext(read_fn(s._addr, 4), 32), lambda s, v: write_fn(s._addr, 4, int(v)))
-    i64 = property(lambda s: _sext(read_fn(s._addr, 8), 64), lambda s, v: write_fn(s._addr, 8, int(v)))
-    b8, b16, b32, b64 = u8, u16, u32, u64
-  return _MemAccessor
-
-_GlobalMemAccessor = _make_mem_accessor(mem_read, mem_write)
-
-class _GlobalMem:
-  """Global memory wrapper that supports MEM[addr].u32 style access."""
-  def __getitem__(self, addr) -> _GlobalMemAccessor: return _GlobalMemAccessor(addr)
-GlobalMem = _GlobalMem()
-
-class LDSMem:
-  """LDS memory wrapper that supports MEM[addr].u32 style access."""
-  __slots__ = ('_lds',)
-  def __init__(self, lds: bytearray): self._lds = lds
-  def _read(self, addr: int, size: int) -> int:
-    addr = addr & 0xffff
-    return int.from_bytes(self._lds[addr:addr+size], 'little') if addr + size <= len(self._lds) else 0
-  def _write(self, addr: int, size: int, val: int):
-    addr = addr & 0xffff
-    if addr + size <= len(self._lds): self._lds[addr:addr+size] = (int(val) & ((1 << (size*8)) - 1)).to_bytes(size, 'little')
-  def __getitem__(self, addr): return _make_mem_accessor(self._read, self._write)(addr)
-
-# SMEM dst register count (for writing result back to SGPRs)
-SMEM_DST_COUNT = {SMEMOp.S_LOAD_B32: 1, SMEMOp.S_LOAD_B64: 2, SMEMOp.S_LOAD_B128: 4, SMEMOp.S_LOAD_B256: 8, SMEMOp.S_LOAD_B512: 16}
+# Memory op tables (not pseudocode - these are format descriptions)
+def _mem_ops(ops, suffix_map):
+  return {getattr(e, f"{p}_{s}"): v for e in ops for s, v in suffix_map.items() for p in [e.__name__.replace("Op", "")]}
+_LOAD_MAP = {'LOAD_B32': (1,4,0), 'LOAD_B64': (2,4,0), 'LOAD_B96': (3,4,0), 'LOAD_B128': (4,4,0), 'LOAD_U8': (1,1,0), 'LOAD_I8': (1,1,1), 'LOAD_U16': (1,2,0), 'LOAD_I16': (1,2,1)}
+_STORE_MAP = {'STORE_B32': (1,4), 'STORE_B64': (2,4), 'STORE_B96': (3,4), 'STORE_B128': (4,4), 'STORE_B8': (1,1), 'STORE_B16': (1,2)}
+FLAT_LOAD, FLAT_STORE = _mem_ops([GLOBALOp, FLATOp], _LOAD_MAP), _mem_ops([GLOBALOp, FLATOp], _STORE_MAP)
+# D16 ops: load/store 16-bit to lower or upper half of VGPR. Format: (size, sign, hi) where hi=1 means upper 16 bits
+_D16_LOAD_MAP = {'LOAD_D16_U8': (1,0,0), 'LOAD_D16_I8': (1,1,0), 'LOAD_D16_B16': (2,0,0),
+                 'LOAD_D16_HI_U8': (1,0,1), 'LOAD_D16_HI_I8': (1,1,1), 'LOAD_D16_HI_B16': (2,0,1)}
+_D16_STORE_MAP = {'STORE_D16_HI_B8': (1,1), 'STORE_D16_HI_B16': (2,1)}  # (size, hi)
+FLAT_D16_LOAD = _mem_ops([GLOBALOp, FLATOp], _D16_LOAD_MAP)
+FLAT_D16_STORE = _mem_ops([GLOBALOp, FLATOp], _D16_STORE_MAP)
+SMEM_LOAD = {SMEMOp.S_LOAD_B32: 1, SMEMOp.S_LOAD_B64: 2, SMEMOp.S_LOAD_B128: 4, SMEMOp.S_LOAD_B256: 8, SMEMOp.S_LOAD_B512: 16}

 # VOPD op -> VOP3 op mapping (VOPD is dual-issue of VOP1/VOP2 ops, use VOP3 enums for pseudocode lookup)
 _VOPD_TO_VOP = {
@@ -138,12 +63,19 @@ _VOPD_TO_VOP = {
  VOPDOp.V_DUAL_ADD_NC_U32: VOP3Op.V_ADD_NC_U32, VOPDOp.V_DUAL_LSHLREV_B32: VOP3Op.V_LSHLREV_B32, VOPDOp.V_DUAL_AND_B32: VOP3Op.V_AND_B32,
 }

+# Compiled pseudocode functions (lazy loaded)
+_COMPILED: dict | None = None
+
+def _get_compiled() -> dict:
+  global _COMPILED
+  if _COMPILED is None: _COMPILED = get_compiled_functions()
+  return _COMPILED

 class WaveState:
-  __slots__ = ('sgpr', 'vgpr', 'scc', 'pc', '_pend_sgpr', 'lds', 'n_lanes')
-  def __init__(self, lds: LDSMem | None = None, n_lanes: int = WAVE_SIZE):
+  __slots__ = ('sgpr', 'vgpr', 'scc', 'pc', 'literal', '_pend_sgpr')
+  def __init__(self):
    self.sgpr, self.vgpr = [0] * SGPR_COUNT, [[0] * VGPR_COUNT for _ in range(WAVE_SIZE)]
-    self.sgpr[EXEC_LO], self.scc, self.pc, self._pend_sgpr, self.lds, self.n_lanes = 0xffffffff, 0, 0, {}, lds, n_lanes
+    self.sgpr[EXEC_LO], self.scc, self.pc, self.literal, self._pend_sgpr = 0xffffffff, 0, 0, 0, {}

  @property
  def vcc(self) -> int: return self.sgpr[VCC_LO] | (self.sgpr[VCC_HI] << 32)
@@ -160,18 +92,18 @@ class WaveState:
  def rsgpr64(self, i: int) -> int: return self.rsgpr(i) | (self.rsgpr(i+1) << 32)
  def wsgpr64(self, i: int, v: int): self.wsgpr(i, v & MASK32); self.wsgpr(i+1, (v >> 32) & MASK32)

-  def _rsrc_base(self, v: int, lane: int, consts, literal: int):
+  def _rsrc_base(self, v: int, lane: int, consts):
    if v < SGPR_COUNT: return self.sgpr[v]
    if v == SCC: return self.scc
    if v < 255: return consts[v - 128]
-    if v == 255: return literal
+    if v == 255: return self.literal
    return self.vgpr[lane][v - 256] if v <= 511 else 0
-  def rsrc(self, v: int, lane: int, literal: int = 0) -> int: return self._rsrc_base(v, lane, _INLINE_CONSTS, literal)
-  def rsrc_f16(self, v: int, lane: int, literal: int = 0) -> int: return self._rsrc_base(v, lane, _INLINE_CONSTS_F16, literal)
-  def rsrc64(self, v: int, lane: int, literal: int = 0) -> int:
+  def rsrc(self, v: int, lane: int) -> int: return self._rsrc_base(v, lane, _INLINE_CONSTS)
+  def rsrc_f16(self, v: int, lane: int) -> int: return self._rsrc_base(v, lane, _INLINE_CONSTS_F16)
+  def rsrc64(self, v: int, lane: int) -> int:
    if 128 <= v < 255: return _INLINE_CONSTS_F64[v - 128]
-    if v == 255: return literal  # literal is already shifted in from_bytes for 64-bit ops
-    return self.rsrc(v, lane, literal) | ((self.rsrc(v+1, lane, literal) if v < VCC_LO or 256 <= v <= 511 else 0) << 32)
+    if v == 255: return self.literal  # literal is already shifted in from_bytes for 64-bit ops
+    return self.rsrc(v, lane) | ((self.rsrc(v+1, lane) if v < VCC_LO or 256 <= v <= 511 else 0) << 32)

  def pend_sgpr_lane(self, reg: int, lane: int, val: int):
    if reg not in self._pend_sgpr: self._pend_sgpr[reg] = 0
@@ -181,131 +113,268 @@ class WaveState:
    self._pend_sgpr.clear()


+def decode_program(data: bytes) -> Program:
+  result: Program = {}
+  i = 0
+  while i < len(data):
+    try: inst_class = detect_format(data[i:])
+    except ValueError: break  # stop at invalid instruction (padding/metadata after code)
+    if inst_class is None: i += 4; continue
+    base_size = inst_class._size()
+    # Pass enough data for potential 64-bit literal (base + 8 bytes max)
+    inst = inst_class.from_bytes(data[i:i+base_size+8])
+    for name, val in inst._values.items():
+      if name != 'op': setattr(inst, name, unwrap(val))  # skip op to preserve property access
+    inst._words = inst.size() // 4
+    result[i // 4] = inst
+    i += inst._words * 4
+  return result
+
 # ═══════════════════════════════════════════════════════════════════════════════
-# EXECUTION - All ops use pseudocode from PDF
+# EXECUTION - All ALU ops use pseudocode from PDF
 # ═══════════════════════════════════════════════════════════════════════════════

-def exec_scalar(st: WaveState, inst: Inst):
-  """Execute scalar instruction. Returns 0 to continue execution."""
+def exec_scalar(st: WaveState, inst: Inst) -> int:
+  """Execute scalar instruction. Returns PC delta or negative for special cases."""
+  compiled = _get_compiled()
+
+  # SOPP: special cases for control flow that has no pseudocode
+  if isinstance(inst, SOPP):
+    if inst.op == SOPPOp.S_ENDPGM: return -1
+    if inst.op == SOPPOp.S_BARRIER: return -2
+
+  # SMEM: memory loads (not ALU)
+  if isinstance(inst, SMEM):
+    addr = st.rsgpr64(inst.sbase * 2) + _sext(inst.offset, 21)
+    if inst.soffset not in (NULL, 0x7f): addr += st.rsrc(inst.soffset, 0)
+    if (cnt := SMEM_LOAD.get(inst.op)) is None: raise NotImplementedError(f"SMEM op {inst.op}")
+    for i in range(cnt): st.wsgpr(inst.sdata + i, mem_read((addr + i * 4) & MASK64, 4))
+    return 0
+
  # Get op enum and lookup compiled function
-  if isinstance(inst, SMEM): ssrc0, sdst = None, None
-  elif isinstance(inst, SOP1): ssrc0, sdst = inst.ssrc0, inst.sdst
+  if isinstance(inst, SOP1): ssrc0, sdst = inst.ssrc0, inst.sdst
  elif isinstance(inst, SOP2): ssrc0, sdst = inst.ssrc0, inst.sdst
  elif isinstance(inst, SOPC): ssrc0, sdst = inst.ssrc0, None
  elif isinstance(inst, SOPK): ssrc0, sdst = inst.sdst, inst.sdst  # sdst is both src and dst
  elif isinstance(inst, SOPP): ssrc0, sdst = None, None
  else: raise NotImplementedError(f"Unknown scalar type {type(inst)}")

-  # SMEM: memory loads
-  if isinstance(inst, SMEM):
-    addr = st.rsgpr64(inst.sbase * 2) + _sext(inst.offset, 21)
-    if inst.soffset not in (NULL, 0x7f): addr += st.rsrc(inst.soffset, 0, inst._literal)
-    result = inst._fn(GlobalMem, addr & MASK64)
-    if 'SDATA' in result:
-      sdata = result['SDATA']
-      for i in range(SMEM_DST_COUNT.get(inst.op, 1)): st.wsgpr(inst.sdata + i, (sdata >> (i * 32)) & MASK32)
-    st.pc += inst._words
-    return 0
+  # SOPP has gaps in the opcode enum - treat unknown opcodes as no-ops
+  try: op = inst.op
+  except ValueError:
+    if isinstance(inst, SOPP): return 0
+    raise
+  fn = compiled.get(type(op), {}).get(op)
+  if fn is None:
+    # SOPP instructions without pseudocode (waits, hints, nops) are no-ops
+    if isinstance(inst, SOPP): return 0
+    raise NotImplementedError(f"{op.name} not in pseudocode")

  # Build context - use inst methods to determine operand sizes
-  literal = inst._literal
-  s0 = st.rsrc64(ssrc0, 0, literal) if inst.is_src_64(0) else (st.rsrc(ssrc0, 0, literal) if not isinstance(inst, (SOPK, SOPP)) else (st.rsgpr(inst.sdst) if isinstance(inst, SOPK) else 0))
-  s1 = st.rsrc64(inst.ssrc1, 0, literal) if inst.is_src_64(1) else (st.rsrc(inst.ssrc1, 0, literal) if isinstance(inst, (SOP2, SOPC)) else inst.simm16 if isinstance(inst, SOPK) else 0)
+  s0 = st.rsrc64(ssrc0, 0) if inst.is_src_64(0) else (st.rsrc(ssrc0, 0) if not isinstance(inst, (SOPK, SOPP)) else (st.rsgpr(inst.sdst) if isinstance(inst, SOPK) else 0))
+  s1 = st.rsrc64(inst.ssrc1, 0) if inst.is_src_64(1) else (st.rsrc(inst.ssrc1, 0) if isinstance(inst, (SOP2, SOPC)) else inst.simm16 if isinstance(inst, SOPK) else 0)
  d0 = st.rsgpr64(sdst) if inst.dst_regs() == 2 and sdst is not None else (st.rsgpr(sdst) if sdst is not None else 0)
-  literal = inst.simm16 if isinstance(inst, (SOPK, SOPP)) else inst._literal
+  literal = inst.simm16 if isinstance(inst, (SOPK, SOPP)) else st.literal

-  # Call compiled function with int parameters
-  result = inst._fn(s0, s1, 0, d0, st.scc, st.vcc & MASK32, 0, st.exec_mask & MASK32, literal, None, pc=st.pc * 4)
+  # Create Reg objects for compiled function - mask VCC/EXEC to 32 bits for wave32
+  result = fn(Reg(s0), Reg(s1), None, Reg(d0), Reg(st.scc), Reg(st.vcc & MASK32), 0, Reg(st.exec_mask & MASK32), literal, None, PC=Reg(st.pc * 4))

-  # Apply results (already int values)
+  # Apply results - extract values from returned Reg objects
  if sdst is not None and 'D0' in result:
-    (st.wsgpr64 if inst.dst_regs() == 2 else st.wsgpr)(sdst, result['D0'])
-  if 'SCC' in result: st.scc = result['SCC'] & 1
-  if 'EXEC' in result: st.exec_mask = result['EXEC']
+    (st.wsgpr64 if inst.dst_regs() == 2 else st.wsgpr)(sdst, result['D0']._val)
+  if 'SCC' in result: st.scc = result['SCC']._val & 1
+  if 'EXEC' in result: st.exec_mask = result['EXEC']._val
  if 'PC' in result:
-    # Convert absolute byte address to word offset
-    pc_val = result['PC']
+    # Convert absolute byte address to word delta
+    pc_val = result['PC']._val
    new_pc = pc_val if pc_val < 0x8000000000000000 else pc_val - 0x10000000000000000
-    st.pc = new_pc // 4
-  else:
-    st.pc += inst._words
+    new_pc_words = new_pc // 4
+    return new_pc_words - st.pc - 1  # -1 because emulator adds inst_words (1 for scalar)
  return 0

-# ═══════════════════════════════════════════════════════════════════════════════
-# VECTOR INSTRUCTIONS
-# ═══════════════════════════════════════════════════════════════════════════════
+def exec_vector(st: WaveState, inst: Inst, lane: int, lds: bytearray | None = None) -> None:
+  """Execute vector instruction for one lane."""
+  compiled = _get_compiled()
+  V = st.vgpr[lane]

-def exec_vopd(st: WaveState, inst, V: list, lane: int) -> None:
-  """VOPD: dual-issue, execute two ops simultaneously (read all inputs before writes)."""
-  literal, vdstx, vdsty = inst._literal, inst.vdstx, (inst.vdsty << 1) | ((inst.vdstx & 1) ^ 1)
-  sx0, sx1, dx, sy0, sy1, dy = st.rsrc(inst.srcx0, lane, literal), V[inst.vsrcx1], V[vdstx], st.rsrc(inst.srcy0, lane, literal), V[inst.vsrcy1], V[vdsty]
-  V[vdstx] = inst._fnx(sx0, sx1, 0, dx, st.scc, st.vcc, lane, st.exec_mask, literal, None)['D0']
-  V[vdsty] = inst._fny(sy0, sy1, 0, dy, st.scc, st.vcc, lane, st.exec_mask, literal, None)['D0']
+  # Memory ops (not ALU pseudocode)
+  if isinstance(inst, FLAT):
+    op, addr_reg, data_reg, vdst, offset, saddr = inst.op, inst.addr, inst.data, inst.vdst, _sext(inst.offset, 13), inst.saddr
+    addr = V[addr_reg] | (V[addr_reg+1] << 32)
+    addr = (st.rsgpr64(saddr) + V[addr_reg] + offset) & MASK64 if saddr not in (NULL, 0x7f) else (addr + offset) & MASK64
+    if op in FLAT_LOAD:
+      cnt, sz, sign = FLAT_LOAD[op]
+      for i in range(cnt): val = mem_read(addr + i * sz, sz); V[vdst + i] = _sext(val, sz * 8) & MASK32 if sign else val
+    elif op in FLAT_STORE:
+      cnt, sz = FLAT_STORE[op]
+      for i in range(cnt): mem_write(addr + i * sz, sz, V[data_reg + i] & ((1 << (sz * 8)) - 1))
+    elif op in FLAT_D16_LOAD:
+      sz, sign, hi = FLAT_D16_LOAD[op]
+      val = mem_read(addr, sz)
+      if sign: val = _sext(val, sz * 8) & 0xffff
+      V[vdst] = _dst16(V[vdst], val, hi)
+    elif op in FLAT_D16_STORE:
+      sz, hi = FLAT_D16_STORE[op]
+      mem_write(addr, sz, _src16(V[data_reg], hi) & ((1 << (sz * 8)) - 1))
+    else: raise NotImplementedError(f"FLAT op {op}")
+    return

-def exec_flat(st: WaveState, inst, V: list, lane: int) -> None:
-  """FLAT/GLOBAL/SCRATCH memory ops."""
-  ndwords = _op_ndwords(inst.op_name)
-  addr = V[inst.addr] | (V[inst.addr + 1] << 32)
-  ADDR = (st.rsgpr64(inst.saddr) + V[inst.addr] + _sext(inst.offset, 13)) & MASK64 if inst.saddr not in (NULL, 0x7f) else (addr + _sext(inst.offset, 13)) & MASK64
-  vdata_src = inst.vdst if 'LOAD' in inst.op_name else inst.data
-  result = inst._fn(GlobalMem, ADDR, _vgpr_read(V, vdata_src, ndwords), V[inst.vdst])
-  if 'VDATA' in result: _vgpr_write(V, inst.vdst, result['VDATA'], ndwords)
-  if 'RETURN_DATA' in result: _vgpr_write(V, inst.vdst, result['RETURN_DATA'], ndwords)
+  if isinstance(inst, DS):
+    fn = compiled.get(DSOp, {}).get(inst.op)
+    if fn is None: raise NotImplementedError(f"DS op {inst.op.name} not in pseudocode")
+    # Prepare data registers as lists of dwords
+    data0 = [V[inst.data0 + i] for i in range(4)]  # up to 4 dwords
+    data1 = [V[inst.data1 + i] for i in range(4)] if inst.data1 else [0, 0, 0, 0]
+    result = fn(lds, V[inst.addr], data0, data1, inst.vdst, inst.offset0, inst.offset1)
+    # Write results for loads
+    if 'vdst' in result:
+      for i, val in enumerate(result['vdst']): V[inst.vdst + i] = val & MASK32
+    return

-def exec_ds(st: WaveState, inst, V: list, lane: int) -> None:
-  """DS (LDS) memory ops."""
-  ndwords = _op_ndwords(inst.op_name)
-  data0, data1 = _vgpr_read(V, inst.data0, ndwords), _vgpr_read(V, inst.data1, ndwords) if inst.data1 is not None else 0
-  result = inst._fn(st.lds, V[inst.addr], data0, data1, inst.offset0, inst.offset1)
-  if 'RETURN_DATA' in result and ('_RTN' in inst.op_name or '_LOAD' in inst.op_name):
-    _vgpr_write(V, inst.vdst, result['RETURN_DATA'], ndwords * 2 if '_2ADDR_' in inst.op_name else ndwords)
+  # VOPD: dual-issue, execute two ops simultaneously (read all inputs before writes)
+  if isinstance(inst, VOPD):
+    vdsty = (inst.vdsty << 1) | ((inst.vdstx & 1) ^ 1)
+    inputs = [(inst.opx, st.rsrc(inst.srcx0, lane), V[inst.vsrcx1], V[inst.vdstx], inst.vdstx),
+              (inst.opy, st.rsrc(inst.srcy0, lane), V[inst.vsrcy1], V[vdsty], vdsty)]
+    def exec_vopd(vopd_op, s0, s1, d0):
+      op = _VOPD_TO_VOP[vopd_op]
+      return compiled[type(op)][op](Reg(s0), Reg(s1), None, Reg(d0), Reg(st.scc), Reg(st.vcc), lane, Reg(st.exec_mask), st.literal, None)['D0']._val
+    for vopd_op, s0, s1, d0, dst in inputs: V[dst] = exec_vopd(vopd_op, s0, s1, d0)
+    return

-def exec_vop(st: WaveState, inst: Inst, V: list, lane: int) -> None:
-  """VOP1/VOP2/VOP3/VOP3SD/VOP3P/VOPC: standard ALU ops."""
-  if isinstance(inst, VOP3P):
-    src0, src1, src2, vdst, dst_hi = inst.src0, inst.src1, inst.src2, inst.vdst, False
-    neg, abs_, opsel = inst.neg, 0, inst.opsel
-  elif isinstance(inst, VOP1):
-    src0, src1, src2, vdst = inst.src0, None, None, inst.vdst & 0x7f if inst.is_dst_16() else inst.vdst
-    neg, abs_, opsel, dst_hi = 0, 0, 0, (inst.vdst & 0x80) != 0 and inst.is_dst_16()
+  # VOP3SD: has extra scalar dest for carry output
+  if isinstance(inst, VOP3SD):
+    fn = compiled[VOP3SDOp][inst.op]
+    # Read sources based on register counts from inst properties
+    def rsrc_n(src, regs): return st.rsrc64(src, lane) if regs == 2 else st.rsrc(src, lane)
+    s0, s1, s2 = rsrc_n(inst.src0, inst.src_regs(0)), rsrc_n(inst.src1, inst.src_regs(1)), rsrc_n(inst.src2, inst.src_regs(2))
+    # Carry-in ops use src2 as carry bitmask instead of VCC
+    vcc = st.rsgpr64(inst.src2) if 'CO_CI' in inst.op_name else st.vcc
+    result = fn(Reg(s0), Reg(s1), Reg(s2), Reg(V[inst.vdst]), Reg(st.scc), Reg(vcc), lane, Reg(st.exec_mask), st.literal, None)
+    d0_val = result['D0']._val
+    V[inst.vdst] = d0_val & MASK32
+    if inst.dst_regs() == 2: V[inst.vdst + 1] = (d0_val >> 32) & MASK32
+    if 'VCC' in result: st.pend_sgpr_lane(inst.sdst, lane, (result['VCC']._val >> lane) & 1)
+    return
+
+  # Get op enum and sources (None means "no source" for that operand)
+  # dst_hi: for VOP1/VOP2 16-bit dst ops, bit 7 of vdst indicates .h (high 16-bit) destination
+  dst_hi = False
+  if isinstance(inst, VOP1):
+    if inst.op == VOP1Op.V_NOP: return
+    src0, src1, src2 = inst.src0, None, None
+    dst_hi = (inst.vdst & 0x80) != 0 and inst.is_dst_16()
+    vdst = inst.vdst & 0x7f if inst.is_dst_16() else inst.vdst
  elif isinstance(inst, VOP2):
-    src0, src1, src2, vdst = inst.src0, inst.vsrc1 + 256, None, inst.vdst & 0x7f if inst.is_dst_16() else inst.vdst
-    neg, abs_, opsel, dst_hi = 0, 0, 0, (inst.vdst & 0x80) != 0 and inst.is_dst_16()
-  elif isinstance(inst, (VOP3, VOP3SD)):
-    src0, src1, src2, vdst = inst.src0, inst.src1, (None if isinstance(inst, VOP3) and inst.op.value < 256 else inst.src2), inst.vdst
-    neg, abs_, opsel, dst_hi = (inst.neg, inst.abs, inst.opsel, False) if isinstance(inst, VOP3) else (0, 0, 0, False)
+    src0, src1, src2 = inst.src0, inst.vsrc1 + 256, None
+    dst_hi = (inst.vdst & 0x80) != 0 and inst.is_dst_16()
+    vdst = inst.vdst & 0x7f if inst.is_dst_16() else inst.vdst
+  elif isinstance(inst, VOP3):
+    # VOP3 ops 0-255 are VOPC comparisons encoded as VOP3 - inst.op returns VOPCOp for these
+    src0, src1, src2, vdst = inst.src0, inst.src1, (None if inst.op.value < 256 else inst.src2), inst.vdst
  elif isinstance(inst, VOPC):
-    src0, src1, src2, vdst, neg, abs_, opsel, dst_hi = inst.src0, inst.vsrc1 + 256, None, VCC_LO, 0, 0, 0, False
-  else:
-    raise NotImplementedError(f"exec_vop: unhandled instruction type {type(inst).__name__}")
+    # For 16-bit VOPC, vsrc1 uses same encoding as VOP2 16-bit: bit 7 selects hi(1) or lo(0) half
+    # vsrc1 field is 8 bits: [6:0] = VGPR index, [7] = hi flag
+    src0, src1, src2, vdst = inst.src0, inst.vsrc1 + 256, None, VCC_LO
+  elif isinstance(inst, VOP3P):
+    # VOP3P: Packed 16-bit operations using compiled functions
+    # WMMA: wave-level matrix multiply-accumulate (special handling - needs cross-lane access)
+    if 'WMMA' in inst.op_name:
+      if lane == 0:  # Only execute once per wave, write results for all lanes
+        exec_wmma(st, inst, inst.op)
+      return
+    # V_FMA_MIX: Mixed precision FMA - opsel_hi controls f32(0) vs f16(1), opsel selects which f16 half
+    # Handle inline because abs/neg must be applied AFTER type conversion
+    if inst.op in (VOP3POp.V_FMA_MIX_F32, VOP3POp.V_FMA_MIXLO_F16, VOP3POp.V_FMA_MIXHI_F16):
+      opsel, opsel_hi, opsel_hi2 = getattr(inst, 'opsel', 0), getattr(inst, 'opsel_hi', 0), getattr(inst, 'opsel_hi2', 0)
+      neg, abs_ = getattr(inst, 'neg', 0), getattr(inst, 'neg_hi', 0)  # neg_hi reused as abs for FMA_MIX
+      raws = [st.rsrc(inst.src0, lane), st.rsrc(inst.src1, lane), st.rsrc(inst.src2, lane) if inst.src2 is not None else 0]
+      is_f16 = [opsel_hi & 1, opsel_hi & 2, opsel_hi2]
+      srcs = [_f16(_src16(raws[i], bool(opsel & (1<<i)))) if is_f16[i] else _f32(raws[i]) for i in range(3)]
+      for i in range(3):
+        if abs_ & (1<<i): srcs[i] = abs(srcs[i])
+        if neg & (1<<i): srcs[i] = -srcs[i]
+      result_f = srcs[0] * srcs[1] + srcs[2]
+      V = st.vgpr[lane]
+      V[inst.vdst] = _i32(result_f) if inst.op == VOP3POp.V_FMA_MIX_F32 else _dst16(V[inst.vdst], _i16(result_f), inst.op == VOP3POp.V_FMA_MIXHI_F16)
+      return
+    # VOP3P packed ops: opsel selects halves for lo, opsel_hi for hi; neg toggles f16 sign
+    raws = [st.rsrc_f16(inst.src0, lane), st.rsrc_f16(inst.src1, lane), st.rsrc_f16(inst.src2, lane) if inst.src2 is not None else 0]
+    opsel, opsel_hi, opsel_hi2 = getattr(inst, 'opsel', 0), getattr(inst, 'opsel_hi', 3), getattr(inst, 'opsel_hi2', 1)
+    neg, neg_hi = getattr(inst, 'neg', 0), getattr(inst, 'neg_hi', 0)
+    hi_sels = [opsel_hi & 1, opsel_hi & 2, opsel_hi2]
+    srcs = [((_src16(raws[i], hi_sels[i]) ^ (0x8000 if neg_hi & (1<<i) else 0)) << 16) |
+            (_src16(raws[i], opsel & (1<<i)) ^ (0x8000 if neg & (1<<i) else 0)) for i in range(3)]
+    result = compiled[VOP3POp][inst.op](Reg(srcs[0]), Reg(srcs[1]), Reg(srcs[2]), Reg(0), Reg(st.scc), Reg(st.vcc), lane, Reg(st.exec_mask), st.literal, None)
+    st.vgpr[lane][inst.vdst] = result['D0']._val & MASK32
+    return
+  else: raise NotImplementedError(f"Unknown vector type {type(inst)}")

-  s0 = _read_src(st, inst, src0, 0, lane, neg, abs_, opsel)
-  s1 = _read_src(st, inst, src1, 1, lane, neg, abs_, opsel)
-  s2 = _read_src(st, inst, src2, 2, lane, neg, abs_, opsel)
-  if isinstance(inst, VOP2) and inst.is_16bit(): d0 = _src16(V[vdst], dst_hi)
-  elif inst.dst_regs() == 2: d0 = V[vdst] | (V[vdst + 1] << 32)
-  else: d0 = V[vdst]
+  op_cls = type(inst.op)
+  if (fn := compiled.get(op_cls, {}).get(inst.op)) is None: raise NotImplementedError(f"{inst.op_name} not in pseudocode")

-  if isinstance(inst, VOP3SD) and 'CO_CI' in inst.op_name: vcc_for_fn = st.rsgpr64(inst.src2)
-  elif isinstance(inst, VOP3) and inst.op in (VOP3Op.V_CNDMASK_B32, VOP3Op.V_CNDMASK_B16) and src2 is not None and src2 < 256: vcc_for_fn = st.rsgpr64(src2)
-  else: vcc_for_fn = st.vcc
+  # Read sources (with VOP3 modifiers if applicable)
+  neg, abs_ = (getattr(inst, 'neg', 0), getattr(inst, 'abs', 0)) if isinstance(inst, VOP3) else (0, 0)
+  opsel = getattr(inst, 'opsel', 0) if isinstance(inst, VOP3) else 0
+  def mod_src(val: int, idx: int, is64=False) -> int:
+    to_f, to_i = (_f64, _i64) if is64 else (_f32, _i32)
+    if (abs_ >> idx) & 1: val = to_i(abs(to_f(val)))
+    if (neg >> idx) & 1: val = to_i(-to_f(val))
+    return val
+
+  # Use inst methods to determine operand sizes (inst.is_src_16, inst.is_src_64, etc.)
+  is_vop2_16bit = isinstance(inst, VOP2) and inst.is_16bit()
+
+  # Read sources based on register counts and dtypes from inst properties
+  def read_src(src, idx, regs, is_src_16):
+    if src is None: return 0
+    if regs == 2: return mod_src(st.rsrc64(src, lane), idx, is64=True)
+    if is_src_16 and isinstance(inst, VOP3):
+      raw = st.rsrc_f16(src, lane) if 128 <= src < 255 else st.rsrc(src, lane)
+      val = _src16(raw, bool(opsel & (1 << idx)))
+      if abs_ & (1 << idx): val &= 0x7fff
+      if neg & (1 << idx): val ^= 0x8000
+      return val
+    if is_src_16 and isinstance(inst, (VOP1, VOP2, VOPC)):
+      if src >= 256: return _src16(mod_src(st.rsrc(_vgpr_masked(src), lane), idx), _vgpr_hi(src))
+      return mod_src(st.rsrc_f16(src, lane), idx) & 0xffff
+    return mod_src(st.rsrc(src, lane), idx)
+
+  s0 = read_src(src0, 0, inst.src_regs(0), inst.is_src_16(0))
+  s1 = read_src(src1, 1, inst.src_regs(1), inst.is_src_16(1)) if src1 is not None else 0
+  s2 = read_src(src2, 2, inst.src_regs(2), inst.is_src_16(2)) if src2 is not None else 0
+  # Read destination (accumulator for VOP2 f16, 64-bit for 64-bit ops)
+  d0 = _src16(V[vdst], dst_hi) if is_vop2_16bit else (V[vdst] | (V[vdst + 1] << 32)) if inst.dst_regs() == 2 else V[vdst]
+
+  # V_CNDMASK_B32/B16: VOP3 encoding uses src2 as mask (not VCC); VOP2 uses VCC implicitly
+  # Pass the correct mask as vcc to the function so pseudocode VCC.u64[laneId] works correctly
+  vcc_for_fn = st.rsgpr64(src2) if inst.op in (VOP3Op.V_CNDMASK_B32, VOP3Op.V_CNDMASK_B16) and isinstance(inst, VOP3) and src2 is not None and src2 < 256 else st.vcc
+
+  # Execute compiled function - pass src0_idx and vdst_idx for lane instructions
+  # For VGPR access: src0 index is the VGPR number (src0 - 256 if VGPR, else src0 for SGPR)
  src0_idx = (src0 - 256) if src0 is not None and src0 >= 256 else (src0 if src0 is not None else 0)
-  extra_kwargs = {'opsel': opsel, 'opsel_hi': inst.opsel_hi | (inst.opsel_hi2 << 2)} if isinstance(inst, VOP3P) and 'FMA_MIX' in inst.op_name else {}
-  result = inst._fn(s0, s1, s2, d0, st.scc, vcc_for_fn, lane, st.exec_mask, inst._literal, st.vgpr, src0_idx, vdst, **extra_kwargs)
+  result = fn(Reg(s0), Reg(s1), Reg(s2), Reg(d0), Reg(st.scc), Reg(vcc_for_fn), lane, Reg(st.exec_mask), st.literal, st.vgpr, src0_idx, vdst)

-  # Check if this is a VOPC instruction (either standalone VOPC or VOP3 with VOPC opcode)
-  is_vopc = isinstance(inst.op, VOPCOp) or (isinstance(inst, VOP3) and inst.op.value < 256)
+  # Apply results - extract values from returned Reg objects
+  if 'vgpr_write' in result:
+    # Lane instruction wrote to VGPR: (lane, vgpr_idx, value)
+    wr_lane, wr_idx, wr_val = result['vgpr_write']
+    st.vgpr[wr_lane][wr_idx] = wr_val
  if 'VCC' in result:
-    if isinstance(inst, VOP3SD): st.pend_sgpr_lane(inst.sdst, lane, (result['VCC'] >> lane) & 1)
-    else: st.pend_sgpr_lane(VCC_LO if isinstance(inst, VOP2) and 'CO_CI' in inst.op_name else vdst, lane, (result['VCC'] >> lane) & 1)
+    # VOP2 carry ops write to VCC implicitly; VOPC/VOP3 write to vdst
+    st.pend_sgpr_lane(VCC_LO if isinstance(inst, VOP2) and 'CO_CI' in inst.op_name else vdst, lane, (result['VCC']._val >> lane) & 1)
  if 'EXEC' in result:
-    st.pend_sgpr_lane(EXEC_LO, lane, (result['EXEC'] >> lane) & 1)
-  elif is_vopc:
-    st.pend_sgpr_lane(vdst, lane, (result['D0'] >> lane) & 1)
-  if not is_vopc:
-    d0_val = result['D0']
-    if inst.dst_regs() == 2: V[vdst], V[vdst + 1] = d0_val & MASK32, (d0_val >> 32) & MASK32
-    elif not isinstance(inst, VOP3P) and inst.is_dst_16(): V[vdst] = _dst16(V[vdst], d0_val, bool(opsel & 8) if isinstance(inst, VOP3) else dst_hi)
+    # V_CMPX instructions write to EXEC per-lane (not to vdst)
+    st.pend_sgpr_lane(EXEC_LO, lane, (result['EXEC']._val >> lane) & 1)
+  elif op_cls is VOPCOp:
+    # VOPC comparison result stored in D0 bitmask, extract lane bit (non-CMPX only)
+    st.pend_sgpr_lane(vdst, lane, (result['D0']._val >> lane) & 1)
+  if op_cls is not VOPCOp and 'vgpr_write' not in result:
+    writes_to_sgpr = 'READFIRSTLANE' in inst.op_name or 'READLANE' in inst.op_name
+    d0_val = result['D0']._val
+    if writes_to_sgpr: st.wsgpr(vdst, d0_val & MASK32)
+    elif inst.dst_regs() == 2: V[vdst], V[vdst + 1] = d0_val & MASK32, (d0_val >> 32) & MASK32
+    elif inst.is_dst_16(): V[vdst] = _dst16(V[vdst], d0_val, bool(opsel & 8) if isinstance(inst, VOP3) else dst_hi)
    else: V[vdst] = d0_val & MASK32

 # ═══════════════════════════════════════════════════════════════════════════════
@@ -330,104 +399,64 @@ def exec_wmma(st: WaveState, inst, op: VOP3POp) -> None:
  else:
    for i in range(256): st.vgpr[i % 32][vdst + i//32] = _i32(mat_d[i])

-# ═══════════════════════════════════════════════════════════════════════════════
-# PROGRAM DECODE
-# ═══════════════════════════════════════════════════════════════════════════════
-
-# Wave-level dispatch functions: (st, inst) -> return_code (0 = continue, -1 = end, -2 = barrier)
-def dispatch_endpgm(st, inst): return -1
-def dispatch_barrier(st, inst): st.pc += inst._words; return -2
-def dispatch_nop(st, inst): st.pc += inst._words; return 0
-def dispatch_wmma(st, inst): exec_wmma(st, inst, inst.op); st.pc += inst._words; return 0
-def dispatch_writelane(st, inst): st.vgpr[st.rsrc(inst.src1, 0, inst._literal) & 0x1f][inst.vdst] = st.rsrc(inst.src0, 0, inst._literal) & MASK32; st.pc += inst._words; return 0
-def dispatch_readlane(st, inst):
-  src0_idx = (inst.src0 - 256) if inst.src0 >= 256 else inst.src0
-  s1 = st.rsrc(inst.src1, 0, inst._literal) if getattr(inst, 'src1', None) is not None else 0
-  result = inst._fn(0, s1, 0, 0, st.scc, st.vcc, 0, st.exec_mask, inst._literal, st.vgpr, src0_idx, inst.vdst)
-  st.wsgpr(inst.vdst, result['D0'])
-  st.pc += inst._words; return 0
-
-# Per-lane dispatch wrapper: wraps per-lane exec functions into wave-level dispatch
-@functools.cache
-def dispatch_lane(exec_fn):
-  def dispatch(st, inst):
-    exec_mask, vgpr, n_lanes = st.exec_mask, st.vgpr, st.n_lanes
-    for lane in range(n_lanes):
-      if exec_mask >> lane & 1: exec_fn(st, inst, vgpr[lane], lane)
-    st.commit_pends()
-    st.pc += inst._words
-    return 0
-  return dispatch
-
-def decode_program(data: bytes) -> dict[int, Inst]:
-  result: dict[int, Inst] = {}
-  i = 0
-  while i < len(data):
-    inst = decode_inst(data[i:])
-    inst._words = inst.size() // 4
-
-    # Determine dispatch function and pcode function
-    if isinstance(inst, SOPP) and inst.op == SOPPOp.S_CODE_END: break
-    elif isinstance(inst, SOPP) and inst.op == SOPPOp.S_ENDPGM: inst._dispatch = dispatch_endpgm
-    elif isinstance(inst, SOPP) and inst.op == SOPPOp.S_BARRIER: inst._dispatch = dispatch_barrier
-    elif isinstance(inst, SOPP) and inst.op in (SOPPOp.S_CLAUSE, SOPPOp.S_WAITCNT, SOPPOp.S_WAITCNT_DEPCTR, SOPPOp.S_SENDMSG, SOPPOp.S_SET_INST_PREFETCH_DISTANCE, SOPPOp.S_DELAY_ALU): inst._dispatch = dispatch_nop
-    elif isinstance(inst, (SOP1, SOP2, SOPC, SOPK, SOPP, SMEM)): inst._dispatch = exec_scalar
-    elif isinstance(inst, VOP1) and inst.op == VOP1Op.V_NOP: inst._dispatch = dispatch_nop
-    elif isinstance(inst, VOP3P) and 'WMMA' in inst.op_name: inst._dispatch = dispatch_wmma
-    elif isinstance(inst, VOP3) and inst.op == VOP3Op.V_WRITELANE_B32: inst._dispatch = dispatch_writelane
-    elif isinstance(inst, (VOP1, VOP3)) and inst.op in (VOP1Op.V_READFIRSTLANE_B32, VOP3Op.V_READFIRSTLANE_B32, VOP3Op.V_READLANE_B32): inst._dispatch = dispatch_readlane
-    elif isinstance(inst, VOPD): inst._dispatch = dispatch_lane(exec_vopd)
-    elif isinstance(inst, FLAT): inst._dispatch = dispatch_lane(exec_flat)
-    elif isinstance(inst, DS): inst._dispatch = dispatch_lane(exec_ds)
-    else: inst._dispatch = dispatch_lane(exec_vop)
-
-    # Compile pcode for instructions that use it (not VOPD which has _fnx/_fny, not special dispatches)
-    # VOPD needs separate functions for X and Y ops
-    if isinstance(inst, VOPD):
-      def _compile_vopd_op(op): return compile_pseudocode(type(op).__name__, op.name, PSEUDOCODE_STRINGS[type(op)][op])
-      inst._fnx, inst._fny = _compile_vopd_op(_VOPD_TO_VOP[inst.opx]), _compile_vopd_op(_VOPD_TO_VOP[inst.opy])
-    elif inst._dispatch not in (dispatch_endpgm, dispatch_barrier, dispatch_nop, dispatch_wmma, dispatch_writelane):
-      assert type(inst.op) != int, f"inst op of {inst} is int"
-      inst._fn = compile_pseudocode(type(inst.op).__name__, inst.op.name, PSEUDOCODE_STRINGS[type(inst.op)][inst.op])
-    result[i // 4] = inst
-    i += inst._words * 4
-  return result
-
 # ═══════════════════════════════════════════════════════════════════════════════
 # MAIN EXECUTION LOOP
 # ═══════════════════════════════════════════════════════════════════════════════

-def exec_wave(program: dict[int, Inst], st: WaveState) -> int:
-  while (inst := program.get(st.pc)) and (result := inst._dispatch(st, inst)) == 0: pass
-  return result
+def step_wave(program: Program, st: WaveState, lds: bytearray, n_lanes: int) -> int:
+  inst = program.get(st.pc)
+  if inst is None: return 1
+  inst_words, st.literal = inst._words, getattr(inst, '_literal', None) or 0

-def exec_workgroup(program: dict[int, Inst], workgroup_id: tuple[int, int, int], local_size: tuple[int, int, int], args_ptr: int, rsrc2: int) -> None:
+  if isinstance(inst, (SOP1, SOP2, SOPC, SOPK, SOPP, SMEM)):
+    delta = exec_scalar(st, inst)
+    if delta == -1: return -1  # endpgm
+    if delta == -2: st.pc += inst_words; return -2  # barrier
+    st.pc += inst_words + delta
+  else:
+    # V_READFIRSTLANE/V_READLANE write to SGPR, execute once; others execute per-lane with exec_mask
+    is_readlane = isinstance(inst, (VOP1, VOP3)) and ('READFIRSTLANE' in inst.op_name or 'READLANE' in inst.op_name)
+    exec_mask = 1 if is_readlane else st.exec_mask
+    for lane in range(1 if is_readlane else n_lanes):
+      if exec_mask & (1 << lane): exec_vector(st, inst, lane, lds)
+    st.commit_pends()
+    st.pc += inst_words
+  return 0
+
+def exec_wave(program: Program, st: WaveState, lds: bytearray, n_lanes: int) -> int:
+  while st.pc in program:
+    result = step_wave(program, st, lds, n_lanes)
+    if result == -1: return 0
+    if result == -2: return -2
+  return 0
+
+def exec_workgroup(program: Program, workgroup_id: tuple[int, int, int], local_size: tuple[int, int, int], args_ptr: int,
+                   wg_id_sgpr_base: int, wg_id_enables: tuple[bool, bool, bool]) -> None:
  lx, ly, lz = local_size
-  total_threads = lx * ly * lz
-  # GRANULATED_LDS_SIZE is in 512-byte units (see ops_amd.py: lds_size = ((group_segment_size + 511) // 512))
-  lds_size = ((rsrc2 & hsa.AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE) >> hsa.AMD_COMPUTE_PGM_RSRC_TWO_GRANULATED_LDS_SIZE_SHIFT) * 512
-  lds = LDSMem(bytearray(lds_size)) if lds_size else None
-  waves: list[WaveState] = []
+  total_threads, lds = lx * ly * lz, bytearray(65536)
+  waves: list[tuple[WaveState, int, int]] = []
  for wave_start in range(0, total_threads, WAVE_SIZE):
-    n_lanes = min(WAVE_SIZE, total_threads - wave_start)
-    st = WaveState(lds, n_lanes)
+    n_lanes, st = min(WAVE_SIZE, total_threads - wave_start), WaveState()
    st.exec_mask = (1 << n_lanes) - 1
-    st.wsgpr64(0, args_ptr)  # s[0:1] = kernel arguments pointer
-    # COMPUTE_PGM_RSRC2: USER_SGPR_COUNT is where workgroup IDs start, ENABLE_SGPR_WORKGROUP_ID_X/Y/Z control which are passed
-    sgpr_idx = (rsrc2 & hsa.AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT) >> hsa.AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT_SHIFT
-    if rsrc2 & hsa.AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X: st.sgpr[sgpr_idx] = workgroup_id[0]; sgpr_idx += 1
-    if rsrc2 & hsa.AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Y: st.sgpr[sgpr_idx] = workgroup_id[1]; sgpr_idx += 1
-    if rsrc2 & hsa.AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_Z: st.sgpr[sgpr_idx] = workgroup_id[2]
-    # VGPR0 = packed workitem IDs: (Z << 20) | (Y << 10) | X
-    for tid in range(wave_start, wave_start + n_lanes):
-      st.vgpr[tid - wave_start][0] = ((tid // (lx * ly)) << 20) | (((tid // lx) % ly) << 10) | (tid % lx)
-    waves.append(st)
-  while waves:
-    waves = [st for st in waves if exec_wave(program, st) != -1]
+    st.wsgpr64(0, args_ptr)
+    # Set workgroup IDs in SGPRs based on USER_SGPR_COUNT and enable flags from COMPUTE_PGM_RSRC2
+    sgpr_idx = wg_id_sgpr_base
+    for wg_id, enabled in zip(workgroup_id, wg_id_enables):
+      if enabled: st.sgpr[sgpr_idx] = wg_id; sgpr_idx += 1
+    # Set workitem IDs in VGPR0 using packed method: v0 = (Z << 20) | (Y << 10) | X
+    for i in range(n_lanes):
+      tid = wave_start + i
+      st.vgpr[i][0] = ((tid // (lx * ly)) << 20) | (((tid // lx) % ly) << 10) | (tid % lx)
+    waves.append((st, n_lanes, wave_start))
+  has_barrier = any(isinstance(inst, SOPP) and inst.op == SOPPOp.S_BARRIER for inst in program.values())
+  for _ in range(2 if has_barrier else 1):
+    for st, n_lanes, _ in waves: exec_wave(program, st, lds, n_lanes)

 def run_asm(lib: int, lib_sz: int, gx: int, gy: int, gz: int, lx: int, ly: int, lz: int, args_ptr: int, rsrc2: int = 0x19c) -> int:
  program = decode_program((ctypes.c_char * lib_sz).from_address(lib).raw)
+  if not program: return -1
+  wg_id_enables = tuple(bool((rsrc2 >> (7+i)) & 1) for i in range(3))
  for gidz in range(gz):
    for gidy in range(gy):
-      for gidx in range(gx): exec_workgroup(program, (gidx, gidy, gidz), (lx, ly, lz), args_ptr, rsrc2)
+      for gidx in range(gx): exec_workgroup(program, (gidx, gidy, gidz), (lx, ly, lz), args_ptr, (rsrc2 >> 1) & 0x1f, wg_id_enables)
  return 0
@@ -1,319 +1,670 @@
-# Generic PDF text extractor - no external dependencies
-import re, zlib
-from tinygrad.helpers import fetch, merge_dicts
+# Generate AMD ISA autogen files from PDF documentation
+# Combines format/enum generation (previously in dsl.py) and pseudocode compilation (previously in pcode.py)
+# Usage: python -m extra.assembly.amd.pdf [--arch rdna3|rdna4|cdna|all]
+import re, functools
+from pathlib import Path
+from concurrent.futures import ProcessPoolExecutor

 PDF_URLS = {
  "rdna3": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content",
  "rdna4": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content",
-  "cdna": "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf",
+  "cdna": ["https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf",
+           "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"],
 }

-# ═══════════════════════════════════════════════════════════════════════════════
-# Generic PDF extraction tools
-# ═══════════════════════════════════════════════════════════════════════════════
+# Field type mappings and ordering
+FIELD_TYPES = {'SSRC0': 'SSrc', 'SSRC1': 'SSrc', 'SOFFSET': 'SSrc', 'SADDR': 'SSrc', 'SRC0': 'Src', 'SRC1': 'Src', 'SRC2': 'Src',
+  'SDST': 'SGPRField', 'SBASE': 'SGPRField', 'SDATA': 'SGPRField', 'SRSRC': 'SGPRField', 'VDST': 'VGPRField', 'VSRC1': 'VGPRField',
+  'VDATA': 'VGPRField', 'VADDR': 'VGPRField', 'ADDR': 'VGPRField', 'DATA': 'VGPRField', 'DATA0': 'VGPRField', 'DATA1': 'VGPRField',
+  'SIMM16': 'SImm', 'OFFSET': 'Imm', 'OPX': 'VOPDOp', 'OPY': 'VOPDOp', 'SRCX0': 'Src', 'SRCY0': 'Src',
+  'VSRCX1': 'VGPRField', 'VSRCY1': 'VGPRField', 'VDSTX': 'VGPRField', 'VDSTY': 'VDSTYEnc'}
+FIELD_ORDER = {
+  'SOP2': ['op', 'sdst', 'ssrc0', 'ssrc1'], 'SOP1': ['op', 'sdst', 'ssrc0'], 'SOPC': ['op', 'ssrc0', 'ssrc1'],
+  'SOPK': ['op', 'sdst', 'simm16'], 'SOPP': ['op', 'simm16'], 'VOP1': ['op', 'vdst', 'src0'], 'VOPC': ['op', 'src0', 'vsrc1'],
+  'VOP2': ['op', 'vdst', 'src0', 'vsrc1'], 'VOP3SD': ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2', 'clmp'],
+  'SMEM': ['op', 'sdata', 'sbase', 'soffset', 'offset', 'glc', 'dlc'], 'DS': ['op', 'vdst', 'addr', 'data0', 'data1'],
+  'VOP3': ['op', 'vdst', 'src0', 'src1', 'src2', 'omod', 'neg', 'abs', 'clmp', 'opsel'],
+  'VOP3P': ['op', 'vdst', 'src0', 'src1', 'src2', 'neg', 'neg_hi', 'opsel', 'opsel_hi', 'clmp'],
+  'FLAT': ['op', 'vdst', 'addr', 'data', 'saddr', 'offset', 'seg', 'dlc', 'glc', 'slc'],
+  'MUBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
+  'MTBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
+  'MIMG': ['op', 'vdata', 'vaddr', 'srsrc', 'ssamp', 'dmask', 'dim', 'unrm', 'dlc', 'glc', 'slc'],
+  'EXP': ['en', 'target', 'vsrc0', 'vsrc1', 'vsrc2', 'vsrc3', 'done', 'row'],
+  'VINTERP': ['op', 'vdst', 'src0', 'src1', 'src2', 'waitexp', 'clmp', 'opsel', 'neg'],
+  'VOPD': ['opx', 'opy', 'vdstx', 'vdsty', 'srcx0', 'vsrcx1', 'srcy0', 'vsrcy1'],
+  'LDSDIR': ['op', 'vdst', 'attr', 'attr_chan', 'wait_va']}
+SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'}
+FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO',
+  '4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'}
+INST_PATTERN = re.compile(r'^([SVD]S?_[A-Z0-9_]+)\s+(\d+)\s*$', re.M)

-def extract(url: str) -> list[list[tuple[float, float, str, str]]]:
-  """Extract positioned text from PDF. Returns list of text elements (x, y, text, font) per page."""
-  data = fetch(url).read_bytes()
-
-  # Parse xref table to locate objects
-  xref: dict[int, int] = {}
-  pos = int(re.search(rb'startxref\s+(\d+)', data).group(1)) + 4
-  while data[pos:pos+7] != b'trailer':
-    while data[pos:pos+1] in b' \r\n': pos += 1
-    line_end = data.find(b'\n', pos)
-    start_obj, count = map(int, data[pos:line_end].split()[:2])
-    pos = line_end + 1
-    for i in range(count):
-      if data[pos+17:pos+18] == b'n' and (off := int(data[pos:pos+10])) > 0: xref[start_obj + i] = off
-      pos += 20
-
-  def get_stream(n: int) -> bytes:
-    obj = data[xref[n]:data.find(b'endobj', xref[n])]
-    raw = obj[obj.find(b'stream\n') + 7:obj.find(b'\nendstream')]
-    return zlib.decompress(raw) if b'/FlateDecode' in obj else raw
-
-  # Find page content streams and extract text
-  pages = []
-  for n in sorted(xref):
-    if b'/Type /Page' not in data[xref[n]:xref[n]+500]: continue
-    if not (m := re.search(rb'/Contents (\d+) 0 R', data[xref[n]:xref[n]+500])): continue
-    stream = get_stream(int(m.group(1))).decode('latin-1')
-    elements, font = [], ''
-    for bt in re.finditer(r'BT(.*?)ET', stream, re.S):
-      x, y = 0.0, 0.0
-      for m in re.finditer(r'(/F[\d.]+) [\d.]+ Tf|([\d.+-]+) ([\d.+-]+) Td|[\d.+-]+ [\d.+-]+ [\d.+-]+ [\d.+-]+ ([\d.+-]+) ([\d.+-]+) Tm|<([0-9A-Fa-f]+)>.*?Tj|\[([^\]]+)\] TJ', bt.group(1)):
-        if m.group(1): font = m.group(1)
-        elif m.group(2): x, y = x + float(m.group(2)), y + float(m.group(3))
-        elif m.group(4): x, y = float(m.group(4)), float(m.group(5))
-        elif m.group(6) and (t := bytes.fromhex(m.group(6)).decode('latin-1')).strip(): elements.append((x, y, t, font))
-        elif m.group(7) and (t := ''.join(bytes.fromhex(h).decode('latin-1') for h in re.findall(r'<([0-9A-Fa-f]+)>', m.group(7)))).strip(): elements.append((x, y, t, font))
-    pages.append(sorted(elements, key=lambda e: (-e[1], e[0])))
-  return pages
-
-def extract_tables(pages: list[list[tuple[float, float, str, str]]]) -> dict[int, tuple[str, list[list[str]]]]:
-  """Extract numbered tables from PDF pages. Returns {table_num: (title, rows)} where rows is list of cells per row."""
-  def group_by_y(texts, key=lambda y: round(y)):
-    by_y: dict[int, list[tuple[float, float, str]]] = {}
-    for x, y, t, _ in texts:
-      by_y.setdefault(key(y), []).append((x, y, t))
-    return by_y
-
-  # Find all table headers by merging text on same line
-  table_positions = []
-  for page_idx, texts in enumerate(pages):
-    for items in group_by_y(texts).values():
-      line = ''.join(t for _, t in sorted((x, t) for x, _, t in items))
-      if m := re.search(r'Table (\d+)\. (.+)', line):
-        table_positions.append((int(m.group(1)), m.group(2).strip(), page_idx, items[0][1]))
-  table_positions.sort(key=lambda t: (t[2], -t[3]))
-
-  # For each table, find rows with matching X positions
-  result: dict[int, tuple[str, list[list[str]]]] = {}
-  for num, title, start_page, header_y in table_positions:
-    rows, col_xs = [], None
-    for page_idx in range(start_page, len(pages)):
-      page_texts = [(x, y, t) for x, y, t, _ in pages[page_idx] if 30 < y < 760 and (page_idx > start_page or y < header_y)]
-      for items in sorted(group_by_y([(x, y, t, '') for x, y, t in page_texts], key=lambda y: round(y / 5)).values(), key=lambda items: -items[0][1]):
-        xs = tuple(sorted(round(x) for x, _, _ in items))
-        if col_xs is None:
-          if len(xs) < 2: continue  # Skip single-column rows before table starts
-          col_xs = xs
-        elif len(xs) == 1 and xs[0] in col_xs: continue  # Skip continuation rows at known column positions
-        elif not any(c in xs for c in col_xs[:2]): break  # Row missing first columns = end of table
-        rows.append([t for _, t in sorted((x, t) for x, _, t in items)])
-      else: continue
-      break
-    if rows: result[num] = (title, rows)
-  return result
+# Patterns that can't be handled by the DSL (require special handling in emu.py)
+UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS',
+               'vscnt', 'vmcnt', 'expcnt', 'lgkmcnt',
+               'CVT_OFF_TABLE', 'ThreadMask',
+               'S1[i', 'C.i32',
+               'if n.', 'DST.u32', 'addrd = DST', 'addr = DST',
+               'BARRIER_STATE', 'ReallocVgprs',
+               'GPR_IDX', 'VSKIP', 'specified in', 'TTBL',
+               'fp6', 'bf6']  # Malformed pseudocode from PDF

 # ═══════════════════════════════════════════════════════════════════════════════
-# AMD specific extraction
+# COMPILER: pseudocode -> Python (minimal transforms)
 # ═══════════════════════════════════════════════════════════════════════════════

-def extract_enums(tables: dict[int, tuple[str, list[list[str]]]]) -> dict[str, dict[int, str]]:
-  """Extract all enums from tables. Returns {enum_name: {value: name}}."""
-  enums: dict[str, dict[int, str]] = {}
-  for num, (title, rows) in tables.items():
-    # Opcode enums from "XXX Opcodes" tables
-    if m := re.match(r'(\w+) (?:Y-)?Opcodes', title):
-      fmt_name = 'VOPD' if 'Y-Opcodes' in title else m.group(1)
-      ops: dict[int, str] = {}
-      for row in rows:
-        for i in range(0, len(row) - 1, 2):
-          if row[i].isdigit() and re.match(r'^[A-Z][A-Z0-9_]+$', row[i + 1]):
-            ops[int(row[i])] = row[i + 1]
-      if ops: enums[fmt_name] = ops
-    # BufFmt from "Data Format" tables
-    if 'Data Format' in title:
-      for row in rows:
-        for i in range(0, len(row) - 1, 2):
-          if row[i].isdigit() and re.match(r'^[\dA-Z_]+$', row[i + 1]) and 'INVALID' not in row[i + 1]:
-            enums.setdefault('BufFmt', {})[int(row[i])] = row[i + 1]
-  return enums
-
-def extract_ins(tables: dict[int, tuple[str, list[list[str]]]]) -> tuple[dict[str, list[tuple[str, int, int]]], dict[str, str]]:
-  """Extract formats and encodings from 'XXX Fields' tables. Returns (formats, encodings)."""
-  formats: dict[str, list[tuple[str, int, int]]] = {}
-  encodings: dict[str, str] = {}
-  for num, (title, rows) in tables.items():
-    if not (m := re.match(r'(\w+) Fields$', title)): continue
-    fmt_name = m.group(1)
-    fields = []
-    for row in rows:
-      if len(row) < 2: continue
-      if (bits := re.match(r'\[?(\d+):(\d+)\]?$', row[1])) or (bits := re.match(r'\[(\d+)\]$', row[1])):
-        field_name = row[0].lower()
-        hi, lo = int(bits.group(1)), int(bits.group(2)) if bits.lastindex >= 2 else int(bits.group(1))
-        if field_name == 'encoding' and len(row) >= 3:
-          enc_bits = None
-          if "'b" in row[2]: enc_bits = row[2].split("'b")[-1].replace('_', '')
-          elif (enc := re.search(r':\s*([01_]+)', row[2])): enc_bits = enc.group(1).replace('_', '')
-          if enc_bits:
-            # If encoding bits exceed field width, extend field to match (AMD docs sometimes have this)
-            declared_width, actual_width = hi - lo + 1, len(enc_bits)
-            if actual_width > declared_width: lo = hi - actual_width + 1
-            encodings[fmt_name] = enc_bits
-        fields.append((field_name, hi, lo))
-    if fields: formats[fmt_name] = fields
-  return formats, encodings
-
-def extract_pcode(pages: list[list[tuple[float, float, str, str]]], enums: dict[str, dict[int, str]]) -> dict[tuple[str, int], str]:
-  """Extract pseudocode for instructions. Returns {(name, opcode): pseudocode}."""
-  # Build lookup from instruction name to opcode
-  name_to_op = {name: op for ops in enums.values() for op, name in ops.items()}
-
-  # First pass: find all instruction headers across all pages
-  all_instructions: list[tuple[int, float, str, int]] = []  # (page_idx, y, name, opcode)
-  for page_idx, page in enumerate(pages):
-    by_y: dict[int, list[tuple[float, str]]] = {}
-    for x, y, t, _ in page:
-      by_y.setdefault(round(y), []).append((x, t))
-    for y, items in sorted(by_y.items(), reverse=True):
-      left = [(x, t) for x, t in items if 55 < x < 65]
-      right = [(x, t) for x, t in items if 535 < x < 550]
-      if left and right and left[0][1] in name_to_op and right[0][1].isdigit():
-        all_instructions.append((page_idx, y, left[0][1], int(right[0][1])))
-
-  # Second pass: extract pseudocode between consecutive instructions
-  pcode: dict[tuple[str, int], str] = {}
-  for i, (page_idx, y, name, opcode) in enumerate(all_instructions):
-    # Get end boundary from next instruction
-    if i + 1 < len(all_instructions):
-      next_page, next_y = all_instructions[i + 1][0], all_instructions[i + 1][1]
+def compile_pseudocode(pseudocode: str) -> str:
+  """Compile pseudocode to Python. Transforms are minimal - most syntax just works."""
+  pseudocode = re.sub(r'\bpass\b', 'pass_', pseudocode)  # 'pass' is Python keyword
+  raw_lines = pseudocode.strip().split('\n')
+  joined_lines: list[str] = []
+  for line in raw_lines:
+    line = line.strip()
+    if joined_lines and (joined_lines[-1].rstrip().endswith(('||', '&&', '(', ',')) or
+                         (joined_lines[-1].count('(') > joined_lines[-1].count(')'))):
+      joined_lines[-1] = joined_lines[-1].rstrip() + ' ' + line
    else:
-      next_page, next_y = page_idx, 0
-    # Collect F6 text from current position to next instruction (pseudocode is at x ≈ 69)
-    lines = []
-    for p in range(page_idx, next_page + 1):
-      start_y = y if p == page_idx else 800
-      end_y = next_y if p == next_page else 0
-      lines.extend((p, y2, t) for x, y2, t, f in pages[p] if f in ('/F6.0', '/F7.0') and end_y < y2 < start_y and 60 < x < 80)
-    if lines:
-      # Sort by page first, then by y descending within each page (higher y = earlier text in PDF)
-      sorted_lines = sorted(lines, key=lambda x: (x[0], -x[1]))
-      # Stop at large Y gaps (>30) - indicates section break (Notes, examples, etc)
-      filtered = [sorted_lines[0]]
-      for j in range(1, len(sorted_lines)):
-        prev_page, prev_y, _ = sorted_lines[j-1]
-        curr_page, curr_y, _ = sorted_lines[j]
-        if curr_page == prev_page and prev_y - curr_y > 30: break
-        if curr_page != prev_page and prev_y > 60 and curr_y < 730: break  # examples spilled to next page (not at very top)
-        filtered.append(sorted_lines[j])
-      pcode_lines = [t.replace('Ê', '').strip() for _, _, t in filtered]
-      if pcode_lines: pcode[(name, opcode)] = '\n'.join(pcode_lines)
-  return pcode
+      joined_lines.append(line)

-# ═══════════════════════════════════════════════════════════════════════════════
-# Write autogen files
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def write_enums(enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write enum.py file from extracted enums."""
-  lines = ["# autogenerated from AMD ISA PDF by pdf.py - do not edit", "from enum import IntEnum", ""]
-  for name, values in sorted(enums.items()):
-    suffix = "Op" if name not in ('Src', 'BufFmt') else ("Enum" if name == 'Src' else "")
-    prefix = "BUF_FMT_" if name == 'BufFmt' else ""
-    lines.append(f"class {name}{suffix}(IntEnum):")
-    for val, member in sorted(values.items()):
-      lines.append(f"  {prefix}{member} = {val}")
-    lines.append("")
-  with open(path, "w") as f:
-    f.write("\n".join(lines))
-
-def write_ins(formats: dict[str, list[tuple[str, int, int]]], encodings: dict[str, str], enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write ins.py file from extracted formats and enums."""
-  # Field types and ordering
-  def field_type(name, fmt):
-    if name == 'op' and fmt in enums: return f'Annotated[BitField, {fmt}Op]'
-    if name in ('opx', 'opy'): return 'Annotated[BitField, VOPDOp]'
-    if name == 'vdsty': return 'VDSTYEnc'
-    if name in ('vdst', 'vsrc1', 'vaddr', 'vdata', 'data', 'data0', 'data1', 'addr', 'vsrc0', 'vsrc2', 'vsrc3'): return 'VGPRField'
-    if name in ('sdst', 'sbase', 'sdata', 'srsrc', 'ssamp'): return 'SGPRField'
-    if name.startswith('ssrc') or name in ('saddr', 'soffset'): return 'SSrc'
-    if name in ('src0', 'srcx0', 'srcy0') or name.startswith('src') and name[3:].isdigit(): return 'Src'
-    if name.startswith('simm'): return 'SImm'
-    if name == 'offset' or name.startswith('imm'): return 'Imm'
-    return None
-  field_priority = ['encoding', 'op', 'opx', 'opy', 'vdst', 'vdstx', 'vdsty', 'sdst', 'vdata', 'sdata', 'addr', 'vaddr', 'data', 'data0', 'data1',
-                    'src0', 'srcx0', 'srcy0', 'vsrc0', 'ssrc0', 'src1', 'vsrc1', 'vsrcx1', 'vsrcy1', 'ssrc1', 'src2', 'vsrc2', 'src3', 'vsrc3',
-                    'saddr', 'sbase', 'srsrc', 'ssamp', 'soffset', 'offset', 'simm16', 'en', 'target', 'attr', 'attr_chan',
-                    'omod', 'neg', 'neg_hi', 'abs', 'clmp', 'opsel', 'opsel_hi', 'waitexp', 'wait_va',
-                    'dmask', 'dim', 'seg', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe', 'unrm', 'done', 'row']
-  def sort_fields(fields):
-    order = {name: i for i, name in enumerate(field_priority)}
-    return sorted(fields, key=lambda f: (order.get(f[0], 1000), f[2]))
-
-  # Generate format classes
-  lines = ["# autogenerated from AMD ISA PDF by pdf.py - do not edit", "# ruff: noqa: F401,F403",
-           "from typing import Annotated",
-           "from extra.assembly.amd.dsl import *",
-           f"from extra.assembly.amd.autogen.{arch}.enum import *", "import functools", ""]
-  for fmt_name, fields in sorted(formats.items()):
-    lines.append(f"class {fmt_name}(Inst):")
-    for name, hi, lo in sort_fields(fields):
-      bits_str = f"bits[{hi}:{lo}]" if hi != lo else f"bits[{hi}]"
-      if name == 'encoding' and fmt_name in encodings: lines.append(f"  encoding = {bits_str} == 0b{encodings[fmt_name]}")
+  lines = []
+  indent, need_pass, in_first_match_loop = 0, False, False
+  declared_arrays: dict[str, int] = {}  # Track declared arrays: name -> size
+  for line in joined_lines:
+    line = line.strip()
+    if not line or line.startswith('//'): continue
+    if line.startswith('if '):
+      lines.append('  ' * indent + f"if {_expr(line[3:].rstrip(' then'), declared_arrays)}:")
+      indent += 1
+      need_pass = True
+    elif line.startswith('elsif '):
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      lines.append('  ' * indent + f"elif {_expr(line[6:].rstrip(' then'), declared_arrays)}:")
+      indent += 1
+      need_pass = True
+    elif line == 'else':
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      lines.append('  ' * indent + "else:")
+      indent += 1
+      need_pass = True
+    elif line.startswith('endif'):
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      need_pass = False
+    elif line.startswith('endfor'):
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      need_pass, in_first_match_loop = False, False
+    elif m := re.match(r'declare\s+(\w+)\s*:\s*\d+\'[FBU]\[(\d+)\]', line):
+      # Handle array declarations: declare in : 32'F[3] or declare S : 32'B[3]
+      arr_name, arr_size = m[1], int(m[2])
+      declared_arrays[arr_name] = arr_size
+      py_name = f"{arr_name}_" if arr_name == 'in' else arr_name  # 'in' is Python keyword
+      if arr_name == 'S':
+        lines.append('  ' * indent + f"{py_name} = [S0, S1, S2]")  # Map to source registers
      else:
-        ftype = field_type(name, fmt_name)
-        lines.append(f"  {name}{f':{ftype}' if ftype else ''} = {bits_str}")
+        lines.append('  ' * indent + f"{py_name} = [Reg(0) for _ in range({arr_size})]")
+    elif line.startswith('declare '):
+      pass  # Ignore other declare statements
+    elif m := re.match(r'for (\w+) in (.+?)\s*:\s*(.+?) do', line):
+      start, end = _expr(m[2].strip(), declared_arrays), _expr(m[3].strip(), declared_arrays)
+      lines.append('  ' * indent + f"for {m[1]} in range({start}, int({end})+1):")
+      indent += 1
+      need_pass, in_first_match_loop = True, True
+    elif '=' in line and not line.startswith('=='):
+      need_pass = False
+      line = line.rstrip(';')
+      if m := re.match(r'\{\s*D1\.[ui]1\s*,\s*D0\.[ui]64\s*\}\s*=\s*(.+)', line):
+        rhs = _expr(m[1], declared_arrays)
+        lines.append('  ' * indent + f"_full = {rhs}")
+        lines.append('  ' * indent + f"D0.u64 = int(_full) & 0xffffffffffffffff")
+        lines.append('  ' * indent + f"D1 = Reg((int(_full) >> 64) & 1)")
+      elif any(op in line for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^=')):
+        for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^='):
+          if op in line:
+            lhs, rhs = line.split(op, 1)
+            lhs_s = _expr(lhs.strip(), declared_arrays)  # Transform LHS too for array access
+            lines.append('  ' * indent + f"{lhs_s} {op} {_expr(rhs.strip(), declared_arrays)}")
+            break
+      else:
+        lhs, rhs = line.split('=', 1)
+        lhs_s, rhs_s = lhs.strip(), rhs.strip()
+        lhs_t = _expr(lhs_s, declared_arrays)  # Transform LHS for array access
+        stmt = _assign(lhs_t, _expr(rhs_s, declared_arrays), declared_arrays)
+        if in_first_match_loop and rhs_s == 'i' and (lhs_s == 'tmp' or lhs_s == 'D0.i32'):
+          stmt += "; break"
+        lines.append('  ' * indent + stmt)
+  if need_pass: lines.append('  ' * indent + "pass")
+  return '\n'.join(lines)
+
+def _assign(lhs: str, rhs: str, declared_arrays: dict[str, int] | None = None) -> str:
+  # Check for array element assignment: in_[i] should not wrap in Reg()
+  if declared_arrays and re.match(r'\w+_?\[\w+\]', lhs):
+    return f"{lhs} = {rhs}"
+  if lhs in ('tmp', 'SCC', 'VCC', 'EXEC', 'D0', 'D1', 'saveexec', 'PC'):
+    return f"{lhs} = Reg({rhs})"
+  return f"{lhs} = {rhs}"
+
+def _expr(e: str, declared_arrays: dict[str, int] | None = None) -> str:
+  e = e.strip()
+  # Handle OPSEL_HI.u3[i] and OPSEL.u3[i] - bit extraction from opsel fields
+  e = re.sub(r'(OPSEL(?:_HI)?)\.u\d+\[(\w+)\]', r'((\1 >> \2) & 1)', e)
+  # Rename 'in' to 'in_' to avoid Python keyword conflict
+  e = re.sub(r'\bin\[', 'in_[', e)
+  e = e.replace('&&', ' and ').replace('||', ' or ').replace('<>', ' != ')
+  e = re.sub(r'!([^=])', r' not \1', e)
+  e = re.sub(r'\{\s*(\w+\.u32)\s*,\s*(\w+\.u32)\s*\}', r'_pack32(\1, \2)', e)
+  def pack(m):
+    hi, lo = _expr(m[1].strip(), declared_arrays), _expr(m[2].strip(), declared_arrays)
+    return f'_pack({hi}, {lo})'
+  e = re.sub(r'\{\s*([^,{}]+)\s*,\s*([^,{}]+)\s*\}', pack, e)
+  e = re.sub(r"1201'B\(2\.0\s*/\s*PI\)", "TWO_OVER_PI_1201", e)
+  e = re.sub(r"\d+'([0-9a-fA-Fx]+)[UuFf]*", r'\1', e)
+  e = re.sub(r"\d+'[FIBU]\(", "(", e)
+  e = re.sub(r'\bB\(', '(', e)
+  e = re.sub(r'([0-9a-fA-Fx])ULL\b', r'\1', e)
+  e = re.sub(r'([0-9a-fA-Fx])LL\b', r'\1', e)
+  e = re.sub(r'([0-9a-fA-Fx])U\b', r'\1', e)
+  e = re.sub(r'(\d\.?\d*)F\b', r'\1', e)
+  e = re.sub(r'(\[laneId\])\.[uib]\d+', r'\1', e)
+  e = e.replace('+INF', 'INF').replace('-INF', '(-INF)')
+  e = re.sub(r'NAN\.f\d+', 'float("nan")', e)
+  def convert_verilog_slice(m):
+    start, width = m.group(1).strip(), m.group(2).strip()
+    return f'[({start}) + ({width}) - 1 : ({start})]'
+  e = re.sub(r'\[([^:\[\]]+)\s*\+:\s*([^:\[\]]+)\]', convert_verilog_slice, e)
+  def process_brackets(s):
+    result, i = [], 0
+    while i < len(s):
+      if s[i] == '[':
+        depth, start = 1, i + 1
+        j = start
+        while j < len(s) and depth > 0:
+          if s[j] == '[': depth += 1
+          elif s[j] == ']': depth -= 1
+          j += 1
+        inner = _expr(s[start:j-1], declared_arrays)
+        result.append('[' + inner + ']')
+        i = j
+      else:
+        result.append(s[i])
+        i += 1
+    return ''.join(result)
+  e = process_brackets(e)
+  while '?' in e:
+    depth, bracket, q = 0, 0, -1
+    for i, c in enumerate(e):
+      if c == '(': depth += 1
+      elif c == ')': depth -= 1
+      elif c == '[': bracket += 1
+      elif c == ']': bracket -= 1
+      elif c == '?' and depth == 0 and bracket == 0: q = i; break
+    if q < 0: break
+    depth, bracket, col = 0, 0, -1
+    for i in range(q + 1, len(e)):
+      if e[i] == '(': depth += 1
+      elif e[i] == ')': depth -= 1
+      elif e[i] == '[': bracket += 1
+      elif e[i] == ']': bracket -= 1
+      elif e[i] == ':' and depth == 0 and bracket == 0: col = i; break
+    if col < 0: break
+    cond, t, f = e[:q].strip(), e[q+1:col].strip(), e[col+1:].strip()
+    e = f'(({t}) if ({cond}) else ({f}))'
+  return e
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# PDF PARSING WITH PAGE CACHING
+# ═══════════════════════════════════════════════════════════════════════════════
+
+class CachedPDF:
+  """PDF wrapper with page text/table caching for faster repeated access."""
+  def __init__(self, pdf):
+    self._pdf, self._text_cache, self._table_cache = pdf, {}, {}
+  def __len__(self): return len(self._pdf.pages)
+  def text(self, i):
+    if i not in self._text_cache: self._text_cache[i] = self._pdf.pages[i].extract_text() or ''
+    return self._text_cache[i]
+  def tables(self, i):
+    if i not in self._table_cache: self._table_cache[i] = [t.extract() for t in self._pdf.pages[i].find_tables()]
+    return self._table_cache[i]
+
+def _parse_bits(s: str) -> tuple[int, int] | None:
+  return (int(m.group(1)), int(m.group(2) or m.group(1))) if (m := re.match(r'\[(\d+)(?::(\d+))?\]', s)) else None
+
+def _parse_fields_table(table: list, fmt: str, enums: set[str]) -> list[tuple]:
+  fields = []
+  for row in table[1:]:
+    if not row or not row[0]: continue
+    name, bits_str = row[0].split('\n')[0].strip(), (row[1] or '').split('\n')[0].strip()
+    if not (bits := _parse_bits(bits_str)): continue
+    enc_val, hi, lo = None, bits[0], bits[1]
+    if name == 'ENCODING' and row[2]:
+      if m := re.search(r"(?:'b|Must be:\s*)([01_]+)", row[2]):
+        enc_bits = m.group(1).replace('_', '')
+        enc_val, declared_width, actual_width = int(enc_bits, 2), hi - lo + 1, len(enc_bits)
+        if actual_width > declared_width: lo = hi - actual_width + 1
+    ftype = f"{fmt}Op" if name == 'OP' and f"{fmt}Op" in enums else FIELD_TYPES.get(name.upper())
+    fields.append((name, hi, lo, enc_val, ftype))
+  return fields
+
+def _parse_single_pdf(url: str):
+  """Parse a single PDF and return (formats, enums, src_enum, doc_name, instructions)."""
+  import pdfplumber
+  from tinygrad.helpers import fetch
+
+  pdf = CachedPDF(pdfplumber.open(fetch(url)))
+  total_pages = len(pdf)
+
+  # Auto-detect document type
+  first_page = pdf.text(0)
+  is_cdna4, is_cdna3 = 'CDNA4' in first_page or 'CDNA 4' in first_page, 'CDNA3' in first_page or 'MI300' in first_page
+  is_cdna, is_rdna4 = is_cdna3 or is_cdna4, 'RDNA4' in first_page or 'RDNA 4' in first_page
+  is_rdna35, is_rdna3 = 'RDNA3.5' in first_page or 'RDNA 3.5' in first_page, 'RDNA3' in first_page and 'RDNA3.5' not in first_page
+  doc_name = "CDNA4" if is_cdna4 else "CDNA3" if is_cdna3 else "RDNA4" if is_rdna4 else "RDNA3.5" if is_rdna35 else "RDNA3" if is_rdna3 else "Unknown"
+
+  # Find Microcode Formats section (for formats/enums)
+  microcode_start = next((i for i in range(int(total_pages * 0.2), total_pages)
+                          if re.search(r'\d+\.\d+\.\d+\.\s+SOP2\b|Chapter \d+\.\s+Microcode Formats', pdf.text(i))), int(total_pages * 0.9))
+  # Find Instructions section (for pseudocode)
+  instr_start = next((i for i in range(int(total_pages * 0.1), int(total_pages * 0.5))
+                      if re.search(r'Chapter \d+\.\s+Instructions\b', pdf.text(i))), total_pages // 3)
+  instr_end = next((i for start in [int(total_pages * 0.6), int(total_pages * 0.5), instr_start]
+                    for i in range(start, min(start + 100, total_pages))
+                    if re.search(r'Chapter \d+\.\s+Microcode Formats', pdf.text(i))), total_pages)
+
+  # Parse src enum from SSRC encoding table
+  src_enum = dict(SRC_EXTRAS)
+  for i in range(microcode_start, min(microcode_start + 10, total_pages)):
+    text = pdf.text(i)
+    if 'SSRC0' in text and 'VCC_LO' in text:
+      for m in re.finditer(r'^(\d+)\s+(\S+)', text, re.M):
+        val, name = int(m.group(1)), m.group(2).rstrip('.:')
+        if name in FLOAT_MAP: src_enum[val] = FLOAT_MAP[name]
+        elif re.match(r'^[A-Z][A-Z0-9_]*$', name): src_enum[val] = name
+      break
+
+  # Parse opcode tables
+  full_text = '\n'.join(pdf.text(i) for i in range(microcode_start, min(microcode_start + 50, total_pages)))
+  enums: dict[str, dict[int, str]] = {}
+  for m in re.finditer(r'Table \d+\. (\w+) Opcodes(.*?)(?=Table \d+\.|\n\d+\.\d+\.\d+\.\s+\w+\s*\nDescription|$)', full_text, re.S):
+    if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+([A-Z][A-Z0-9_]+)', m.group(2))}:
+      enums[m.group(1) + "Op"] = ops
+  if vopd_m := re.search(r'Table \d+\. VOPD Y-Opcodes\n(.*?)(?=Table \d+\.|15\.\d)', full_text, re.S):
+    if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+(V_DUAL_\w+)', vopd_m.group(1))}:
+      enums["VOPDOp"] = ops
+  enum_names = set(enums.keys())
+
+  # Parse instruction formats
+  def is_fields_table(t): return t and len(t) > 1 and t[0] and 'Field' in str(t[0][0] or '')
+  def has_encoding(fields): return any(f[0] == 'ENCODING' for f in fields)
+  def has_header_before_fields(text): return (pos := text.find('Field Name')) != -1 and bool(re.search(r'\d+\.\d+\.\d+\.\s+\w+\s*\n', text[:pos]))
+
+  format_headers = []
+  for i in range(50):
+    if microcode_start + i >= total_pages: break
+    text = pdf.text(microcode_start + i)
+    for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n?Description', text): format_headers.append((m.group(1), i, m.start()))
+    for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n', text):
+      fmt_name = m.group(1)
+      if is_cdna and fmt_name.isupper() and len(fmt_name) >= 2: format_headers.append((fmt_name, i, m.start()))
+      elif m.start() > len(text) - 200 and 'Description' not in text[m.end():] and i + 1 < 50:
+        next_text = pdf.text(microcode_start + i + 1).lstrip()
+        if next_text.startswith('Description') or (next_text.startswith('"RDNA') and 'Description' in next_text[:200]):
+          format_headers.append((fmt_name, i, m.start()))
+
+  formats: dict[str, list] = {}
+  for fmt_name, rel_idx, header_pos in format_headers:
+    if fmt_name in formats: continue
+    page_idx = microcode_start + rel_idx
+    text = pdf.text(page_idx)
+    field_pos = text.find('Field Name', header_pos)
+    fields = None
+    for offset in range(3):
+      if page_idx + offset >= total_pages: break
+      if offset > 0 and has_header_before_fields(pdf.text(page_idx + offset)): break
+      for t in pdf.tables(page_idx + offset) if offset > 0 or field_pos > header_pos else []:
+        if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)) and has_encoding(f): fields = f; break
+      if fields: break
+    if not fields and field_pos > header_pos:
+      for t in pdf.tables(page_idx):
+        if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)): fields = f; break
+    if not fields: continue
+    field_names = {f[0] for f in fields}
+    for pg_offset in range(1, 3):
+      if page_idx + pg_offset >= total_pages or has_header_before_fields(pdf.text(page_idx + pg_offset)): break
+      for t in pdf.tables(page_idx + pg_offset):
+        if is_fields_table(t) and (extra := _parse_fields_table(t, fmt_name, enum_names)) and not has_encoding(extra):
+          for ef in extra:
+            if ef[0] not in field_names: fields.append(ef); field_names.add(ef[0])
+          break
+    formats[fmt_name] = fields
+
+  # Fix known PDF errors
+  if 'SMEM' in formats:
+    formats['SMEM'] = [(n, 13 if n == 'DLC' else 14 if n == 'GLC' else h, 13 if n == 'DLC' else 14 if n == 'GLC' else l, e, t)
+                       for n, h, l, e, t in formats['SMEM']]
+  if doc_name in ('RDNA3', 'RDNA3.5'):
+    if 'SOPPOp' in enums: assert 8 not in enums['SOPPOp']; enums['SOPPOp'][8] = 'S_WAITCNT_DEPCTR'
+    if 'DSOp' in enums:
+      for k, v in {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'}.items():
+        assert k not in enums['DSOp']; enums['DSOp'][k] = v
+    if 'FLATOp' in enums:
+      for k, v in {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'}.items():
+        assert k not in enums['FLATOp']; enums['FLATOp'][k] = v
+
+  # Extract pseudocode for instructions
+  all_text = '\n'.join(pdf.text(i) for i in range(instr_start, instr_end))
+  matches = list(INST_PATTERN.finditer(all_text))
+  raw_pseudocode: dict[tuple[str, int], str] = {}
+  for i, match in enumerate(matches):
+    name, opcode = match.group(1), int(match.group(2))
+    start, end = match.end(), matches[i + 1].start() if i + 1 < len(matches) else match.end() + 2000
+    snippet = all_text[start:end].strip()
+    if pseudocode := _extract_pseudocode(snippet): raw_pseudocode[(name, opcode)] = pseudocode
+
+  return {"formats": formats, "enums": enums, "src_enum": src_enum, "doc_name": doc_name, "pseudocode": raw_pseudocode, "is_cdna": is_cdna}
+
+def _extract_pseudocode(text: str) -> str | None:
+  """Extract pseudocode from an instruction description snippet."""
+  lines, result, depth, in_lambda = text.split('\n'), [], 0, 0
+  for line in lines:
+    s = line.strip()
+    if not s or re.match(r'^\d+ of \d+$', s) or re.match(r'^\d+\.\d+\..*Instructions', s): continue
+    if s.startswith(('Notes', 'Functional examples')): break
+    if s.startswith(('"RDNA', 'AMD ', 'CDNA')): continue
+    if '= lambda(' in s: in_lambda += 1; continue
+    if in_lambda > 0:
+      if s.endswith(');'): in_lambda -= 1
+      continue
+    if s.startswith('if '): depth += 1
+    elif s.startswith('endif'): depth = max(0, depth - 1)
+    if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue
+    if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue
+    is_code = (any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =',
+                                    'D0[', 'D1[', 'S0[', 'S1[', 'S2[', 'MEM[', 'RETURN_DATA', 'DATA.', 'DATA0', 'DATA1', 'ADDR']) or
+               s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or
+               re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s))
+    if is_code: result.append(s)
+  return '\n'.join(result) if result else None
+
+def _merge_results(results: list[dict]) -> dict:
+  """Merge multiple PDF parse results into a superset."""
+  merged = {"formats": {}, "enums": {}, "src_enum": dict(SRC_EXTRAS), "doc_names": [], "pseudocode": {}, "is_cdna": False}
+  for r in results:
+    merged["doc_names"].append(r["doc_name"])
+    merged["is_cdna"] = merged["is_cdna"] or r["is_cdna"]
+    for val, name in r["src_enum"].items():
+      if val in merged["src_enum"]: assert merged["src_enum"][val] == name
+      else: merged["src_enum"][val] = name
+    for enum_name, ops in r["enums"].items():
+      if enum_name not in merged["enums"]: merged["enums"][enum_name] = {}
+      for val, name in ops.items():
+        if val in merged["enums"][enum_name]: assert merged["enums"][enum_name][val] == name
+        else: merged["enums"][enum_name][val] = name
+    for fmt_name, fields in r["formats"].items():
+      if fmt_name not in merged["formats"]: merged["formats"][fmt_name] = list(fields)
+      else:
+        existing = {f[0]: (f[1], f[2]) for f in merged["formats"][fmt_name]}
+        for f in fields:
+          if f[0] in existing: assert existing[f[0]] == (f[1], f[2])
+          else: merged["formats"][fmt_name].append(f)
+    for key, pc in r["pseudocode"].items():
+      if key not in merged["pseudocode"]: merged["pseudocode"][key] = pc
+  return merged
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# CODE GENERATION
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _generate_enum_py(enums, src_enum, doc_name) -> str:
+  """Generate enum.py content (just enums, no dsl.py dependency)."""
+  def enum_lines(name, items): return [f"class {name}(IntEnum):"] + [f"  {n} = {v}" for v, n in sorted(items.items())] + [""]
+  lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit", "from enum import IntEnum", ""]
+  lines += enum_lines("SrcEnum", src_enum) + sum([enum_lines(n, ops) for n, ops in sorted(enums.items())], [])
+  return '\n'.join(lines)
+
+def _generate_ins_py(formats, enums, src_enum, doc_name) -> str:
+  """Generate ins.py content (instruction formats and helpers, imports dsl.py and enum.py)."""
+  def field_key(f, order): return order.index(f[0].lower()) if f[0].lower() in order else 1000
+  lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit",
+           "# ruff: noqa: F401,F403", "from typing import Annotated",
+           "from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField",
+           "from extra.assembly.amd.autogen.{arch}.enum import *",
+           "import functools", ""]
+  format_defaults = {'VOP3P': {'opsel_hi': 3, 'opsel_hi2': 1}}
+  lines.append("# instruction formats")
+  for fmt_name, fields in sorted(formats.items()):
+    base = "Inst64" if max(f[1] for f in fields) > 31 or fmt_name == 'VOP3SD' else "Inst32"
+    order = FIELD_ORDER.get(fmt_name, [])
+    lines.append(f"class {fmt_name}({base}):")
+    if enc := next((f for f in fields if f[0] == 'ENCODING'), None):
+      lines.append(f"  encoding = bits[{enc[1]}:{enc[2]}] == 0b{enc[3]:b}" if enc[1] != enc[2] else f"  encoding = bits[{enc[1]}] == {enc[3]}")
+    if defaults := format_defaults.get(fmt_name): lines.append(f"  _defaults = {defaults}")
+    for name, hi, lo, _, ftype in sorted([f for f in fields if f[0] != 'ENCODING'], key=lambda f: field_key(f, order)):
+      ann = f":Annotated[BitField, {ftype}]" if ftype and ftype.endswith('Op') else f":{ftype}" if ftype else ""
+      lines.append(f"  {name.lower()}{ann} = bits[{hi}]" if hi == lo else f"  {name.lower()}{ann} = bits[{hi}:{lo}]")
    lines.append("")
-
-  # Generate instruction helpers
  lines.append("# instruction helpers")
-  for fmt_name, ops in sorted(enums.items()):
-    seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt_name, "")
-    tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt_name, f"{fmt_name}, {fmt_name}Op")
-    suffix = "_e32" if fmt_name in ("VOP1", "VOP2", "VOPC") else "_e64" if fmt_name == "VOP3" and len(ops) > 0 else ""
-    if fmt_name in formats or fmt_name in ("GLOBAL", "SCRATCH"):
-      for op_val, name in sorted(ops.items()):
-        fn_suffix = suffix if fmt_name != "VOP3" or op_val < 512 else ""
-        lines.append(f"{name.lower()}{fn_suffix} = functools.partial({tgt}.{name}{seg})")
+  for cls_name, ops in sorted(enums.items()):
+    fmt = cls_name[:-2]
+    for op_val, name in sorted(ops.items()):
+      seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt, "")
+      tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt, f"{fmt}, {cls_name}")
+      if fmt in formats or fmt in ("GLOBAL", "SCRATCH"):
+        suffix = "_e32" if fmt in ("VOP1", "VOP2", "VOPC") else "_e64" if fmt == "VOP3" and op_val < 512 else ""
+        if name in ('V_FMAMK_F32', 'V_FMAMK_F16'):
+          lines.append(f"def {name.lower()}{suffix}(vdst, src0, K, vsrc1): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
+        elif name in ('V_FMAAK_F32', 'V_FMAAK_F16'):
+          lines.append(f"def {name.lower()}{suffix}(vdst, src0, vsrc1, K): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
+        else: lines.append(f"{name.lower()}{suffix} = functools.partial({tgt}.{name}{seg})")
+  src_names = {name for _, name in src_enum.items()}
+  lines += [""] + [f"{name} = SrcEnum.{name}" for _, name in sorted(src_enum.items()) if name not in {'DPP8', 'DPP16'}]
+  if "NULL" in src_names: lines.append("OFF = NULL\n")
+  return '\n'.join(lines)

-  with open(path, "w") as f:
-    f.write("\n".join(lines))
+def _generate_gen_pcode_py(enums, pseudocode, arch) -> str:
+  """Generate gen_pcode.py content (compiled pseudocode functions)."""
+  # Get op enums for this arch (import from .ins which re-exports from .enum)
+  import importlib
+  autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}.ins")
+  OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp', 'DSOp'] if hasattr(autogen, name)]

-def write_pcode(pcode: dict[tuple[str, int], str], enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write str_pcode.py file from extracted pseudocode."""
-  # Group pseudocode by enum class
-  by_enum: dict[str, list[tuple[str, int, str]]] = {}
-  for fmt_name, ops in enums.items():
-    for opcode, name in ops.items():
-      if (name, opcode) in pcode: by_enum.setdefault(f"{fmt_name}Op", []).append((name, opcode, pcode[(name, opcode)]))
-  # Generate file
-  enum_names = sorted(by_enum.keys())
-  lines = [f"# autogenerated by pdf.py - do not edit", f"# to regenerate: python -m extra.assembly.amd.pdf",
-           "# ruff: noqa: E501", f"from extra.assembly.amd.autogen.{arch}.enum import {', '.join(enum_names)}", ""]
-  for enum_name in enum_names:
-    lines.append(f"{enum_name}_PCODE = {{")
-    for name, opcode, code in sorted(by_enum[enum_name], key=lambda x: x[1]):
-      lines.append(f"  {enum_name}.{name}: {code!r},")
-    lines.append("}\n")
-  lines.append(f"PSEUDOCODE_STRINGS = {{{', '.join(f'{e}: {e}_PCODE' for e in enum_names)}}}")
-  with open(path, "w") as f:
-    f.write("\n".join(lines))
+  # Build defined ops mapping
+  defined_ops: dict[tuple, list] = {}
+  for enum_cls in OP_ENUMS:
+    for op in enum_cls:
+      if op.name.startswith(('S_', 'V_', 'DS_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op))
+
+  enum_names = [e.__name__ for e in OP_ENUMS]
+  lines = [f'''# autogenerated by pdf.py - do not edit
+# to regenerate: python -m extra.assembly.amd.pdf --arch {arch}
+# ruff: noqa: E501,F405,F403
+# mypy: ignore-errors
+from extra.assembly.amd.autogen.{arch}.enum import {", ".join(enum_names)}
+from extra.assembly.amd.pcode import *
+''']
+
+  instructions: dict = {cls: {} for cls in OP_ENUMS}
+  for key, pc in pseudocode.items():
+    if key in defined_ops:
+      for enum_cls, enum_val in defined_ops[key]: instructions[enum_cls][enum_val] = pc
+
+  for enum_cls in OP_ENUMS:
+    cls_name = enum_cls.__name__
+    if not instructions.get(enum_cls): continue
+    fn_entries = []
+    for op, pc in instructions[enum_cls].items():
+      if any(p in pc for p in UNSUPPORTED): continue
+      try:
+        code = compile_pseudocode(pc)
+        code = _apply_pseudocode_fixes(op, code)
+        fn_name, fn_code = _generate_function(cls_name, op, pc, code)
+        lines.append(fn_code)
+        fn_entries.append((op, fn_name))
+      except Exception as e: print(f"  Warning: Failed to compile {op.name}: {e}")
+    if fn_entries:
+      lines.append(f'{cls_name}_FUNCTIONS = {{')
+      for op, fn_name in fn_entries: lines.append(f"  {cls_name}.{op.name}: {fn_name},")
+      lines.append('}\n')
+
+  # Add V_WRITELANE_B32 if VOP3Op exists
+  if 'VOP3Op' in enum_names:
+    lines.append('''
+# V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode)
+def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0):
+  wr_lane = s1 & 0x1f
+  return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)}
+VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32
+''')
+
+  lines.append('COMPILED_FUNCTIONS = {')
+  for enum_cls in OP_ENUMS:
+    if instructions.get(enum_cls): lines.append(f'  {enum_cls.__name__}: {enum_cls.__name__}_FUNCTIONS,')
+  lines.append('}\n\ndef get_compiled_functions(): return COMPILED_FUNCTIONS')
+  return '\n'.join(lines)
+
+def _apply_pseudocode_fixes(op, code: str) -> str:
+  """Apply known fixes for PDF pseudocode bugs."""
+  if op.name == 'V_DIV_FMAS_F32':
+    code = code.replace('D0.f32 = 2.0 ** 32 * fma(S0.f32, S1.f32, S2.f32)',
+                        'D0.f32 = (2.0 ** 64 if exponent(S2.f32) > 127 else 2.0 ** -64) * fma(S0.f32, S1.f32, S2.f32)')
+  if op.name == 'V_DIV_FMAS_F64':
+    code = code.replace('D0.f64 = 2.0 ** 64 * fma(S0.f64, S1.f64, S2.f64)',
+                        'D0.f64 = (2.0 ** 128 if exponent(S2.f64) > 1023 else 2.0 ** -128) * fma(S0.f64, S1.f64, S2.f64)')
+  if op.name == 'V_DIV_SCALE_F32':
+    code = code.replace('D0.f32 = float("nan")', 'VCC = Reg(0x1); D0.f32 = float("nan")')
+    code = code.replace('elif S1.f32 == DENORM.f32:\n  D0.f32 = ldexp(S0.f32, 64)', 'elif False:\n  pass')
+    code += '\nif S1.f32 == DENORM.f32:\n  D0.f32 = float("nan")'
+    code = code.replace('elif exponent(S2.f32) <= 23:\n  D0.f32 = ldexp(S0.f32, 64)', 'elif exponent(S2.f32) <= 23:\n  VCC = Reg(0x1); D0.f32 = ldexp(S0.f32, 64)')
+    code = code.replace('elif S2.f32 / S1.f32 == DENORM.f32:\n  VCC = Reg(0x1)\n  if S0.f32 == S2.f32:\n    D0.f32 = ldexp(S0.f32, 64)', 'elif S2.f32 / S1.f32 == DENORM.f32:\n  VCC = Reg(0x1)')
+  if op.name == 'V_DIV_SCALE_F64':
+    code = code.replace('D0.f64 = float("nan")', 'VCC = Reg(0x1); D0.f64 = float("nan")')
+    code = code.replace('elif S1.f64 == DENORM.f64:\n  D0.f64 = ldexp(S0.f64, 128)', 'elif False:\n  pass')
+    code += '\nif S1.f64 == DENORM.f64:\n  D0.f64 = float("nan")'
+    code = code.replace('elif exponent(S2.f64) <= 52:\n  D0.f64 = ldexp(S0.f64, 128)', 'elif exponent(S2.f64) <= 52:\n  VCC = Reg(0x1); D0.f64 = ldexp(S0.f64, 128)')
+    code = code.replace('elif S2.f64 / S1.f64 == DENORM.f64:\n  VCC = Reg(0x1)\n  if S0.f64 == S2.f64:\n    D0.f64 = ldexp(S0.f64, 128)', 'elif S2.f64 / S1.f64 == DENORM.f64:\n  VCC = Reg(0x1)')
+  if op.name == 'V_DIV_FIXUP_F32':
+    code = code.replace('D0.f32 = ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))',
+                        'D0.f32 = ((-OVERFLOW_F32) if (sign_out) else (OVERFLOW_F32)) if isNAN(S0.f32) else ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))')
+  if op.name == 'V_DIV_FIXUP_F64':
+    code = code.replace('D0.f64 = ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))',
+                        'D0.f64 = ((-OVERFLOW_F64) if (sign_out) else (OVERFLOW_F64)) if isNAN(S0.f64) else ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))')
+  if op.name == 'V_TRIG_PREOP_F64':
+    code = code.replace('result = F((TWO_OVER_PI_1201[1200 : 0] << shift.u32) & 0x1fffffffffffff)',
+                        'result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff)')
+  return code
+
+def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]:
+  """Generate a single compiled pseudocode function."""
+  has_d1 = '{ D1' in pc
+  is_cmpx = (cls_name in ('VOPCOp', 'VOP3Op')) and 'EXEC.u64[laneId]' in pc
+  is_div_scale = 'DIV_SCALE' in op.name
+  has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale)
+  has_opsel = 'OPSEL' in pc  # FMA_MIX and similar instructions need OPSEL/OPSEL_HI
+  combined = code + pc
+
+  fn_name = f"_{cls_name}_{op.name}"
+  # Function accepts Reg objects directly (uppercase names), laneId is passed directly as int
+  params = "S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None"
+  if has_opsel: params += ", OPSEL=0, OPSEL_HI=0"
+  lines = [f"def {fn_name}({params}):"]
+
+  # Registers that need special handling (not passed directly)
+  # Only init if used but not first assigned as `name = Reg(...)` in the compiled code
+  def needs_init(name): return name in combined and not re.search(rf'^\s*{name}\s*=\s*Reg\(', code, re.MULTILINE)
+  special_regs = [('D1', 'Reg(0)'), ('SIMM16', 'Reg(literal)'), ('SIMM32', 'Reg(literal)'),
+                  ('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)')]
+  if needs_init('tmp'): special_regs.insert(0, ('tmp', 'Reg(0)'))
+  if needs_init('saveexec'): special_regs.insert(0, ('saveexec', 'Reg(EXEC._val)'))
+  used = {name for name, _ in special_regs if name in combined}
+
+  # Detect which registers are modified (not just read) - look for assignments
+  modifies_d0 = is_div_scale or bool(re.search(r'\bD0\b[.\[]', combined))
+  modifies_exec = is_cmpx or bool(re.search(r'EXEC\.(u32|u64|b32|b64)\s*=', combined))
+  modifies_vcc = has_sdst or bool(re.search(r'VCC\.(u32|u64|b32|b64)\s*=|VCC\.u64\[laneId\]\s*=', combined))
+  modifies_scc = bool(re.search(r'\bSCC\s*=', combined))
+  modifies_pc = bool(re.search(r'\bPC\s*=', combined))
+
+  # Build init code for special registers
+  init_lines = []
+  if is_div_scale: init_lines.append("  D0 = Reg(S0._val)")
+  for name, init in special_regs:
+    if name in used: init_lines.append(f"  {name} = {init}")
+  if 'EXEC_LO' in code: init_lines.append("  EXEC_LO = SliceProxy(EXEC, 31, 0)")
+  if 'EXEC_HI' in code: init_lines.append("  EXEC_HI = SliceProxy(EXEC, 63, 32)")
+  if 'VCCZ' in code and not re.search(r'^\s*VCCZ\s*=', code, re.MULTILINE): init_lines.append("  VCCZ = Reg(1 if VCC._val == 0 else 0)")
+  if 'EXECZ' in code and not re.search(r'^\s*EXECZ\s*=', code, re.MULTILINE): init_lines.append("  EXECZ = Reg(1 if EXEC._val == 0 else 0)")
+  code_lines = [line for line in code.split('\n') if line.strip()]
+  if init_lines:
+    lines.extend(init_lines)
+    if code_lines: lines.append("  # --- compiled pseudocode ---")
+  for line in code_lines:
+    lines.append(f"  {line}")
+
+  # Build result dict - only include registers that are modified
+  result_items = []
+  if modifies_d0: result_items.append("'D0': D0")
+  if modifies_scc: result_items.append("'SCC': SCC")
+  if modifies_vcc: result_items.append("'VCC': VCC")
+  if modifies_exec: result_items.append("'EXEC': EXEC")
+  if has_d1: result_items.append("'D1': D1")
+  if modifies_pc: result_items.append("'PC': PC")
+  lines.append(f"  return {{{', '.join(result_items)}}}\n")
+  return fn_name, '\n'.join(lines)
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# MAIN GENERATION
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def generate_arch(arch: str) -> dict:
+  """Generate enum.py, ins.py and gen_pcode.py for a single architecture."""
+  urls = PDF_URLS[arch]
+  if isinstance(urls, str): urls = [urls]
+
+  print(f"\n{'='*60}\nGenerating {arch}...")
+  print(f"Parsing {len(urls)} PDF(s)...")
+  results = [_parse_single_pdf(url) for url in urls]
+  merged = _merge_results(results) if len(results) > 1 else results[0]
+  doc_name = "+".join(merged["doc_names"]) if len(results) > 1 else merged["doc_name"]
+
+  base_path = Path(f"extra/assembly/amd/autogen/{arch}")
+  base_path.mkdir(parents=True, exist_ok=True)
+  (base_path / "__init__.py").touch()
+
+  # Write enum.py (enums only, no dsl.py dependency)
+  enum_path = base_path / "enum.py"
+  enum_content = _generate_enum_py(merged["enums"], merged["src_enum"], doc_name)
+  enum_path.write_text(enum_content)
+  print(f"Generated {enum_path}: SrcEnum ({len(merged['src_enum'])}) + {len(merged['enums'])} enums")
+
+  # Write ins.py (instruction formats and helpers, imports dsl.py and enum.py)
+  ins_path = base_path / "ins.py"
+  ins_content = _generate_ins_py(merged["formats"], merged["enums"], merged["src_enum"], doc_name).replace("{arch}", arch)
+  ins_path.write_text(ins_content)
+  print(f"Generated {ins_path}: {len(merged['formats'])} formats")
+
+  # Write gen_pcode.py (needs enum.py to exist first for imports)
+  pcode_path = base_path / "gen_pcode.py"
+  pcode_content = _generate_gen_pcode_py(merged["enums"], merged["pseudocode"], arch)
+  pcode_path.write_text(pcode_content)
+  print(f"Generated {pcode_path}: {len(merged['pseudocode'])} instructions")
+
+  return merged
+
+def _generate_arch_wrapper(arch: str):
+  """Wrapper for multiprocessing - returns arch name for ordering."""
+  generate_arch(arch)
+  return arch
+
+def generate_all():
+  """Generate all architectures in parallel."""
+  with ProcessPoolExecutor() as executor:
+    list(executor.map(_generate_arch_wrapper, PDF_URLS.keys()))

 if __name__ == "__main__":
-  import pathlib
-  for arch, url in PDF_URLS.items():
-    print(f"Processing {arch}...")
-    pages = extract(url)
-    tables = extract_tables(pages)
-    enums = extract_enums(tables)
-    formats, encodings = extract_ins(tables)
-    pcode = extract_pcode(pages, enums)
-    # Fix known PDF errors
-    if arch == 'rdna3':
-      fixes = {'SOPP': {8: 'S_WAITCNT_DEPCTR', 58: 'S_TTRACEDATA', 59: 'S_TTRACEDATA_IMM'},
-               'SOPK': {22: 'S_SUBVECTOR_LOOP_BEGIN', 23: 'S_SUBVECTOR_LOOP_END'},
-               'SMEM': {34: 'S_ATC_PROBE', 35: 'S_ATC_PROBE_BUFFER'},
-               'DS': {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'},
-               'FLAT': {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'}}
-      for fmt, ops in fixes.items(): enums[fmt] = merge_dicts([enums[fmt], ops])
-    if arch == 'rdna4':
-      fixes = {'SMEM': {34: 'S_ATC_PROBE', 35: 'S_ATC_PROBE_BUFFER'},
-               'SOP1': {81: 'S_BARRIER_INIT', 82: 'S_BARRIER_JOIN'},
-               'SOPP': {21: 'S_BARRIER_LEAVE', 58: 'S_TTRACEDATA', 59: 'S_TTRACEDATA_IMM'}}
-      for fmt, ops in fixes.items(): enums[fmt] = merge_dicts([enums[fmt], ops])
-    if arch in ('rdna3', 'rdna4'):
-      # RDNA SMEM: PDF says DLC=[14], GLC=[16] but hardware uses DLC=[13], GLC=[14]
-      if 'SMEM' in formats:
-        formats['SMEM'] = [(n, 13 if n == 'dlc' else 14 if n == 'glc' else h, 13 if n == 'dlc' else 14 if n == 'glc' else l)
-                           for n, h, l in formats['SMEM']]
-    if arch == 'cdna':
-      # CDNA DS: PDF is missing the GDS field (bit 16)
-      if 'DS' in formats and not any(n == 'gds' for n, _, _ in formats['DS']):
-        formats['DS'].append(('gds', 16, 16))
-      # CDNA DPP/SDWA: PDF only documents modifier fields (bits[63:32]), need to add VOP overlay fields (bits[31:0])
-      vop_overlay = [('encoding', 8, 0), ('vop_op', 16, 9), ('vdst', 24, 17), ('vop2_op', 31, 25)]
-      if 'DPP' in formats and not any(n == 'encoding' for n, _, _ in formats['DPP']):
-        formats['DPP'] = vop_overlay + [('bc' if n == 'bound_ctrl' else n, h, l) for n, h, l in formats['DPP']]
-        encodings['DPP'] = '11111010'
-      if 'SDWA' in formats and not any(n == 'encoding' for n, _, _ in formats['SDWA']):
-        formats['SDWA'] = vop_overlay + [(n, h, l) for n, h, l in formats['SDWA']]
-        encodings['SDWA'] = '11111001'
-    base = pathlib.Path(__file__).parent / "autogen" / arch
-    write_enums(enums, arch, base / "enum.py")
-    write_ins(formats, encodings, enums, arch, base / "ins.py")
-    write_pcode(pcode, enums, arch, base / "str_pcode.py")
-    print(f"  {len(tables)} tables, {len(pcode)} pcode -> {base}")
+  import argparse
+  parser = argparse.ArgumentParser(description="Generate AMD ISA autogen files from PDF documentation")
+  parser.add_argument("--arch", choices=list(PDF_URLS.keys()) + ["all"], default="rdna3")
+  args = parser.parse_args()
+  if args.arch == "all": generate_all()
+  else: generate_arch(args.arch)
@@ -1,381 +0,0 @@
-"""SQTT (SQ Thread Trace) packet encoder and decoder for AMD GPUs.
-
-This module provides encoding and decoding of raw SQTT byte streams.
-The format is nibble-based with variable-width packets determined by a state machine.
-Uses BitField infrastructure from dsl.py, similar to GPU instruction encoding.
-"""
-from __future__ import annotations
-from enum import IntEnum
-from typing import get_type_hints
-from extra.assembly.amd.dsl import BitField, bits
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# FIELD ENUMS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class MemSrc(IntEnum):
-  LDS = 0
-  LDS_ALT = 1
-  VMEM = 2
-  VMEM_ALT = 3
-
-class AluSrc(IntEnum):
-  NONE = 0
-  SALU = 1
-  VALU = 2
-  VALU_ALT = 3
-
-class InstOp(IntEnum):
-  """SQTT instruction operation types.
-
-  Memory ops appear in two ranges depending on which SIMD executes them:
-  - 0x1x-0x2x range: ops on traced SIMD
-  - 0x5x range: ops on other SIMD (OTHER_ prefix)
-
-  GLOBAL memory ops encoding depends on addressing mode AND size:
-  - Loads: 0x21 (saddr=SGPR) or 0x22 (saddr=NULL), all sizes same
-  - Stores: base + size_offset, where VADDR is shifted +1 from SADDR
-    SADDR: 0x24(32) 0x25(64) 0x26(96) 0x27(128)
-    VADDR: 0x25(32) 0x26(64) 0x27(96) 0x28(128)
-
-  OTHER_ range follows same pattern but values overlap differently.
-  """
-  SALU = 0x0
-  SMEM = 0x1
-  JUMP = 0x3              # branch taken
-  JUMP_NO = 0x4           # branch not taken
-  MESSAGE = 0x9
-  VALU_TRANS = 0xb        # transcendental: exp, log, rcp, sqrt, sin, cos
-  VALU_64_SHIFT = 0xd     # 64-bit shifts: lshl, lshr, ashr
-  VALU_MAD64 = 0xe        # 64-bit multiply-add
-  VALU_64 = 0xf           # 64-bit: add, mul, fma, rcp, sqrt, rounding, frexp, div helpers
-  VINTERP = 0x12          # interpolation: v_interp_p10_f32, v_interp_p2_f32
-  BARRIER = 0x13
-
-  # FLAT memory ops on traced SIMD (0x1x range)
-  FLAT_LOAD = 0x1c
-  FLAT_STORE = 0x1d
-  FLAT_STORE_64 = 0x1e
-  FLAT_STORE_96 = 0x1f
-  FLAT_STORE_128 = 0x20
-
-  # GLOBAL memory ops on traced SIMD (0x2x range)
-  GLOBAL_LOAD = 0x21             # saddr=SGPR, all sizes
-  GLOBAL_LOAD_VADDR = 0x22       # saddr=NULL, all sizes
-  GLOBAL_STORE = 0x24            # saddr=SGPR, 32-bit
-  GLOBAL_STORE_64 = 0x25         # saddr=SGPR 64 or saddr=NULL 32
-  GLOBAL_STORE_96 = 0x26         # saddr=SGPR 96 or saddr=NULL 64
-  GLOBAL_STORE_128 = 0x27        # saddr=SGPR 128 or saddr=NULL 96
-  GLOBAL_STORE_VADDR_128 = 0x28  # saddr=NULL, 128-bit
-
-  # LDS ops on traced SIMD
-  LDS_LOAD = 0x29
-  LDS_STORE = 0x2b
-  LDS_STORE_64 = 0x2c
-  LDS_STORE_128 = 0x2e
-
-  # Memory ops on other SIMD (0x5x range)
-  OTHER_LDS_LOAD = 0x50
-  OTHER_LDS_STORE = 0x51
-  OTHER_LDS_STORE_64 = 0x52
-  OTHER_LDS_STORE_128 = 0x54
-  OTHER_FLAT_LOAD = 0x55
-  OTHER_FLAT_STORE = 0x56
-  OTHER_FLAT_STORE_64 = 0x57
-  OTHER_FLAT_STORE_96 = 0x58
-  OTHER_FLAT_STORE_128 = 0x59
-  OTHER_GLOBAL_LOAD = 0x5a             # saddr=SGPR, all sizes
-  OTHER_GLOBAL_LOAD_VADDR = 0x5b       # saddr=NULL or saddr=SGPR store 32
-  OTHER_GLOBAL_STORE_64 = 0x5c         # saddr=SGPR 64 or saddr=NULL 32
-  OTHER_GLOBAL_STORE_96 = 0x5d         # saddr=SGPR 96 or saddr=NULL 64
-  OTHER_GLOBAL_STORE_128 = 0x5e        # saddr=SGPR 128 or saddr=NULL 96
-  OTHER_GLOBAL_STORE_VADDR_128 = 0x5f  # saddr=NULL, 128-bit
-
-  # EXEC-modifying ops (0x7x range)
-  SALU_SAVEEXEC = 0x72    # s_*_saveexec_b32/b64
-  VALU_CMPX = 0x73        # v_cmpx_*
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# PACKET TYPE BASE CLASS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class PacketType:
-  """Base class for SQTT packet types."""
-  _encoding: tuple[BitField, int] | None = None
-  _field_types: dict[str, type] = {}
-  _values: dict[str, int]
-  _raw: int
-  _time: int
-
-  def __init_subclass__(cls, **kwargs):
-    super().__init_subclass__(**kwargs)
-    if 'encoding' in cls.__dict__ and isinstance(cls.__dict__['encoding'], tuple):
-      cls._encoding = cls.__dict__['encoding']
-    # Cache field type annotations for enum conversion
-    try: cls._field_types = {k: v for k, v in get_type_hints(cls).items() if isinstance(v, type) and issubclass(v, IntEnum)}
-    except Exception: cls._field_types = {}
-    # Cache fields and precompute extraction info: (name, lo, mask, enum_type)
-    cls._fields = {k: v for k, v in cls.__dict__.items() if isinstance(v, BitField) and k != 'encoding'}
-    cls._extract_info = [(name, bf.lo, bf.mask(), cls._field_types.get(name)) for name, bf in cls._fields.items()]
-    cls._size_nibbles = ((max((f.hi for f in cls._fields.values()), default=0) + 4) // 4)
-
-  @classmethod
-  def from_raw(cls, raw: int, time: int = 0):
-    inst = object.__new__(cls)
-    inst._raw, inst._time, inst._values = raw, time, {}
-    for name, lo, mask, enum_type in cls._extract_info:
-      val = (raw >> lo) & mask
-      if enum_type is not None:
-        try: val = enum_type(val)
-        except ValueError: pass
-      inst._values[name] = val
-    return inst
-
-  def __getattr__(self, name: str):
-    if name.startswith('_'): raise AttributeError(name)
-    return self._values.get(name, 0)
-
-  def __repr__(self) -> str:
-    fields_str = ", ".join(f"{k}={v}" for k, v in self._values.items() if not k.startswith('_'))
-    return f"{self.__class__.__name__}({fields_str})"
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# PACKET TYPE DEFINITIONS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class VALUINST(PacketType):  # exclude: 1 << 2
-  encoding = bits[2:0] == 0b011
-  delta = bits[5:3]
-  flag = bits[6:6]
-  wave = bits[11:7]
-
-class VMEMEXEC(PacketType):  # exclude: 1 << 0
-  encoding = bits[3:0] == 0b1111
-  delta = bits[5:4]
-  src: MemSrc = bits[7:6]
-
-class ALUEXEC(PacketType):  # exclude: 1 << 1
-  encoding = bits[3:0] == 0b1110
-  delta = bits[5:4]
-  src: AluSrc = bits[7:6]
-
-class IMMEDIATE(PacketType):  # exclude: 1 << 5
-  encoding = bits[3:0] == 0b1101
-  delta = bits[6:4]
-  wave = bits[11:7]
-
-class IMMEDIATE_MASK(PacketType):  # exclude: 1 << 5
-  encoding = bits[4:0] == 0b00100
-  delta = bits[7:5]
-  mask = bits[23:8]
-
-class WAVERDY(PacketType):  # exclude: 1 << 3
-  encoding = bits[4:0] == 0b10100
-  delta = bits[7:5]
-  mask = bits[23:8]
-
-class TS_DELTA_S8_W3(PacketType):
-  encoding = bits[6:0] == 0b0100001
-  delta = bits[10:8]
-  _padding = bits[63:11]
-
-class WAVEEND(PacketType):  # exclude: 1 << 4
-  encoding = bits[4:0] == 0b10101
-  delta = bits[7:5]
-  flag7 = bits[8:8]
-  simd = bits[10:9]
-  cu_lo = bits[13:11]
-  wave = bits[19:15]
-  @property
-  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)
-
-class WAVESTART(PacketType):  # exclude: 1 << 4
-  encoding = bits[4:0] == 0b01100
-  delta = bits[6:5]
-  flag7 = bits[7:7]
-  simd = bits[9:8]
-  cu_lo = bits[12:10]
-  wave = bits[17:13]
-  id7 = bits[31:18]
-  @property
-  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)
-
-class TS_DELTA_S5_W2(PacketType):
-  encoding = bits[4:0] == 0b11100
-  delta = bits[6:5]
-  _padding = bits[47:7]
-
-class WAVEALLOC(PacketType):  # exclude: 1 << 10
-  encoding = bits[4:0] == 0b00101
-  delta = bits[7:5]
-  _padding = bits[19:8]
-
-class TS_DELTA_S5_W3(PacketType):
-  encoding = bits[4:0] == 0b00110
-  delta = bits[7:5]
-  _padding = bits[51:8]
-
-class PERF(PacketType):  # exclude: 1 << 11
-  encoding = bits[4:0] == 0b10110
-  delta = bits[7:5]
-  arg = bits[27:8]
-
-class TS_DELTA_SHORT(PacketType):
-  encoding = bits[3:0] == 0b1000
-  delta = bits[7:4]
-
-class NOP(PacketType):
-  encoding = bits[3:0] == 0b0000
-  delta = None  # type: ignore
-  _padding = bits[3:0]
-
-class TS_WAVE_STATE(PacketType):
-  encoding = bits[6:0] == 0b1010001
-  delta = bits[15:7]
-  coarse = bits[23:16]
-  @property
-  def wave_interest(self) -> bool: return bool(self.coarse & 1)
-  @property
-  def terminate_all(self) -> bool: return bool(self.coarse & 8)
-
-class EVENT(PacketType):  # exclude: 1 << 7
-  encoding = bits[7:0] == 0b01100001
-  delta = bits[10:8]
-  event = bits[23:11]
-
-class EVENT_BIG(PacketType):
-  encoding = bits[7:0] == 0b11100001
-  delta = bits[10:8]
-  event = bits[31:11]
-
-class REG(PacketType):
-  encoding = bits[3:0] == 0b1001
-  delta = bits[6:4]
-  slot = bits[9:7]
-  hi_byte = bits[15:8]
-  subop = bits[31:16]
-  val32 = bits[63:32]
-  @property
-  def is_config(self) -> bool: return bool(self.hi_byte & 0x80)
-
-class SNAPSHOT(PacketType):
-  encoding = bits[6:0] == 0b1110001
-  delta = bits[9:7]
-  snap = bits[63:10]
-
-class TS_DELTA_OR_MARK(PacketType):
-  encoding = bits[6:0] == 0b0000001
-  delta = bits[47:12]
-  bit8 = bits[8:8]
-  bit9 = bits[9:9]
-  @property
-  def is_marker(self) -> bool: return bool(self.bit9 and not self.bit8)
-
-class LAYOUT_HEADER(PacketType):
-  encoding = bits[6:0] == 0b0010001
-  delta = None  # type: ignore
-  layout = bits[12:7]
-  simd = bits[14:13]
-  group = bits[17:15]
-  sel_a = bits[31:28]
-  sel_b = bits[36:33]
-  flag4 = bits[59:59]
-  _padding = bits[63:60]
-
-class INST(PacketType):
-  encoding = bits[2:0] == 0b010
-  delta = bits[6:4]
-  flag1 = bits[3:3]
-  flag2 = bits[7:7]
-  wave = bits[12:8]
-  op: InstOp = bits[19:13]
-
-class UTILCTR(PacketType):
-  encoding = bits[6:0] == 0b0110001
-  delta = bits[8:7]
-  ctr = bits[47:9]
-
-# All packet types in encoding priority order (more specific masks first, NOP last as fallback)
-PACKET_TYPES: list[type[PacketType]] = [
-  EVENT, EVENT_BIG,
-  TS_DELTA_S8_W3, TS_WAVE_STATE, SNAPSHOT, TS_DELTA_OR_MARK, LAYOUT_HEADER, UTILCTR,
-  IMMEDIATE_MASK, WAVERDY, WAVEEND, WAVESTART, TS_DELTA_S5_W2, WAVEALLOC, TS_DELTA_S5_W3, PERF,
-  VMEMEXEC, ALUEXEC, IMMEDIATE, TS_DELTA_SHORT, REG,
-  VALUINST, INST,
-  NOP,
-]
-
-def _build_state_table() -> tuple[bytes, dict[int, type[PacketType]]]:
-  table = [len(PACKET_TYPES) - 1] * 256  # default to NOP
-  opcode_to_class: dict[int, type[PacketType]] = {i: cls for i, cls in enumerate(PACKET_TYPES)}
-
-  for byte_val in range(256):
-    for opcode, pkt_cls in enumerate(PACKET_TYPES):
-      if pkt_cls._encoding is None: continue
-      mask_bf, pattern = pkt_cls._encoding
-      if (byte_val & mask_bf.mask()) == pattern:
-        table[byte_val] = opcode
-        break
-
-  return bytes(table), opcode_to_class
-
-STATE_TO_OPCODE, OPCODE_TO_CLASS = _build_state_table()
-
-# Precompute special case opcodes
-_TS_DELTA_OR_MARK_OPCODE = next(op for op, cls in OPCODE_TO_CLASS.items() if cls is TS_DELTA_OR_MARK)
-_TS_DELTA_SHORT_OPCODE = next(op for op, cls in OPCODE_TO_CLASS.items() if cls is TS_DELTA_SHORT)
-_TS_DELTA_OR_MARK_BIT8 = (TS_DELTA_OR_MARK.bit8.lo, TS_DELTA_OR_MARK.bit8.mask())
-_TS_DELTA_OR_MARK_BIT9 = (TS_DELTA_OR_MARK.bit9.lo, TS_DELTA_OR_MARK.bit9.mask())
-
-# Combined lookup: opcode -> (pkt_cls, nib_count, delta_lo, delta_mask, special_case)
-# special_case: 0=none, 1=TS_DELTA_OR_MARK, 2=TS_DELTA_SHORT
-_DECODE_INFO: dict[int, tuple] = {}
-for _opcode, _pkt_cls in OPCODE_TO_CLASS.items():
-  _delta_field = getattr(_pkt_cls, 'delta', None)
-  _delta_lo = _delta_field.lo if _delta_field else 0
-  _delta_mask = _delta_field.mask() if _delta_field else 0
-  _special = 1 if _opcode == _TS_DELTA_OR_MARK_OPCODE else (2 if _opcode == _TS_DELTA_SHORT_OPCODE else 0)
-  _DECODE_INFO[_opcode] = (_pkt_cls, _pkt_cls._size_nibbles, _delta_lo, _delta_mask, _special)
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# DECODER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def decode(data: bytes) -> list[PacketType]:
-  """Decode raw SQTT blob into list of packet instances."""
-  packets: list[PacketType] = []
-  packets_append = packets.append
-  n = len(data)
-  reg = 0
-  offset = 0
-  nib_count = 16
-  time = 0
-  state_to_opcode = STATE_TO_OPCODE
-  decode_info = _DECODE_INFO
-  mask64 = (1 << 64) - 1
-
-  while (offset >> 3) < n:
-    target = offset + nib_count * 4
-    while offset < target and (offset >> 3) < n:
-      byte = data[offset >> 3]
-      nib = (byte >> (offset & 4)) & 0xF
-      reg = ((reg >> 4) | (nib << 60)) & mask64
-      offset += 4
-    if offset < target: break
-
-    opcode = state_to_opcode[reg & 0xFF]
-    pkt_cls, nib_count, delta_lo, delta_mask, special = decode_info[opcode]
-
-    delta = (reg >> delta_lo) & delta_mask
-
-    if special == 1:  # TS_DELTA_OR_MARK
-      bit8 = (reg >> _TS_DELTA_OR_MARK_BIT8[0]) & _TS_DELTA_OR_MARK_BIT8[1]
-      bit9 = (reg >> _TS_DELTA_OR_MARK_BIT9[0]) & _TS_DELTA_OR_MARK_BIT9[1]
-      if bit9 and not bit8: delta = 0
-    elif special == 2:  # TS_DELTA_SHORT
-      delta = delta + 8
-
-    time += delta
-    packets_append(pkt_cls.from_raw(reg, time))
-
-  return packets
@@ -1,12 +1,13 @@
 #!/usr/bin/env python3
-"""Benchmark comparing Python vs Rust RDNA3 emulators on real tinygrad kernels."""
-import ctypes, time, os
+"""Benchmark comparing Python vs Rust RDNA3 emulators on synthetic and real tinygrad kernels."""
+import ctypes, time, os, struct, cProfile, pstats, io
 from pathlib import Path
+from typing import Callable

 # Set AMD=1 before importing tinygrad
 os.environ["AMD"] = "1"

-from extra.assembly.amd.emu import run_asm as python_run_asm, set_valid_mem_ranges, decode_program
+from extra.assembly.amd.emu import run_asm as python_run_asm, set_valid_mem_ranges, decode_program, step_wave, WaveState, WAVE_SIZE

 REMU_PATH = Path(__file__).parents[3] / "remu/target/release/libremu.so"
 if not REMU_PATH.exists():
@@ -41,7 +42,7 @@ def setup_buffers(buf_sizes: list[int], init_data: dict[int, bytes] | None = Non
  ranges.add((args_ptr, ctypes.sizeof(args)))
  return buffers, args, args_ptr, ranges

-def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size, args_ptr, rsrc2: int, iterations: int = 5):
+def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size, args_ptr, iterations: int = 5):
  """Benchmark an emulator and return average time."""
  gx, gy, gz = global_size
  lx, ly, lz = local_size
@@ -49,13 +50,13 @@ def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size
  lib_ptr = ctypes.addressof(kernel_buf)

  # Warmup
-  run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr, rsrc2)
+  run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr)

  # Timed runs
  times = []
  for _ in range(iterations):
    start = time.perf_counter()
-    result = run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr, rsrc2)
+    result = run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr)
    end = time.perf_counter()
    if result != 0:
      print(f"  {name} returned error: {result}")
@@ -64,12 +65,27 @@ def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size

  return sum(times) / len(times)

-def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], dict[int, bytes], int] | None:
-  """Get a real tinygrad kernel by operation name. Returns (code, global_size, local_size, buf_sizes, buf_data, rsrc2)."""
+def create_synthetic_kernel(n_ops: int) -> bytes:
+  """Create a synthetic kernel with n_ops vector operations."""
+  instructions = []
+  # VOP2 instructions: v_add_f32, v_mul_f32, v_max_f32, v_min_f32
+  ops = [
+    (0b0000011 << 25) | (1 << 17) | (0 << 9) | 256,  # v_add_f32 v0, v0, v1
+    (0b0001000 << 25) | (1 << 17) | (0 << 9) | 256,  # v_mul_f32 v0, v0, v1
+    (0b0010000 << 25) | (1 << 17) | (0 << 9) | 256,  # v_max_f32 v0, v0, v1
+    (0b0001111 << 25) | (1 << 17) | (0 << 9) | 256,  # v_min_f32 v0, v0, v1
+  ]
+  for i in range(n_ops):
+    instructions.append(ops[i % len(ops)])
+  # S_ENDPGM
+  instructions.append((0b101111111 << 23) | (48 << 16) | 0)
+  return b''.join(struct.pack('<I', inst) for inst in instructions)
+
+def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], dict[int, bytes]] | None:
+  """Get a real tinygrad kernel by operation name. Returns (code, global_size, local_size, buf_sizes, buf_data)."""
  try:
    from tinygrad import Tensor
    from tinygrad.runtime.support.elf import elf_loader
-    from tinygrad.runtime.autogen import hsa
    import numpy as np
    np.random.seed(42)

@@ -96,9 +112,7 @@ def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], d
      lowered = ei.lower()
      if ei.ast.op.name == 'SINK' and lowered.prg and lowered.prg.p.lib:
        lib = bytes(lowered.prg.p.lib)
-        image = memoryview(bytearray(lib))
        _, sections, _ = elf_loader(lib)
-        rodata_entry = next((sh.header.sh_addr for sh in sections if sh.name == ".rodata"), -1)
        for sec in sections:
          if sec.name == '.text':
            buf_sizes = [b.nbytes for b in lowered.bufs]
@@ -108,22 +122,67 @@ def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], d
              if hasattr(buf, 'base') and buf.base is not None and hasattr(buf.base, '_buf'):
                try: buf_data[i] = bytes(buf.base._buf)
                except: pass
-            # Extract rsrc2 from ELF (same as ops_amd.py)
-            group_segment_size = image[rodata_entry:rodata_entry+4].cast("I")[0]
-            lds_size = ((group_segment_size + 511) // 512) & 0x1FF
-            code = hsa.amd_kernel_code_t.from_buffer_copy(bytes(image[rodata_entry:rodata_entry+256]) + b'\x00'*256)
-            rsrc2 = code.compute_pgm_rsrc2 | (lds_size << 15)
-            return (bytes(sec.content), tuple(lowered.prg.p.global_size), tuple(lowered.prg.p.local_size), buf_sizes, buf_data, rsrc2)
+            return (bytes(sec.content), tuple(lowered.prg.p.global_size), tuple(lowered.prg.p.local_size), buf_sizes, buf_data)
    return None
  except Exception as e:
    print(f"  Error getting kernel: {e}")
    return None

+def profile_python_emu(kernel: bytes, global_size, local_size, args_ptr, n_runs: int = 1):
+  """Profile the Python emulator to find bottlenecks."""
+  gx, gy, gz = global_size
+  lx, ly, lz = local_size
+  kernel_buf = (ctypes.c_char * len(kernel)).from_buffer_copy(kernel)
+  lib_ptr = ctypes.addressof(kernel_buf)
+
+  pr = cProfile.Profile()
+  pr.enable()
+  for _ in range(n_runs):
+    python_run_asm(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr)
+  pr.disable()
+
+  s = io.StringIO()
+  ps = pstats.Stats(pr, stream=s).sort_stats('cumulative')
+  ps.print_stats(20)
+  return s.getvalue()
+
+def measure_step_rate(kernel: bytes, n_steps: int = 10000) -> float:
+  """Measure raw step_wave() performance (steps per second)."""
+  program = decode_program(kernel)
+  if not program: return 0.0
+
+  st = WaveState()
+  st.exec_mask = 0xffffffff
+  lds = bytearray(65536)
+  n_lanes = 32
+
+  # Reset PC for each measurement
+  start = time.perf_counter()
+  for _ in range(n_steps):
+    st.pc = 0
+    while st.pc in program:
+      result = step_wave(program, st, lds, n_lanes)
+      if result == -1: break
+  elapsed = time.perf_counter() - start
+  return n_steps / elapsed if elapsed > 0 else 0
+
+# Test configurations
+SYNTHETIC_TESTS = [
+  ("synthetic_10ops", 10, (1, 1, 1), (32, 1, 1)),
+  ("synthetic_100ops", 100, (1, 1, 1), (32, 1, 1)),
+  ("synthetic_500ops", 500, (1, 1, 1), (32, 1, 1)),
+  ("synthetic_100ops_4wg", 100, (4, 1, 1), (32, 1, 1)),
+  ("synthetic_100ops_16wg", 100, (16, 1, 1), (32, 1, 1)),
+]
+
 TINYGRAD_TESTS = ["add", "mul", "reduce_sum", "softmax", "exp", "gelu", "matmul_small"]

 def main():
  import argparse
  parser = argparse.ArgumentParser(description="Benchmark RDNA3 emulators")
+  parser.add_argument("--profile", action="store_true", help="Profile Python emulator")
+  parser.add_argument("--synthetic-only", action="store_true", help="Only run synthetic tests")
+  parser.add_argument("--tinygrad-only", action="store_true", help="Only run tinygrad tests")
  parser.add_argument("--iterations", type=int, default=3, help="Number of iterations per benchmark")
  args = parser.parse_args()

@@ -138,55 +197,98 @@ def main():

  results = []

-  print("\n[TINYGRAD KERNELS]")
-  print("-" * 90)
+  # Synthetic workloads
+  if not args.tinygrad_only:
+    print("\n[SYNTHETIC WORKLOADS]")
+    print("-" * 90)

-  for op_name in TINYGRAD_TESTS:
-    print(f"\n{op_name}:", end=" ", flush=True)
-    kernel_info = get_tinygrad_kernel(op_name)
-    if kernel_info is None:
-      print("failed to compile")
-      continue
+    for name, n_ops, global_size, local_size in SYNTHETIC_TESTS:
+      kernel = create_synthetic_kernel(n_ops)
+      n_insts = count_instructions(kernel)
+      n_workgroups = global_size[0] * global_size[1] * global_size[2]
+      n_threads = local_size[0] * local_size[1] * local_size[2]
+      total_work = n_insts * n_workgroups * n_threads

-    kernel, global_size, local_size, buf_sizes, buf_data, rsrc2 = kernel_info
-    n_insts = count_instructions(kernel)
-    n_workgroups = global_size[0] * global_size[1] * global_size[2]
-    n_threads = local_size[0] * local_size[1] * local_size[2]
-    total_work = n_insts * n_workgroups * n_threads
+      print(f"\n{name}: {n_insts} insts × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")

-    print(f"{n_insts} insts × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")
+      buf_sizes = [4096]
+      buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes)
+      set_valid_mem_ranges(ranges)

-    buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes, buf_data)
-    set_valid_mem_ranges(ranges)
+      # Benchmark
+      py_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, args.iterations)
+      rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, args.iterations) if rust_remu else None

-    py_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, rsrc2, args.iterations)
-    rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, rsrc2, args.iterations) if rust_remu else None
+      if py_time:
+        py_rate = total_work / py_time / 1e6
+        print(f"  Python: {py_time*1000:8.3f} ms  ({py_rate:7.2f} M ops/s)")
+      if rust_time:
+        rust_rate = total_work / rust_time / 1e6
+        speedup = py_time / rust_time if py_time else 0
+        print(f"  Rust:   {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")

-    if py_time:
-      py_rate = total_work / py_time / 1e6
-      print(f"  Python: {py_time*1000:8.3f} ms  ({py_rate:7.2f} M ops/s)")
-    if rust_time:
-      rust_rate = total_work / rust_time / 1e6
-      speedup = py_time / rust_time if py_time else 0
-      print(f"  Rust:   {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")
+      results.append(("synthetic", name, n_insts, n_workgroups, py_time, rust_time))

-    results.append((op_name, n_insts, n_workgroups, py_time, rust_time))
+  # Tinygrad kernels
+  if not args.synthetic_only:
+    print("\n[TINYGRAD KERNELS]")
+    print("-" * 90)
+
+    for op_name in TINYGRAD_TESTS:
+      print(f"\n{op_name}:", end=" ", flush=True)
+      kernel_info = get_tinygrad_kernel(op_name)
+      if kernel_info is None:
+        print("failed to compile")
+        continue
+
+      kernel, global_size, local_size, buf_sizes, buf_data = kernel_info
+      n_insts = count_instructions(kernel)
+      n_workgroups = global_size[0] * global_size[1] * global_size[2]
+      n_threads = local_size[0] * local_size[1] * local_size[2]
+      total_work = n_insts * n_workgroups * n_threads
+
+      print(f"{n_insts} insts × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")
+
+      buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes, buf_data)
+      set_valid_mem_ranges(ranges)
+
+      py_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, args.iterations)
+      rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, args.iterations) if rust_remu else None
+
+      if py_time:
+        py_rate = total_work / py_time / 1e6
+        print(f"  Python: {py_time*1000:8.3f} ms  ({py_rate:7.2f} M ops/s)")
+      if rust_time:
+        rust_rate = total_work / rust_time / 1e6
+        speedup = py_time / rust_time if py_time else 0
+        print(f"  Rust:   {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")
+
+      results.append(("tinygrad", op_name, n_insts, n_workgroups, py_time, rust_time))
+
+      # Optional profiling
+      if args.profile and py_time:
+        print("\n  [PROFILE - Top 10 functions]")
+        profile_output = profile_python_emu(kernel, global_size, local_size, args_ptr)
+        for line in profile_output.split('\n')[5:15]:
+          if line.strip(): print(f"    {line}")

  # Summary table
  print("\n" + "=" * 90)
  print("SUMMARY")
  print("=" * 90)
-  print(f"{'Name':<25} {'Insts':<8} {'WGs':<6} {'Python (ms)':<14} {'Rust (ms)':<14} {'Speedup':<10}")
+  print(f"{'Type':<10} {'Name':<25} {'Insts':<8} {'WGs':<6} {'Python (ms)':<14} {'Rust (ms)':<14} {'Speedup':<10}")
  print("-" * 90)

-  for name, n_insts, n_wgs, py_time, rust_time in results:
+  for test_type, name, n_insts, n_wgs, py_time, rust_time in results:
    py_ms = f"{py_time*1000:.3f}" if py_time else "error"
    if rust_time:
      rust_ms = f"{rust_time*1000:.3f}"
      speedup = f"{py_time/rust_time:.1f}x" if py_time else "N/A"
    else:
      rust_ms, speedup = "N/A", "N/A"
-    print(f"{name:<25} {n_insts:<8} {n_wgs:<6} {py_ms:<14} {rust_ms:<14} {speedup:<10}")
+    print(f"{test_type:<10} {name:<25} {n_insts:<8} {n_wgs:<6} {py_ms:<14} {rust_ms:<14} {speedup:<10}")
+
+

 if __name__ == "__main__":
  main()
@@ -30,8 +30,8 @@ def get_llvm_objdump():
 class ExecContext:
  """Context for running compiled pseudocode in tests."""
  def __init__(self, s0=0, s1=0, s2=0, d0=0, scc=0, vcc=0, lane=0, exec_mask=0xffffffff, literal=0, vgprs=None, src0_idx=0, vdst_idx=0):
-    from extra.assembly.amd.pcode import Reg, MASK32, MASK64, TypedView
-    self._Reg, self._MASK64, self._TypedView = Reg, MASK64, TypedView
+    from extra.assembly.amd.pcode import Reg, MASK32, MASK64, SliceProxy
+    self._Reg, self._MASK64, self._SliceProxy = Reg, MASK64, SliceProxy
    self.S0, self.S1, self.S2 = Reg(s0), Reg(s1), Reg(s2)
    self.D0, self.D1 = Reg(d0), Reg(0)
    self.SCC, self.VCC, self.EXEC = Reg(scc), Reg(vcc), Reg(exec_mask)
@@ -51,7 +51,7 @@ class ExecContext:
    ns.update({
      'S0': self.S0, 'S1': self.S1, 'S2': self.S2, 'D0': self.D0, 'D1': self.D1,
      'SCC': self.SCC, 'VCC': self.VCC, 'EXEC': self.EXEC,
-      'EXEC_LO': self._TypedView(self.EXEC, 31, 0), 'EXEC_HI': self._TypedView(self.EXEC, 63, 32),
+      'EXEC_LO': self._SliceProxy(self.EXEC, 31, 0), 'EXEC_HI': self._SliceProxy(self.EXEC, 63, 32),
      'tmp': self.tmp, 'saveexec': self.saveexec,
      'lane': self.lane, 'laneId': self.laneId, 'literal': self.literal,
      'SIMM16': self.SIMM16, 'SIMM32': self.SIMM32, 'VGPR': self.VGPR, 'SRC0': self.SRC0, 'VDST': self.VDST,
@@ -1 +0,0 @@
-"""Hardware-validated emulator tests for RDNA3 instructions."""
@@ -1,202 +0,0 @@
-"""Test infrastructure for hardware-validated RDNA3 emulator tests.
-
-Uses run_asm() with memory output, so tests can run on both emulator and real hardware.
-Set USE_HW=1 to run on both emulator and real hardware, comparing results.
-"""
-import ctypes, os, struct
-from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.dsl import RawImm
-from extra.assembly.amd.emu import WaveState, run_asm, set_valid_mem_ranges
-from extra.assembly.amd.pcode import _i32, _f32
-
-VCC = SrcEnum.VCC_LO  # For VOP3SD sdst field
-USE_HW = os.environ.get("USE_HW", "0") == "1"
-FLOAT_TOLERANCE = 1e-5
-
-# Output buffer layout: vgpr[16][32], sgpr[16], vcc, scc
-N_VGPRS, N_SGPRS, WAVE_SIZE = 16, 16, 32
-VGPR_BYTES = N_VGPRS * WAVE_SIZE * 4  # 16 regs * 32 lanes * 4 bytes = 2048
-SGPR_BYTES = N_SGPRS * 4  # 16 regs * 4 bytes = 64
-OUT_BYTES = VGPR_BYTES + SGPR_BYTES + 8  # + vcc + scc
-
-# Float conversion helpers
-def f2i(f: float) -> int: return _i32(f)
-def i2f(i: int) -> float: return _f32(i)
-def f2i64(f: float) -> int: return struct.unpack('<Q', struct.pack('<d', f))[0]
-def i642f(i: int) -> float: return struct.unpack('<d', struct.pack('<Q', i))[0]
-
-def assemble(instructions: list) -> bytes:
-  return b''.join(inst.to_bytes() for inst in instructions)
-
-def get_prologue_epilogue(n_lanes: int) -> tuple[list, list]:
-  """Generate prologue and epilogue instructions for state capture."""
-  prologue = [
-    s_mov_b32(s[80], s[0]),
-    s_mov_b32(s[81], s[1]),
-    v_mov_b32_e32(v[255], v[0]),
-  ]
-  for i in range(N_VGPRS):
-    prologue.append(v_mov_b32_e32(v[i], 0))
-  for i in range(N_SGPRS):
-    prologue.append(s_mov_b32(s[i], 0))
-  prologue.append(s_mov_b32(s[SrcEnum.VCC_LO - 128], 0))
-
-  epilogue = [
-    s_mov_b32(s[90], SrcEnum.VCC_LO),
-    s_cselect_b32(s[91], 1, 0),
-    s_load_b64(s[92:93], s[80], 0, soffset=SrcEnum.NULL),
-    s_waitcnt(lgkmcnt=0),
-    v_lshlrev_b32_e32(v[240], 2, v[255]),
-  ]
-  for i in range(N_VGPRS):
-    epilogue.append(global_store_b32(addr=v[240], data=v[i], saddr=s[92], offset=i * WAVE_SIZE * 4))
-  epilogue.append(v_mov_b32_e32(v[241], 0))
-  epilogue.append(v_cmp_eq_u32_e32(v[255], v[241]))
-  epilogue.append(s_and_saveexec_b32(s[94], SrcEnum.VCC_LO))
-  epilogue.append(v_mov_b32_e32(v[240], 0))
-  for i in range(N_SGPRS):
-    epilogue.append(v_mov_b32_e32(v[243], s[i]))
-    epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92], offset=VGPR_BYTES + i * 4))
-  epilogue.append(v_mov_b32_e32(v[243], s[90]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92], offset=VGPR_BYTES + SGPR_BYTES))
-  epilogue.append(v_mov_b32_e32(v[243], s[91]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92], offset=VGPR_BYTES + SGPR_BYTES + 4))
-  epilogue.append(s_mov_b32(s[SrcEnum.EXEC_LO - 128], s[94]))
-  epilogue.append(s_endpgm())
-  return prologue, epilogue
-
-def parse_output(out_buf: bytes, n_lanes: int) -> WaveState:
-  """Parse output buffer into WaveState."""
-  st = WaveState()
-  for i in range(N_VGPRS):
-    for lane in range(n_lanes):
-      off = i * WAVE_SIZE * 4 + lane * 4
-      st.vgpr[lane][i] = struct.unpack_from('<I', out_buf, off)[0]
-  for i in range(N_SGPRS):
-    st.sgpr[i] = struct.unpack_from('<I', out_buf, VGPR_BYTES + i * 4)[0]
-  st.vcc = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES)[0]
-  st.scc = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES + 4)[0]
-  return st
-
-def run_program_emu(instructions: list, n_lanes: int = 1) -> WaveState:
-  """Run instructions via emulator run_asm, dump state to memory, return WaveState."""
-  out_buf = (ctypes.c_uint8 * OUT_BYTES)(*([0] * OUT_BYTES))
-  out_addr = ctypes.addressof(out_buf)
-
-  prologue, epilogue = get_prologue_epilogue(n_lanes)
-  code = assemble(prologue + instructions + epilogue)
-
-  args = (ctypes.c_uint64 * 1)(out_addr)
-  args_ptr = ctypes.addressof(args)
-  kernel_buf = (ctypes.c_char * len(code)).from_buffer_copy(code)
-  lib_ptr = ctypes.addressof(kernel_buf)
-
-  set_valid_mem_ranges({(out_addr, OUT_BYTES), (args_ptr, 8)})
-  # rsrc2: USER_SGPR_COUNT=2, ENABLE_SGPR_WORKGROUP_ID_X/Y/Z=1, LDS_SIZE=128 (64KB)
-  rsrc2 = 0x19c | (128 << 15)
-  result = run_asm(lib_ptr, len(code), 1, 1, 1, n_lanes, 1, 1, args_ptr, rsrc2)
-  assert result == 0, f"run_asm failed with {result}"
-
-  return parse_output(bytes(out_buf), n_lanes)
-
-def run_program_hw(instructions: list, n_lanes: int = 1) -> WaveState:
-  """Run instructions on real AMD hardware via HIPCompiler and AMDProgram."""
-  from tinygrad.device import Device
-  from tinygrad.runtime.ops_amd import AMDProgram
-  from tinygrad.runtime.support.compiler_amd import HIPCompiler
-  from tinygrad.helpers import flat_mv
-
-  dev = Device["AMD"]
-  compiler = HIPCompiler(dev.arch)
-
-  prologue, epilogue = get_prologue_epilogue(n_lanes)
-  code = assemble(prologue + instructions + epilogue)
-
-  byte_str = ', '.join(f'0x{b:02x}' for b in code)
-  asm_src = f""".text
-.globl test
-.p2align 8
-.type test,@function
-test:
-.byte {byte_str}
-
-.rodata
-.p2align 6
-.amdhsa_kernel test
-  .amdhsa_next_free_vgpr 256
-  .amdhsa_next_free_sgpr 96
-  .amdhsa_wavefront_size32 1
-  .amdhsa_user_sgpr_kernarg_segment_ptr 1
-  .amdhsa_kernarg_size 8
-  .amdhsa_group_segment_fixed_size 65536
-.end_amdhsa_kernel
-
-.amdgpu_metadata
---
-amdhsa.version:
-  - 1
-  - 0
-amdhsa.kernels:
-  - .name: test
-    .symbol: test.kd
-    .kernarg_segment_size: 8
-    .group_segment_fixed_size: 65536
-    .private_segment_fixed_size: 0
-    .kernarg_segment_align: 8
-    .wavefront_size: 32
-    .sgpr_count: 96
-    .vgpr_count: 256
-    .max_flat_workgroup_size: 1024
-...
-.end_amdgpu_metadata
-"""
-
-  lib = compiler.compile(asm_src)
-  prg = AMDProgram(dev, "test", lib)
-
-  out_gpu = dev.allocator.alloc(OUT_BYTES)
-  prg(out_gpu, global_size=(1, 1, 1), local_size=(n_lanes, 1, 1), wait=True)
-
-  out_buf = bytearray(OUT_BYTES)
-  dev.allocator._copyout(flat_mv(memoryview(out_buf)), out_gpu)
-
-  return parse_output(bytes(out_buf), n_lanes)
-
-def compare_wave_states(emu_st: WaveState, hw_st: WaveState, n_lanes: int, n_vgprs: int = N_VGPRS) -> list[str]:
-  """Compare two WaveStates and return list of differences."""
-  import math
-  diffs = []
-  for i in range(n_vgprs):
-    for lane in range(n_lanes):
-      emu_val = emu_st.vgpr[lane][i]
-      hw_val = hw_st.vgpr[lane][i]
-      if emu_val != hw_val:
-        emu_f, hw_f = _f32(emu_val), _f32(hw_val)
-        if math.isnan(emu_f) and math.isnan(hw_f):
-          continue
-        diffs.append(f"v[{i}] lane {lane}: emu=0x{emu_val:08x} ({emu_f:.6g}) hw=0x{hw_val:08x} ({hw_f:.6g})")
-  for i in range(N_SGPRS):
-    emu_val = emu_st.sgpr[i]
-    hw_val = hw_st.sgpr[i]
-    if emu_val != hw_val:
-      diffs.append(f"s[{i}]: emu=0x{emu_val:08x} hw=0x{hw_val:08x}")
-  if emu_st.vcc != hw_st.vcc:
-    diffs.append(f"vcc: emu=0x{emu_st.vcc:08x} hw=0x{hw_st.vcc:08x}")
-  if emu_st.scc != hw_st.scc:
-    diffs.append(f"scc: emu={emu_st.scc} hw={hw_st.scc}")
-  return diffs
-
-def run_program(instructions: list, n_lanes: int = 1) -> WaveState:
-  """Run instructions and return WaveState.
-
-  If USE_HW=1, runs on both emulator and hardware, compares results, and raises if they differ.
-  Otherwise, runs only on emulator.
-  """
-  emu_st = run_program_emu(instructions, n_lanes)
-  if USE_HW:
-    hw_st = run_program_hw(instructions, n_lanes)
-    diffs = compare_wave_states(emu_st, hw_st, n_lanes)
-    if diffs:
-      raise AssertionError(f"Emulator vs Hardware mismatch:\n" + "\n".join(diffs))
-    return hw_st
-  return emu_st
@@ -1,629 +0,0 @@
-"""Tests for DS instructions - data share (LDS) operations.
-
-Includes: ds_store_b32, ds_load_b32, ds_store_2addr_*, ds_load_2addr_*,
-          ds_add_*, ds_max_*, ds_min_*, ds_and_*, ds_or_*, ds_xor_*,
-          ds_inc_*, ds_dec_*, ds_cmpstore_*, ds_storexchg_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestDS2Addr(unittest.TestCase):
-  """Tests for DS_*_2ADDR instructions."""
-
-  def test_ds_store_load_2addr_b32(self):
-    """DS_STORE_2ADDR_B32 and DS_LOAD_2ADDR_B32 with offset * 4."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB)
-
-  def test_ds_store_load_2addr_b64(self):
-    """DS_STORE_2ADDR_B64 and DS_LOAD_2ADDR_B64."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B64, addr=v[10], data0=v[0], data1=v[2], vdst=v[0], offset0=0, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4], offset0=0, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][6], 0x12345678)
-    self.assertEqual(st.vgpr[0][7], 0x9ABCDEF0)
-
-
-class TestDS2AddrMore(unittest.TestCase):
-  """Additional DS_*_2ADDR tests."""
-
-  def test_ds_store_load_2addr_b32_nonzero_offsets(self):
-    """DS_STORE_2ADDR_B32 with non-zero offsets (offset*4 scaling)."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0x11111111),
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x22222222),
-      v_mov_b32_e32(v[1], s[2]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=2, offset1=5),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2], offset0=2, offset1=5),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x11111111, "v2 should have value from offset 8 (2*4)")
-    self.assertEqual(st.vgpr[0][3], 0x22222222, "v3 should have value from offset 20 (5*4)")
-
-  def test_ds_2addr_b64_no_overlap(self):
-    """DS_LOAD_2ADDR_B64 with adjacent offsets should not overlap."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0x11111111),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_mov_b32(s[2], 0x22222222),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=4),
-      s_mov_b32(s[2], 0x33333333),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=8),
-      s_mov_b32(s[2], 0x44444444),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=12),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should be 0x11111111")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should be 0x22222222")
-    self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should be 0x33333333")
-    self.assertEqual(st.vgpr[0][7], 0x44444444, "v7 should be 0x44444444")
-
-  def test_ds_load_2addr_b32_no_overwrite(self):
-    """DS_LOAD_2ADDR_B32 should only write 2 VGPRs."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[2]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[4], s[2]),  # Sentinel
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF, "v4 should be untouched")
-
-  def test_ds_load_b64_no_overwrite(self):
-    """DS_LOAD_B64 should only write 2 VGPRs."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_store_b64(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0x12345678),
-      v_mov_b32_e32(v[4], s[2]),  # Sentinel
-      ds_load_b64(addr=v[10], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][3], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][4], 0x12345678, "v4 should be untouched")
-
-
-class TestDSAtomic(unittest.TestCase):
-  """Tests for DS atomic operations."""
-
-  def test_ds_max_rtn_u32(self):
-    """DS_MAX_RTN_U32: atomically store max and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_max_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100, "v2 should have old value (100)")
-    self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200")
-
-  def test_ds_min_rtn_u32(self):
-    """DS_MIN_RTN_U32: atomically store min and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_min_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 200)
-    self.assertEqual(st.vgpr[0][3], 100)
-
-  def test_ds_and_rtn_b32(self):
-    """DS_AND_RTN_B32: atomically AND and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xFF00FF00),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0xFFFF0000),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_and_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xFF00FF00)
-    self.assertEqual(st.vgpr[0][3], 0xFF000000)
-
-  def test_ds_or_rtn_b32(self):
-    """DS_OR_RTN_B32: atomically OR and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0x00FF0000),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0x000000FF),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_or_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x00FF0000)
-    self.assertEqual(st.vgpr[0][3], 0x00FF00FF)
-
-  def test_ds_xor_rtn_b32(self):
-    """DS_XOR_RTN_B32: atomically XOR and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0xFFFFFFFF),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_xor_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0x55555555)
-
-  def test_ds_inc_rtn_u32(self):
-    """DS_INC_RTN_U32: increment with wrap."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 5),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 10),  # limit
-      v_mov_b32_e32(v[1], s[2]),
-      ds_inc_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 5)
-    self.assertEqual(st.vgpr[0][3], 6)
-
-  def test_ds_dec_rtn_u32(self):
-    """DS_DEC_RTN_U32: decrement with wrap."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 5),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 10),  # limit
-      v_mov_b32_e32(v[1], s[2]),
-      ds_dec_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 5)
-    self.assertEqual(st.vgpr[0][3], 4)
-
-  def test_ds_cmpstore_b32_match(self):
-    """DS_CMPSTORE_B32: conditional store when compare matches."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),  # new value
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[2], s[2]),  # compare = 100 (matches)
-      ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 200)
-
-  def test_ds_cmpstore_b32_no_match(self):
-    """DS_CMPSTORE_B32: no store when compare doesn't match."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),  # new value
-      s_mov_b32(s[2], 50),
-      v_mov_b32_e32(v[2], s[2]),  # compare = 50 (doesn't match)
-      ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 100)
-
-  def test_ds_max_u32_no_rtn(self):
-    """DS_MAX_U32 (no RTN): atomically store max, no return value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_max_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200")
-
-  def test_ds_add_u32_no_rtn_preserves_vdst(self):
-    """DS_ADD_U32 (no RTN) should NOT write to vdst."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[2]),  # sentinel
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 50),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_add_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xDEADBEEF, "v2 should preserve sentinel")
-    self.assertEqual(st.vgpr[0][3], 150, "v3 should have 100 + 50 = 150")
-
-  def test_ds_add_rtn_u32_writes_vdst(self):
-    """DS_ADD_RTN_U32 should write old value to vdst."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[2]),  # sentinel
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 50),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_add_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100, "v2 should have old value (100)")
-    self.assertEqual(st.vgpr[0][3], 150, "v3 should have 100 + 50 = 150")
-
-  def test_ds_dec_rtn_u32_wrap(self):
-    """DS_DEC_RTN_U32: decrement wraps when value is 0 or > limit."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0),  # Start at 0
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 10),  # limit
-      v_mov_b32_e32(v[1], s[2]),
-      ds_dec_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0, "v2 should have old value (0)")
-    # When mem == 0 or mem > limit, result = limit
-    self.assertEqual(st.vgpr[0][3], 10, "v3 should wrap to limit (10)")
-
-
-class TestDSStorexchg(unittest.TestCase):
-  """Tests for DS_STOREXCHG instructions."""
-
-  def test_ds_storexchg_rtn_b32(self):
-    """DS_STOREXCHG_RTN_B32: exchange value and return old."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STOREXCHG_RTN_B32, addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB)
-
-
-class TestDSRegisterWidth(unittest.TestCase):
-  """Regression tests: DS loads should only write correct number of VGPRs."""
-
-  def test_ds_load_b32_no_overwrite(self):
-    """DS_LOAD_B32 should only write 1 VGPR."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),  # sentinel
-      ds_store_b32(addr=v[0], data0=v[1], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[0], vdst=v[1], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][2], 0x11111111, "v2 should be untouched")
-
-
-class TestDS2AddrStride64(unittest.TestCase):
-  """Tests for DS_*_2ADDR_STRIDE64 (offset * 256 for B32, offset * 512 for B64)."""
-
-  def test_ds_store_load_2addr_stride64_b32(self):
-    """DS_STORE_2ADDR_STRIDE64_B32: stores at ADDR + offset*256."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[2], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA, "v2 from addr 256")
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB, "v3 from addr 512")
-
-  def test_ds_store_load_2addr_stride64_b64(self):
-    """DS_STORE_2ADDR_STRIDE64_B64: stores at ADDR + offset*512."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0], data1=v[2], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[4], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][6], 0x12345678)
-    self.assertEqual(st.vgpr[0][7], 0x9ABCDEF0)
-
-  def test_ds_storexchg_2addr_rtn_b32(self):
-    """DS_STOREXCHG_2ADDR_RTN_B32: exchange at two addresses."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[6], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "old val 0")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "old val 1")
-    self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "new val 0")
-    self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "new val 1")
-
-
-  def test_ds_storexchg_rtn_b64(self):
-    """DS_STOREXCHG_RTN_B64: exchange 64-bit value and return old."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[0]),   # initial low
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[0]),   # initial high
-      DS(DSOp.DS_STORE_B64, addr=v[10], data0=v[0], vdst=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[2], s[0]),   # new low
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[3], s[0]),   # new high
-      DS(DSOp.DS_STOREXCHG_RTN_B64, addr=v[10], data0=v[2], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B64, addr=v[10], vdst=v[6], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF, "v4 should have old low dword")
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE, "v5 should have old high dword")
-    self.assertEqual(st.vgpr[0][6], 0x12345678, "v6 should have new low dword")
-    self.assertEqual(st.vgpr[0][7], 0x9ABCDEF0, "v7 should have new high dword")
-
-  def test_ds_store_load_2addr_stride64_b64_roundtrip(self):
-    """DS_STORE_2ADDR_STRIDE64_B64 followed by DS_LOAD_2ADDR_STRIDE64_B64 works correctly."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0], data1=v[0], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[2], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x11111111, "v2 should have val1 low")
-    self.assertEqual(st.vgpr[0][3], 0x22222222, "v3 should have val1 high")
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have val2 low")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have val2 high")
-
-  def test_ds_storexchg_2addr_stride64_rtn_b32(self):
-    """DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32: exchange at two addresses (offset*256)."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[6], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have old value")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have old value")
-    self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "v6 should have new value")
-    self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "v7 should have new value")
-
-  def test_ds_storexchg_2addr_stride64_rtn_b64_returns_old(self):
-    """DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64: returns old values correctly."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0], data1=v[0], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[6], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[7], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64, addr=v[10], data0=v[6], data1=v[6], vdst=v[8], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][8], 0x11111111, "v8 should have old val1 low")
-    self.assertEqual(st.vgpr[0][9], 0x22222222, "v9 should have old val1 high")
-    self.assertEqual(st.vgpr[0][10], 0x11111111, "v10 should have old val2 low")
-    self.assertEqual(st.vgpr[0][11], 0x22222222, "v11 should have old val2 high")
-
-
-class TestAtomicOrdering(unittest.TestCase):
-  """Tests for atomic operation return values and ordering."""
-
-  def test_ds_add_rtn_sequence(self):
-    """DS_ADD_RTN returns correct old values in sequence."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      v_mov_b32_e32(v[0], 100),
-      DS(DSOp.DS_STORE_B32, addr=v[10], data0=v[0], vdst=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[1], 25),
-      DS(DSOp.DS_ADD_RTN_U32, addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_ADD_RTN_U32, addr=v[10], data0=v[1], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B32, addr=v[10], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100, "First add should return 100")
-    self.assertEqual(st.vgpr[0][3], 125, "Second add should return 125")
-    self.assertEqual(st.vgpr[0][4], 150, "Final value should be 150")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,363 +0,0 @@
-"""Tests for FLAT instructions - flat memory operations.
-
-Includes: flat_load_*, flat_store_*, flat_atomic_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestFlatAtomic(unittest.TestCase):
-  """Tests for FLAT atomic instructions."""
-
-  def _make_test(self, setup_instrs, atomic_instr, check_fn, test_offset=2000):
-    """Helper to create atomic test instructions."""
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ] + setup_instrs + [atomic_instr, s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    check_fn(st)
-
-  def test_flat_atomic_add_u32(self):
-    """FLAT_ATOMIC_ADD_U32 adds to memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_swap_b32(self):
-    """FLAT_ATOMIC_SWAP_B32 swaps memory value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_and_b32(self):
-    """FLAT_ATOMIC_AND_B32 ANDs with memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xFF00FF00),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xFFFF0000),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_AND_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0xFF00FF00)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_or_b32(self):
-    """FLAT_ATOMIC_OR_B32 ORs with memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0x00FF0000),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0x0000FF00),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_OR_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0x00FF0000)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_inc_u32(self):
-    """FLAT_ATOMIC_INC_U32 increments and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 10),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 100),  # threshold
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 10)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_dec_u32(self):
-    """FLAT_ATOMIC_DEC_U32 decrements and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 10),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_DEC_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 10)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_sub_u32(self):
-    """FLAT_ATOMIC_SUB_U32 subtracts from memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 30),
-      v_mov_b32_e32(v[3], s[0]),  # sub 30
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SUB_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100, "v4 should have old value (100)")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_xor_b32(self):
-    """FLAT_ATOMIC_XOR_B32 XORs with memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      v_mov_b32_e32(v[3], s[0]),  # XOR mask
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_XOR_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA, "v4 should have old value")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_min_u32(self):
-    """FLAT_ATOMIC_MIN_U32 stores min and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[3], s[0]),  # compare value (smaller)
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_MIN_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100, "v4 should have old value (100)")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_max_u32(self):
-    """FLAT_ATOMIC_MAX_U32 stores max and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[3], s[0]),  # compare value (larger)
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_MAX_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 50, "v4 should have old value (50)")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_inc_u64_returns_old_value(self):
-    """FLAT_ATOMIC_INC_U64 should return full 64-bit old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      # Store initial 64-bit value: 0xCAFEBABE_DEADBEEF
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Threshold: 0xFFFFFFFF_FFFFFFFF
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      v_mov_b32_e32(v[4], s[0]),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0xDEADBEEF, "v6 should have old value low dword")
-      self.assertEqual(st.vgpr[0][7], 0xCAFEBABE, "v7 should have old value high dword")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_add_u64(self):
-    """FLAT_ATOMIC_ADD_U64 adds 64-bit value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0x00000001),  # add 1
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x00000000),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0x11111111, "v6 should have old value low")
-      self.assertEqual(st.vgpr[0][7], 0x22222222, "v7 should have old value high")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_swap_b64(self):
-    """FLAT_ATOMIC_SWAP_B64 swaps 64-bit value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xCCCCCCCC),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0xDDDDDDDD),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "v6 should have old value low")
-      self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "v7 should have old value high")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-
-class TestFlatLoad(unittest.TestCase):
-  """Tests for FLAT load instructions."""
-
-  def test_flat_load_b32(self):
-    """FLAT_LOAD_B32 loads 32-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B32, addr=v[0], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-
-  def test_flat_load_b64(self):
-    """FLAT_LOAD_B64 loads 64-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B64, addr=v[0], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE)
-
-  def test_flat_load_b96(self):
-    """FLAT_LOAD_B96 loads 96-bit (3 dword) value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0x33333333),
-      v_mov_b32_e32(v[4], s[0]),
-      global_store_b96(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B96, addr=v[0], vdst=v[5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][5], 0x11111111)
-    self.assertEqual(st.vgpr[0][6], 0x22222222)
-    self.assertEqual(st.vgpr[0][7], 0x33333333)
-
-  def test_flat_load_b128(self):
-    """FLAT_LOAD_B128 loads 128-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0x33333333),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x44444444),
-      v_mov_b32_e32(v[5], s[0]),
-      global_store_b128(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B128, addr=v[0], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][6], 0x11111111)
-    self.assertEqual(st.vgpr[0][7], 0x22222222)
-    self.assertEqual(st.vgpr[0][8], 0x33333333)
-    self.assertEqual(st.vgpr[0][9], 0x44444444)
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,364 +0,0 @@
-"""Tests for GLOBAL instructions - global memory operations.
-
-Includes: global_load_*, global_store_*, global_atomic_*, global_load_d16_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestGlobalAtomic(unittest.TestCase):
-  """Tests for GLOBAL atomic instructions."""
-
-  def _make_test(self, setup_instrs, atomic_instr, check_fn, test_offset=2000):
-    """Helper to create atomic test instructions."""
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ] + setup_instrs + [atomic_instr, s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    check_fn(st)
-
-  def test_global_atomic_add_u32(self):
-    """GLOBAL_ATOMIC_ADD_U32 adds to memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(GLOBALOp.GLOBAL_ATOMIC_ADD_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1, seg=2)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_global_atomic_add_u64(self):
-    """GLOBAL_ATOMIC_ADD_U64 adds 64-bit value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x00000000),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0x00000001),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x00000000),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(GLOBALOp.GLOBAL_ATOMIC_ADD_U64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1, seg=2)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0xFFFFFFFF)
-      self.assertEqual(st.vgpr[0][7], 0x00000000)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-
-class TestGlobalLoad(unittest.TestCase):
-  """Tests for GLOBAL load instructions."""
-
-  def test_global_load_b96(self):
-    """GLOBAL_LOAD_B96 loads 96-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0xCCCCCCCC),
-      v_mov_b32_e32(v[4], s[0]),
-      global_store_b96(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_B96, addr=v[0], vdst=v[5], saddr=SrcEnum.NULL, offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][5], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][6], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][7], 0xCCCCCCCC)
-
-  def test_global_load_b128(self):
-    """GLOBAL_LOAD_B128 loads 128-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[5], s[0]),
-      global_store_b128(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_B128, addr=v[0], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][6], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][7], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][8], 0x12345678)
-    self.assertEqual(st.vgpr[0][9], 0x9ABCDEF0)
-
-
-class TestGlobalStore(unittest.TestCase):
-  """Tests for GLOBAL store instructions."""
-
-  def test_global_store_b64_basic(self):
-    """GLOBAL_STORE_B64 stores 8 bytes from v[n:n+1] to memory."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      s_mov_b32(s[5], 0xCAFEBABE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], s[5]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b64(addr=v[0], data=v[2], saddr=s[2], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_B64, addr=v[0], vdst=v[4], data=v[4], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[4]),
-      v_mov_b32_e32(v[1], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][1], 0xCAFEBABE)
-
-
-class TestD16HiLoads(unittest.TestCase):
-  """Tests for D16_HI load instructions that load into high 16 bits."""
-
-  def test_global_load_d16_hi_b16_preserves_low_bits(self):
-    """GLOBAL_LOAD_D16_HI_B16 must preserve low 16 bits of destination."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000BEEF),
-      v_mov_b32_e32(v[3], s[4]),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[0], vdst=v[3], data=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0xCAFEBEEF, f"Expected 0xCAFEBEEF, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_b16_data_differs_from_vdst(self):
-    """GLOBAL_LOAD_D16_HI_B16 where data field differs from vdst."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b16(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000DEAD),
-      v_mov_b32_e32(v[0], s[4]),  # data field - should NOT affect result
-      v_mov_b32_e32(v[1], 0),     # vdst - low bits should be preserved
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[1]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0xCAFE0000, f"Expected 0xCAFE0000, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_u8_data_differs_from_vdst(self):
-    """GLOBAL_LOAD_D16_HI_U8 where data field differs from vdst."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xAB),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b8(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000DEAD),
-      v_mov_b32_e32(v[4], s[4]),  # data field
-      s_mov_b32(s[4], 0x0000BEEF),
-      v_mov_b32_e32(v[5], s[4]),  # vdst
-      v_mov_b32_e32(v[3], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_U8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0x00ABBEEF, f"Expected 0x00ABBEEF, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_b16_same_addr_and_dst_zero_addr(self):
-    """GLOBAL_LOAD_D16_HI_B16 with same register for addr and vdst, addr value=0."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b16(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[1], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[1]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0xCAFE0000, f"Expected 0xCAFE0000, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_b16_tril_exact_pattern(self):
-    """Exact pattern from tril() failure: data=v0 differs from vdst=v1."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0x01010101),
-      v_mov_b32_e32(v[10], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b32(addr=v[3], data=v[10], saddr=s[2], offset=TEST_OFFSET),
-      global_store_b32(addr=v[3], data=v[10], saddr=s[2], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      # Set v[0] to 0x0101 (simulating prior u16 load result)
-      s_mov_b32(s[4], 0x0101),
-      v_mov_b32_e32(v[0], s[4]),
-      # Set v[1] to 0
-      v_mov_b32_e32(v[1], 0),
-      # Load using v[1] as addr AND vdst, but v[0] as data
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2], offset=TEST_OFFSET+6, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[1]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    # Expected: hi=0x0101 (loaded), lo=0x0000 (from v1) -> 0x01010000
-    self.assertEqual(result, 0x01010000, f"Expected 0x01010000, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_i8_data_differs_from_vdst(self):
-    """GLOBAL_LOAD_D16_HI_I8 where data field differs from vdst."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0x80),  # negative signed byte = -128
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b8(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000DEAD),
-      v_mov_b32_e32(v[4], s[4]),  # data field
-      s_mov_b32(s[4], 0x0000BEEF),
-      v_mov_b32_e32(v[5], s[4]),  # vdst
-      v_mov_b32_e32(v[3], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_I8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    # 0x80 sign-extended = 0xFF80, lo=0xBEEF -> 0xFF80BEEF
-    self.assertEqual(result, 0xFF80BEEF, f"Expected 0xFF80BEEF, got 0x{result:08x}")
-
-  def test_global_store_b64_tril_pattern(self):
-    """Test the exact pattern from tril() kernel that was failing."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0x01010101),
-      v_mov_b32_e32(v[10], s[4]),
-      v_mov_b32_e32(v[11], s[4]),
-      s_mov_b32(s[4], 0x01),
-      v_mov_b32_e32(v[12], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b64(addr=v[0], data=v[10], saddr=s[2], offset=TEST_OFFSET),
-      global_store_b8(addr=v[0], data=v[12], saddr=s[2], offset=TEST_OFFSET+8),
-      s_waitcnt(vmcnt=0),
-
-      v_mov_b32_e32(v[2], 0),
-      v_mov_b32_e32(v[1], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_U16, addr=v[2], vdst=v[0], data=v[0], saddr=s[2], offset=TEST_OFFSET+3, seg=2),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2], offset=TEST_OFFSET+6, seg=2),
-      FLAT(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[3], data=v[3], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      FLAT(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[4], data=v[4], saddr=s[2], offset=TEST_OFFSET+8, seg=2),
-      s_waitcnt(vmcnt=0),
-
-      v_and_b32_e32(v[5], 0xffff, v[0]),
-      v_lshlrev_b32_e32(v[0], 24, v[0]),
-      v_lshrrev_b32_e32(v[5], 8, v[5]),
-      v_or_b32_e32(v[0], v[3], v[0]),
-      v_or_b32_e32(v[1], v[5], v[1]),
-
-      global_store_b64(addr=v[2], data=v[0], saddr=s[2], offset=TEST_OFFSET+16),
-      s_waitcnt(vmcnt=0),
-
-      FLAT(GLOBALOp.GLOBAL_LOAD_B64, addr=v[2], vdst=v[6], data=v[6], saddr=s[2], offset=TEST_OFFSET+16, seg=2),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[6]),
-      v_mov_b32_e32(v[1], v[7]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-
-    v0 = st.vgpr[0][0]
-    v1 = st.vgpr[0][1]
-    self.assertEqual(v0, 0x01000001, f"v0: expected 0x01000001, got 0x{v0:08x}")
-    self.assertEqual(v1, 0x01010001, f"v1: expected 0x01010001, got 0x{v1:08x}")
-
-    byte5 = (v1 >> 8) & 0xff
-    self.assertEqual(byte5, 0x00, f"byte5: expected 0x00, got 0x{byte5:02x}")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,342 +0,0 @@
-"""Tests for SOP instructions - scalar operations.
-
-Includes: s_add_u32, s_mov_b32, s_and_b32, s_or_b32, s_quadmask_b32, s_wqm_b32,
-          s_cbranch_vccnz, s_cbranch_vccz
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestBasicScalar(unittest.TestCase):
-  """Tests for basic scalar operations."""
-
-  def test_s_add_u32(self):
-    """S_ADD_U32 adds two scalar values."""
-    instructions = [
-      s_mov_b32(s[0], 100),
-      s_mov_b32(s[1], 200),
-      s_add_u32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 300)
-
-  def test_s_add_u32_carry(self):
-    """S_ADD_U32 sets SCC on overflow."""
-    instructions = [
-      s_mov_b32(s[0], 64),
-      s_not_b32(s[0], s[0]),  # ~64 = 0xffffffbf
-      s_mov_b32(s[1], 64),
-      s_add_u32(s[2], s[0], s[1]),  # 0xffffffbf + 64 = 0xffffffff
-      s_mov_b32(s[3], 1),
-      s_add_u32(s[4], s[2], s[3]),  # 0xffffffff + 1 = overflow
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0)
-    self.assertEqual(st.scc, 1)
-
-  def test_s_brev_b32(self):
-    """S_BREV_B32 reverses bits of a 32-bit value."""
-    # 10 = 0b00000000000000000000000000001010
-    # reversed = 0b01010000000000000000000000000000 = 0x50000000
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_brev_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0x50000000)
-
-  def test_s_brev_b32_all_ones(self):
-    """S_BREV_B32 with all ones stays all ones."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_brev_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0xFFFFFFFF)
-
-  def test_s_brev_b32_single_bit(self):
-    """S_BREV_B32 with bit 0 set becomes bit 31."""
-    instructions = [
-      s_mov_b32(s[0], 1),
-      s_brev_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0x80000000)
-
-
-class TestQuadmaskWqm(unittest.TestCase):
-  """Tests for S_QUADMASK_B32 and S_WQM_B32."""
-
-  def test_s_quadmask_b32_all_quads_active(self):
-    """S_QUADMASK_B32 with all quads active."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # All lanes active
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Each quad (4 lanes) with any bit set -> 1 bit in result
-    # 32 lanes = 8 quads, all active -> 0xFF
-    self.assertEqual(st.sgpr[1], 0xFF)
-
-  def test_s_quadmask_b32_alternating_quads(self):
-    """S_QUADMASK_B32 with alternating quads active."""
-    instructions = [
-      s_mov_b32(s[0], 0x0F0F0F0F),  # Quads 0,2,4,6 active
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Quads 0,2,4,6 have at least one bit -> 0b01010101 = 0x55
-    self.assertEqual(st.sgpr[1], 0x55)
-
-  def test_s_quadmask_b32_no_quads_active(self):
-    """S_QUADMASK_B32 with no quads active."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0)
-
-  def test_s_quadmask_b32_single_lane_per_quad(self):
-    """S_QUADMASK_B32 with single lane active in each quad."""
-    instructions = [
-      s_mov_b32(s[0], 0x11111111),  # Bit 0 of each nibble
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # All 8 quads have at least one lane -> 0xFF
-    self.assertEqual(st.sgpr[1], 0xFF)
-
-  def test_s_wqm_b32_all_active(self):
-    """S_WQM_B32 with all lanes active returns all 1s."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_wqm_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0xFFFFFFFF)
-
-  def test_s_wqm_b32_alternating_quads(self):
-    """S_WQM_B32 with single lane per quad expands to full quads."""
-    instructions = [
-      s_mov_b32(s[0], 0x11111111),  # One lane per quad
-      s_wqm_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Each quad with any bit expands to all 4 bits
-    self.assertEqual(st.sgpr[1], 0xFFFFFFFF)
-
-  def test_s_wqm_b32_zero(self):
-    """S_WQM_B32 with zero input returns zero."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_wqm_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0)
-
-
-class TestBranch(unittest.TestCase):
-  """Tests for branch instructions."""
-
-  def test_cbranch_vccnz_ignores_vcc_hi(self):
-    """S_CBRANCH_VCCNZ should only check VCC_LO in wave32."""
-    instructions = [
-      # Set VCC_LO = 0, VCC_HI = 1
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 0),
-      s_mov_b32(s[SrcEnum.VCC_HI - 128], 1),
-      v_mov_b32_e32(v[0], 0),
-      # If VCC_HI is incorrectly used, branch will be taken
-      s_cbranch_vccnz(1),  # Skip next instruction if VCC != 0
-      v_mov_b32_e32(v[0], 42),  # This should execute
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 42, "Branch should NOT be taken (VCC_LO is 0)")
-
-  def test_cbranch_vccz_ignores_vcc_hi(self):
-    """S_CBRANCH_VCCZ should only check VCC_LO in wave32."""
-    instructions = [
-      # Set VCC_LO = 1, VCC_HI = 0
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 1),
-      s_mov_b32(s[SrcEnum.VCC_HI - 128], 0),
-      v_mov_b32_e32(v[0], 0),
-      # If VCC_HI is incorrectly used, branch will be taken
-      s_cbranch_vccz(1),  # Skip next instruction if VCC == 0
-      v_mov_b32_e32(v[0], 42),  # This should execute
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 42, "Branch should NOT be taken (VCC_LO is 1)")
-
-  def test_cbranch_vccnz_branches_on_vcc_lo(self):
-    """S_CBRANCH_VCCNZ branches when VCC_LO is non-zero."""
-    instructions = [
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 1),
-      v_mov_b32_e32(v[0], 0),
-      s_cbranch_vccnz(1),  # Skip next instruction if VCC != 0
-      v_mov_b32_e32(v[0], 42),  # This should be skipped
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0, "Branch should be taken (VCC_LO is 1)")
-
-
-class Test64BitLiterals(unittest.TestCase):
-  """Tests for 64-bit literal encoding in instructions."""
-
-  def test_64bit_literal_negative_encoding(self):
-    """64-bit literal -2^32 encodes correctly."""
-    lit = -4294967296.0  # -2^32
-    lit_bits = f2i64(lit)
-    instructions = [
-      s_mov_b32(s[0], lit_bits & 0xffffffff),
-      s_mov_b32(s[1], lit_bits >> 32),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = i642f(st.vgpr[0][0] | (st.vgpr[0][1] << 32))
-    self.assertAlmostEqual(result, -4294967296.0, places=5)
-
-  def test_64bit_literal_positive_encoding(self):
-    """64-bit instruction encodes large positive literals correctly."""
-    large_val = 0x12345678
-    inst = v_add_f64(v[2], v[0], large_val)
-    self.assertIsNotNone(inst._literal, "Literal should be set")
-    actual_lit = (inst._literal >> 32) & 0xffffffff
-    self.assertEqual(actual_lit, large_val, f"Literal should be {large_val:#x}, got {actual_lit:#x}")
-
-
-class TestSCCBehavior(unittest.TestCase):
-  """Tests for SCC condition code behavior."""
-
-  def test_scc_from_s_cmp(self):
-    """SCC should be set by scalar compare."""
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_cmp_eq_u32(s[0], 10),
-      s_cselect_b32(s[1], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 1, "SCC should be true")
-    self.assertEqual(st.scc, 1)
-
-  def test_scc_clear(self):
-    """SCC should be cleared by failing compare."""
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_cmp_eq_u32(s[0], 20),
-      s_cselect_b32(s[1], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0, "SCC should be false")
-    self.assertEqual(st.scc, 0)
-
-
-class TestSignedArithmetic(unittest.TestCase):
-  """Tests for S_ADD_I32, S_SUB_I32 and their SCC overflow behavior."""
-
-  def test_s_add_i32_no_overflow(self):
-    """S_ADD_I32: 1 + 1 = 2, no overflow, SCC=0."""
-    instructions = [
-      s_mov_b32(s[0], 1),
-      s_add_i32(s[1], s[0], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 2)
-    self.assertEqual(st.scc, 0, "No overflow, SCC should be 0")
-
-  def test_s_add_i32_positive_overflow(self):
-    """S_ADD_I32: MAX_INT + 1 overflows, SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0x7FFFFFFF),  # MAX_INT
-      s_add_i32(s[1], s[0], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0x80000000)  # Wraps to MIN_INT
-    self.assertEqual(st.scc, 1, "Overflow, SCC should be 1")
-
-  def test_s_add_i32_negative_no_overflow(self):
-    """S_ADD_I32: -10 + 20 = 10, no overflow."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFF6),  # -10 in two's complement
-      s_mov_b32(s[1], 20),
-      s_add_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 10)
-    self.assertEqual(st.scc, 0)
-
-  def test_s_add_i32_negative_overflow(self):
-    """S_ADD_I32: MIN_INT + (-1) underflows, SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),  # MIN_INT
-      s_mov_b32(s[1], 0xFFFFFFFF),  # -1
-      s_add_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0x7FFFFFFF)  # Wraps to MAX_INT
-    self.assertEqual(st.scc, 1, "Underflow, SCC should be 1")
-
-  def test_s_sub_i32_no_overflow(self):
-    """S_SUB_I32: 10 - 5 = 5, no overflow."""
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_mov_b32(s[1], 5),
-      s_sub_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 5)
-    self.assertEqual(st.scc, 0)
-
-  def test_s_sub_i32_overflow(self):
-    """S_SUB_I32: MAX_INT - (-1) overflows, SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0x7FFFFFFF),  # MAX_INT
-      s_mov_b32(s[1], 0xFFFFFFFF),  # -1
-      s_sub_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0x80000000)  # Wraps to MIN_INT
-    self.assertEqual(st.scc, 1, "Overflow, SCC should be 1")
-
-  def test_s_mul_hi_u32(self):
-    """S_MUL_HI_U32: high 32 bits of u32 * u32."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),  # 2^31
-      s_mov_b32(s[1], 4),
-      s_mul_hi_u32(s[2], s[0], s[1]),  # (2^31 * 4) >> 32 = 2
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 2)
-
-  def test_s_mul_i32(self):
-    """S_MUL_I32: signed multiply low 32 bits."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # -1
-      s_mov_b32(s[1], 10),
-      s_mul_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0xFFFFFFF6)  # -10
-
-  def test_division_sequence_from_llvm(self):
-    """Test the division sequence pattern from LLVM-generated code."""
-    # This sequence is from the sin kernel and computes integer division
-    # s10 = dividend, s18 = divisor, result in s6/s14
-    dividend = 0x28BE60DB  # Some value from the sin kernel
-    divisor = 3  # Simplified divisor
-    instructions = [
-      s_mov_b32(s[10], dividend),
-      s_mov_b32(s[18], divisor),
-      # Compute reciprocal approximation: s6 = ~0 / divisor (approx)
-      s_mov_b32(s[11], 0),
-      s_sub_i32(s[11], s[11], s[18]),  # s11 = -divisor
-      # For testing, just verify basic arithmetic works
-      s_mul_i32(s[6], s[10], 2),
-      s_add_i32(s[7], s[6], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[6], (dividend * 2) & 0xFFFFFFFF)
-    self.assertEqual(st.sgpr[7], ((dividend * 2) + 1) & 0xFFFFFFFF)
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,451 +0,0 @@
-"""Tests for VOP2 instructions - two operand vector operations.
-
-Includes: v_add_f32, v_mul_f32, v_and_b32, v_or_b32, v_xor_b32,
-          v_lshrrev_b32, v_lshlrev_b32, v_fmac_f32, v_fmaak_f32, v_fmamk_f32,
-          v_add_nc_u32, v_cndmask_b32, v_add_f16, v_mul_f16
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestBasicArithmetic(unittest.TestCase):
-  """Tests for basic arithmetic VOP2 instructions."""
-
-  def test_v_add_f32(self):
-    """V_ADD_F32 adds two floats."""
-    instructions = [
-      v_mov_b32_e32(v[0], 1.0),
-      v_mov_b32_e32(v[1], 2.0),
-      v_add_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 3.0, places=5)
-
-  def test_v_mul_f32(self):
-    """V_MUL_F32 multiplies two floats."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 4.0),
-      v_mul_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 8.0, places=5)
-
-  def test_v_fmac_f32(self):
-    """V_FMAC_F32: d = d + a*b using inline constants."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 4.0),
-      v_mov_b32_e32(v[2], 1.0),
-      v_fmac_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
-
-  def test_v_fmaak_f32(self):
-    """V_FMAAK_F32: d = a * b + K using inline constants."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 4.0),
-      v_fmaak_f32_e32(v[2], v[0], v[1], 0x3f800000),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
-
-  def test_v_fmamk_f32_basic(self):
-    """V_FMAMK_F32: d = a * K + b."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 1.0),
-      v_fmamk_f32_e32(v[2], v[0], 0x40800000, v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
-
-  def test_v_fmamk_f32_small_constant(self):
-    """V_FMAMK_F32 with small constant."""
-    instructions = [
-      v_mov_b32_e32(v[0], 4.0),
-      v_mov_b32_e32(v[1], 1.0),
-      v_fmamk_f32_e32(v[2], v[0], f2i(0.5), v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 3.0, places=5)
-
-
-class TestBitManipulation(unittest.TestCase):
-  """Tests for bit manipulation VOP2 instructions."""
-
-  def test_v_and_b32(self):
-    """V_AND_B32 bitwise and."""
-    instructions = [
-      s_mov_b32(s[0], 0xff),
-      s_mov_b32(s[1], 0x0f),
-      v_mov_b32_e32(v[0], s[0]),
-      v_and_b32_e32(v[1], s[1], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x0f)
-
-  def test_v_and_b32_quadrant(self):
-    """V_AND_B32 for quadrant extraction (n & 3)."""
-    instructions = [
-      s_mov_b32(s[0], 15915),
-      v_mov_b32_e32(v[0], s[0]),
-      v_and_b32_e32(v[1], 3, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 15915 & 3)
-
-  def test_v_lshrrev_b32(self):
-    """V_LSHRREV_B32 logical shift right."""
-    instructions = [
-      s_mov_b32(s[0], 0xff00),
-      v_mov_b32_e32(v[0], s[0]),
-      v_lshrrev_b32_e32(v[1], 8, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0xff)
-
-  def test_v_lshlrev_b32(self):
-    """V_LSHLREV_B32 logical shift left."""
-    instructions = [
-      s_mov_b32(s[0], 0xff),
-      v_mov_b32_e32(v[0], s[0]),
-      v_lshlrev_b32_e32(v[1], 8, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0xff00)
-
-  def test_v_xor_b32(self):
-    """V_XOR_B32 bitwise xor (used in sin for sign)."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),
-      s_mov_b32(s[1], f2i(1.0)),
-      v_mov_b32_e32(v[0], s[1]),
-      v_xor_b32_e32(v[1], s[0], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][1]), -1.0, places=5)
-
-  def test_v_xor_b32_sign_flip(self):
-    """V_XOR_B32 for sign flip pattern."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),
-      v_mov_b32_e32(v[0], -2.0),
-      v_xor_b32_e32(v[1], s[0], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][1]), 2.0, places=5)
-
-
-class TestSpecialValues(unittest.TestCase):
-  """Tests for special float values - inf, nan, zero handling."""
-
-  def test_v_mul_f32_zero_times_inf(self):
-    """V_MUL_F32: 0 * inf = NaN."""
-    import math
-    instructions = [
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[0], 0x7f800000),
-      v_mov_b32_e32(v[1], s[0]),
-      v_mul_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertTrue(math.isnan(i2f(st.vgpr[0][2])))
-
-  def test_v_add_f32_inf_minus_inf(self):
-    """V_ADD_F32: inf + (-inf) = NaN."""
-    import math
-    instructions = [
-      s_mov_b32(s[0], 0x7f800000),
-      s_mov_b32(s[1], 0xff800000),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertTrue(math.isnan(i2f(st.vgpr[0][2])))
-
-
-class TestF16Ops(unittest.TestCase):
-  """Tests for 16-bit VOP2 operations."""
-
-  def test_v_add_f16_basic(self):
-    """V_ADD_F16 adds two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4200, f"Expected 0x4200 (f16 3.0), got 0x{result:04x}")
-
-  def test_v_add_f16_negative(self):
-    """V_ADD_F16 with negative values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0xc000),  # f16 -2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0xbc00, f"Expected 0xbc00 (f16 -1.0), got 0x{result:04x}")
-
-  def test_v_mul_f16_basic(self):
-    """V_MUL_F16 multiplies two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      s_mov_b32(s[1], 0x4200),  # f16 3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mul_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4600, f"Expected 0x4600 (f16 6.0), got 0x{result:04x}")
-
-  def test_v_mul_f16_by_zero(self):
-    """V_MUL_F16 by zero."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0),
-      v_mul_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x0000, f"Expected 0x0000 (f16 0.0), got 0x{result:04x}")
-
-  def test_v_fmac_f16_basic(self):
-    """V_FMAC_F16: d = d + a*b."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      s_mov_b32(s[1], 0x4200),  # f16 3.0
-      s_mov_b32(s[2], 0x3c00),  # f16 1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      v_fmac_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(result, 0x4700, f"Expected 0x4700 (f16 7.0), got 0x{result:04x}")
-
-  def test_v_fmaak_f16_basic(self):
-    """V_FMAAK_F16: d = a * b + K."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      s_mov_b32(s[1], 0x4200),  # f16 3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_fmaak_f16_e32(v[2], v[0], v[1], 0x3c00),  # + f16 1.0
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(result, 0x4700, f"Expected 0x4700 (f16 7.0), got 0x{result:04x}")
-
-
-class TestHiHalfOps(unittest.TestCase):
-  """Tests for VOP2 16-bit operations with hi-half operands."""
-
-  def test_v_add_f16_src0_hi_fold(self):
-    """V_ADD_F16 with src0 hi-half fold (same register, different halves)."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # lo=f16(1.0), hi=f16(2.0)
-      v_mov_b32_e32(v[0], s[0]),
-      VOP3(VOP3Op.V_ADD_F16, vdst=v[1], src0=v[0], src1=v[0], opsel=0b0001),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    self.assertEqual(result, 0x4200, f"Expected f16(3.0)=0x4200, got 0x{result:04x}")
-
-  def test_v_add_f16_src0_hi_different_reg(self):
-    """V_ADD_F16 with src0 hi-half from different register."""
-    instructions = [
-      s_mov_b32(s[0], 0x40000000),  # hi=f16(2.0), lo=0
-      s_mov_b32(s[1], 0x00003c00),  # hi=0, lo=f16(1.0)
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      VOP3(VOP3Op.V_ADD_F16, vdst=v[2], src0=v[0], src1=v[1], opsel=0b0001),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4200, f"Expected f16(3.0)=0x4200, got 0x{result:04x}")
-
-  def test_v_mul_f16_src0_hi(self):
-    """V_MUL_F16 with src0 from high half."""
-    instructions = [
-      s_mov_b32(s[0], 0x40000000),  # hi=f16(2.0), lo=0
-      s_mov_b32(s[1], 0x00004200),  # hi=0, lo=f16(3.0)
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      VOP3(VOP3Op.V_MUL_F16, vdst=v[2], src0=v[0], src1=v[1], opsel=0b0001),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
-
-  def test_v_mul_f16_hi_half(self):
-    """V_MUL_F16 reading from high half."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # lo=1.0, hi=2.0
-      v_mov_b32_e32(v[0], s[0]),
-      VOP3(VOP3Op.V_MUL_F16, vdst=v[1], src0=v[0], src1=v[0], opsel=0b0011),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    self.assertEqual(result, 0x4400, f"Expected f16(4.0)=0x4400, got 0x{result:04x}")
-
-  def test_v_fma_f16_hi_dest(self):
-    """V_FMA_F16 writing to high half with opsel.
-
-    Uses V_FMA_F16 (not V_FMAC_F16) because it has explicit src2 operand
-    which makes opsel handling clearer.
-    """
-    instructions = [
-      s_mov_b32(s[0], 0x3c000000),  # hi=f16(1.0), lo=0
-      s_mov_b32(s[1], 0x4000),      # f16(2.0) in lo
-      s_mov_b32(s[2], 0x4200),      # f16(3.0) in lo
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      # V_FMA_F16: dst = src0 * src1 + src2
-      # opsel=0b1100: bit2=src2 hi, bit3=dst hi
-      # So: v[0].hi = v[1].lo * v[2].lo + v[0].hi = 2.0 * 3.0 + 1.0 = 7.0
-      VOP3(VOP3Op.V_FMA_F16, vdst=v[0], src0=v[1], src1=v[2], src2=v[0], opsel=0b1100),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][0] >> 16) & 0xffff
-    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(hi, 0x4700, f"Expected f16(7.0)=0x4700 in hi, got 0x{hi:04x}")
-
-  def test_v_add_f16_multilane(self):
-    """V_ADD_F16 with multiple lanes."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    for lane in range(4):
-      result = st.vgpr[lane][2] & 0xffff
-      self.assertEqual(result, 0x4200, f"Lane {lane}: expected 0x4200, got 0x{result:04x}")
-
-
-class TestCndmask(unittest.TestCase):
-  """Tests for V_CNDMASK_B32 and V_CNDMASK_B16."""
-
-  def test_v_cndmask_b16_select_src0(self):
-    """V_CNDMASK_B16 selects src0 when VCC bit is 0."""
-    instructions = [
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 0),  # VCC = 0
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cndmask_b16(v[2], v[0], v[1], VCC),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x3c00, f"Expected src0=0x3c00, got 0x{result:04x}")
-
-  def test_v_cndmask_b16_select_src1(self):
-    """V_CNDMASK_B16 selects src1 when VCC bit is 1."""
-    instructions = [
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 1),  # VCC = 1
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cndmask_b16(v[2], v[0], v[1], VCC),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4000, f"Expected src1=0x4000, got 0x{result:04x}")
-
-  def test_v_cndmask_b16_write_hi(self):
-    """V_CNDMASK_B16 can write to high 16 bits with opsel."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c003800),  # src0: hi=1.0, lo=0.5
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x4000c000),  # src1: hi=2.0, lo=-2.0
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], 0xDEAD0000),  # v2 initial: hi=0xDEAD, lo=0
-      v_mov_b32_e32(v[2], s[2]),
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 0),  # vcc = 0, select src0
-      # opsel=0b1011: bit0=src0 hi, bit1=src1 hi, bit3=dst hi
-      VOP3(VOP3Op.V_CNDMASK_B16, vdst=v[2], src0=v[0], src1=v[1], src2=SrcEnum.VCC_LO, opsel=0b1011),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][2] >> 16) & 0xffff
-    lo = st.vgpr[0][2] & 0xffff
-    # vcc=0 selects src0.h = 1.0 = 0x3c00, writes to hi
-    self.assertEqual(hi, 0x3c00, f"Expected hi=0x3c00 (1.0), got 0x{hi:04x}")
-    self.assertEqual(lo, 0x0000, f"Expected lo preserved as 0, got 0x{lo:04x}")
-
-
-class TestSpecialFloatValues(unittest.TestCase):
-  """Tests for special float value handling in VOP2 instructions."""
-
-  def test_neg_zero_add(self):
-    """-0.0 + 0.0 = +0.0 (IEEE 754)."""
-    neg_zero = 0x80000000
-    instructions = [
-      s_mov_b32(s[0], neg_zero),
-      v_mov_b32_e32(v[0], s[0]),
-      v_add_f32_e32(v[1], 0.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x00000000, "Should be +0.0")
-
-  def test_neg_zero_mul(self):
-    """-0.0 * -1.0 = +0.0."""
-    neg_zero = 0x80000000
-    instructions = [
-      s_mov_b32(s[0], neg_zero),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mul_f32_e32(v[1], -1.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x00000000, "Should be +0.0")
-
-  def test_inf_minus_inf(self):
-    """+inf - inf = NaN."""
-    import math
-    pos_inf = 0x7f800000
-    neg_inf = 0xff800000
-    instructions = [
-      s_mov_b32(s[0], pos_inf),
-      s_mov_b32(s[1], neg_inf),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_sub_f32_e32(v[2], v[0], v[1]),  # inf - (-inf) = inf
-      v_add_f32_e32(v[3], v[0], v[1]),  # inf + (-inf) = NaN
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], pos_inf, "inf - (-inf) = inf")
-    self.assertTrue(math.isnan(i2f(st.vgpr[0][3])), "inf + (-inf) = NaN")
-
-  def test_denormal_f32_mul_ftz(self):
-    """Denormal * normal - RDNA3 flushes denormals to zero (FTZ mode)."""
-    smallest_denorm = 0x00000001  # Smallest positive denormal
-    instructions = [
-      s_mov_b32(s[0], smallest_denorm),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mul_f32_e32(v[1], 2.0, v[0]),  # Denormal input gets flushed to 0
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x00000000)
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,538 +0,0 @@
-"""Tests for VOP3P instructions - packed 16-bit vector operations.
-
-Includes: v_pk_add_f16, v_pk_mul_f16, v_pk_fma_f16, v_pack_b32_f16, v_wmma_*, v_dot2_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestPackInstructions(unittest.TestCase):
-  """Tests for pack instructions."""
-
-  def test_v_pack_b32_f16(self):
-    """V_PACK_B32_F16 packs two f16 values into one 32-bit register."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pack_b32_f16(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x40003c00, f"Expected 0x40003c00, got 0x{result:08x}")
-
-  def test_v_pack_b32_f16_opsel_hi_hi(self):
-    """V_PACK_B32_F16 with opsel to read high halves."""
-    inst = v_pack_b32_f16(v[2], v[0], v[1])
-    inst._values['opsel'] = 0b0011
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # hi=2.0, lo=1.0
-      s_mov_b32(s[1], 0x44004200),  # hi=4.0, lo=3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      inst,
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x44004000, f"Expected 0x44004000, got 0x{result:08x}")
-
-
-class TestPackMore(unittest.TestCase):
-  """Additional pack instruction tests."""
-
-  def test_v_pack_b32_f16_basic(self):
-    """V_PACK_B32_F16 packs two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pack_b32_f16(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x40003c00, f"Expected 0x40003c00, got 0x{result:08x}")
-
-  def test_v_pack_b32_f16_with_cvt(self):
-    """V_PACK_B32_F16 after V_CVT_F16_F32 conversions."""
-    instructions = [
-      s_mov_b32(s[0], 0x3f800000),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cvt_f16_f32_e32(v[2], v[0]),
-      v_cvt_f16_f32_e32(v[3], v[1]),
-      v_pack_b32_f16(v[4], v[2], v[3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][4]
-    self.assertEqual(result, 0x3c003c00, f"Expected 0x3c003c00, got 0x{result:08x}")
-
-  def test_v_pack_b32_f16_packed_sources(self):
-    """V_PACK_B32_F16 with packed f16 sources (reads lo halves)."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # hi=2.0, lo=1.0
-      s_mov_b32(s[1], 0x44004200),  # hi=4.0, lo=3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pack_b32_f16(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    # Expected: hi=v1.lo=0x4200 (3.0), lo=v0.lo=0x3c00 (1.0) -> 0x42003c00
-    self.assertEqual(result, 0x42003c00, f"Expected 0x42003c00, got 0x{result:08x}")
-
-  def test_v_pack_b32_f16_opsel_lo_hi(self):
-    """V_PACK_B32_F16 with opsel=0b0010 to read lo from src0, hi from src1."""
-    inst = v_pack_b32_f16(v[2], v[0], v[1])
-    inst._values['opsel'] = 0b0010
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),
-      s_mov_b32(s[1], 0x44004200),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      inst,
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x44003c00, f"Expected 0x44003c00, got 0x{result:08x}")
-
-  def test_v_pack_b32_f16_opsel_hi_lo(self):
-    """V_PACK_B32_F16 with opsel=0b0001 to read hi from src0, lo from src1."""
-    inst = v_pack_b32_f16(v[2], v[0], v[1])
-    inst._values['opsel'] = 0b0001
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),
-      s_mov_b32(s[1], 0x44004200),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      inst,
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x42004000, f"Expected 0x42004000, got 0x{result:08x}")
-
-  def test_v_pack_b32_f16_zeros(self):
-    """V_PACK_B32_F16 with zero values."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      v_pack_b32_f16(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0)
-
-  def test_v_pack_b32_f16_both_positive(self):
-    """V_PACK_B32_F16 with positive f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x4200),  # f16 3.0
-      s_mov_b32(s[1], 0x4400),  # f16 4.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pack_b32_f16(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x44004200, f"Expected 0x44004200, got 0x{result:08x}")
-
-
-class TestFmaMix(unittest.TestCase):
-  """Tests for V_FMA_MIX_F32 and V_FMA_MIXLO_F16."""
-
-  def test_v_fma_mix_f32_all_f32_sources(self):
-    """V_FMA_MIX_F32 with all f32 sources."""
-    instructions = [
-      s_mov_b32(s[0], f2i(2.0)),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], f2i(3.0)),
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], f2i(1.0)),
-      v_mov_b32_e32(v[2], s[2]),
-      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = i2f(st.vgpr[0][3])
-    self.assertAlmostEqual(result, 7.0, places=5)
-
-  def test_v_fma_mix_f32_src2_f16_lo(self):
-    """V_FMA_MIX_F32 with src2 as f16 from lo bits."""
-    from extra.assembly.amd.pcode import f32_to_f16
-    f16_2 = f32_to_f16(2.0)
-    instructions = [
-      s_mov_b32(s[0], f2i(1.0)),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], f2i(3.0)),
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], f16_2),
-      v_mov_b32_e32(v[2], s[2]),
-      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = i2f(st.vgpr[0][3])
-    self.assertAlmostEqual(result, 5.0, places=5)
-
-  def test_v_fma_mix_f32_src2_f16_hi(self):
-    """V_FMA_MIX_F32 with src2 as f16 from hi bits."""
-    from extra.assembly.amd.pcode import f32_to_f16
-    f16_2 = f32_to_f16(2.0)
-    val = (f16_2 << 16) | 0
-    instructions = [
-      s_mov_b32(s[0], f2i(1.0)),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], f2i(3.0)),
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], val),
-      v_mov_b32_e32(v[2], s[2]),
-      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=4, opsel_hi=0, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = i2f(st.vgpr[0][3])
-    self.assertAlmostEqual(result, 5.0, places=5)
-
-  def test_v_fma_mix_f32_with_abs(self):
-    """V_FMA_MIX_F32 with abs modifier on src2."""
-    instructions = [
-      s_mov_b32(s[0], f2i(2.0)),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], f2i(3.0)),
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], f2i(-1.0)),
-      v_mov_b32_e32(v[2], s[2]),
-      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=0, neg_hi=4),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = i2f(st.vgpr[0][3])
-    self.assertAlmostEqual(result, 7.0, places=5)
-
-  def test_v_fma_mixlo_f16(self):
-    """V_FMA_MIXLO_F16 writes to low 16 bits of destination."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], f2i(2.0)),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], f2i(3.0)),
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], f2i(1.0)),
-      v_mov_b32_e32(v[2], s[2]),
-      s_mov_b32(s[3], 0xdead0000),
-      v_mov_b32_e32(v[3], s[3]),
-      VOP3P(VOP3POp.V_FMA_MIXLO_F16, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][3] & 0xffff)
-    hi = (st.vgpr[0][3] >> 16) & 0xffff
-    self.assertAlmostEqual(lo, 7.0, places=1)
-    self.assertEqual(hi, 0xdead, f"hi should be preserved, got 0x{hi:04x}")
-
-  def test_v_fma_mixlo_f16_all_f32_sources(self):
-    """V_FMA_MIXLO_F16 with all f32 sources."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], f2i(1.0)),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], f2i(2.0)),
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], f2i(3.0)),
-      v_mov_b32_e32(v[2], s[2]),
-      v_mov_b32_e32(v[3], 0),
-      VOP3P(VOP3POp.V_FMA_MIXLO_F16, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][3] & 0xffff)
-    # 1*2+3 = 5
-    self.assertAlmostEqual(lo, 5.0, places=1)
-
-  def test_v_fma_mixlo_f16_sin_case(self):
-    """V_FMA_MIXLO_F16 case from sin kernel."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0x3f800000),  # f32 1.0
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[1], 0xaf05a309),  # f32 tiny negative
-      s_mov_b32(s[6], s[1]),
-      s_mov_b32(s[2], 0xc0490fdb),  # f32 -π
-      v_mov_b32_e32(v[5], s[2]),
-      s_mov_b32(s[3], 0x3f800000),
-      v_mov_b32_e32(v[3], s[3]),
-      VOP3P(VOP3POp.V_FMA_MIXLO_F16, vdst=v[3], src0=v[3], src1=s[6], src2=v[5], opsel=0, opsel_hi=0, opsel_hi2=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][3] & 0xffff)
-    self.assertAlmostEqual(lo, -3.14159, delta=0.01)
-
-
-class TestVOP3P(unittest.TestCase):
-  """Tests for VOP3P packed 16-bit operations."""
-
-  def test_v_pk_add_f16_basic(self):
-    """V_PK_ADD_F16 adds two packed f16 values."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # hi=2.0, lo=1.0
-      s_mov_b32(s[1], 0x44004200),  # hi=4.0, lo=3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pk_add_f16(v[2], v[0], v[1], opsel_hi=3, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
-    self.assertAlmostEqual(lo, 4.0, places=2)
-    self.assertAlmostEqual(hi, 6.0, places=2)
-
-  def test_v_pk_mul_f16_basic(self):
-    """V_PK_MUL_F16 multiplies two packed f16 values."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0x42004000),  # hi=3.0, lo=2.0
-      s_mov_b32(s[1], 0x45004400),  # hi=5.0, lo=4.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pk_mul_f16(v[2], v[0], v[1], opsel_hi=3, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
-    self.assertAlmostEqual(lo, 8.0, places=1)
-    self.assertAlmostEqual(hi, 15.0, places=1)
-
-  def test_v_pk_fma_f16_basic(self):
-    """V_PK_FMA_F16: D = A * B + C for packed f16."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0x42004000),  # A: hi=3.0, lo=2.0
-      s_mov_b32(s[1], 0x45004400),  # B: hi=5.0, lo=4.0
-      s_mov_b32(s[2], 0x3c003c00),  # C: hi=1.0, lo=1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      v_pk_fma_f16(v[3], v[0], v[1], v[2], opsel_hi=3, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][3]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
-    self.assertAlmostEqual(lo, 9.0, places=1)   # 2*4+1
-    self.assertAlmostEqual(hi, 16.0, places=0)  # 3*5+1
-
-  def test_v_pk_add_f16_with_inline_constant(self):
-    """V_PK_ADD_F16 with inline constant POS_ONE (1.0).
-    Inline constants for VOP3P are f16 values in the low 16 bits only.
-    hi half of inline constant is 0, so hi result = v0.hi + 0 = 1.0.
-    """
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0x3c003c00),  # packed f16: hi=1.0, lo=1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_pk_add_f16(v[1], v[0], SrcEnum.POS_ONE, opsel_hi=3, opsel_hi2=1),  # Add inline constant 1.0
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
-    # lo = 1.0 + 1.0 = 2.0, hi = 1.0 + 0.0 = 1.0 (inline const hi half is 0)
-    self.assertAlmostEqual(lo, 2.0, places=2)
-    self.assertAlmostEqual(hi, 1.0, places=2)
-
-  def test_v_pk_mul_f16_with_inline_constant(self):
-    """V_PK_MUL_F16 with inline constant POS_TWO (2.0).
-    Inline constant has value only in low 16 bits, hi is 0.
-    """
-    from extra.assembly.amd.pcode import _f16
-    # v0 = packed (3.0, 4.0), multiply by POS_TWO
-    # lo = 3.0 * 2.0 = 6.0, hi = 4.0 * 0.0 = 0.0 (inline const hi is 0)
-    instructions = [
-      s_mov_b32(s[0], 0x44004200),  # packed f16: hi=4.0, lo=3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_pk_mul_f16(v[1], v[0], SrcEnum.POS_TWO, opsel_hi=3, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
-    self.assertAlmostEqual(lo, 6.0, places=1)
-    self.assertAlmostEqual(hi, 0.0, places=1)
-
-
-class TestWMMA(unittest.TestCase):
-  """Tests for WMMA (Wave Matrix Multiply-Accumulate) instructions."""
-
-  def test_v_wmma_f32_16x16x16_f16_all_ones(self):
-    """V_WMMA_F32_16X16X16_F16 with all ones produces 16.0."""
-    instructions = []
-    instructions.append(s_mov_b32(s[0], 0x3c003c00))  # packed f16 1.0
-    for i in range(16, 32):
-      instructions.append(v_mov_b32_e32(v[i], s[0]))
-    for i in range(8):
-      instructions.append(v_mov_b32_e32(v[i], 0))
-    instructions.append(v_wmma_f32_16x16x16_f16(v[0], v[16], v[24], v[0]))
-    st = run_program(instructions, n_lanes=32)
-    expected = f2i(16.0)
-    for lane in range(32):
-      for reg in range(8):
-        result = st.vgpr[lane][reg]
-        self.assertEqual(result, expected, f"v[{reg}] lane {lane}: expected 16.0, got {i2f(result)}")
-
-  def test_v_wmma_f32_16x16x16_f16_with_accumulator(self):
-    """V_WMMA_F32_16X16X16_F16 with non-zero accumulator."""
-    instructions = []
-    instructions.append(s_mov_b32(s[0], 0x3c003c00))
-    instructions.append(s_mov_b32(s[1], f2i(5.0)))
-    for i in range(16, 32):
-      instructions.append(v_mov_b32_e32(v[i], s[0]))
-    for i in range(8):
-      instructions.append(v_mov_b32_e32(v[i], s[1]))
-    instructions.append(v_wmma_f32_16x16x16_f16(v[0], v[16], v[24], v[0]))
-    st = run_program(instructions, n_lanes=32)
-    expected = f2i(21.0)  # 16 + 5
-    for lane in range(32):
-      for reg in range(8):
-        result = st.vgpr[lane][reg]
-        self.assertEqual(result, expected, f"v[{reg}] lane {lane}: expected 21.0, got {i2f(result)}")
-
-
-class TestSpecialOps(unittest.TestCase):
-  """Tests for special operations (SAD, PERM, DOT2)."""
-
-  def test_v_sad_u8_basic(self):
-    """V_SAD_U8 computes sum of absolute differences."""
-    instructions = [
-      s_mov_b32(s[0], 0x04030201),  # bytes: 1, 2, 3, 4
-      s_mov_b32(s[1], 0x05040302),  # bytes: 2, 3, 4, 5
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], 0),
-      v_sad_u8(v[3], v[0], v[1], v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # |1-2| + |2-3| + |3-4| + |4-5| = 1 + 1 + 1 + 1 = 4
-    self.assertEqual(st.vgpr[0][3], 4)
-
-  def test_v_sad_u8_identical_bytes(self):
-    """V_SAD_U8 with identical inputs returns accumulator."""
-    instructions = [
-      s_mov_b32(s[0], 0x04030201),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 10),
-      v_mov_b32_e32(v[2], s[1]),
-      v_sad_u8(v[3], v[0], v[0], v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Same inputs -> SAD = 0, result = accumulator = 10
-    self.assertEqual(st.vgpr[0][3], 10)
-
-  def test_v_sad_u16_basic(self):
-    """V_SAD_U16 computes sum of absolute differences of u16 pairs."""
-    instructions = [
-      s_mov_b32(s[0], 0x00030001),  # hi=3, lo=1
-      s_mov_b32(s[1], 0x00050002),  # hi=5, lo=2
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], 0),
-      v_sad_u16(v[3], v[0], v[1], v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # |1-2| + |3-5| = 1 + 2 = 3
-    self.assertEqual(st.vgpr[0][3], 3)
-
-  def test_v_sad_u32_basic(self):
-    """V_SAD_U32 computes absolute difference of u32 values."""
-    instructions = [
-      s_mov_b32(s[0], 100),
-      s_mov_b32(s[1], 70),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], 0),
-      v_sad_u32(v[3], v[0], v[1], v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # |100-70| = 30
-    self.assertEqual(st.vgpr[0][3], 30)
-
-  def test_v_msad_u8_masked(self):
-    """V_MSAD_U8 masked SAD operation."""
-    instructions = [
-      s_mov_b32(s[0], 0x04030201),
-      s_mov_b32(s[1], 0x05040302),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], 0),
-      v_msad_u8(v[3], v[0], v[1], v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # V_MSAD_U8 skips bytes where src0 is 0
-    # Since no bytes are 0, result same as V_SAD_U8 = 4
-    self.assertEqual(st.vgpr[0][3], 4)
-
-  def test_v_perm_b32_select_bytes(self):
-    """V_PERM_B32 selects bytes from two sources.
-
-    V_PERM_B32 concatenates {S1, S0} as a 64-bit value with S1 in low 32 bits.
-    Selector byte values 0-3 select from S1, values 4-7 select from S0.
-    """
-    instructions = [
-      s_mov_b32(s[0], 0x44332211),  # src0: bytes 4-7 in 64-bit view
-      s_mov_b32(s[1], 0x88776655),  # src1: bytes 0-3 in 64-bit view
-      s_mov_b32(s[2], 0x07060504),  # select bytes 4,5,6,7 (from src0)
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_perm_b32(v[2], v[0], v[1], s[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x44332211)
-
-  def test_v_dot2_f32_bf16_basic(self):
-    """V_DOT2_F32_BF16 computes dot product of bf16 pairs."""
-    # bf16 1.0 = 0x3f80, bf16 2.0 = 0x4000
-    instructions = [
-      s_mov_b32(s[0], 0x3f803f80),  # packed bf16: lo=1.0, hi=1.0
-      s_mov_b32(s[1], 0x40003f80),  # packed bf16: lo=1.0, hi=2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], 0),
-      v_dot2_f32_bf16(v[3], v[0], v[1], v[2], opsel_hi=3, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # 1.0*1.0 + 1.0*2.0 + 0 = 3.0
-    result = i2f(st.vgpr[0][3])
-    self.assertAlmostEqual(result, 3.0, places=4)
-
-
-class TestPackedMixedSigns(unittest.TestCase):
-  """Tests for packed operations with mixed sign values."""
-
-  def test_pk_add_f16_mixed_signs(self):
-    """V_PK_ADD_F16 with mixed positive/negative values."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0xc0003c00),  # packed: hi=-2.0, lo=1.0
-      s_mov_b32(s[1], 0x3c003c00),  # packed: hi=1.0, lo=1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pk_add_f16(v[2], v[0], v[1], opsel_hi=3, opsel_hi2=1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
-    self.assertAlmostEqual(lo, 2.0, places=2)   # 1.0 + 1.0
-    self.assertAlmostEqual(hi, -1.0, places=2)  # -2.0 + 1.0
-
-  def test_pk_mul_f16_zero(self):
-    """V_PK_MUL_F16 with zero."""
-    from extra.assembly.amd.pcode import _f16
-    instructions = [
-      s_mov_b32(s[0], 0x40004000),  # packed: 2.0, 2.0
-      s_mov_b32(s[1], 0x00000000),  # packed: 0.0, 0.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_pk_mul_f16(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2]
-    self.assertEqual(result, 0x00000000, "2.0 * 0.0 should be 0.0")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,486 +0,0 @@
-"""Tests for VOPC instructions - vector compare operations.
-
-Includes: v_cmp_class_f32, v_cmp_class_f16, v_cmp_eq_*, v_cmp_lt_*, v_cmp_gt_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-VCC = 106  # SGPR index for VCC_LO
-
-class TestCmpClass(unittest.TestCase):
-  """Tests for V_CMP_CLASS_F32 float classification."""
-
-  def test_cmp_class_quiet_nan(self):
-    """V_CMP_CLASS_F32 detects quiet NaN."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000010),  # bit 1 = quiet NaN
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect quiet NaN")
-
-  def test_cmp_class_signaling_nan(self):
-    """V_CMP_CLASS_F32 detects signaling NaN."""
-    signal_nan = 0x7f800001
-    instructions = [
-      s_mov_b32(s[0], signal_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000001),  # bit 0 = signaling NaN
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect signaling NaN")
-
-  def test_cmp_class_positive_inf(self):
-    """V_CMP_CLASS_F32 detects +inf."""
-    pos_inf = 0x7f800000
-    instructions = [
-      s_mov_b32(s[0], pos_inf),
-      s_mov_b32(s[1], 0b1000000000),  # bit 9 = +inf
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect +inf")
-
-  def test_cmp_class_negative_inf(self):
-    """V_CMP_CLASS_F32 detects -inf."""
-    neg_inf = 0xff800000
-    instructions = [
-      s_mov_b32(s[0], neg_inf),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000100),  # bit 2 = -inf
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect -inf")
-
-  def test_cmp_class_normal_positive(self):
-    """V_CMP_CLASS_F32 detects positive normal."""
-    instructions = [
-      v_mov_b32_e32(v[0], 1.0),
-      s_mov_b32(s[1], 0b0100000000),  # bit 8 = positive normal
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive normal")
-
-  def test_cmp_class_normal_negative(self):
-    """V_CMP_CLASS_F32 detects negative normal."""
-    instructions = [
-      v_mov_b32_e32(v[0], -1.0),
-      v_mov_b32_e32(v[1], 0b0000001000),  # bit 3 = negative normal
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative normal")
-
-  def test_cmp_class_quiet_nan_not_signaling(self):
-    """Quiet NaN does not match signaling NaN mask."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000001),  # bit 0 = signaling NaN only
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "Quiet NaN should not match signaling mask")
-
-  def test_cmp_class_signaling_nan_not_quiet(self):
-    """Signaling NaN does not match quiet NaN mask."""
-    signal_nan = 0x7f800001
-    instructions = [
-      s_mov_b32(s[0], signal_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000010),  # bit 1 = quiet NaN only
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "Signaling NaN should not match quiet mask")
-
-  def test_v_cmp_sets_vcc_bits(self):
-    """V_CMP_EQ sets VCC bits based on per-lane comparison."""
-    instructions = [
-      s_mov_b32(s[0], 5),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cmp_eq_u32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should match")
-
-
-class TestCmpClassF16(unittest.TestCase):
-  """Tests for V_CMP_CLASS_F16 float classification.
-
-  Class bit mapping:
-    bit 0 = signaling NaN
-    bit 1 = quiet NaN
-    bit 2 = -infinity
-    bit 3 = -normal
-    bit 4 = -denormal
-    bit 5 = -zero
-    bit 6 = +zero
-    bit 7 = +denormal
-    bit 8 = +normal
-    bit 9 = +infinity
-  """
-
-  def test_cmp_class_f16_positive_zero(self):
-    """V_CMP_CLASS_F16: +zero matches bit 6."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0x0000),  # f16 +0.0
-      v_mov_b32_e32(v[1], 0x40),     # bit 6 = +zero
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive zero")
-
-  def test_cmp_class_f16_negative_zero(self):
-    """V_CMP_CLASS_F16: -zero matches bit 5."""
-    instructions = [
-      s_mov_b32(s[0], 0x8000),       # f16 -0.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x20),     # bit 5 = -zero
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative zero")
-
-  def test_cmp_class_f16_positive_normal(self):
-    """V_CMP_CLASS_F16: +1.0 (normal) matches bit 8."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),       # f16 +1.0
-      s_mov_b32(s[1], 0x100),        # bit 8 = +normal
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive normal")
-
-  def test_cmp_class_f16_negative_normal(self):
-    """V_CMP_CLASS_F16: -1.0 (normal) matches bit 3."""
-    instructions = [
-      s_mov_b32(s[0], 0xbc00),       # f16 -1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x08),     # bit 3 = -normal
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative normal")
-
-  def test_cmp_class_f16_positive_infinity(self):
-    """V_CMP_CLASS_F16: +inf matches bit 9."""
-    instructions = [
-      s_mov_b32(s[0], 0x7c00),       # f16 +inf
-      s_mov_b32(s[1], 0x200),        # bit 9 = +inf
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive infinity")
-
-  def test_cmp_class_f16_negative_infinity(self):
-    """V_CMP_CLASS_F16: -inf matches bit 2."""
-    instructions = [
-      s_mov_b32(s[0], 0xfc00),       # f16 -inf
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x04),     # bit 2 = -inf
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative infinity")
-
-  def test_cmp_class_f16_quiet_nan(self):
-    """V_CMP_CLASS_F16: quiet NaN matches bit 1."""
-    instructions = [
-      s_mov_b32(s[0], 0x7e00),       # f16 quiet NaN
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x02),     # bit 1 = quiet NaN
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect quiet NaN")
-
-  def test_cmp_class_f16_signaling_nan(self):
-    """V_CMP_CLASS_F16: signaling NaN matches bit 0."""
-    instructions = [
-      s_mov_b32(s[0], 0x7c01),       # f16 signaling NaN
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x01),     # bit 0 = signaling NaN
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect signaling NaN")
-
-  def test_cmp_class_f16_positive_denormal(self):
-    """V_CMP_CLASS_F16: positive denormal matches bit 7."""
-    instructions = [
-      v_mov_b32_e32(v[0], 1),        # f16 +denormal (0x0001)
-      v_mov_b32_e32(v[1], 0x80),     # bit 7 = +denormal
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive denormal")
-
-  def test_cmp_class_f16_negative_denormal(self):
-    """V_CMP_CLASS_F16: negative denormal matches bit 4."""
-    instructions = [
-      s_mov_b32(s[0], 0x8001),       # f16 -denormal
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x10),     # bit 4 = -denormal
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative denormal")
-
-  def test_cmp_class_f16_combined_mask_zeros(self):
-    """V_CMP_CLASS_F16: mask 0x60 covers both +zero and -zero."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),         # f16 +0.0
-      v_mov_b32_e32(v[1], 0x60),      # bits 5 and 6 (+-zero)
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with mask 0x60")
-
-  def test_cmp_class_f16_combined_mask_1f8(self):
-    """V_CMP_CLASS_F16: mask 0x1f8 covers -normal,-denorm,-zero,+zero,+denorm,+normal.
-
-    This is the exact mask used in the f16 sin kernel at PC=46.
-    """
-    instructions = [
-      v_mov_b32_e32(v[0], 0),         # f16 +0.0
-      s_mov_b32(s[0], 0x1f8),
-      v_mov_b32_e32(v[1], s[0]),      # mask 0x1f8
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with mask 0x1f8")
-
-  def test_cmp_class_f16_vop3_encoding(self):
-    """V_CMP_CLASS_F16 in VOP3 encoding (v_cmp_class_f16_e64)."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),         # f16 +0.0
-      s_mov_b32(s[0], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with VOP3 encoding")
-
-  def test_cmp_class_f16_vop3_normal_positive(self):
-    """V_CMP_CLASS_F16 VOP3 encoding with +1.0 (normal)."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),        # f16 +1.0
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +1.0 (normal) with mask 0x1f8")
-
-  def test_cmp_class_f16_vop3_nan_fails_mask(self):
-    """V_CMP_CLASS_F16 VOP3: NaN should NOT match mask 0x1f8 (no NaN bits set)."""
-    instructions = [
-      s_mov_b32(s[0], 0x7e00),        # f16 quiet NaN
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "VCC should be 0 for NaN with mask 0x1f8 (no NaN bits)")
-
-  def test_cmp_class_f16_vop3_inf_fails_mask(self):
-    """V_CMP_CLASS_F16 VOP3: +inf should NOT match mask 0x1f8 (no inf bits set)."""
-    instructions = [
-      s_mov_b32(s[0], 0x7c00),        # f16 +inf
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "VCC should be 0 for +inf with mask 0x1f8 (no inf bits)")
-
-
-class TestCmpInt(unittest.TestCase):
-  """Tests for integer comparison operations."""
-
-  def test_v_cmp_eq_u32(self):
-    """V_CMP_EQ_U32 sets VCC bits based on per-lane comparison."""
-    instructions = [
-      s_mov_b32(s[0], 5),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cmp_eq_u32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should match")
-
-  def test_cmp_eq_u16_opsel_lo_lo(self):
-    """V_CMP_EQ_U16 comparing lo halves."""
-    instructions = [
-      s_mov_b32(s[0], 0x12340005),  # lo=5, hi=0x1234
-      s_mov_b32(s[1], 0xABCD0005),  # lo=5, hi=0xABCD
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_eq_u16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Lo halves should be equal")
-
-  def test_cmp_eq_u16_opsel_hi_hi(self):
-    """V_CMP_EQ_U16 comparing hi halves with VOP3 opsel.
-
-    VOPC doesn't have opsel, so we use VOP3 form for hi-half comparisons.
-    VOP3 compares write result to SGPR via vdst field.
-    """
-    instructions = [
-      s_mov_b32(s[2], 0x00051234),  # hi=5, lo=0x1234
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x0005ABCD),  # hi=5, lo=0xABCD
-      v_mov_b32_e32(v[1], s[2]),
-      # opsel=3 means compare hi halves, vdst=v[0] actually writes to s[0]
-      VOP3(VOP3Op.V_CMP_EQ_U16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Result is in sgpr[0], not vcc
-    self.assertEqual(st.sgpr[0] & 1, 1, "Hi halves should be equal: 5==5")
-
-  def test_cmp_eq_u16_opsel_hi_hi_equal(self):
-    """V_CMP_EQ_U16 VOP3 with opsel=3 compares hi halves (equal case)."""
-    instructions = [
-      s_mov_b32(s[2], 0x12340005),  # lo=5, hi=0x1234
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x12340009),  # lo=9, hi=0x1234
-      v_mov_b32_e32(v[1], s[2]),
-      VOP3(VOP3Op.V_CMP_EQ_U16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "hi==hi should be true: 0x1234==0x1234")
-
-  def test_cmp_gt_u16_opsel_hi(self):
-    """V_CMP_GT_U16 VOP3 with opsel=3 compares hi halves."""
-    instructions = [
-      s_mov_b32(s[2], 0x99990005),  # lo=5, hi=0x9999
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x12340005),  # lo=5, hi=0x1234
-      v_mov_b32_e32(v[1], s[2]),
-      VOP3(VOP3Op.V_CMP_GT_U16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "hi>hi should be true: 0x9999>0x1234")
-
-
-class TestCmpFloat(unittest.TestCase):
-  """Tests for float comparison operations."""
-
-  def test_v_cmp_lt_f16_vsrc1_hi(self):
-    """V_CMP_LT_F16 with both operands from high half using VOP3 opsel."""
-    instructions = [
-      s_mov_b32(s[2], 0x3c000000),  # hi=1.0 (f16), lo=0
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x40000000),  # hi=2.0 (f16), lo=0
-      v_mov_b32_e32(v[1], s[2]),
-      # opsel=3 means read hi halves for both src0 and src1
-      VOP3(VOP3Op.V_CMP_LT_F16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Result is in sgpr[0]
-    self.assertEqual(st.sgpr[0] & 1, 1, "1.0 < 2.0 should be true")
-
-  def test_v_cmp_gt_f16_vsrc1_hi(self):
-    """V_CMP_GT_F16 with both operands from high half using VOP3 opsel."""
-    instructions = [
-      s_mov_b32(s[2], 0x40000000),  # hi=2.0 (f16), lo=0
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x3c000000),  # hi=1.0 (f16), lo=0
-      v_mov_b32_e32(v[1], s[2]),
-      # opsel=3 means read hi halves for both src0 and src1
-      VOP3(VOP3Op.V_CMP_GT_F16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Result is in sgpr[0]
-    self.assertEqual(st.sgpr[0] & 1, 1, "2.0 > 1.0 should be true")
-
-  def test_v_cmp_eq_f16_vsrc1_hi_equal(self):
-    """v_cmp_eq_f16 with equal low and high halves."""
-    instructions = [
-      s_mov_b32(s[0], 0x42004200),  # hi=3.0 (0x4200), lo=3.0 (0x4200)
-      v_mov_b32_e32(v[0], s[0]),
-      v_cmp_eq_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Expected vcc=1 (3.0 == 3.0)")
-
-  def test_v_cmp_neq_f16_vsrc1_hi(self):
-    """v_cmp_neq_f16 with different low and high halves."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # hi=2.0 (0x4000), lo=1.0 (0x3c00)
-      v_mov_b32_e32(v[0], s[0]),
-      v_cmp_lg_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Expected vcc=1 (1.0 != 2.0)")
-
-  def test_v_cmp_nge_f16_inf_self(self):
-    """v_cmp_nge_f16 comparing -inf with itself (unordered less than).
-
-    Regression test: -inf < -inf should be false (IEEE 754).
-    """
-    instructions = [
-      s_mov_b32(s[0], 0xFC00FC00),  # both halves = -inf (0xFC00)
-      v_mov_b32_e32(v[0], s[0]),
-      v_cmp_nge_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "Expected vcc=0 (-inf >= -inf)")
-
-  def test_v_cmp_f16_multilane(self):
-    """v_cmp_lt_f16 with vsrc1=v128 across multiple lanes."""
-    instructions = [
-      # Lane 0: v0 = 0x40003c00 (hi=2.0, lo=1.0) -> 1.0 < 2.0 = true
-      # Lane 1: v0 = 0x3c004000 (hi=1.0, lo=2.0) -> 2.0 < 1.0 = false
-      v_mov_b32_e32(v[0], 0x40003c00),  # default
-      v_cmp_eq_u32_e32(1, v[255]),  # vcc = (lane == 1)
-      v_cndmask_b32_e64(v[0], v[0], 0x3c004000, SrcEnum.VCC_LO),
-      v_cmp_lt_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=2)
-    self.assertEqual(st.vcc & 1, 1, "Lane 0: expected vcc=1 (1.0 < 2.0)")
-    self.assertEqual((st.vcc >> 1) & 1, 0, "Lane 1: expected vcc=0 (2.0 < 1.0)")
-
-
-class TestVCCBehavior(unittest.TestCase):
-  """Tests for VCC condition code behavior."""
-
-  def test_vcc_all_lanes_true(self):
-    """VCC should have all bits set when all lanes compare true."""
-    instructions = [
-      v_mov_b32_e32(v[0], 5),
-      v_mov_b32_e32(v[1], 5),
-      v_cmp_eq_u32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=32)
-    self.assertEqual(st.vcc, 0xFFFFFFFF, "All 32 lanes should be true")
-
-  def test_vcc_lane_dependent(self):
-    """VCC should differ per lane based on lane_id comparison."""
-    instructions = [
-      v_mov_b32_e32(v[0], 16),
-      v_cmp_lt_u32_e32(v[255], v[0]),  # lanes 0-15 are < 16
-    ]
-    st = run_program(instructions, n_lanes=32)
-    self.assertEqual(st.vcc & 0xFFFF, 0xFFFF, "Lanes 0-15 should be true")
-    self.assertEqual(st.vcc >> 16, 0x0000, "Lanes 16-31 should be false")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -9,9 +9,10 @@ os.environ["AMD"] = "1"
 os.environ["MOCKGPU"] = "1"
 os.environ["PYTHON_REMU"] = "1"

-from extra.assembly.amd.emu import WaveState, decode_program, WAVE_SIZE, set_valid_mem_ranges, LDSMem
+from extra.assembly.amd.emu import WaveState, decode_program, step_wave, WAVE_SIZE, set_valid_mem_ranges
 from extra.assembly.amd.test.helpers import KernelInfo
-from extra.assembly.amd.test.bench_emu import REMU_PATH
+
+REMU_PATH = Path(__file__).parents[3] / "remu/target/release/libremu.so"

 def _is_f32_nan(bits: int) -> bool:
  """Check if 32-bit value is a NaN (exponent all 1s, mantissa non-zero)."""
@@ -91,15 +92,19 @@ class PythonEmulator:
  def __init__(self):
    self.state: WaveState | None = None
    self.program: dict | None = None
+    self.lds: bytearray | None = None
+    self.n_lanes = 0

  def create(self, kernel: bytes, n_lanes: int):
    self.program = decode_program(kernel)
-    self.state = WaveState(LDSMem(bytearray(65536)), n_lanes)
+    self.state = WaveState()
    self.state.exec_mask = (1 << n_lanes) - 1
+    self.lds = bytearray(65536)
+    self.n_lanes = n_lanes

  def step(self) -> int:
-    assert self.program is not None and self.state is not None
-    return self.program[self.state.pc]._dispatch(self.state, self.program[self.state.pc])
+    assert self.program is not None and self.state is not None and self.lds is not None
+    return step_wave(self.program, self.state, self.lds, self.n_lanes)
  def set_sgpr(self, idx: int, val: int):
    assert self.state is not None
    self.state.sgpr[idx] = val & 0xffffffff
@@ -158,9 +163,8 @@ def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: t
            # Instructions with known Rust emulator bugs - sync Python to Rust after execution
            # v_div_scale/v_div_fixup: Rust has different VCC handling
            # v_cvt_f16_f32: Rust clears high 16 bits, but hardware (and Python) preserves them
-            # s_add_i32/s_sub_i32: Rust has incorrect SCC overflow detection
            sync_after = any(x in inst_str for x in ('v_div_scale_f32', 'v_div_scale_f64', 'v_div_fixup_f32', 'v_div_fixup_f64',
-                                                      'v_cvt_f16_f32', 's_add_i32', 's_sub_i32'))
+                                                      'v_cvt_f16_f32'))
            diffs = rust_before.diff(python_before, n_lanes)
            if diffs:
              trace_lines = []
@@ -393,9 +397,6 @@ class TestTinygradKernels(unittest.TestCase):
    x_np = np.random.randn(16, 10).astype(np.float32)
    self._test_kernel(lambda T: (T(x_np.tolist()).reshape(16,10) + 0).cross_entropy((T(classes).int().reshape(16) + 0)))
  def test_isinf(self): self._test_kernel(lambda T: T([float('-inf'), 0., float('inf'), 1.1]*8).isinf())
-  def test_sin_f64(self):
-    from tinygrad import dtypes
-    self._test_kernel(lambda T: T([2.0], dtype=dtypes.float64).sin())

 if __name__ == "__main__":
  unittest.main()
@@ -3,7 +3,7 @@
 import unittest
 from extra.assembly.amd.autogen.rdna3.ins import *
 from extra.assembly.amd.dsl import encode_src, RawImm
-from extra.assembly.amd.decode import detect_format
+from extra.assembly.amd.asm import detect_format

 class TestMUBUF(unittest.TestCase):
  """Test MUBUF (buffer) instructions."""
@@ -21,9 +21,6 @@ class TestIntegration(unittest.TestCase):
    self.assertEqual(repr(self.inst), repr(reasm))
    print(desc)

-  def test_wmma(self):
-    self.inst = v_wmma_f32_16x16x16_f16(v[0:7], v[189:192], v[140:143], v[0:7])
-
  def test_load_b128(self):
    self.inst = s_load_b128(s[4:7], s[0:1], NULL, 0)

@@ -1,122 +1,201 @@
 #!/usr/bin/env python3
-"""Test AMD assembler/disassembler against LLVM test vectors."""
-import unittest, re, subprocess, functools
+"""Test RDNA3 assembler/disassembler against LLVM test vectors."""
+import unittest, re, subprocess
 from tinygrad.helpers import fetch
-from extra.assembly.amd.asm import asm, disasm
-from extra.assembly.amd.decode import decode_inst, detect_format
+from extra.assembly.amd.autogen.rdna3.ins import *
+from extra.assembly.amd.asm import asm
 from extra.assembly.amd.test.helpers import get_llvm_mc

-LLVM_BASE = "https://raw.githubusercontent.com/llvm/llvm-project/llvmorg-21.1.0/llvm/test/MC/AMDGPU"
+LLVM_BASE = "https://raw.githubusercontent.com/llvm/llvm-project/main/llvm/test/MC/AMDGPU"

-RDNA_FILES = ['gfx11_asm_sop1.s', 'gfx11_asm_sop2.s', 'gfx11_asm_sopp.s', 'gfx11_asm_sopk.s', 'gfx11_asm_sopc.s',
-  'gfx11_asm_vop1.s', 'gfx11_asm_vop2.s', 'gfx11_asm_vopc.s', 'gfx11_asm_vop3.s', 'gfx11_asm_vop3p.s', 'gfx11_asm_vinterp.s',
-  'gfx11_asm_vopd.s', 'gfx11_asm_vopcx.s', 'gfx11_asm_vop3_from_vop1.s', 'gfx11_asm_vop3_from_vop2.s', 'gfx11_asm_vop3_from_vopc.s',
-  'gfx11_asm_vop3_from_vopcx.s', 'gfx11_asm_ds.s', 'gfx11_asm_smem.s', 'gfx11_asm_flat.s', 'gfx11_asm_mubuf.s', 'gfx11_asm_mtbuf.s',
-  'gfx11_asm_mimg.s', 'gfx11_asm_wmma.s', 'gfx11_asm_vop3_features.s', 'gfx11_asm_vop3p_features.s', 'gfx11_asm_vopd_features.s',
-  'gfx11_asm_vop3_alias.s', 'gfx11_asm_vop3p_alias.s', 'gfx11_asm_vopc_alias.s', 'gfx11_asm_vopcx_alias.s', 'gfx11_asm_vinterp_alias.s',
-  'gfx11_asm_smem_alias.s', 'gfx11_asm_mubuf_alias.s', 'gfx11_asm_mtbuf_alias.s']
-# CDNA test files - includes gfx9 files for shared instructions, plus gfx90a/gfx942 specific files
-# gfx90a_ldst_acc.s has MIMG mixed in, filtered via is_mimg check
-CDNA_FILES = ['gfx9_asm_sop1.s', 'gfx9_asm_sop2.s', 'gfx9_asm_sopp.s', 'gfx9_asm_sopk.s', 'gfx9_asm_sopc.s',
-  'gfx9_asm_vop1.s', 'gfx9_asm_vop2.s', 'gfx9_asm_vopc.s', 'gfx9_asm_vop3.s', 'gfx9_asm_vop3p.s',
-  'gfx9_asm_ds.s', 'gfx9_asm_flat.s', 'gfx9_asm_smem.s', 'gfx9_asm_mubuf.s', 'gfx9_asm_mtbuf.s',
-  'gfx90a_ldst_acc.s', 'gfx90a_asm_features.s', 'flat-scratch-gfx942.s', 'gfx942_asm_features.s',
-  'mai-gfx90a.s', 'mai-gfx942.s']
-# RDNA4 (gfx12) test files - excludes alias/err/fake16/dpp files, and vimage/vsample (not supported)
-# NOTE: vflat/vdsdir excluded - not implemented; features.s has mixed formats
-RDNA4_FILES = ['gfx12_asm_sop1.s', 'gfx12_asm_sop2.s', 'gfx12_asm_sopp.s', 'gfx12_asm_sopk.s', 'gfx12_asm_sopc.s',
-  'gfx12_asm_vop1.s', 'gfx12_asm_vop2.s', 'gfx12_asm_vopc.s', 'gfx12_asm_vopcx.s', 'gfx12_asm_vop3.s', 'gfx12_asm_vop3c.s',
-  'gfx12_asm_vop3cx.s', 'gfx12_asm_vop3p.s', 'gfx12_asm_vop3_from_vop1.s', 'gfx12_asm_vop3_from_vop2.s',
-  'gfx12_asm_vop3p_features.s', 'gfx12_asm_vopd.s', 'gfx12_asm_vopd_features.s',
-  'gfx12_asm_ds.s', 'gfx12_asm_smem.s',
-  'gfx12_asm_vbuffer_mubuf.s', 'gfx12_asm_vbuffer_mtbuf.s', 'gfx12_asm_wmma_w32.s', 'gfx12_asm_exp.s']
+# Format info: (filename, format_class, op_enum)
+LLVM_TEST_FILES = {
+  # Scalar ALU
+  'sop1': ('gfx11_asm_sop1.s', SOP1, SOP1Op),
+  'sop2': ('gfx11_asm_sop2.s', SOP2, SOP2Op),
+  'sopp': ('gfx11_asm_sopp.s', SOPP, SOPPOp),
+  'sopk': ('gfx11_asm_sopk.s', SOPK, SOPKOp),
+  'sopc': ('gfx11_asm_sopc.s', SOPC, SOPCOp),
+  # Vector ALU
+  'vop1': ('gfx11_asm_vop1.s', VOP1, VOP1Op),
+  'vop2': ('gfx11_asm_vop2.s', VOP2, VOP2Op),
+  'vopc': ('gfx11_asm_vopc.s', VOPC, VOPCOp),
+  'vop3': ('gfx11_asm_vop3.s', VOP3, VOP3Op),
+  'vop3p': ('gfx11_asm_vop3p.s', VOP3P, VOP3POp),
+  'vop3sd': ('gfx11_asm_vop3.s', VOP3SD, VOP3SDOp),  # VOP3SD shares file with VOP3
+  'vinterp': ('gfx11_asm_vinterp.s', VINTERP, VINTERPOp),
+  'vopd': ('gfx11_asm_vopd.s', VOPD, VOPDOp),
+  'vopcx': ('gfx11_asm_vopcx.s', VOPC, VOPCOp),  # VOPCX uses VOPC format
+  # VOP3 promotions (VOP1/VOP2/VOPC promoted to VOP3 encoding)
+  'vop3_from_vop1': ('gfx11_asm_vop3_from_vop1.s', VOP3, VOP3Op),
+  'vop3_from_vop2': ('gfx11_asm_vop3_from_vop2.s', VOP3, VOP3Op),
+  'vop3_from_vopc': ('gfx11_asm_vop3_from_vopc.s', VOP3, VOP3Op),
+  'vop3_from_vopcx': ('gfx11_asm_vop3_from_vopcx.s', VOP3, VOP3Op),
+  # Memory
+  'ds': ('gfx11_asm_ds.s', DS, DSOp),
+  'smem': ('gfx11_asm_smem.s', SMEM, SMEMOp),
+  'flat': ('gfx11_asm_flat.s', FLAT, FLATOp),
+  'mubuf': ('gfx11_asm_mubuf.s', MUBUF, MUBUFOp),
+  'mtbuf': ('gfx11_asm_mtbuf.s', MTBUF, MTBUFOp),
+  'mimg': ('gfx11_asm_mimg.s', MIMG, MIMGOp),
+  # WMMA (matrix multiply)
+  'wmma': ('gfx11_asm_wmma.s', VOP3P, VOP3POp),
+  # Additional features
+  'vop3_features': ('gfx11_asm_vop3_features.s', VOP3, VOP3Op),
+  'vop3p_features': ('gfx11_asm_vop3p_features.s', VOP3P, VOP3POp),
+  'vopd_features': ('gfx11_asm_vopd_features.s', VOPD, VOPDOp),
+  # Alias files (alternative mnemonics)
+  'vop3_alias': ('gfx11_asm_vop3_alias.s', VOP3, VOP3Op),
+  'vop3p_alias': ('gfx11_asm_vop3p_alias.s', VOP3P, VOP3POp),
+  'vopc_alias': ('gfx11_asm_vopc_alias.s', VOPC, VOPCOp),
+  'vopcx_alias': ('gfx11_asm_vopcx_alias.s', VOPC, VOPCOp),
+  'vinterp_alias': ('gfx11_asm_vinterp_alias.s', VINTERP, VINTERPOp),
+  'smem_alias': ('gfx11_asm_smem_alias.s', SMEM, SMEMOp),
+  'mubuf_alias': ('gfx11_asm_mubuf_alias.s', MUBUF, MUBUFOp),
+  'mtbuf_alias': ('gfx11_asm_mtbuf_alias.s', MTBUF, MTBUFOp),
+}

-def _is_mimg(data: bytes) -> bool: return (int.from_bytes(data[:4], 'little') >> 26) & 0x3f == 0b111100
-
-def _parse_llvm_tests(text: str, pattern: str) -> list[tuple[str, bytes]]:
-  tests = []
-  for block in text.split('\n\n'):
-    asm_text, encoding = None, None
-    for line in block.split('\n'):
-      line = line.strip()
-      if not line or line.startswith(('.', ';')): continue
-      if not line.startswith('//'):
-        asm_text = line.split('//')[0].strip() or asm_text
-      if m := re.search(pattern + r'[^:]*:.*?(?:encoding:\s*)?\[(0x[0-9a-f,x\s]+)\]', line, re.I):
-        encoding = m.group(1).replace('0x', '').replace(',', '').replace(' ', '')
-    if asm_text and encoding:
-      try: tests.append((asm_text, bytes.fromhex(encoding)))
-      except ValueError: pass
+def parse_llvm_tests(text: str) -> list[tuple[str, bytes]]:
+  """Parse LLVM test format into (asm, expected_bytes) pairs."""
+  tests, lines = [], text.split('\n')
+  for i, line in enumerate(lines):
+    line = line.strip()
+    if not line or line.startswith(('//', '.', ';')): continue
+    asm_text = line.split('//')[0].strip()
+    if not asm_text: continue
+    for j in range(i, min(i + 3, len(lines))):
+      # Match GFX11, W32, or W64 encodings (all valid for gfx11)
+      # Format 1: "// GFX11: v_foo ... ; encoding: [0x01,0x02,...]"
+      # Format 2: "// GFX11: [0x01,0x02,...]" (used by DS, older files)
+      if m := re.search(r'(?:GFX11|W32|W64)[^:]*:.*?encoding:\s*\[(.*?)\]', lines[j]):
+        hex_bytes = m.group(1).replace('0x', '').replace(',', '').replace(' ', '')
+      elif m := re.search(r'(?:GFX11|W32|W64)[^:]*:\s*\[(0x[0-9a-fA-F,x\s]+)\]', lines[j]):
+        hex_bytes = m.group(1).replace('0x', '').replace(',', '').replace(' ', '')
+      else:
+        continue
+      if hex_bytes:
+        try: tests.append((asm_text, bytes.fromhex(hex_bytes)))
+        except ValueError: pass
+      break
  return tests

-@functools.cache
-def _get_tests(f: str, arch: str) -> list[tuple[str, bytes]]:
-  text = fetch(f"{LLVM_BASE}/{f}").read_bytes().decode('utf-8', errors='ignore')
-  if arch == "rdna3":
-    tests = _parse_llvm_tests(text, r'(?:GFX11|W32|W64)')
-  elif arch == "rdna4":
-    # Match GFX12 but not GFX1250 (which has different lit64 encoding)
-    tests = _parse_llvm_tests(text, r'(?:GFX12(?!50)|W32|W64)')
-  elif 'gfx90a' in f or 'gfx942' in f:
-    tests = _parse_llvm_tests(text, r'(?:GFX90A|GFX942)')
-  else:
-    tests = _parse_llvm_tests(text, r'(?:VI9|GFX9|CHECK)')
-  return [(a, d) for a, d in tests if not _is_mimg(d)] if arch == "cdna" else tests
+def try_assemble(text: str):
+  """Try to assemble instruction text, return bytes or None on failure."""
+  try: return asm(text).to_bytes()
+  except: return None

-def _compile_asm_batch(instrs: list[str], arch: str = "rdna3") -> list[bytes]:
+def compile_asm_batch(instrs: list[str]) -> list[bytes]:
+  """Compile multiple instructions with a single llvm-mc call."""
  if not instrs: return []
-  mcpu = {'rdna3': 'gfx1100', 'rdna4': 'gfx1200'}.get(arch, 'gfx1100')
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
-    input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True, timeout=30)
-  if result.returncode != 0: raise RuntimeError(f"llvm-mc failed: {result.stderr.strip()}")
-  return [bytes.fromhex(line.split('encoding:')[1].strip()[1:-1].replace('0x', '').replace(',', '').replace(' ', ''))
-          for line in result.stdout.split('\n') if 'encoding:' in line]
+  asm_text = ".text\n" + "\n".join(instrs) + "\n"
+  result = subprocess.run(
+    [get_llvm_mc(), '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+    input=asm_text, capture_output=True, text=True, timeout=30)
+  if result.returncode != 0: raise RuntimeError(f"llvm-mc batch failed: {result.stderr.strip()}")
+  # Parse all encodings from output
+  results = []
+  for line in result.stdout.split('\n'):
+    if 'encoding:' not in line: continue
+    enc = line.split('encoding:')[1].strip()
+    if enc.startswith('[') and enc.endswith(']'):
+      results.append(bytes.fromhex(enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')))
+  if len(results) != len(instrs): raise RuntimeError(f"expected {len(instrs)} encodings, got {len(results)}")
+  return results

-def _make_test(f: str, arch: str, test_type: str):
+class TestLLVM(unittest.TestCase):
+  """Test assembler and disassembler against all LLVM test vectors."""
+  tests: dict[str, list[tuple[str, bytes]]] = {}
+
+  @classmethod
+  def setUpClass(cls):
+    for name, (filename, _, _) in LLVM_TEST_FILES.items():
+      try:
+        data = fetch(f"{LLVM_BASE}/{filename}").read_bytes()
+        cls.tests[name] = parse_llvm_tests(data.decode('utf-8', errors='ignore'))
+      except Exception as e:
+        print(f"Warning: couldn't fetch {filename}: {e}")
+        cls.tests[name] = []
+
+# Generate test methods dynamically for each format
+def _make_asm_test(name):
  def test(self):
-    tests = _get_tests(f, arch)
-    name = f"{arch}_{test_type}_{f}"
-    if test_type == "roundtrip":
-      for _, data in tests:
-        decoded = detect_format(data, arch).from_bytes(data)
-        self.assertEqual(decoded.to_bytes()[:len(data)], data)
-      print(f"{name}: {len(tests)} passed")
-    elif test_type == "asm":
-      passed, skipped = 0, 0
-      for asm_text, expected in tests:
-        try:
-          self.assertEqual(asm(asm_text, arch).to_bytes(), expected)
-          passed += 1
-        except: skipped += 1
-      print(f"{name}: {passed} passed, {skipped} skipped")
-    elif test_type == "disasm":
-      to_test = []
-      for _, data in tests:
-        try:
-          decoded = decode_inst(data, arch)
-          # Skip if roundtrip fails, disasm fails, or op_name is missing (disasm starts with space)
-          if decoded.to_bytes()[:len(data)] == data and (d := disasm(decoded)) and not d.startswith(' '): to_test.append((data, d))
-        except: pass
-      skipped = len(tests) - len(to_test)
-      print(f"{name}: {len(to_test)} passed, {skipped} skipped")
-      if arch in ("rdna3", "rdna4"):
-        self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
-        for (data, _), llvm in zip(to_test, _compile_asm_batch([t[1] for t in to_test], arch)): self.assertEqual(llvm, data)
+    passed, failed, skipped = 0, 0, 0
+    for asm_text, expected in self.tests.get(name, []):
+      result = try_assemble(asm_text)
+      if result is None: skipped += 1
+      elif result == expected: passed += 1
+      else: failed += 1
+    print(f"{name.upper()} asm: {passed} passed, {failed} failed, {skipped} skipped")
+    self.assertEqual(failed, 0)
  return test

-class TestLLVM(unittest.TestCase): pass
+def _make_disasm_test(name):
+  def test(self):
+    _, fmt_cls, op_enum = LLVM_TEST_FILES[name]
+    # VOP3SD opcodes that share encoding with VOP3 (only for vop3sd test, not vopc promotions)
+    vop3sd_opcodes = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770}
+    is_vopc_promotion = name in ('vop3_from_vopc', 'vop3_from_vopcx')
+    undocumented = {'smem': {34, 35}, 'sopk': {22, 23}, 'sopp': {8, 58, 59}}

-for f in RDNA_FILES:
-  setattr(TestLLVM, f"test_rdna3_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "roundtrip"))
-  setattr(TestLLVM, f"test_rdna3_asm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "asm"))
-  setattr(TestLLVM, f"test_rdna3_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "disasm"))
-for f in CDNA_FILES:
-  setattr(TestLLVM, f"test_cdna_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "roundtrip"))
-  setattr(TestLLVM, f"test_cdna_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "disasm"))
-for f in RDNA4_FILES:
-  setattr(TestLLVM, f"test_rdna4_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "roundtrip"))
-  setattr(TestLLVM, f"test_rdna4_asm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "asm"))
-  setattr(TestLLVM, f"test_rdna4_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "disasm"))
+    # First pass: decode all instructions and collect disasm strings
+    to_test: list[tuple[str, bytes, str | None, str | None]] = []  # (asm_text, data, disasm_str, error)
+    skipped = 0
+    for asm_text, data in self.tests.get(name, []):
+      if len(data) > fmt_cls._size(): continue
+      temp_inst = fmt_cls.from_bytes(data)
+      temp_op = temp_inst._values.get('op', 0)
+      temp_op = temp_op.val if hasattr(temp_op, 'val') else temp_op
+      if temp_op in undocumented.get(name, set()): skipped += 1; continue
+      if name == 'sopp':
+        simm16 = temp_inst._values.get('simm16', 0)
+        simm16 = simm16.val if hasattr(simm16, 'val') else simm16
+        sopp_no_imm = {48, 54, 53, 55, 60, 61, 62}
+        if temp_op in sopp_no_imm and simm16 != 0: skipped += 1; continue
+      try:
+        if fmt_cls.__name__ in ('VOP3', 'VOP3SD'):
+          temp = VOP3.from_bytes(data)
+          op_val = temp._values.get('op', 0)
+          op_val = op_val.val if hasattr(op_val, 'val') else op_val
+          is_vop3sd = (op_val in vop3sd_opcodes) and not is_vopc_promotion
+          decoded = VOP3SD.from_bytes(data) if is_vop3sd else VOP3.from_bytes(data)
+          if is_vop3sd: VOP3SDOp(op_val)
+          else: VOP3Op(op_val)
+        else:
+          decoded = fmt_cls.from_bytes(data)
+          op_val = decoded._values.get('op', 0)
+          op_val = op_val.val if hasattr(op_val, 'val') else op_val
+          op_enum(op_val)
+        if decoded.to_bytes()[:len(data)] != data:
+          to_test.append((asm_text, data, None, "decode roundtrip failed"))
+          continue
+        to_test.append((asm_text, data, decoded.disasm(), None))
+      except Exception as e:
+        to_test.append((asm_text, data, None, f"exception: {e}"))
+
+    # Batch compile all disasm strings with single llvm-mc call
+    disasm_strs = [(i, t[2]) for i, t in enumerate(to_test) if t[2] is not None]
+    llvm_results = compile_asm_batch([s for _, s in disasm_strs]) if disasm_strs else []
+    llvm_map = {i: llvm_results[j] for j, (i, _) in enumerate(disasm_strs)}
+
+    # Match results back
+    passed, failed = 0, 0
+    failures: list[str] = []
+    for idx, (asm_text, data, disasm_str, error) in enumerate(to_test):
+      if error:
+        failed += 1; failures.append(f"{error} for {data.hex()}")
+      elif disasm_str is not None and idx in llvm_map:
+        llvm_bytes = llvm_map[idx]
+        if llvm_bytes is not None and llvm_bytes == data: passed += 1
+        elif llvm_bytes is not None: failed += 1; failures.append(f"'{disasm_str}': expected={data.hex()} got={llvm_bytes.hex()}")
+
+    print(f"{name.upper()} disasm: {passed} passed, {failed} failed" + (f", {skipped} skipped" if skipped else ""))
+    if failures[:10]: print("  " + "\n  ".join(failures[:10]))
+    self.assertEqual(failed, 0)
+  return test
+
+for name in LLVM_TEST_FILES:
+  setattr(TestLLVM, f'test_{name}_asm', _make_asm_test(name))
+  setattr(TestLLVM, f'test_{name}_disasm', _make_disasm_test(name))

 if __name__ == "__main__":
  unittest.main()
@@ -20,12 +20,11 @@ runner = get_runner(dev.device, si.ast)
 prg = runner._prg
 lib = bytearray(prg.lib)

-# Find s_endpgm (0xBFB00000) and replace with V_MOVRELD_B32 (op=66) which has no pcode
-# VOP1 encoding: bits[31:25]=0x7E, op=bits[16:9], so op=66 -> 66<<9 = 0x8400
+# Find s_endpgm (0xBFB00000) and replace with invalid SOPP op=127 (0xBFFF0000)
 found = False
 for i in range(0, len(lib) - 4, 4):
  if struct.unpack("<I", lib[i:i+4])[0] == 0xBFB00000:
-    lib[i:i+4] = struct.pack("<I", 0x7E008400)
+    lib[i:i+4] = struct.pack("<I", 0xBFFF0000)
    found = True
    break
 assert found, "s_endpgm not found"
@@ -47,7 +46,8 @@ dev.synchronize()
    elapsed = time.perf_counter() - st

    self.assertNotEqual(result.returncode, 0, "should have raised")
-    self.assertTrue("Error" in result.stderr, f"expected an error in stderr, got: {result.stderr[:500]}")
+    self.assertTrue("NotImplementedError" in result.stderr or "ValueError" in result.stderr,
+                    f"expected NotImplementedError or ValueError in stderr")
    # Should exit immediately, not wait for the full timeout
    self.assertLess(elapsed, 9.0, f"should exit immediately on emulator exception, took {elapsed:.1f}s")

@@ -1,16 +1,12 @@
 #!/usr/bin/env python3
 """Tests for the RDNA3 pseudocode DSL."""
 import unittest
-from extra.assembly.amd.pcode import (Reg, TypedView, TypedView, MASK32, MASK64,
-                                       _f32, _i32, _f16, _i16, f32_to_f16, isNAN, _bf16, _ibf16, bf16_to_f32, f32_to_bf16,
-                                       BYTE_PERMUTE, v_sad_u8, v_msad_u8, _compile_pseudocode, _expr, compile_pseudocode)
+from extra.assembly.amd.pcode import (Reg, TypedView, SliceProxy, MASK32, MASK64,
+                                       _f32, _i32, _f16, _i16, f32_to_f16, _isnan, _bf16, _ibf16, bf16_to_f32, f32_to_bf16,
+                                       BYTE_PERMUTE, v_sad_u8, v_msad_u8)
+from extra.assembly.amd.pdf import compile_pseudocode, _expr
 from extra.assembly.amd.test.helpers import ExecContext
-from extra.assembly.amd.autogen.rdna3.str_pcode import VOP3SDOp_PCODE, VOPCOp_PCODE
-from extra.assembly.amd.autogen.rdna3.enum import VOP3SDOp, VOPCOp
-
-# Compile pseudocode functions on demand for regression tests
-_VOP3SDOp_V_DIV_SCALE_F32 = compile_pseudocode('VOP3SDOp', 'V_DIV_SCALE_F32', VOP3SDOp_PCODE[VOP3SDOp.V_DIV_SCALE_F32])
-_VOPCOp_V_CMP_CLASS_F32 = compile_pseudocode('VOPCOp', 'V_CMP_CLASS_F32', VOPCOp_PCODE[VOPCOp.V_CMP_CLASS_F32])
+from extra.assembly.amd.autogen.rdna3.gen_pcode import _VOP3SDOp_V_DIV_SCALE_F32, _VOPCOp_V_CMP_CLASS_F32

 class TestReg(unittest.TestCase):
  def test_u32_read(self):
@@ -46,7 +42,7 @@ class TestReg(unittest.TestCase):
 class TestTypedView(unittest.TestCase):
  def test_bit_slice(self):
    r = Reg(0xDEADBEEF)
-    # Slices return TypedView which supports .u32, .u16 etc (matching pseudocode like S1.u32[1:0].u32)
+    # Slices return SliceProxy which supports .u32, .u16 etc (matching pseudocode like S1.u32[1:0].u32)
    self.assertEqual(r.u32[7:0].u32, 0xEF)
    self.assertEqual(r.u32[15:8].u32, 0xBE)
    self.assertEqual(r.u32[23:16].u32, 0xAD)
@@ -71,7 +67,7 @@ class TestTypedView(unittest.TestCase):
    # S0.u32[S1.u32[4:0]] - access bit at position from another register
    s0 = Reg(0b11010101)
    s1 = Reg(3)
-    bit_pos = s1.u32[4:0]  # TypedView, int value = 3
+    bit_pos = s1.u32[4:0]  # SliceProxy, int value = 3
    bit_val = s0.u32[int(bit_pos)]  # bit 3 of s0 = 0
    self.assertEqual(int(bit_pos), 3)
    self.assertEqual(bit_val, 0)
@@ -89,7 +85,7 @@ class TestTypedView(unittest.TestCase):
    self.assertFalse(r1.u32 < r2.u32)
    self.assertTrue(r1.u32 != r2.u32)

-class TestTypedView(unittest.TestCase):
+class TestSliceProxy(unittest.TestCase):
  def test_slice_read(self):
    r = Reg(0x56781234)
    self.assertEqual(r[15:0].u16, 0x1234)
@@ -158,19 +154,19 @@ class TestExecContext(unittest.TestCase):
    self.assertEqual(ctx.SCC._val, 0)

  def test_ternary(self):
-    code = _compile_pseudocode("D0.u32 = S0.u32 > S1.u32 ? 1'1U : 1'0U")
+    code = compile_pseudocode("D0.u32 = S0.u32 > S1.u32 ? 1'1U : 1'0U")
    ctx = ExecContext(s0=5, s1=3)
    ctx.run(code)
    self.assertEqual(ctx.D0._val, 1)

  def test_pack(self):
-    code = _compile_pseudocode("D0 = { S1[15:0].u16, S0[15:0].u16 }")
+    code = compile_pseudocode("D0 = { S1[15:0].u16, S0[15:0].u16 }")
    ctx = ExecContext(s0=0x1234, s1=0x5678)
    ctx.run(code)
    self.assertEqual(ctx.D0._val, 0x56781234)

  def test_tmp_with_typed_access(self):
-    code = _compile_pseudocode("""tmp = S0.u32 + S1.u32
+    code = compile_pseudocode("""tmp = S0.u32 + S1.u32
 D0.u32 = tmp.u32""")
    ctx = ExecContext(s0=100, s1=200)
    ctx.run(code)
@@ -178,7 +174,7 @@ D0.u32 = tmp.u32""")

  def test_s_add_u32_pattern(self):
    # Real pseudocode pattern from S_ADD_U32
-    code = _compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
+    code = compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
 SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U
 D0.u32 = tmp.u32""")
    # Test overflow case
@@ -188,7 +184,7 @@ D0.u32 = tmp.u32""")
    self.assertEqual(ctx.SCC._val, 1)  # Carry set

  def test_s_add_u32_no_overflow(self):
-    code = _compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
+    code = compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
 SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U
 D0.u32 = tmp.u32""")
    ctx = ExecContext(s0=100, s1=200)
@@ -210,7 +206,7 @@ D0.u32 = tmp.u32""")

  def test_for_loop(self):
    # CTZ pattern - find first set bit
-    code = _compile_pseudocode("""tmp = -1
+    code = compile_pseudocode("""tmp = -1
 for i in 0 : 31 do
  if S0.u32[i] == 1 then
    tmp = i
@@ -237,13 +233,14 @@ class TestPseudocodeRegressions(unittest.TestCase):
    Bug: when VCC._val == vcc (both 0), VCC wasn't returned, so VCC bits weren't written.
    This caused division to produce wrong results for multiple lanes."""
    # Normal case: 1.0 / 3.0, no scaling needed, VCC should be 0
-    s0 = 0x3f800000  # 1.0
-    s1 = 0x40400000  # 3.0
-    s2 = 0x3f800000  # 1.0 (numerator)
-    result = _VOP3SDOp_V_DIV_SCALE_F32(s0, s1, s2, 0, 0, 0, 0, 0xffffffff, 0, None)
+    S0 = Reg(0x3f800000)  # 1.0
+    S1 = Reg(0x40400000)  # 3.0
+    S2 = Reg(0x3f800000)  # 1.0 (numerator)
+    D0, SCC, VCC, EXEC = Reg(0), Reg(0), Reg(0), Reg(0xffffffff)
+    result = _VOP3SDOp_V_DIV_SCALE_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
    # Must always have VCC in result
    self.assertIn('VCC', result, "V_DIV_SCALE_F32 must always return VCC")
-    self.assertEqual(result['VCC'] & 1, 0, "VCC lane 0 should be 0 when no scaling needed")
+    self.assertEqual(result['VCC']._val & 1, 0, "VCC lane 0 should be 0 when no scaling needed")

  def test_v_cmp_class_f32_detects_quiet_nan(self):
    """V_CMP_CLASS_F32 must correctly identify quiet NaN vs signaling NaN.
@@ -252,28 +249,32 @@ class TestPseudocodeRegressions(unittest.TestCase):
    signal_nan = 0x7f800001  # signaling NaN: exponent=255, bit22=0
    # Test quiet NaN detection (bit 1 in mask)
    s1_quiet = 0b0000000010  # bit 1 = quiet NaN
-    result = _VOPCOp_V_CMP_CLASS_F32(quiet_nan, s1_quiet, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 1, "Should detect quiet NaN with quiet NaN mask")
+    S0, S1, S2, D0, SCC, VCC, EXEC = Reg(quiet_nan), Reg(s1_quiet), Reg(0), Reg(0), Reg(0), Reg(0), Reg(0xffffffff)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 1, "Should detect quiet NaN with quiet NaN mask")
    # Test signaling NaN detection (bit 0 in mask)
    s1_signal = 0b0000000001  # bit 0 = signaling NaN
-    result = _VOPCOp_V_CMP_CLASS_F32(signal_nan, s1_signal, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 1, "Should detect signaling NaN with signaling NaN mask")
+    S0, S1 = Reg(signal_nan), Reg(s1_signal)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 1, "Should detect signaling NaN with signaling NaN mask")
    # Test that quiet NaN doesn't match signaling NaN mask
-    result = _VOPCOp_V_CMP_CLASS_F32(quiet_nan, s1_signal, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 0, "Quiet NaN should not match signaling NaN mask")
+    S0, S1 = Reg(quiet_nan), Reg(s1_signal)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 0, "Quiet NaN should not match signaling NaN mask")
    # Test that signaling NaN doesn't match quiet NaN mask
-    result = _VOPCOp_V_CMP_CLASS_F32(signal_nan, s1_quiet, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 0, "Signaling NaN should not match quiet NaN mask")
+    S0, S1 = Reg(signal_nan), Reg(s1_quiet)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 0, "Signaling NaN should not match quiet NaN mask")

-  def testisNAN_with_typed_view(self):
-    """isNAN must work with TypedView objects, not just Python floats.
-    Bug: isNAN checked isinstance(x, float) which returned False for TypedView."""
+  def test_isnan_with_typed_view(self):
+    """_isnan must work with TypedView objects, not just Python floats.
+    Bug: _isnan checked isinstance(x, float) which returned False for TypedView."""
    nan_reg = Reg(0x7fc00000)  # quiet NaN
    normal_reg = Reg(0x3f800000)  # 1.0
    inf_reg = Reg(0x7f800000)  # +inf
-    self.assertTrue(isNAN(nan_reg.f32), "isNAN should return True for NaN TypedView")
-    self.assertFalse(isNAN(normal_reg.f32), "isNAN should return False for normal TypedView")
-    self.assertFalse(isNAN(inf_reg.f32), "isNAN should return False for inf TypedView")
+    self.assertTrue(_isnan(nan_reg.f32), "_isnan should return True for NaN TypedView")
+    self.assertFalse(_isnan(normal_reg.f32), "_isnan should return False for normal TypedView")
+    self.assertFalse(_isnan(inf_reg.f32), "_isnan should return False for inf TypedView")

 class TestBF16(unittest.TestCase):
  """Tests for BF16 (bfloat16) support."""
@@ -312,7 +313,7 @@ class TestBF16(unittest.TestCase):
    self.assertAlmostEqual(float(r.bf16), 3.0, places=1)

  def test_bf16_slice_property(self):
-    """Test TypedView.bf16 property."""
+    """Test SliceProxy.bf16 property."""
    r = Reg(0x40404040)  # Two bf16 3.0 values
    self.assertAlmostEqual(r[15:0].bf16, 3.0, places=1)
    self.assertAlmostEqual(r[31:16].bf16, 3.0, places=1)
@@ -1,71 +0,0 @@
-#!/usr/bin/env python3
-"""Test pdf.py PDF parser and enum generation."""
-import unittest, tempfile, importlib.util
-from extra.assembly.amd.pdf import extract, extract_tables, extract_enums, extract_pcode, write_enums, PDF_URLS
-
-EXPECTED = {
-  "rdna3": {"pages": 655, "tables": 115, "sop2_ops": 67, "sop2_first": "S_ADD_U32"},
-  "rdna4": {"pages": 711, "tables": 125, "sop2_ops": 74, "sop2_first": "S_ADD_CO_U32"},
-  "cdna":  {"pages": 610, "tables": 104, "sop2_ops": 52, "sop2_first": "S_ADD_U32"},
-}
-
-class TestPDF2(unittest.TestCase):
-  @classmethod
-  def setUpClass(cls):
-    cls.data = {name: extract(url) for name, url in PDF_URLS.items()}
-    cls.tables = {name: extract_tables(pages) for name, pages in cls.data.items()}
-    cls.enums = {name: extract_enums(cls.tables[name]) for name in PDF_URLS}
-    cls.pcode = {name: extract_pcode(cls.data[name], cls.enums[name]) for name in PDF_URLS}
-
-  def test_page_counts(self):
-    for name, exp in EXPECTED.items():
-      self.assertEqual(len(self.data[name]), exp["pages"], f"{name} page count")
-
-  def test_table_counts(self):
-    for name, exp in EXPECTED.items():
-      self.assertEqual(len(self.tables[name]), exp["tables"], f"{name} table count")
-
-  def test_tables_sequential(self):
-    for name in PDF_URLS:
-      nums = sorted(self.tables[name].keys())
-      missing = set(range(1, max(nums) + 1)) - set(nums)
-      self.assertEqual(missing, set(), f"{name} missing tables: {missing}")
-
-  def test_generate_enums(self):
-    for name, exp in EXPECTED.items():
-      with tempfile.NamedTemporaryFile(mode='w', suffix='.py', delete=False) as f:
-        write_enums(self.enums[name], name, f.name)
-        spec = importlib.util.spec_from_file_location("enum", f.name)
-        mod = importlib.util.module_from_spec(spec)
-        spec.loader.exec_module(mod)
-        # Check SOP2Op
-        self.assertTrue(hasattr(mod, 'SOP2Op'), f"{name} missing SOP2Op")
-        self.assertEqual(len(mod.SOP2Op), exp["sop2_ops"], f"{name} SOP2Op count")
-        self.assertEqual(mod.SOP2Op(0).name, exp["sop2_first"], f"{name} SOP2Op first")
-        # Check all enums have at least 2 ops
-        for attr in dir(mod):
-          if attr.endswith('Op'):
-            self.assertGreaterEqual(len(getattr(mod, attr)), 2, f"{name} {attr} has too few ops")
-
-  def test_pcode_rdna3_tricky(self):
-    """Test specific pseudocode patterns that are tricky to extract correctly."""
-    pcode = self.pcode['rdna3']
-    # BUFFER_ATOMIC_MAX_U64: should have 4 statements (not truncated)
-    self.assertEqual(pcode[('BUFFER_ATOMIC_MAX_U64', 72)],
-      'tmp = MEM[ADDR].u64;\nsrc = DATA.u64;\nMEM[ADDR].u64 = src >= tmp ? src : tmp;\nRETURN_DATA.u64 = tmp')
-    # GLOBAL_STORE_B128: should have 4 MEM stores (not truncated)
-    self.assertEqual(pcode[('GLOBAL_STORE_B128', 29)],
-      'MEM[ADDR].b32 = VDATA[31 : 0];\nMEM[ADDR + 4U].b32 = VDATA[63 : 32];\nMEM[ADDR + 8U].b32 = VDATA[95 : 64];\nMEM[ADDR + 12U].b32 = VDATA[127 : 96]')
-    # S_CMOVK_I32: should have full if/endif block
-    self.assertEqual(pcode[('S_CMOVK_I32', 2)],
-      "if SCC then\nD0.i32 = 32'I(signext(SIMM16.i16))\nendif")
-
-  def test_pcode_no_examples(self):
-    """Pseudocode should not contain example lines with '=>'."""
-    for name in PDF_URLS:
-      for (op_name, opcode), code in self.pcode[name].items():
-        # No example lines (test vectors like "S_CTZ_I32_B32(0xaaaaaaaa) => 1")
-        self.assertNotIn('=>', code, f"{name} {op_name} contains example line with '=>'")
-
-if __name__ == "__main__":
-  unittest.main()
@@ -0,0 +1,150 @@
+#!/usr/bin/env python3
+"""Test that PDF parser correctly extracts format fields."""
+import unittest, os
+from extra.assembly.amd.autogen.rdna3.ins import SOP1, SOP2, SOPK, SOPP, VOP1, VOP2, VOP3SD, VOPC, FLAT, VOPD, SOP1Op, SOP2Op, VOP1Op, VOP3Op
+
+# expected formats with key fields and whether they have ENCODING
+EXPECTED_FORMATS = {
+  'DPP16': (['SRC0', 'DPP_CTRL', 'BANK_MASK', 'ROW_MASK'], False),
+  'DPP8': (['SRC0', 'LANE_SEL0', 'LANE_SEL7'], False),
+  'DS': (['OP', 'ADDR', 'DATA0', 'DATA1', 'VDST'], True),
+  'EXP': (['EN', 'TARGET', 'VSRC0', 'VSRC1', 'VSRC2', 'VSRC3'], True),
+  'FLAT': (['OP', 'ADDR', 'DATA', 'SADDR', 'VDST', 'OFFSET'], True),
+  'LDSDIR': (['VDST', 'OP'], True),
+  'MIMG': (['OP', 'VADDR', 'VDATA', 'SRSRC', 'DMASK'], True),
+  'MTBUF': (['OP', 'VADDR', 'VDATA', 'SRSRC', 'FORMAT', 'SOFFSET'], True),
+  'MUBUF': (['OP', 'VADDR', 'VDATA', 'SRSRC', 'SOFFSET'], True),
+  'SMEM': (['OP', 'SBASE', 'SDATA', 'OFFSET', 'SOFFSET'], True),
+  'SOP1': (['OP', 'SDST', 'SSRC0'], True),
+  'SOP2': (['OP', 'SDST', 'SSRC0', 'SSRC1'], True),
+  'SOPC': (['OP', 'SSRC0', 'SSRC1'], True),
+  'SOPK': (['OP', 'SDST', 'SIMM16'], True),
+  'SOPP': (['OP', 'SIMM16'], True),
+  'VINTERP': (['OP', 'VDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOP1': (['OP', 'VDST', 'SRC0'], True),
+  'VOP2': (['OP', 'VDST', 'SRC0', 'VSRC1'], True),
+  'VOP3': (['OP', 'VDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOP3P': (['OP', 'VDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOP3SD': (['OP', 'VDST', 'SDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOPC': (['OP', 'SRC0', 'VSRC1'], True),
+  'VOPD': (['OPX', 'OPY', 'SRCX0', 'SRCY0', 'VDSTX', 'VDSTY'], True),
+}
+
+# Skip PDF parsing tests by default - only run with TEST_PDF_PARSER=1
+# These are slow (~5s) and only needed when regenerating autogen/
+@unittest.skipUnless(os.environ.get("TEST_PDF_PARSER"), "set TEST_PDF_PARSER=1 to run PDF parser tests")
+class TestPDFParserGenerate(unittest.TestCase):
+  """Test the PDF parser by running generate() and checking results."""
+
+  def test_pdf_parser(self):
+    """Single test that validates all PDF parser outputs."""
+    from extra.assembly.amd.dsl import generate
+    result = generate()
+
+    # test_all_formats_present
+    for fmt_name in EXPECTED_FORMATS:
+      self.assertIn(fmt_name, result["formats"], f"missing format {fmt_name}")
+
+    # test_format_count
+    self.assertEqual(len(result["formats"]), 23)
+
+    # test_no_duplicate_fields
+    for fmt_name, fields in result["formats"].items():
+      field_names = [f[0] for f in fields]
+      self.assertEqual(len(field_names), len(set(field_names)), f"{fmt_name} has duplicate fields: {field_names}")
+
+    # test_expected_fields
+    for fmt_name, (expected_fields, has_encoding) in EXPECTED_FORMATS.items():
+      fields = {f[0] for f in result["formats"].get(fmt_name, [])}
+      for field in expected_fields:
+        self.assertIn(field, fields, f"{fmt_name} missing {field}")
+      if has_encoding:
+        self.assertIn("ENCODING", fields, f"{fmt_name} should have ENCODING")
+      else:
+        self.assertNotIn("ENCODING", fields, f"{fmt_name} should not have ENCODING")
+
+    # test_vopd_no_dpp16_fields
+    vopd_fields = {f[0] for f in result["formats"].get("VOPD", [])}
+    for field in ['DPP_CTRL', 'BANK_MASK', 'ROW_MASK']:
+      self.assertNotIn(field, vopd_fields, f"VOPD should not have {field}")
+
+    # test_dpp16_no_vinterp_fields
+    dpp16_fields = {f[0] for f in result["formats"].get("DPP16", [])}
+    for field in ['VDST', 'WAITEXP']:
+      self.assertNotIn(field, dpp16_fields, f"DPP16 should not have {field}")
+
+    # test_sopp_no_smem_fields
+    sopp_fields = {f[0] for f in result["formats"].get("SOPP", [])}
+    for field in ['SBASE', 'SDATA']:
+      self.assertNotIn(field, sopp_fields, f"SOPP should not have {field}")
+
+class TestPDFParser(unittest.TestCase):
+  """Verify format classes have correct fields from PDF parsing."""
+
+  def test_sop2_fields(self):
+    """SOP2 should have op, sdst, ssrc0, ssrc1."""
+    for field in ['op', 'sdst', 'ssrc0', 'ssrc1']:
+      self.assertIn(field, SOP2._fields)
+    self.assertEqual(SOP2._fields['op'].hi, 29)
+    self.assertEqual(SOP2._fields['op'].lo, 23)
+
+  def test_sop1_fields(self):
+    """SOP1 should have op, sdst, ssrc0 with correct bit positions."""
+    for field in ['op', 'sdst', 'ssrc0']:
+      self.assertIn(field, SOP1._fields)
+    self.assertNotIn('simm16', SOP1._fields)
+    self.assertEqual(SOP1._fields['ssrc0'].hi, 7)
+    self.assertEqual(SOP1._fields['ssrc0'].lo, 0)
+    assert SOP1._encoding is not None
+    self.assertEqual(SOP1._encoding[0].hi, 31)
+    self.assertEqual(SOP1._encoding[1], 0b101111101)
+
+  def test_vop3sd_fields(self):
+    """VOP3SD should have all fields including src0/src1/src2 from page continuation."""
+    for field in ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2']:
+      self.assertIn(field, VOP3SD._fields)
+    self.assertEqual(VOP3SD._fields['src0'].hi, 40)
+    self.assertEqual(VOP3SD._fields['src0'].lo, 32)
+    self.assertEqual(VOP3SD._size(), 8)
+
+  def test_flat_has_vdst(self):
+    """FLAT should have vdst field."""
+    self.assertIn('vdst', FLAT._fields)
+    self.assertEqual(FLAT._fields['vdst'].hi, 63)
+    self.assertEqual(FLAT._fields['vdst'].lo, 56)
+
+  def test_encoding_bits(self):
+    """Verify encoding bits are correct for major formats."""
+    tests = [
+      (SOP2, 31, 30, 0b10),
+      (SOPK, 31, 28, 0b1011),
+      (SOPP, 31, 23, 0b101111111),
+      (VOP1, 31, 25, 0b0111111),
+      (VOP2, 31, 31, 0b0),
+      (VOPC, 31, 25, 0b0111110),
+      (FLAT, 31, 26, 0b110111),
+    ]
+    for cls, hi, lo, val in tests:
+      assert cls._encoding is not None
+      self.assertEqual(cls._encoding[0].hi, hi, f"{cls.__name__} encoding hi")
+      self.assertEqual(cls._encoding[0].lo, lo, f"{cls.__name__} encoding lo")
+      self.assertEqual(cls._encoding[1], val, f"{cls.__name__} encoding val")
+
+  def test_opcode_enums_exist(self):
+    """Verify opcode enums are generated with expected counts."""
+    self.assertGreater(len(SOP1Op), 50)
+    self.assertGreater(len(SOP2Op), 50)
+    self.assertGreater(len(VOP1Op), 50)
+    self.assertGreater(len(VOP3Op), 200)
+
+  def test_vopd_no_duplicate_fields(self):
+    """VOPD should not have duplicate fields and should not include DPP16 fields."""
+    field_names = list(VOPD._fields.keys())
+    self.assertEqual(len(field_names), len(set(field_names)))
+    for field in ['srcx0', 'srcy0', 'opx', 'opy']:
+      self.assertIn(field, VOPD._fields)
+    for field in ['dpp_ctrl', 'bank_mask', 'row_mask']:
+      self.assertNotIn(field, VOPD._fields)
+
+if __name__ == "__main__":
+  unittest.main()
@@ -1,18 +1,12 @@
 #!/usr/bin/env python3
 """Roundtrip tests: generate tinygrad kernels, decode instructions, re-encode, verify match."""
 import unittest, io, sys, re, subprocess, os
+from extra.assembly.amd.autogen.rdna3.ins import *
 from extra.assembly.amd.dsl import Inst
 from extra.assembly.amd.asm import asm
-from extra.assembly.amd.decode import decode_inst, detect_format
+from extra.assembly.amd.asm import detect_format
 from extra.assembly.amd.test.helpers import get_llvm_mc, get_llvm_objdump

-# arch: (mcpu, mattr)
-ARCH_CONFIG = {
-  'rdna3': ('gfx1100', '+real-true16,+wavefrontsize32'),
-  'rdna4': ('gfx1200', '+real-true16,+wavefrontsize32'),
-  'cdna': ('gfx942', '+wavefrontsize64'),
-}
-
 def disassemble_lib(lib: bytes, compiler) -> list[tuple[str, bytes]]:
  """Disassemble ELF binary and return list of (instruction_text, machine_code_bytes)."""
  old_stdout = sys.stdout
@@ -36,40 +30,61 @@ def disassemble_lib(lib: bytes, compiler) -> list[tuple[str, bytes]]:
      continue
  return results

-def compile_asm(instr: str, arch: str = 'rdna3') -> bytes:
-  """Compile a single instruction using LLVM."""
-  return compile_asm_batch([instr], arch)[0]
+def compile_asm(instr: str, compiler=None) -> bytes:
+  """Compile a single instruction with llvm-mc and return the machine code bytes."""
+  llvm_mc = get_llvm_mc()
+  result = subprocess.run(
+    [llvm_mc, '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+    input=f".text\n{instr}\n", capture_output=True, text=True)
+  if result.returncode != 0: raise RuntimeError(f"llvm-mc failed for '{instr}': {result.stderr.strip()}")
+  # Parse encoding: [0x01,0x39,0x0a,0x7e]
+  for line in result.stdout.split('\n'):
+    if 'encoding:' in line:
+      enc = line.split('encoding:')[1].strip()
+      if enc.startswith('[') and enc.endswith(']'):
+        hex_vals = enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')
+        return bytes.fromhex(hex_vals)
+  raise RuntimeError(f"no encoding found in llvm-mc output for: {instr}")

-def compile_asm_batch(instrs: list[str], arch: str = 'rdna3') -> list[bytes]:
+def compile_asm_batch(instrs: list[str]) -> list[bytes]:
  """Compile multiple instructions with a single llvm-mc call."""
  if not instrs: return []
-  mcpu, mattr = ARCH_CONFIG[arch]
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', f'-mattr={mattr}', '-show-encoding'],
-                          input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True)
+  llvm_mc = get_llvm_mc()
+  src = ".text\n" + "\n".join(instrs) + "\n"
+  result = subprocess.run(
+    [llvm_mc, '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+    input=src, capture_output=True, text=True)
  if result.returncode != 0: raise RuntimeError(f"llvm-mc batch failed: {result.stderr.strip()}")
+  # Parse all encodings in order
  encodings = []
  for line in result.stdout.split('\n'):
    if 'encoding:' in line:
      enc = line.split('encoding:')[1].strip()
      if enc.startswith('[') and enc.endswith(']'):
-        encodings.append(bytes.fromhex(enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')))
+        hex_vals = enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')
+        encodings.append(bytes.fromhex(hex_vals))
  if len(encodings) != len(instrs): raise RuntimeError(f"expected {len(instrs)} encodings, got {len(encodings)}")
  return encodings

-def compile_and_disasm_batch(instrs: list[str], arch: str = 'rdna3') -> list[str]:
+def compile_and_disasm_batch(instrs: list[str], compiler) -> list[str]:
  """Compile instructions with LLVM and get LLVM's disassembly."""
-  import tempfile
+  import tempfile, os
  if not instrs: return []
-  mcpu, mattr = ARCH_CONFIG[arch]
-  src = ".text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n" + "\n".join(f"  {instr}" for instr in instrs) + "\n"
+  # Build assembly source with all instructions
+  src = ".text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n"
+  src += "\n".join(f"  {instr}" for instr in instrs) + "\n"
+  # Use llvm-mc to assemble to object file
  with tempfile.NamedTemporaryFile(suffix='.o', delete=False) as f:
    obj_path = f.name
  try:
-    result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', f'-mattr={mattr}', '-filetype=obj', '-o', obj_path],
-                            input=src, capture_output=True, text=True)
+    result = subprocess.run(
+      [get_llvm_mc(), '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-filetype=obj', '-o', obj_path],
+      input=src, capture_output=True, text=True)
    if result.returncode != 0: raise RuntimeError(f"llvm-mc failed: {result.stderr.strip()}")
-    result = subprocess.run([get_llvm_objdump(), '-d', f'--mcpu={mcpu}', obj_path], capture_output=True, text=True)
+    # Disassemble with llvm-objdump
+    result = subprocess.run([get_llvm_objdump(), '-d', '--mcpu=gfx1100', obj_path], capture_output=True, text=True)
    if result.returncode != 0: raise RuntimeError(f"llvm-objdump failed: {result.stderr.strip()}")
+    # Parse disassembly output
    results: list[str] = []
    for line in result.stdout.splitlines():
      if '//' not in line: continue
@@ -81,7 +96,6 @@ def compile_and_disasm_batch(instrs: list[str], arch: str = 'rdna3') -> list[str

 class TestTinygradKernelRoundtrip(unittest.TestCase):
  """Test roundtrip on real tinygrad-generated kernels using get_kernels_from_tinygrad pattern."""
-  arch = 'rdna3'

  def _test_kernel_roundtrip(self, op_fn):
    """Generate kernel from op_fn, test:
@@ -89,14 +103,11 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
    2. asm(disasm()) matches LLVM output
    3. our disasm() matches LLVM's disassembly string exactly
    """
-    arch = self.arch
-    mcpu, mattr = ARCH_CONFIG[arch]
-
    from extra.assembly.amd.test.test_compare_emulators import get_kernels_from_tinygrad
    from tinygrad.runtime.support.compiler_amd import HIPCompiler

    kernels, _, _ = get_kernels_from_tinygrad(op_fn)
-    compiler = HIPCompiler(mcpu)
+    compiler = HIPCompiler('gfx1100')

    # First pass: decode all instructions and collect info
    decoded_instrs: list[tuple] = []  # list of (ki, offset, orig_bytes, decoded, our_disasm, decode_ok, decode_err)
@@ -104,7 +115,7 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
      offset = 0
      while offset < len(kernel.code):
        remaining = kernel.code[offset:]
-        fmt = detect_format(remaining, arch)
+        fmt = detect_format(remaining)
        if fmt is None:
          decoded_instrs.append((ki, offset, None, None, None, False, "no format"))
          offset += 4
@@ -141,11 +152,11 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
      disasm_test_instrs.append((idx, our_disasm))

    # Batch compile for asm test
-    asm_llvm_results = compile_asm_batch([d for _, d in asm_test_instrs], arch)
+    asm_llvm_results = compile_asm_batch([d for _, d in asm_test_instrs])
    asm_llvm_map = {idx: result for (idx, _), result in zip(asm_test_instrs, asm_llvm_results)}

    # Batch compile+disasm for disasm comparison test
-    disasm_llvm_results = compile_and_disasm_batch([d for _, d in disasm_test_instrs], arch)
+    disasm_llvm_results = compile_and_disasm_batch([d for _, d in disasm_test_instrs], compiler)
    disasm_llvm_map = {idx: result for (idx, _), result in zip(disasm_test_instrs, disasm_llvm_results)}

    # Now evaluate results
@@ -196,9 +207,9 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
      else:
        disasm_skipped += 1

-    print(f"[{arch}] decode roundtrip: {decode_passed} passed, {decode_failed} failed, {decode_skipped} skipped")
-    print(f"[{arch}] asm vs llvm: {asm_passed} passed, {asm_failed} failed, {asm_skipped} skipped")
-    print(f"[{arch}] disasm vs llvm: {disasm_passed} passed, {disasm_failed} failed, {disasm_skipped} skipped")
+    print(f"decode roundtrip: {decode_passed} passed, {decode_failed} failed, {decode_skipped} skipped")
+    print(f"asm vs llvm: {asm_passed} passed, {asm_failed} failed, {asm_skipped} skipped")
+    print(f"disasm vs llvm: {disasm_passed} passed, {disasm_failed} failed, {disasm_skipped} skipped")
    self.assertEqual(decode_failed, 0, f"Decode failures:\n" + "\n".join(decode_failures[:20]))
    self.assertEqual(asm_failed, 0, f"Asm failures:\n" + "\n".join(asm_failures[:20]))
    # Note: disasm string comparison is informational only - formatting differences between LLVM versions are expected
@@ -248,11 +259,5 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
  # Fused ops
  def test_fma(self): self._test_kernel_roundtrip(lambda T: (T([1.0, 2.0]) * T([3.0, 4.0]) + T([5.0, 6.0])))

-@unittest.skip("no asm support for RDNA4")
-class TestTinygradKernelRoundtripRDNA4(TestTinygradKernelRoundtrip): arch = 'rdna4'
-
-@unittest.skip("no asm support for CDNA")
-class TestTinygradKernelRoundtripCDNA(TestTinygradKernelRoundtrip): arch = 'cdna'
-
 if __name__ == "__main__":
  unittest.main()
@@ -1,206 +0,0 @@
-#!/usr/bin/env python3
-"""Tests for SQTT packet decoding using real captured examples."""
-import pickle, unittest, ctypes
-from pathlib import Path
-from tinygrad.helpers import DEBUG, colored
-from tinygrad.runtime.autogen import rocprof
-from tinygrad.runtime.support.elf import elf_loader
-from extra.assembly.amd.decode import decode_inst
-from extra.assembly.amd.autogen.rdna3.ins import SOPP
-from extra.assembly.amd.autogen.rdna3.enum import SOPPOp
-from extra.assembly.amd.sqtt import (decode, LAYOUT_HEADER, WAVESTART, WAVEEND, INST, VALUINST, IMMEDIATE, IMMEDIATE_MASK,
-                                     ALUEXEC, VMEMEXEC, PACKET_TYPES, InstOp, AluSrc, MemSrc)
-
-EXAMPLES_DIR = Path(__file__).parent.parent.parent.parent / "sqtt/examples"
-# INST ops for non-traced SIMDs (excluded from instruction count)
-OTHER_SIMD_OPS = {InstOp.OTHER_LDS_LOAD, InstOp.OTHER_LDS_STORE, InstOp.OTHER_LDS_STORE_64, InstOp.OTHER_LDS_STORE_128,
-                  InstOp.OTHER_FLAT_LOAD, InstOp.OTHER_FLAT_STORE, InstOp.OTHER_FLAT_STORE_64, InstOp.OTHER_FLAT_STORE_96,
-                  InstOp.OTHER_FLAT_STORE_128, InstOp.OTHER_GLOBAL_LOAD, InstOp.OTHER_GLOBAL_LOAD_VADDR,
-                  InstOp.OTHER_GLOBAL_STORE_64, InstOp.OTHER_GLOBAL_STORE_96, InstOp.OTHER_GLOBAL_STORE_128,
-                  InstOp.OTHER_GLOBAL_STORE_VADDR_128}
-
-PACKET_COLORS = {
-  "INST": "WHITE", "VALUINST": "BLACK", "VMEMEXEC": "yellow", "ALUEXEC": "yellow",
-  "IMMEDIATE": "YELLOW", "IMMEDIATE_MASK": "YELLOW", "WAVERDY": "cyan", "WAVEALLOC": "cyan",
-  "WAVEEND": "blue", "WAVESTART": "blue", "PERF": "magenta", "EVENT": "red", "EVENT_BIG": "red",
-  "REG": "green", "LAYOUT_HEADER": "white", "SNAPSHOT": "white", "UTILCTR": "green",
-}
-
-def format_packet(p, time_offset: int = 0) -> str:
-  name, cycle = type(p).__name__, p._time - time_offset
-  if isinstance(p, INST):
-    op_name = p.op.name if isinstance(p.op, InstOp) else f"0x{p.op:02x}"
-    fields = f"wave={p.wave} op={op_name}" + (" flag1" if p.flag1 else "") + (" flag2" if p.flag2 else "")
-  elif isinstance(p, VALUINST): fields = f"wave={p.wave}" + (" flag" if p.flag else "")
-  elif isinstance(p, ALUEXEC): fields = f"src={p.src.name if isinstance(p.src, AluSrc) else p.src}"
-  elif isinstance(p, VMEMEXEC): fields = f"src={p.src.name if isinstance(p.src, MemSrc) else p.src}"
-  elif isinstance(p, (WAVESTART, WAVEEND)): fields = f"wave={p.wave} simd={p.simd} cu={p.cu}"
-  elif hasattr(p, '_values'):
-    fields = " ".join(f"{k}=0x{v:x}" if k in {'snap', 'val32'} else f"{k}={v}"
-                      for k, v in p._values.items() if not k.startswith('_') and k != 'delta')
-  else: fields = ""
-  return f"{cycle:8}: {colored(f'{name:18}', PACKET_COLORS.get(name, 'white'))} {fields}"
-
-def print_packets(packets: list) -> None:
-  skip = {"NOP", "TS_DELTA_SHORT", "TS_WAVE_STATE", "TS_DELTA_OR_MARK", "TS_DELTA_S5_W2", "TS_DELTA_S5_W3", "TS_DELTA_S8_W3", "REG", "EVENT"}
-  time_offset = packets[0]._time if packets else 0
-  for p in packets:
-    if type(p).__name__ not in skip: print(format_packet(p, time_offset))
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# ROCPROF DECODER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int):
-  """Run rocprof decoder on SQTT blobs, returning raw occupancy and instruction records."""
-  image, sections, _ = elf_loader(lib)
-  text = next((sh for sh in sections if sh.name == ".text"), None)
-  assert text is not None, "no .text section found"
-  text_off, text_size = text.header.sh_addr, text.header.sh_size
-
-  blob_iter, current_blob = iter(blobs), [None]
-  occupancy_records: list[tuple[int, int, int, int, bool]] = []  # (wave_id, simd, cu, time, is_start)
-  wave_insts: list[list[tuple[int, int]]] = []  # per-wave list of (time, stall)
-
-  @rocprof.rocprof_trace_decoder_se_data_callback_t
-  def copy_cb(buf, buf_size, _):
-    blob = next(blob_iter, None)
-    if blob is None: return 0
-    current_blob[0] = (ctypes.c_ubyte * len(blob)).from_buffer_copy(blob)
-    buf[0] = ctypes.cast(current_blob[0], ctypes.POINTER(ctypes.c_ubyte))
-    buf_size[0] = len(current_blob[0])
-    return len(current_blob[0])
-
-  @rocprof.rocprof_trace_decoder_trace_callback_t
-  def trace_cb(record_type, events_ptr, n, _):
-    if record_type == rocprof.ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY:
-      for ev in (rocprof.rocprofiler_thread_trace_decoder_occupancy_t * n).from_address(events_ptr):
-        occupancy_records.append((ev.wave_id, ev.simd, ev.cu, ev.time, ev.start))
-    elif record_type == rocprof.ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE:
-      for ev in (rocprof.rocprofiler_thread_trace_decoder_wave_t * n).from_address(events_ptr):
-        if ev.instructions_size > 0:
-          sz = ev.instructions_size * ctypes.sizeof(rocprof.rocprofiler_thread_trace_decoder_inst_t)
-          insts_blob = bytearray(sz)
-          ctypes.memmove((ctypes.c_char * sz).from_buffer(insts_blob), ev.instructions_array, sz)
-          insts = list((rocprof.rocprofiler_thread_trace_decoder_inst_t * ev.instructions_size).from_buffer(insts_blob))
-          wave_insts.append([(inst.time, inst.stall) for inst in insts])
-    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-
-  @rocprof.rocprof_trace_decoder_isa_callback_t
-  def isa_cb(instr_ptr, mem_size_ptr, size_ptr, pc, _):
-    offset = pc.address - base
-    if offset < text_off or offset >= text_off + text_size:
-      mem_size_ptr[0] = 0
-      return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-    try:
-      inst = decode_inst(data := image[offset:])
-      mem_size_ptr[0] = inst._size()
-    except (ValueError, AssertionError):
-      mem_size_ptr[0] = 0
-      return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-    if isinstance(inst, SOPP) and inst.op == SOPPOp.S_ENDPGM: mem_size_ptr[0] = 0
-    # rocprof parses instruction string to determine type; v_nop works for all
-    if (max_sz := size_ptr[0]) == 0: return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES
-    ctypes.memmove(instr_ptr, b"v_nop", min(5, max_sz - 1))
-    size_ptr[0] = min(5, max_sz - 1)
-    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-
-  rocprof.rocprof_trace_decoder_parse_data(copy_cb, trace_cb, isa_cb, None)
-  return occupancy_records, wave_insts
-
-class TestSQTTExamples(unittest.TestCase):
-  @classmethod
-  def setUpClass(cls):
-    cls.examples = {}
-    for pkl_path in sorted(EXAMPLES_DIR.glob("*.pkl")):
-      with open(pkl_path, "rb") as f:
-        data = pickle.load(f)
-      sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
-      prg = next((e for e in data if type(e).__name__ == "ProfileProgramEvent"), None)
-      if sqtt_events and prg:
-        cls.examples[pkl_path.stem] = (sqtt_events, prg.lib, prg.base)
-
-  def test_examples_loaded(self):
-    self.assertGreater(len(self.examples), 0, "no example files found")
-
-  def test_decode_all_examples(self):
-    for name, (events, *_) in self.examples.items():
-      for i, event in enumerate(events):
-        with self.subTest(example=name, event=i):
-          packets = decode(event.blob)
-          if DEBUG >= 2: print(f"\n=== {name} event {i} ==="); print_packets(packets)
-          self.assertGreater(len(packets), 0, f"no packets decoded from {name} event {i}")
-          self.assertIsInstance(packets[0], LAYOUT_HEADER, f"first packet should be LAYOUT_HEADER in {name}")
-
-  def test_packet_types_valid(self):
-    for name, (events, *_) in self.examples.items():
-      for i, event in enumerate(events):
-        with self.subTest(example=name, event=i):
-          for pkt in decode(event.blob):
-            self.assertIn(type(pkt), PACKET_TYPES, f"unknown packet type {type(pkt)} in {name}")
-
-  def test_wave_lifecycle(self):
-    for name, (events, *_) in self.examples.items():
-      if "empty" in name: continue
-      with self.subTest(example=name):
-        all_packets = [p for e in events for p in decode(e.blob)]
-        self.assertGreater(len([p for p in all_packets if isinstance(p, WAVESTART)]), 0, f"no WAVESTART in {name}")
-        self.assertGreater(len([p for p in all_packets if isinstance(p, WAVEEND)]), 0, f"no WAVEEND in {name}")
-
-  def test_time_monotonic(self):
-    for name, (events, *_) in self.examples.items():
-      for i, event in enumerate(events):
-        with self.subTest(example=name, event=i):
-          times = [p._time for p in decode(event.blob)]
-          self.assertEqual(times, sorted(times), f"timestamps not monotonic in {name}")
-
-  def test_gemm_has_instructions(self):
-    for name, (events, *_) in self.examples.items():
-      if "gemm" not in name: continue
-      with self.subTest(example=name):
-        all_packets = [p for e in events for p in decode(e.blob)]
-        self.assertGreater(len([p for p in all_packets if isinstance(p, INST)]), 0, f"no INST packets in {name}")
-
-  def test_rocprof_wave_times_match(self):
-    """Wave start/end times must match rocprof exactly."""
-    for name, (events, lib, base) in self.examples.items():
-      with self.subTest(example=name):
-        occupancy, _ = run_rocprof_decoder([e.blob for e in events], lib, base)
-        # extract from rocprof occupancy records
-        roc_starts: dict[tuple[int, int, int], int] = {}
-        roc_waves: list[tuple[int, int]] = []
-        for wave_id, simd, cu, time, is_start in occupancy:
-          key = (wave_id, simd, cu)
-          if is_start: roc_starts[key] = time
-          elif key in roc_starts: roc_waves.append((roc_starts.pop(key), time))
-        # extract from our decoder
-        our_waves: list[tuple[int, int]] = []
-        for event in events:
-          packets = decode(event.blob)
-          wave_starts: dict[tuple[int, int, int], int] = {}
-          for p in packets:
-            if isinstance(p, WAVESTART): wave_starts[(p.wave, p.simd, p.cu)] = p._time
-            elif isinstance(p, WAVEEND) and (key := (p.wave, p.simd, p.cu)) in wave_starts:
-              our_waves.append((wave_starts[key], p._time))
-        self.assertEqual(sorted(our_waves), sorted(roc_waves), f"wave times mismatch in {name}")
-
-  def test_rocprof_inst_times_match(self):
-    """Instruction times must match rocprof exactly (excluding s_endpgm)."""
-    for name, (events, lib, base) in self.examples.items():
-      with self.subTest(example=name):
-        _, wave_insts = run_rocprof_decoder([e.blob for e in events], lib, base)
-        # skip last inst per wave (s_endpgm) - it needs special handling (time + duration instead of time + stall)
-        roc_insts = [time + stall for insts in wave_insts for time, stall in insts[:-1]]
-        # extract from our decoder
-        our_insts: list[int] = []
-        for event in events:
-          for p in decode(event.blob):
-            if isinstance(p, INST) and p.op not in OTHER_SIMD_OPS: our_insts.append(p._time)
-            elif isinstance(p, VALUINST): our_insts.append(p._time)
-            elif isinstance(p, IMMEDIATE): our_insts.append(p._time)
-            elif isinstance(p, IMMEDIATE_MASK):
-              for _ in range(bin(p.mask).count('1')): our_insts.append(p._time)
-        self.assertEqual(sorted(our_insts), sorted(roc_insts), f"instruction times mismatch in {name}")
-
-if __name__ == "__main__":
-  unittest.main()
@@ -1,101 +0,0 @@
-from typing import Callable, Any
-from tinygrad import Tensor, dtypes, nn, UOp
-from tinygrad.uop.ops import KernelInfo, AxisType, Ops
-
-def quantize_to_fp8(x: Tensor, dtype=dtypes.fp8e4m3):
-  fp8_min = -448.0 if dtype == dtypes.fp8e4m3 else -57344.0
-  fp8_max = 448.0 if dtype == dtypes.fp8e4m3 else 57344.0
-  x_abs_max = x.abs().max().detach()
-  scale = fp8_max / (x_abs_max + 1e-8)
-  x_scaled = x * scale
-  x_det = x_scaled.detach()
-  x_clamped = x_det.clamp(fp8_min, fp8_max)
-  x_clamped_ste = x_scaled + (x_clamped - x_det)
-  res = x_clamped_ste.cast(dtype)
-  return res, scale.float().reciprocal()
-
-def custom_matmul(output: UOp, inp: UOp, weight: UOp) -> UOp:
-  SEQ = inp.shape[1]
-  OUT = weight.shape[0]
-  IN = weight.shape[-1]
-  seq_idx = UOp.range(SEQ, 2, AxisType.LOOP)
-  out_idx = UOp.range(OUT, 3, AxisType.LOOP)
-  batch_idx = UOp.range(output.size//SEQ//OUT, 1, AxisType.LOOP)
-  reduce_idx = UOp.range(IN, 0, AxisType.REDUCE)
-  product = (inp.index((seq_idx*IN+reduce_idx+batch_idx*IN*SEQ)) * weight.index((out_idx*IN+reduce_idx))).cast(dtypes.float)
-  reduced = product.reduce(reduce_idx, arg=Ops.ADD)
-  store_op = output.index((seq_idx*OUT+out_idx+batch_idx*OUT*SEQ), ptr=True).store(reduced).end(batch_idx, seq_idx, out_idx)
-  return store_op.sink(arg=KernelInfo(name=f"fp8_matmul_{inp.shape}x{weight.shape}"))
-
-def custom_matmul_backward(gradient: UOp, kernel: UOp) -> tuple[UOp, UOp]:
-  _, input_uop, weight_uop = kernel.src
-  input_tensor = Tensor(input_uop, device=input_uop.device)
-  grad_tensor = Tensor(gradient, device=gradient.device)
-  weight_tensor = Tensor(weight_uop, device=weight_uop.device)
-  grad_quantized, scale = quantize_to_fp8(grad_tensor)
-  scale_scalar = scale.reshape(())
-  grad_weight = Tensor.einsum("bso,bsi->oi", grad_quantized, input_tensor, dtype=dtypes.float)
-  grad_weight = grad_weight * scale_scalar
-  grad_2d = grad_quantized.reshape(grad_tensor.shape[0] * grad_tensor.shape[1], grad_tensor.shape[-1])
-  grad_input = (grad_2d.dot(weight_tensor, dtype=dtypes.float)).contiguous().reshape(input_tensor.shape) * scale
-  return (None, grad_input.uop, grad_weight.uop)
-
-class FP8Linear:
-  def __init__(self, in_features:int, out_features:int, bias:bool=True):
-    self.weight = Tensor.empty(out_features, in_features, dtype=dtypes.float32)
-    self.bias = Tensor.empty(out_features, dtype=dtypes.float32) if bias else None
-
-  def __call__(self, x: Tensor) -> Tensor:
-    original_ndim = len(x.shape)
-    if original_ndim == 2: x = x.reshape(x.shape[0], 1, x.shape[1])
-    batch, seq, _ = x.shape
-    w_fp8, w_scale = quantize_to_fp8(self.weight)
-    x_fp8, x_scale = quantize_to_fp8(x)
-    GPUS = self.weight.device
-    if isinstance(GPUS, tuple) and len(GPUS) > 1:
-      y = Tensor(Tensor.empty((batch//len(GPUS), seq, self.weight.shape[0]), dtype=dtypes.float, device=GPUS).uop.multi(0), device=GPUS)
-    else:
-      y = Tensor.empty((batch, seq, self.weight.shape[0]), dtype=dtypes.float)
-    y = Tensor.custom_kernel(y, x_fp8, w_fp8, fxn=custom_matmul, grad_fxn=custom_matmul_backward)[0]
-    y = y * w_scale * x_scale
-    if self.bias is not None: y = y + self.bias
-    if original_ndim == 2: y = y.reshape(batch, self.weight.shape[0])
-    return y.cast(x.dtype)
-
-def _replace_linear(layer: nn.Linear):
-  fp8_linear = FP8Linear(layer.weight.shape[1], layer.weight.shape[0], layer.bias is not None)
-  fp8_linear.weight = layer.weight
-  if layer.bias is not None: fp8_linear.bias = layer.bias
-  return fp8_linear
-
-def _swap_linear_with_fp8(model, module_filter_fn:Callable[[Any, str],bool]|None=None, fqn:str="", parent:Any|None=None,
-                          attr_name:str="", visited:set|None=None):
-  if visited is None: visited = set()
-  if id(model) in visited: return
-  visited.add(id(model))
-  if isinstance(model, (str, int, float, bool, type(None), Tensor, UOp)): return
-  elif isinstance(model, nn.Linear):
-    if module_filter_fn is not None and not module_filter_fn(model, fqn): return
-    fp8_linear = _replace_linear(model)
-    if parent is not None and attr_name:
-      setattr(parent, attr_name, fp8_linear)
-  elif isinstance(model, list):
-    for i, item in enumerate(model):
-      child_fqn = f"{fqn}.{i}" if fqn else str(i)
-      if isinstance(item, nn.Linear) and (module_filter_fn is None or module_filter_fn(item, child_fqn)): model[i] = _replace_linear(item)
-      else: _swap_linear_with_fp8(item, module_filter_fn, child_fqn, None, "", visited)
-  elif isinstance(model, dict):
-    for key, item in list(model.items()):
-      child_fqn = f"{fqn}.{key}" if fqn else str(key)
-      if isinstance(item, nn.Linear) and (module_filter_fn is None or module_filter_fn(item, child_fqn)): model[key] = _replace_linear(item)
-      else: _swap_linear_with_fp8(item, module_filter_fn, child_fqn, None, "", visited)
-  elif hasattr(model, "__dict__"):
-    for attr_key in list(vars(model).keys()):
-      try: attr = getattr(model, attr_key)
-      except Exception: continue
-      child_fqn = f"{fqn}.{attr_key}" if fqn else attr_key
-      _swap_linear_with_fp8(attr, module_filter_fn, child_fqn, model, attr_key, visited)
-
-def convert_to_float8_training(model, module_filter_fn:Callable[[Any,str],bool]|None=None):
-  _swap_linear_with_fp8(model, module_filter_fn, "", None, "")
-  return model
@@ -1,655 +0,0 @@
-# RDNA3 128x128 tiled GEMM kernel - DSL version
-# Computes C = A @ B for 4096x4096 float32 matrices using 128x128 tiles
-#
-# Architecture: RDNA3 (gfx1100)
-# Tile size: 128x128 (each workgroup computes one tile of C)
-# Workgroup: 128 threads (arranged as 32x4 for coalesced memory access)
-# Inner loop: 8 iterations per K-block, processing 8 columns of A and 8 rows of B
-#
-# Accumulators: 128 vgprs (v[2-117], v[120-124], v[126-129], v[131-133])
-
-import numpy as np
-from pathlib import Path
-from tinygrad import Tensor, Device, Context, GlobalCounters
-from tinygrad.helpers import getenv, colored
-from tinygrad.engine.realize import Runner, Estimates, ExecItem
-from extra.assembly.amd.dsl import s, v, VCC_LO, RawImm, EXEC_LO
-from extra.assembly.amd.autogen.rdna3.ins import *
-
-# =============================================================================
-# Kernel constants
-# =============================================================================
-LDS_SIZE = 8320       # Local data share size in bytes
-MATRIX_DIM = 4096     # Matrix dimension N (assumes square NxN matrices)
-LDS_A_STRIDE = 0x210  # LDS stride for A tile (528 bytes)
-LDS_B_STRIDE = 0x200  # LDS stride for B tile (512 bytes)
-LDS_BASE_OFFSET = 0x1080  # Base LDS offset for tiles
-ADDR_MASK = 0x3fffff80    # Address alignment mask
-
-# s_waitcnt encodings: wait for memory operations to complete
-WAIT_LGKM = 64519    # wait for LDS/GDS/KMEM (lgkm_cnt=0)
-WAIT_ALL = 0         # wait for everything
-WAIT_VMEM = 1015     # wait for VMEM only (vm_cnt=0, lgkm_cnt=63)
-
-# =============================================================================
-# Named register assignments (VGPRs) - COMPACT LAYOUT
-# =============================================================================
-V_LANE_ID_MOD8 = 214      # lane_id & 7 (column within 8-wide tile chunk)
-V_OUTPUT_ROW = 131        # output row coordinate
-V_LANE_MOD8_X4 = 134      # V_LANE_ID_MOD8 << 2 (byte offset)
-V_LANE_DIV8_X4 = 135      # (lane_id >> 3) << 2
-V_ADDR_HI_ZERO = 136      # always 0 (for 64-bit address high bits)
-V_LDS_A_BASE = 133        # LDS A-tile base address for inner loop (in ACC_RESERVED gap)
-V_LDS_B_BASE = 130        # LDS B-tile base address for inner loop (in ACC_RESERVED gap)
-V_GLOBAL_A_ADDR = 131     # global memory A prefetch address (reuses V_OUTPUT_ROW slot during main loop)
-V_GLOBAL_B_ADDR = 154     # global memory B prefetch address
-
-# LDS tile register destinations - SEPARATE from DATA to avoid overlap
-# DATA regs (v155-170) receive global prefetch
-# A on banks 2-3, B on banks 0-1 to avoid bank conflicts in VOPD
-# This layout matches kernel8's optimization for VGPR cache utilization
-V_A_TILE_REGS = [186, 190, 194, 198]  # A tile: banks 2,2,2,2 (186%4=2, 190%4=2, etc.)
-V_B_TILE_REGS = [184, 188, 192, 196, 200, 204, 208, 212]  # B tile: banks 0,0,0,0,0,0,0,0
-
-# =============================================================================
-# Named register assignments (SGPRs)
-# =============================================================================
-S_OUT_PTR = (0, 1)        # output C matrix base pointer
-S_TILE_X = 2              # workgroup_x << 7
-S_TILE_Y = 3              # workgroup_y << 7
-S_DIM_N = 4               # matrix dimension N
-S_LOOP_BOUND = 7          # K-8 (loop termination bound)
-S_A_PTR = (8, 9)          # A matrix base pointer
-S_B_PTR = (10, 11)        # B matrix base pointer
-S_LOOP_CTR = 12           # loop counter (increments by 8)
-S_PREFETCH_FLAG = 13      # prefetch condition flag / row stride in epilogue
-S_WORKGROUP_X = 14        # workgroup_id_x
-S_WORKGROUP_Y = 15        # workgroup_id_y
-# Kernarg load destinations (before copy to working regs)
-S_KERNARG_OUT = (16, 17)  # output pointer from kernarg
-S_KERNARG_A = (20, 21)    # A pointer from kernarg
-S_KERNARG_B = (22, 23)    # B pointer from kernarg
-# Prefetch base pointers (8 pairs each, 16KB/256KB apart)
-S_PREFETCH_B = 24         # s[24:39] - 8 B tile pointers
-S_PREFETCH_A = 40         # s[40:55] - 8 A tile pointers
-
-# =============================================================================
-# Data tables
-# =============================================================================
-
-# Accumulator grid: ACC_GRID[a_idx][b_idx] = vgpr for C[a,b]
-# a_idx: which A value (0-7), b_idx: which B value (0-15)
-# Scattered due to VOPD bank constraints (vdst_x % 4 != vdst_y % 4)
-# Range is from v2 - v129
-ACC_GRID = [
-  [  5,  3,  9,  8,   37, 35, 41, 40,   69, 67, 73, 72,  101, 99,105,104],  # a0
-  [  4,  2,  7,  6,   36, 34, 39, 38,   68, 66, 71, 70,  100, 98,103,102],  # a1
-  [ 17, 16, 13, 11,   49, 48, 45, 43,   81, 80, 77, 75,  113,112,109,107],  # a2
-  [ 15, 14, 12, 10,   47, 46, 44, 42,   79, 78, 76, 74,  111,110,108,106],  # a3
-  [ 21, 19, 25, 24,   53, 51, 57, 56,   85, 83, 89, 88,  117,115,121,120],  # a4
-  [ 20, 18, 23, 22,   52, 50, 55, 54,   84, 82, 87, 86,  116,114,123,122],  # a5
-  [125,128, 29, 27,   33, 32, 61, 59,   65, 64, 93, 91,   97, 96,129,127],  # a6
-  [119,118, 28, 26,   31, 30, 60, 58,   63, 62, 92, 90,   95, 94,124,126],  # a7
-]
-
-# Optimized (a_pair, b_pair) iteration order for better GPU scheduling
-# Interleaves A and B pairs to maximize instruction-level parallelism
-FMAC_PAIR_ORDER = [
-  (0,0),(0,1),(1,1),(1,0), (2,0),(2,1),(3,1),(3,2), (0,2),(0,3),(1,3),(1,2), (2,2),(2,3),(3,3),(3,4),
-  (0,4),(0,5),(1,5),(1,4), (2,4),(2,5),(3,5),(3,6), (0,6),(0,7),(1,7),(1,6), (2,6),(2,7),(3,7),(3,0),
-]
-
-def derive_fmac_pattern(acc_grid, a_tile_regs=None, b_tile_regs=None):
-  """Generate 64 dual FMAC ops from accumulator grid with optimized iteration order."""
-  if a_tile_regs is None: a_tile_regs = V_A_TILE_REGS
-  if b_tile_regs is None: b_tile_regs = V_B_TILE_REGS
-  pattern = []
-  for idx, (a_pair, b_pair) in enumerate(FMAC_PAIR_ORDER):
-    a_even, a_odd = a_pair * 2, a_pair * 2 + 1
-    b_even, b_odd = b_pair * 2, b_pair * 2 + 1
-    a_base, b_base = a_tile_regs[a_pair], b_tile_regs[b_pair]
-    # Op 1: normal order -> C[a_even, b_even] + C[a_odd, b_odd]
-    pattern.append((acc_grid[a_even][b_even], acc_grid[a_odd][b_odd],
-                   a_base, b_base, a_base+1, b_base+1))
-    # Op 2: alternate swapping A vs B to vary register banks
-    if idx % 2 == 0:  # swap B
-      pattern.append((acc_grid[a_even][b_odd], acc_grid[a_odd][b_even],
-                     a_base, b_base+1, a_base+1, b_base))
-    else:  # swap A
-      pattern.append((acc_grid[a_odd][b_even], acc_grid[a_even][b_odd],
-                     a_base+1, b_base, a_base, b_base+1))
-  return pattern
-
-# Derived: 64 dual FMAC operations
-FMAC_PATTERN = derive_fmac_pattern(ACC_GRID)
-
-def derive_permute_swaps(acc_grid, out_regs):
-  """Derive swap sequence to permute accumulators from FMAC layout to output order.
-
-  After FMAC loop: acc_grid[a][b] holds C[a,b]
-  Output order: for row_half in 0,1; col_group in 0-3; row_in_group in 0-3; b_off in 0-3
-    -> need C[row_half*4 + row_in_group, col_group*4 + b_off] in descending reg order
-  """
-  def target_ab(i):
-    row_half, col_group = i // 64, (i // 16) % 4
-    row_in_group, b_off = (i // 4) % 4, i % 4
-    return (row_half * 4 + row_in_group, col_group * 4 + b_off)
-
-  reg_contents = {acc_grid[a][b]: (a, b) for a in range(8) for b in range(16)}
-  ab_location = {ab: r for r, ab in reg_contents.items()}
-
-  swaps = []
-  for i in range(128):
-    target_reg, needed_ab = out_regs[i], target_ab(i)
-    current_reg = ab_location[needed_ab]
-    if current_reg != target_reg:
-      swaps.append((current_reg, target_reg))
-      ab_at_target = reg_contents.get(target_reg)
-      reg_contents[target_reg], ab_location[needed_ab] = needed_ab, target_reg
-      if ab_at_target is not None:
-        reg_contents[current_reg], ab_location[ab_at_target] = ab_at_target, current_reg
-  return swaps
-
-# Derived: swap sequence to arrange accumulators for output
-OUT_REGS = list(range(129, 1, -1))
-PERMUTE_SWAPS = derive_permute_swaps(ACC_GRID, OUT_REGS)
-
-# =============================================================================
-# LDS tile staging registers - COMPACT LAYOUT
-# =============================================================================
-# DATA regs receive contiguous global prefetch, then write to LDS
-# TILE regs receive scattered LDS loads (ds_load_b64 pairs), then feed FMACs
-# These are SEPARATE - DATA lives during prefetch/store, TILE lives during inner loop
-V_LDS_A_ADDR = 153                            # single base register for A stores (use +512 offsets)
-V_LDS_A_DATA = list(range(155, 163))          # 8 data registers for A prefetch (v155-162)
-V_LDS_B_ADDR = 145                            # single base register for B stores (use 16-bit offsets)
-V_LDS_B_DATA = list(range(163, 171))          # 8 data registers for B prefetch (v163-170)
-
-# Global memory prefetch schedule: (vdst1, vdst2, addr_vreg, saddr_lo1, saddr_lo2)
-# First 2 pairs from B prefetch pointers (s[32:39]), next 4 pairs from A prefetch pointers (s[40:55])
-PREFETCH_LOADS = [(V_LDS_A_DATA[4+2*i], V_LDS_A_DATA[4+2*i+1], V_GLOBAL_B_ADDR, S_PREFETCH_B+8+4*i, S_PREFETCH_B+10+4*i) for i in range(2)] + \
-                 [(V_LDS_B_DATA[2*(i-2)], V_LDS_B_DATA[2*(i-2)+1], V_GLOBAL_A_ADDR, S_PREFETCH_A+4*(i-2), S_PREFETCH_A+2+4*(i-2)) for i in range(2, 6)]
-
-# Initial tile prefetch: (vdst, saddr_lo) - load into A data regs using B prefetch pointers (s[24:31])
-INIT_PREFETCH = [(V_LDS_A_DATA[i], S_PREFETCH_B+2*i) for i in range(4)]
-
-# Initial tile loads: (vdst, addr_lo) pairs - use temp regs in accumulator gaps
-INIT_TILE_LOADS = [(23,5),(24,9),(25,7),(26,2),(27,11),(28,13),(29,6),(30,8),(31,10),(12,12),(13,14),(3,2),(4,4),(5,8),(6,6),(7,10)]
-
-# A matrix row offset registers (scattered to avoid accumulator conflicts)
-ROW_REGS = list(range(137, 145))  # v137-v144 (8 regs)
-
-# =============================================================================
-# Kernel class
-# =============================================================================
-
-class Kernel:
-  def __init__(self, arch='gfx1100'):
-    self.instructions, self.labels, self.branch_targets, self.arch = [], {}, {}, arch
-
-  def emit(self, inst): self.instructions.append(inst); return inst
-  def label(self, name): self.labels[name] = len(self.instructions)
-  def branch_to(self, label): self.branch_targets[len(self.instructions) - 1] = label
-
-  def add64(self, dst_lo, dst_hi, src_lo, src_hi, off):
-    """s[dst_lo:dst_hi] = s[src_lo:src_hi] + off"""
-    if off: self.emit(s_add_u32(s[dst_lo], s[src_lo], off)); self.emit(s_addc_u32(s[dst_hi], s[src_hi], 0))
-    elif dst_lo != src_lo: self.emit(s_mov_b64(s[dst_lo:dst_hi], s[src_lo:src_hi]))
-
-  def global_load(self, vdst, addr, saddr=None):
-    """Global load b32"""
-    self.emit(global_load_b32(vdst=v[vdst], addr=v[addr:addr+1],
-              saddr=s[saddr:saddr+2] if saddr else RawImm(124)))
-
-  def waitcnt(self, lgkm=None, vm=None):
-    """Wait for memory operations. lgkm=N waits until N lgkm ops remain, vm=N waits until N vmem ops remain."""
-    from extra.assembly.amd.asm import waitcnt as encode_waitcnt
-    if lgkm == 0 and vm is None: self.emit(s_waitcnt(simm16=WAIT_LGKM))
-    elif vm == 0 and lgkm is None: self.emit(s_waitcnt(simm16=WAIT_VMEM))
-    elif lgkm == 0 and vm == 0: self.emit(s_waitcnt(simm16=WAIT_ALL))
-    elif vm is not None and lgkm is None:
-      self.emit(s_waitcnt(simm16=encode_waitcnt(vmcnt=vm, expcnt=7, lgkmcnt=63)))
-    elif lgkm is not None and vm is None:
-      self.emit(s_waitcnt(simm16=encode_waitcnt(vmcnt=63, expcnt=7, lgkmcnt=lgkm)))
-    else: raise ValueError(f"unsupported waitcnt: lgkm={lgkm}, vm={vm}")
-
-  def barrier(self): self.emit(s_barrier())
-
-  def to_asm(self):
-    import re
-    # Instruction stream with labels
-    label_at = {pos: name for name, pos in self.labels.items()}
-    body = []
-    for i, inst in enumerate(self.instructions):
-      if i in label_at: body.append(f'.{label_at[i]}:')
-      asm = inst.disasm()
-      if i in self.branch_targets:
-        asm = re.sub(r'(s_cbranch_\w+|s_branch)\s+\S+', rf'\1 .{self.branch_targets[i]}', asm)
-      body.append('\t' + asm)
-
-    # HSA kernel descriptor attributes (zeros included for compatibility)
-    hsa = [
-      ('group_segment_fixed_size', LDS_SIZE), ('private_segment_fixed_size', 0), ('kernarg_size', 36),
-      ('user_sgpr_count', 14), ('user_sgpr_dispatch_ptr', 0), ('user_sgpr_queue_ptr', 0),
-      ('user_sgpr_kernarg_segment_ptr', 1), ('user_sgpr_dispatch_id', 0), ('user_sgpr_private_segment_size', 0),
-      ('wavefront_size32', 1), ('uses_dynamic_stack', 0), ('enable_private_segment', 0),
-      ('system_sgpr_workgroup_id_x', 1), ('system_sgpr_workgroup_id_y', 1), ('system_sgpr_workgroup_id_z', 0),
-      ('system_sgpr_workgroup_info', 0), ('system_vgpr_workitem_id', 0), ('next_free_vgpr', 214),
-      ('next_free_sgpr', 16), ('float_round_mode_32', 0), ('float_round_mode_16_64', 0),
-      ('float_denorm_mode_32', 3), ('float_denorm_mode_16_64', 3), ('dx10_clamp', 1), ('ieee_mode', 1),
-      ('fp16_overflow', 0), ('workgroup_processor_mode', 0), ('memory_ordered', 1), ('forward_progress', 0),
-      ('shared_vgpr_count', 0)]
-
-    return '\n'.join([
-      '\t.text', f'\t.amdgcn_target "amdgcn-amd-amdhsa--{self.arch}"',
-      '\t.protected\tkernel', '\t.globl\tkernel', '\t.p2align\t8', '\t.type\tkernel,@function', 'kernel:',
-      *body,
-      '\t.section\t.rodata,"a",@progbits', '\t.p2align\t6, 0x0', '\t.amdhsa_kernel kernel',
-      *[f'\t\t.amdhsa_{k} {v}' for k, v in hsa],
-      '\t.end_amdhsa_kernel', '\t.text', '.Lfunc_end0:', '\t.size\tkernel, .Lfunc_end0-kernel',
-      '\t.amdgpu_metadata', '---', 'amdhsa.kernels:', '  - .args:',
-      *[f'      - .address_space: global\n        .offset: {i*8}\n        .size: 8\n        .value_kind: global_buffer' for i in range(3)],
-      f'    .group_segment_fixed_size: {LDS_SIZE}', '    .kernarg_segment_align: 8',
-      '    .kernarg_segment_size: 24', '    .max_flat_workgroup_size: 128', '    .name: kernel',
-      '    .private_segment_fixed_size: 0', '    .sgpr_count: 60', '    .symbol: kernel.kd',
-      '    .vgpr_count: 214', '    .wavefront_size: 32', f'amdhsa.target: amdgcn-amd-amdhsa--{self.arch}',
-      'amdhsa.version:', '  - 1', '  - 2', '...', '\t.end_amdgpu_metadata'])
-
-
-# =============================================================================
-# Kernel builder
-# =============================================================================
-
-def build_kernel(arch='gfx1100'):
-  k = Kernel(arch)
-
-  # ===========================================================================
-  # PROLOGUE: Load kernel arguments, compute tile coordinates and addresses
-  # ===========================================================================
-  k.emit(s_load_b128(sdata=s[S_KERNARG_A[0]:S_KERNARG_B[1]], sbase=s[0:1], offset=0x0, soffset=RawImm(124)))
-  k.emit(s_load_b64(sdata=s[S_KERNARG_OUT[0]:S_KERNARG_OUT[1]], sbase=s[0:1], offset=0x10, soffset=RawImm(124)))
-  k.emit(s_mov_b32(s[S_DIM_N], MATRIX_DIM))
-  k.emit(s_mov_b32(s[S_LOOP_CTR], 0))  # used by LDS swizzle, always 0 for valid workgroups
-  k.emit(s_lshl_b32(s[S_TILE_X], s[S_WORKGROUP_X], 7))
-  k.emit(s_lshl_b32(s[S_TILE_Y], s[S_WORKGROUP_Y], 7))
-
-  # Lane-derived values
-  k.emit(v_and_b32_e32(v[V_LANE_ID_MOD8], 7, v[0]))
-  k.emit(v_lshrrev_b32_e32(v[4], 3, v[0]))
-  k.emit(v_or_b32_e32(v[1], s[S_TILE_X], v[0]))
-  k.emit(v_or_b32_e32(v[22], s[S_TILE_Y], v[4]))
-  k.emit(v_lshlrev_b32_e32(v[V_LANE_MOD8_X4], 2, v[V_LANE_ID_MOD8]))
-  k.emit(v_mov_b32_e32(v[2], 0))  # v[1] always positive, sign extension is 0
-  k.emit(v_lshlrev_b64(v[5:6], 2, v[1:2]))
-  k.waitcnt(lgkm=0)
-
-  # Copy pointers to working registers
-  k.emit(s_mov_b64(s[S_OUT_PTR[0]:S_OUT_PTR[1]], s[S_KERNARG_OUT[0]:S_KERNARG_OUT[1]]))
-  k.emit(s_mov_b64(s[S_A_PTR[0]:S_A_PTR[1]], s[S_KERNARG_A[0]:S_KERNARG_A[1]]))
-  k.emit(s_mov_b64(s[S_B_PTR[0]:S_B_PTR[1]], s[S_KERNARG_B[0]:S_KERNARG_B[1]]))
-
-  # Compute 8 A and B matrix tile base pointers for prefetch
-  for i in range(8): k.add64(S_PREFETCH_B + i*2, S_PREFETCH_B + i*2 + 1, S_KERNARG_B[0], S_KERNARG_B[1], i * 0x4000)   # B: 16KB apart
-  for i in range(8): k.add64(S_PREFETCH_A + i*2, S_PREFETCH_A + i*2 + 1, S_KERNARG_A[0], S_KERNARG_A[1], i * 0x40000)  # A: 256KB apart
-
-  # Global prefetch addresses: B = (tile_x + lane_id) * 4, A = ((tile_y << 12) + (lane_id/8)*4K + lane_id%8) * 4
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_B_ADDR], s[S_TILE_X], v[0]))
-  k.emit(v_lshlrev_b32_e32(v[V_GLOBAL_B_ADDR], 2, v[V_GLOBAL_B_ADDR]))
-  k.emit(s_lshl_b32(s[19], s[S_TILE_Y], 12))
-  k.emit(v_lshl_add_u32(v[V_GLOBAL_A_ADDR], v[4], 12, v[V_LANE_ID_MOD8]))  # (lane_id/8)*4K + lane_id%8
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_A_ADDR], s[19], v[V_GLOBAL_A_ADDR]))
-  k.emit(v_lshlrev_b32_e32(v[V_GLOBAL_A_ADDR], 2, v[V_GLOBAL_A_ADDR]))
-
-  # ===========================================================================
-  # Tile address computation for initial A/B matrix loads
-  # ===========================================================================
-  k.emit(s_lshl_b32(s[S_LOOP_BOUND], s[S_DIM_N], 4))  # row stride = 16*N
-  k.emit(v_mul_lo_u32(v[ROW_REGS[0]], v[22], s[S_DIM_N]))  # A matrix row offsets
-  for i in range(1, 8): k.emit(v_add_nc_u32_e32(v[ROW_REGS[i]], s[S_LOOP_BOUND], v[ROW_REGS[i-1]]))
-
-  def addr64(dst, base_s):  # 64-bit address: v[dst:dst+1] = s[base_s:base_s+1] + v[dst]*4
-    k.emit(v_mov_b32_e32(v[dst+1], 0))  # offset always positive, sign ext = 0
-    k.emit(v_lshlrev_b64(v[dst:dst+1], 2, v[dst:dst+1]))
-    k.emit(v_add_co_u32(v[dst], VCC_LO, s[base_s], v[dst]))
-    k.emit(v_add_co_ci_u32_e32(v[dst+1], s[base_s+1], v[dst+1]))
-
-  def b_addr(dst, mult, tmp=None):  # B address for col + mult*N
-    tmp = tmp if tmp is not None else dst
-    k.emit(v_mad_u32_u24(v[tmp], s[S_DIM_N], mult, v[1]))
-    if tmp != dst:
-      k.emit(v_mov_b32_e32(v[tmp+1], 0))  # offset always positive
-      k.emit(v_lshlrev_b64(v[dst:dst+1], 2, v[tmp:tmp+1]))
-      k.emit(v_add_co_u32(v[dst], VCC_LO, s[S_B_PTR[0]], v[dst]))
-      k.emit(v_add_co_ci_u32_e32(v[dst+1], s[S_B_PTR[1]], v[dst+1]))
-    else: addr64(dst, S_B_PTR[0])
-
-  def a_addr(dst, row_reg, tmp):  # A address for row_reg + lane_id_mod8
-    k.emit(v_add_nc_u32_e32(v[tmp], v[row_reg], v[V_LANE_ID_MOD8]))
-    k.emit(v_mov_b32_e32(v[tmp+1], 0))  # offset always positive
-    k.emit(v_lshlrev_b64(v[dst:dst+1], 2, v[tmp:tmp+1]))
-    k.emit(v_add_co_u32(v[dst], VCC_LO, s[S_A_PTR[0]], v[dst]))
-    k.emit(v_add_co_ci_u32_e32(v[dst+1], s[S_A_PTR[1]], v[dst+1]))
-
-  # Batch 1: B addresses (cols 0-5) and loads
-  k.emit(v_add_co_u32(v[5], VCC_LO, s[S_B_PTR[0]], v[5]))
-  k.emit(v_add_co_ci_u32_e32(v[6], s[S_B_PTR[1]], v[6]))
-  for dst, mult in [(9,1), (7,2), (2,3), (11,4), (13,5)]: b_addr(dst, mult)
-  k.emit(s_clause(simm16=5))  # 6 consecutive global loads
-  for vdst, addr in INIT_TILE_LOADS[:6]: k.global_load(vdst, addr)
-
-  # Batch 2: A addresses (rows 0-4) and loads
-  for dst, ri in [(6,0), (8,1), (10,2), (12,3), (14,4)]:
-    k.emit(v_add_nc_u32_e32(v[dst], v[ROW_REGS[ri]], v[V_LANE_ID_MOD8]))
-    addr64(dst, S_A_PTR[0])
-  k.emit(s_clause(simm16=4))  # 5 consecutive global loads
-  for vdst, addr in INIT_TILE_LOADS[6:11]: k.global_load(vdst, addr)
-
-  # Batch 3: B cols 6-7, A rows 5-7, and loads
-  for dst, mult, tmp in [(2,6,15), (4,7,4)]: b_addr(dst, mult, tmp)
-  for dst, ri, tmp in [(8,5,16), (6,6,18), (10,7,20)]: a_addr(dst, ROW_REGS[ri], tmp)
-  k.emit(s_clause(simm16=4))  # 5 consecutive global loads
-  for vdst, addr in INIT_TILE_LOADS[11:]: k.global_load(vdst, addr)
-
-  # ===========================================================================
-  # LDS store address computation (bank-conflict-avoiding swizzle)
-  # ===========================================================================
-  # This section computes LDS store addresses with a swizzle pattern to avoid bank conflicts.
-  # Key outputs:
-  #   v[8]: A-tile initial store base (used only for initial stores with stride64)
-  #   V_LDS_B_ADDR (v145): B-tile store base (used for both initial and main loop)
-  #   V_LANE_DIV8_X4 (v135): (lane_id >> 3) << 2 for epilogue
-  #
-  # The swizzle ensures that threads in the same wavefront write to different LDS banks.
-  # Formula: swizzled_addr = base + (lane_id & 7) * LDS_A_STRIDE + swizzle_offset
-  # where swizzle_offset depends on (lane_id >> 3) to distribute across banks.
-
-  # v[22] = tile_y | (lane_id >> 3) from prologue, used as base for row offsets
-  # Compute 7 row offsets for B-tile rows 1-7 (row 0 computed separately in v[9])
-  k.emit(v_add_nc_u32_e32(v[9], s[S_LOOP_CTR], v[22]))  # row 0 base (S_LOOP_CTR=0)
-  for i in range(7): k.emit(v_or_b32_e32(v[10 + i if i < 2 else 12 + i], 16 * (i + 1), v[22]))  # rows 1-7
-
-  # Extract sign bit of workgroup_x (always 0 for valid workgroups, used for masking)
-  k.emit(s_bfe_i32(s[S_LOOP_BOUND], s[S_WORKGROUP_X], 0x10018))
-  k.emit(v_and_b32_e32(v[9], ADDR_MASK, v[9]))
-  k.emit(s_lshr_b32(s[S_LOOP_BOUND], s[S_LOOP_BOUND], 25))
-
-  # Compute masked row offsets for bank conflict avoidance pattern
-  # Pattern: v[row] = row_val - (row_val & ADDR_MASK) extracts lower bits
-  k.emit(v_add_nc_u32_e32(v[19], s[S_LOOP_CTR], v[10]))
-  k.emit(v_add_nc_u32_e32(v[8], s[S_LOOP_BOUND], v[1]))  # A-tile base computation
-  for d, r in zip([20, 21, 32, 33, 34, 35], [11, 14, 15, 16, 17, 18]):
-    k.emit(v_add_nc_u32_e32(v[d], s[S_LOOP_CTR], v[r]))
-  k.emit(v_and_b32_e32(v[8], ADDR_MASK, v[8]))
-  k.emit(v_sub_nc_u32_e32(v[9], v[22], v[9]))  # row 0 swizzle offset
-  for d, s_ in zip([19, 20, 21, 22, 32, 33, 34], [20, 21, 22, 32, 33, 34, 35]):
-    k.emit(v_and_b32_e32(v[d], ADDR_MASK, v[s_]))
-  k.emit(v_sub_nc_u32_e32(v[8], v[1], v[8]))  # A-tile swizzle
-
-  # Apply swizzle offsets and scale to byte offsets
-  k.emit(v_lshlrev_b32_e32(v[9], 2, v[9]))  # row 0 offset * 4
-  for r, t in zip([10, 11, 14, 15, 16, 17, 18], [19, 20, 21, 22, 32, 33, 34]):
-    k.emit(v_sub_nc_u32_e32(v[r], v[r], v[t]))  # rows 1-7 swizzle
-  k.emit(v_bfe_u32(v[2], v[0], 3, 2))  # v[2] = (lane_id >> 3) & 3
-  k.emit(v_lshlrev_b32_e32(v[8], 2, v[8]))  # A-tile base * 4
-
-  # Compute B-tile base address: LDS_A_STRIDE * (lane_id % 8) + row0_offset
-  k.emit(v_mad_u32_u24(v[V_LDS_B_ADDR], LDS_A_STRIDE, v[V_LANE_ID_MOD8], v[9]))
-  # Scale row offsets 1-7 to byte offsets (row 0 already in v[9])
-  for d, r in zip([9, 10, 11, 14, 15, 16, 17], [10, 11, 14, 15, 16, 17, 18]):
-    k.emit(v_lshlrev_b32_e32(v[d], 2, v[r]))
-  k.emit(v_lshlrev_b32_e32(v[V_LANE_DIV8_X4], 2, v[2]))
-  k.emit(v_add_nc_u32_e32(v[8], 0x80, v[8]))  # A-tile initial store base + 128
-
-  # Store initial tile data to LDS
-  k.waitcnt(vm=0)
-  for i, (d0, d1) in enumerate([(0,1), (2,3), (4,5), (11,12)]):
-    k.emit(ds_store_2addr_stride64_b32(addr=v[8], data0=v[INIT_TILE_LOADS[d0][0]], data1=v[INIT_TILE_LOADS[d1][0]], offset0=16+i*4, offset1=18+i*4))
-  # B stores: single base with offsets 0,64,128,192,256,320,384,448
-  for i, idx in enumerate([6,7,8,9,10,13,14,15]):
-    offset = i * 64
-    k.emit(ds_store_b32(addr=v[V_LDS_B_ADDR], data0=v[INIT_TILE_LOADS[idx][0]], offset0=offset & 0xFF, offset1=offset >> 8))
-  k.waitcnt(lgkm=0)
-  k.barrier()
-
-  # ===========================================================================
-  # INIT: Compute LDS base addresses, then zero accumulators
-  # ===========================================================================
-  # v[3] = v[1] & 0x7F (lower 7 bits) since S_LOOP_BOUND=0 for valid workgroups
-  k.emit(v_lshlrev_b32_e32(v[2], 4, v[2]))
-  k.emit(v_add_nc_u32_e32(v[3], s[S_LOOP_BOUND], v[1]))
-  k.emit(v_and_b32_e32(v[3], ADDR_MASK, v[3]))
-  k.emit(v_sub_nc_u32_e32(v[3], v[1], v[3]))
-  k.emit(v_lshl_or_b32(v[V_LDS_B_BASE], v[V_LANE_ID_MOD8], 4, LDS_BASE_OFFSET))
-  k.emit(v_lshl_add_u32(v[V_LDS_A_ADDR], v[3], 2, LDS_BASE_OFFSET))
-  k.emit(v_lshlrev_b32_e32(v[3], 2, v[0]))
-  k.emit(v_and_or_b32(v[V_LDS_A_BASE], 0x180, v[3], v[2]))
-
-  # Zero all 128 accumulators using VOPD dual moves (64 instructions instead of 128)
-  for i in range(0, len(OUT_REGS), 2):
-    k.emit(VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, vdstx=v[OUT_REGS[i]], vdsty=v[OUT_REGS[i+1]], srcx0=0, srcy0=0))
-
-  k.emit(s_add_i32(s[S_LOOP_BOUND], s[S_DIM_N], -8))
-  k.emit(s_add_u32(s[S_A_PTR[0]], s[S_A_PTR[0]], 32))
-  k.emit(s_addc_u32(s[S_A_PTR[1]], s[S_A_PTR[1]], 0))
-  # S_LOOP_CTR is already 0 from prologue initialization
-  k.emit(s_branch(simm16=0)); k.branch_to('LOOP_ENTRY')
-
-  # ===========================================================================
-  # MAIN GEMM LOOP
-  # ===========================================================================
-
-  NO_DS, NO_GLOBAL = getenv("NO_DS", 0), getenv("NO_GLOBAL", 0)
-
-  k.label('LOOP_INC')
-  k.emit(s_add_i32(s[S_LOOP_CTR], s[S_LOOP_CTR], 8))
-  k.emit(s_cmp_ge_i32(s[S_LOOP_CTR], s[S_DIM_N]))
-  k.emit(s_cbranch_scc1(simm16=0)); k.branch_to('EPILOGUE')
-
-  k.label('LOOP_ENTRY')
-  k.emit(s_cmp_lt_i32(s[S_LOOP_CTR], s[S_LOOP_BOUND]))
-  k.emit(s_cselect_b32(s[S_PREFETCH_FLAG], -1, 0))  # s_cselect doesn't modify SCC
-  k.emit(s_cbranch_scc0(simm16=0)); k.branch_to('SKIP_PREFETCH')  # branch if loop_ctr >= loop_bound
-
-  # Advance prefetch pointers
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_B_ADDR], 0x20000, v[V_GLOBAL_B_ADDR]))
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_A_ADDR], 0x20, v[V_GLOBAL_A_ADDR]))
-
-  if not NO_GLOBAL:
-    for vdst, saddr_lo in INIT_PREFETCH:
-      k.global_load(vdst, V_GLOBAL_B_ADDR, saddr_lo)
-
-  k.label('SKIP_PREFETCH')
-
-  # 8 inner loop iterations
-  for iter in range(8):
-    # Load A tile (4 pairs) and B tile (8 pairs) from LDS
-    if not NO_DS:
-      k.emit(s_clause(simm16=11))  # 12 loads total: 4 A + 8 B
-      # A tile: 4 ds_load_b64
-      for i, vdst in enumerate(V_A_TILE_REGS):
-        a_off = (i & 1) * 8 + (i >> 1) * 64 + iter * LDS_A_STRIDE
-        k.emit(ds_load_b64(vdst=v[vdst:vdst+1], addr=v[V_LDS_A_BASE], offset0=a_off & 0xFF, offset1=a_off >> 8))
-      # B tile: 8 ds_load_b64
-      for i, vdst in enumerate(V_B_TILE_REGS):
-        b_off = (i & 1) * 8 + (i & 2) * 64 + (i >> 2) * 256 + iter * LDS_B_STRIDE
-        k.emit(ds_load_b64(vdst=v[vdst:vdst+1], addr=v[V_LDS_B_BASE], offset0=b_off & 0xFF, offset1=b_off >> 8))
-      k.waitcnt(lgkm=0)
-
-    # 64 dual FMACs
-    k.emit(s_clause(simm16=63))
-    for i, (vdst_x, vdst_y, ax, bx, ay, by) in enumerate(FMAC_PATTERN):
-      k.emit(VOPD(VOPDOp.V_DUAL_FMAC_F32, VOPDOp.V_DUAL_FMAC_F32,
-                  vdstx=v[vdst_x], vdsty=v[vdst_y], srcx0=v[ax], vsrcx1=v[bx], srcy0=v[ay], vsrcy1=v[by]))
-
-    # Issue global prefetch AFTER FMACs (first 6 iterations only)
-    if iter < 6 and not NO_GLOBAL:
-      vdst1, vdst2, addr, slo1, slo2 = PREFETCH_LOADS[iter]
-      k.global_load(vdst1, addr, slo1)
-      k.global_load(vdst2, addr, slo2)
-
-  k.emit(s_and_not1_b32(VCC_LO, EXEC_LO, s[S_PREFETCH_FLAG]))
-  k.waitcnt(vm=0)
-  k.barrier()
-  k.emit(s_cbranch_vccnz(simm16=0)); k.branch_to('LOOP_INC')
-
-  # Store prefetched data to LDS
-  # NOTE: Register naming reflects LDS tile organization, not source matrix:
-  #   V_LDS_A_DATA (v155-162) holds data that goes to LDS A-tile region
-  #   V_LDS_B_DATA (v163-170) holds data that goes to LDS B-tile region
-  # The data sources are swapped: A-tile receives B matrix rows, B-tile receives A matrix columns
-  for i in range(4):  # A tile: 8 values via 4 stride64 stores
-    k.emit(ds_store_2addr_stride64_b32(addr=v[V_LDS_A_ADDR], data0=v[V_LDS_A_DATA[i*2]], data1=v[V_LDS_A_DATA[i*2+1]], offset0=i*4, offset1=i*4+2))
-  for i in range(8):  # B tile: 8 values via 8 scalar stores with 64-byte spacing
-    offset = i * 64
-    k.emit(ds_store_b32(addr=v[V_LDS_B_ADDR], data0=v[V_LDS_B_DATA[i]], offset0=offset & 0xFF, offset1=offset >> 8))
-
-  k.waitcnt(lgkm=0)
-  k.barrier()
-  k.emit(s_branch(simm16=0)); k.branch_to('LOOP_INC')
-
-  # ===========================================================================
-  # EPILOGUE: Permute and store results
-  # ===========================================================================
-  k.label('EPILOGUE')
-
-  # Rearrange accumulators from FMAC layout to contiguous output order
-  for a, b in PERMUTE_SWAPS:
-    k.emit(v_swap_b32_e32(v[a], v[b]))
-
-  # Compute output coordinates: v[V_LANE_ID_MOD8] = col, v[V_OUTPUT_ROW] = row
-  k.emit(VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32,
-              vdstx=v[149], vdsty=v[150], srcx0=v[V_LANE_MOD8_X4], vsrcx1=v[0], srcy0=v[V_LANE_DIV8_X4], vsrcy1=v[0]))
-  k.emit(v_and_b32_e32(v[0], 0x60, v[0]))
-  k.emit(v_or_b32_e32(v[V_LANE_ID_MOD8], s[S_TILE_X], v[149]))
-  k.emit(v_add_nc_u32_e32(v[0], s[S_TILE_Y], v[0]))
-  k.emit(v_or_b32_e32(v[V_OUTPUT_ROW], v[0], v[150]))
-
-  # Precompute row offsets: v[144-147] for rows 0-3, v[148-151] for rows 16-19
-  for base, row_off in [(144, 0), (148, 16)]:
-    if row_off: k.emit(v_or_b32_e32(v[1], row_off, v[V_OUTPUT_ROW]))
-    k.emit(v_mul_lo_u32(v[base], v[1] if row_off else v[V_OUTPUT_ROW], s[S_DIM_N]))
-    for i in range(3): k.emit(v_add_nc_u32_e32(v[base + 1 + i], s[S_DIM_N], v[base + i]))
-
-  k.emit(v_mov_b32_e32(v[V_ADDR_HI_ZERO], 0))
-  k.emit(s_lshl_b32(s[S_PREFETCH_FLAG], s[S_DIM_N], 2))  # row stride in bytes
-
-  # Store 128 output values as 32 groups of 4 (128-bit stores)
-  # Layout: 2 row halves (0-3, 16-19) x 4 col groups x 4 rows = 32 stores of 4 floats
-  epilogue_reserved = {V_LANE_ID_MOD8, V_OUTPUT_ROW, V_LANE_MOD8_X4, V_LANE_DIV8_X4, V_ADDR_HI_ZERO}
-
-  for i, (row_half, col_off, row_in_group) in enumerate([(rh, co, ri)
-      for rh in range(2) for co in [0, 32, 64, 96] for ri in range(4)]):
-    row = row_half * 16 + row_in_group
-    srcs = OUT_REGS[i*4:(i+1)*4]
-
-    # Find temp register for scaled values (must not conflict with reserved regs)
-    tmp = max(srcs) + 5
-    while any(r in epilogue_reserved for r in range(tmp, tmp + 4)): tmp += 1
-
-    # Copy values to temp regs for output (alpha=1.0 hardcoded, so just move)
-    for j, src in enumerate(srcs):
-      k.emit(v_mov_b32_e32(v[tmp + j], v[src]))
-
-    # Compute output address
-    if row_in_group == 0:  # first row: compute base address for this column group
-      if col_off == 0: k.emit(v_mov_b32_e32(v[0], v[V_LANE_ID_MOD8]))
-      else: k.emit(v_add_nc_u32_e32(v[0], col_off, v[V_LANE_ID_MOD8]))
-      row_base = 144 + row if row < 4 else 148 + row - 16
-      k.emit(v_add_nc_u32_e32(v[0], v[row_base], v[0]))
-      k.emit(v_lshlrev_b32_e32(v[0], 2, v[0]))
-      k.emit(v_add_co_u32(v[0], VCC_LO, s[S_OUT_PTR[0]], v[0]))
-      k.emit(v_add_co_ci_u32_e32(v[1], s[S_OUT_PTR[1]], v[V_ADDR_HI_ZERO]))
-    else:  # subsequent rows: just add stride
-      k.emit(v_add_co_u32(v[0], VCC_LO, s[S_PREFETCH_FLAG], v[0]))
-      k.emit(v_add_co_ci_u32_e32(v[1], v[1], v[V_ADDR_HI_ZERO]))
-
-    k.emit(global_store_b128(addr=v[0:1], data=v[tmp:tmp+3], saddr=RawImm(124)))
-
-  k.emit(s_sendmsg(simm16=3))
-  k.emit(s_endpgm())
-
-  return k.to_asm()
-
-# =============================================================================
-# Test harness
-# =============================================================================
-
-N = getenv("N", 4096)
-BLOCK_M, BLOCK_N = 128, 128
-THREADS = 128
-
-def test_matmul():
-  dev = Device[Device.DEFAULT]
-  print(f"Device arch: {dev.arch}")
-
-  if getenv("STOCK", 0):
-    # Load the stock kernel from amd_seb/kernel8_batched_gmem.s
-    stock_path = Path(__file__).parent / "amd_seb" / "kernel8_batched_gmem.s"
-    asm = stock_path.read_text()
-    print(f"Loaded stock kernel from {stock_path}")
-  else:
-    asm = build_kernel(dev.arch)
-  if getenv("PRINT_ASM", 0): print(asm)
-
-  binary = dev.compiler.compile(asm)
-  print(f"Compiled! Binary size: {len(binary)} bytes")
-
-  rng = np.random.default_rng(42)
-  a = Tensor(rng.random((N, N), dtype=np.float32) - 0.5)
-  b = Tensor(rng.random((N, N), dtype=np.float32) - 0.5)
-  c = Tensor.empty(N, N)
-  Tensor.realize(a, b, c)
-
-  grid, local = (N // BLOCK_N, N // BLOCK_M, 1), (THREADS, 1, 1)
-  print(f"Grid: {grid}, Local: {local}")
-
-  _prg = dev.runtime("kernel", binary)
-  class AsmRunner(Runner):
-    def __init__(self):
-      super().__init__(colored("kernel", "cyan"), Device.DEFAULT, Estimates(ops=N*N*N*2, mem=N*N*4*3))
-    def __call__(self, rawbufs, var_vals, wait=False):
-      c_buf, a_buf, b_buf = [x.ensure_allocated()._buf for x in rawbufs]
-      return _prg(a_buf, b_buf, c_buf, global_size=grid, local_size=local, wait=wait)
-
-  ei = ExecItem(None, [c.uop.buffer, a.uop.buffer, b.uop.buffer], prg=AsmRunner())
-
-  ets = []
-  with Context(DEBUG=2):
-    for _ in range(getenv("CNT", 5)): ets.append(ei.run(wait=True))
-  print(f"REAL TFLOPS {N * N * N * 2 / min(ets) * 1e-12:.2f}")
-
-  if getenv("VERIFY", 1):
-    GlobalCounters.reset()
-    with Context(DEBUG=2): tc = (a @ b).realize()
-    with Context(DEBUG=0): err = (c - tc).square().mean().item()
-    print(f"mean squared error {err}")
-    if err > 1e-06: raise RuntimeError("matmul is wrong!")
-
-def run_sqtt():
-  """Run with SQTT profiling and write trace files."""
-  import subprocess, os
-
-  # Run test_matmul in a subprocess with SQTT enabled from the start (no verify)
-  env = {**os.environ, "AMD": "1", "SQTT": "1", "CNT": "1", "PROFILE": "1", "PYTHONPATH": ".", "VERIFY": "0"}
-  result = subprocess.run(
-    ["python", "-c", "from extra.gemm.amd_asm_matmul import test_matmul; test_matmul()"],
-    capture_output=True, text=True, env=env, timeout=120
-  )
-  print(result.stdout)
-
-  # Run roc.py to extract trace data
-  result = subprocess.run(
-    ["python", "extra/sqtt/roc.py", "--profile", "/tmp/profile.pkl.tiny", "--kernel", "kernel"],
-    capture_output=True, text=True, env={**os.environ, "DEBUG": "5"}, timeout=60
-  )
-  output = result.stdout + result.stderr
-
-  # Write full output to trace file
-  with open("/tmp/sqtt_trace.txt", "w") as f:
-    f.write(output)
-  print(f"Wrote {len(output)} bytes to /tmp/sqtt_trace.txt")
-
-if __name__ == "__main__":
-  if getenv("ASM", 0): print(build_kernel(Device[Device.DEFAULT].arch))
-  elif getenv("SQTT", 0): run_sqtt()
-  else: test_matmul()
@@ -140,11 +140,11 @@ def hand_spec_kernel3():

  return sink.sink(arg=KernelInfo(opts_to_apply=())).simplify()

-def test_matmul(sink:UOp, dtype=dtypes.float32, N=N):
+def test_matmul(sink:UOp, N=N):
  rng = np.random.default_rng()
-  a = Tensor(rng.random((N, N), dtype=np.float32)-0.5, dtype=dtype)
-  b = Tensor(rng.random((N, N), dtype=np.float32)-0.5, dtype=dtype)
-  hc = Tensor.empty(N, N, dtype=dtype)
+  a = Tensor(rng.random((N, N), dtype=np.float32)-0.5)
+  b = Tensor(rng.random((N, N), dtype=np.float32)-0.5)
+  hc = Tensor.empty(N, N)
  Tensor.realize(a, b, hc)

  ei = ExecItem(sink, [t.uop.buffer for t in [hc, a, b]], prg=get_runner(Device.DEFAULT, sink))
@@ -1,9 +1,9 @@
 	// ** global buffers
 	s_load_dwordx2  s[28:29], s[0:1], 0x0    // C
-	s_load_dwordx2  s[34:35], s[0:1], 0x08   // A
-	s_load_dwordx2  s[32:33], s[0:1], 0x10   // B
+	s_load_dwordx4  s[32:35], s[0:1], 0x8    // A, B
 	// ** others kernel args
 	s_load_dword    s24, s[0:1], 0x18        // N
+	s_load_dword    s54, s[0:1], 0x1C        // num work groups
 	s_waitcnt lgkmcnt(0)
 	// "info"
 	s_mov_b32 s51, 1             // gemm_info = 1
@@ -1,76 +0,0 @@
-.text
-.section	.text.
-.global	gemm
-.p2align	8
-.type	gemm,@function
-
-gemm:
-INSTRUCTIONS
-
-.section .rodata,"a",@progbits
-.p2align 6, 0x0
-.amdhsa_kernel gemm
-  # basic memory requirements
-  .amdhsa_group_segment_fixed_size 30336
-  .amdhsa_private_segment_fixed_size 0
-  .amdhsa_kernarg_size 32
-  # register usage (RSRC1)
-  .amdhsa_next_free_vgpr 256
-  .amdhsa_next_free_sgpr 100
-  # workgroup / workitem IDs (RSRC2)
-  .amdhsa_system_sgpr_workgroup_id_x 1
-  .amdhsa_system_sgpr_workgroup_id_y 1
-  .amdhsa_system_sgpr_workgroup_id_z 1
-  # user SGPRs: kernarg ptr in s[0:1]
-  .amdhsa_user_sgpr_kernarg_segment_ptr 1
-  .amdhsa_user_sgpr_count 2
-  # gfx10+ / gfx11 specifics (RSRC1[29..31])
-  .amdhsa_wavefront_size32 1
-  .amdhsa_workgroup_processor_mode 1
-  .amdhsa_memory_ordered 1
-  .amdhsa_forward_progress 1
-  # misc for gfx11
-  .amdhsa_dx10_clamp 1
-  .amdhsa_ieee_mode 1
-  .amdhsa_uses_dynamic_stack 0
-.end_amdhsa_kernel
-
-.amdgpu_metadata
---
-amdhsa.kernels:
-  - .args:
-      - .address_space:  generic
-        .name:           C
-        .offset:         0
-        .size:           8
-        .value_kind:     global_buffer
-        .value_type:     f16
-      - .address_space:  generic
-        .name:           A
-        .offset:         8
-        .size:           8
-        .value_kind:     global_buffer
-        .value_type:     f16
-      - .address_space:  generic
-        .name:           B
-        .offset:         16
-        .size:           8
-        .value_kind:     global_buffer
-        .value_type:     f16
-    .group_segment_fixed_size: 30336
-    .kernarg_segment_align: 8
-    .kernarg_segment_size: 32
-    .max_flat_workgroup_size: 128
-    .name:           gemm
-    .private_segment_fixed_size: 0
-    .sgpr_count:     70
-    .sgpr_spill_count: 0
-    .symbol:         gemm.kd
-    .vgpr_count:     256
-    .vgpr_spill_count: 0
-    .wavefront_size: 32
-amdhsa.version:
-  - 1
-  - 1
-...
-.end_amdgpu_metadata
@@ -1,30 +0,0 @@
-import math, pathlib
-
-from tinygrad import Device, dtypes
-from tinygrad.uop.ops import UOp, Ops, KernelInfo
-
-from extra.gemm.amd_uop_matmul import test_matmul
-
-N = 4096
-TN = 96
-THREADS_PER_WG = 128
-NUM_WG = math.ceil(N / TN) * math.ceil(N / TN)
-
-dname:str = Device.DEFAULT
-template:str = (pathlib.Path(__file__).parent/"template.s").read_text()
-
-def asm_kernel() -> UOp:
-  lidx = UOp.special(THREADS_PER_WG, "lidx0")
-  gidx = UOp.special(NUM_WG, "gidx0")
-
-  a = UOp.placeholder((N*N,), dtypes.half, slot=1)
-  b = UOp.placeholder((N*N,), dtypes.half, slot=2)
-  c = UOp.placeholder((N*N,), dtypes.half, slot=0)
-
-  src = template.replace("INSTRUCTIONS", (pathlib.Path(__file__).parent/"gemm.s").read_text())
-
-  sink = UOp.sink(a, b, c, lidx, gidx, arg=KernelInfo(name="gemm"))
-  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=dname), UOp(Ops.LINEAR, src=(*sink.src, sink)), UOp(Ops.SOURCE, arg=src)), arg=())
-
-if __name__ == "__main__":
-  test_matmul(asm_kernel(), dtype=dtypes.half, N=N)
@@ -13,7 +13,7 @@ INSTRUCTIONS
  # basic memory requirements
  .amdhsa_group_segment_fixed_size 133120
  .amdhsa_private_segment_fixed_size 0
-  .amdhsa_kernarg_size 28
+  .amdhsa_kernarg_size 32
  # register usage (RSRC1)
  .amdhsa_next_free_vgpr 504
  .amdhsa_next_free_sgpr 96
@@ -61,10 +61,15 @@ amdhsa.kernels:
        .size: 4
        .value_kind: by_value
        .value_type: u32
+      - .name: num_wg
+        .offset: 28
+        .size: 4
+        .value_kind: by_value
+        .value_type: u32
    .group_segment_fixed_size: 133120
    .private_segment_fixed_size: 0
    .kernarg_segment_align: 8
-    .kernarg_segment_size: 28
+    .kernarg_segment_size: 32
    .max_flat_workgroup_size: 256
    .sgpr_count: 88
    .sgpr_spill_count: 0
@@ -2,8 +2,10 @@
 # VIZ=2 to profile
 import pathlib
 from tinygrad import Tensor, Device, dtypes, Context
-from tinygrad.uop.ops import UOp, Ops, KernelInfo
-from tinygrad.helpers import getenv
+from tinygrad.engine.realize import ExecItem, CompiledRunner
+from tinygrad.renderer import ProgramSpec
+from tinygrad.uop.ops import track_rewrites, UOp
+from tinygrad.helpers import TracingKey, getenv

 fp = pathlib.Path(__file__).parent/"gemm.s"

@@ -21,8 +23,8 @@ import torch
 torch.manual_seed(0)
 A = (torch.randn(N, N, dtype=torch.float32, device="cpu") / scale).to(torch.bfloat16).contiguous()
 B = (torch.randn(N, N, dtype=torch.float32, device="cpu") / scale).to(torch.bfloat16).contiguous()
-Bt = B.t().contiguous() # transpose B for the asm gemm
-C_torch = A@B
+Bt = B.t().contiguous() # transpose B for the baseline gemm
+C_torch = A@Bt

 # ** copy buffers to AMD

@@ -31,32 +33,31 @@ C_torch = A@B
 def from_torch(t:torch.Tensor) -> Tensor:
  return Tensor.from_blob(t.data_ptr(), t.shape, dtype=dtypes.bfloat16, device="cpu").to(Device.DEFAULT).realize()

-C_tiny = from_torch(A) @ from_torch(B)
+C_tiny = Tensor.matmul(from_torch(A), from_torch(Bt), dtype=dtypes.float32).cast(dtypes.bfloat16)
 C_asm = Tensor.empty_like(C_tiny)
-
-# ** assembly custom kernel
-
-def custom_asm_gemm(C:UOp, A:UOp, B:UOp) -> UOp:
-  lidx = UOp.special(THREADS_PER_WG, "lidx0")
-  gidx = UOp.special(NUM_WG, "gidx0")
-
-  src = (pathlib.Path(__file__).parent/"template.s").read_text().replace("INSTRUCTIONS", fp.read_text())
-
-  sz = UOp.variable("SZ", 256, 8192)
-
-  sink = UOp.sink(C.base, A.base, B.base, sz, lidx, gidx, arg=KernelInfo(name="gemm"))
-  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=Device.DEFAULT), UOp(Ops.LINEAR, src=(*sink.src, sink)), UOp(Ops.SOURCE, arg=src)), arg=())
-
-C_asm = Tensor.custom_kernel(C_asm, from_torch(A), from_torch(Bt), fxn=custom_asm_gemm)[0]
+C_asm.uop.buffer.allocate()

 # ** run gemms

-sched = Tensor.schedule(C_tiny, C_asm)
-eis = [si.lower() for si in sched]
+# baseline tinygrad
+sched = C_tiny.schedule()
+assert len(sched) == 1
+eis:list[ExecItem] = [sched[-1].lower()]
+ast = sched[-1].ast
+
+# assembly gemm
+@track_rewrites(name=lambda ret: TracingKey(ret.name, (ret.function_name,), ret))
+def get_asm_prg() -> ProgramSpec:
+  src = (pathlib.Path(__file__).parent/"template.s").read_text().replace("INSTRUCTIONS", fp.read_text())
+  lib = Device[Device.DEFAULT].compiler.compile(src)
+  return ProgramSpec("gemm", src, Device.DEFAULT, ast, lib=lib, global_size=[NUM_WG, 1, 1], local_size=[THREADS_PER_WG, 1, 1],
+                     globals=[0, 1, 2], vars=[UOp.variable("SZ", 256, 8192), UOp.variable("NUM_WG", 1, 1024)])
+eis.append(ExecItem(ast, [C_asm.uop.buffer, from_torch(B).uop.buffer, from_torch(A).uop.buffer], fixedvars={"SZ":N, "NUM_WG":NUM_WG},
+                    prg=CompiledRunner(get_asm_prg())))

 with Context(DEBUG=2):
  for ei in eis:
-    et = ei.run({"SZ":N}, wait=True)
+    et = ei.run(wait=True)
    print(f"{(N*N*N*2 / et)*1e-12:.2f} REAL TFLOPS")

 # ** correctness
@@ -1,12 +1,12 @@
-# unpack the complete kernel descriptor of an amdgpu ELF
+# unpack the complete kernel descriptor of an amdgpu ELF of for gfx950
 # https://rocm.docs.amd.com/projects/llvm-project/en/latest/LLVM/llvm/html/AMDGPUUsage.html#code-object-v3-kernel-descriptor
-import struct, pathlib, sys
+import struct, pathlib
 from tinygrad.runtime.support.elf import elf_loader

 def bits(x, lo, hi): return (x >> lo) & ((1 << (hi - lo + 1)) - 1)
 def assert_zero(x, lo, hi): assert bits(x, lo, hi) == 0

-with open(sys.argv[1], "rb") as f:
+with open(fp:=pathlib.Path(__file__).parent/"lib", "rb") as f:
  lib = f.read()

 image, sections, relocs = elf_loader(lib)
@@ -49,7 +49,7 @@ print("COMPUTE_PGM_RSRC3: 0x%08x" % pgm_rsrc3)
 print("COMPUTE_PGM_RSRC1: 0x%08x" % pgm_rsrc1)
 print("COMPUTE_PGM_RSRC2: 0x%08x" % pgm_rsrc2)

-# rsrc 3 (gfx950)
+# rsrc 3

 accum_offset_raw = bits(pgm_rsrc3, 0, 5)
 assert_zero(pgm_rsrc3, 6, 15)
@@ -169,10 +169,10 @@ assert_zero(desc, 458, 459)
 uses_dynamic_stack = bits(desc, 459, 460)
 print("DESC.USES_DYNAMIC_STACK:", uses_dynamic_stack)

-# gfx950 only
 assert_zero(desc, 460, 463)
 kernarg_preload_spec_length = bits(desc, 464, 470)
 print("DESC.KERNARG_PRELOAD_SPEC_LENGTH:", kernarg_preload_spec_length)
+
 kernarg_preload_spec_offset = bits(desc, 471, 479)
 print("DESC.KERNARG_PRELOAD_SPEC_OFFSET:", kernarg_preload_spec_offset)

@@ -1,42 +1,8 @@
-import argparse, os, hashlib, functools
-from typing import Iterator, Callable
-from tinygrad.helpers import getenv, DEBUG, round_up, Timing, tqdm, fetch, ceildiv
+import argparse, os, hashlib
+from tinygrad.helpers import getenv, DEBUG, round_up, Timing, tqdm, fetch
 from extra.hevc.hevc import parse_hevc_file_headers, untile_nv12, to_bgr, nv_gpu
 from tinygrad import Tensor, dtypes, Device, Variable, TinyJit

-# rounds up hevc input data to 32 bytes, so more optimal kernels can be generated
-HEVC_ROUNDUP = getenv("DATA_ROUNDUP", 32)
-
-@functools.cache
-def _hevc_jitted_decoder(out_image_size:tuple[int, int], max_hist:int, inplace:bool):
-  def hevc_decode_frame(pos:Variable, hevc_tensor:Tensor, offset:Variable, sz:Variable, opaque:Tensor, i:Variable, *hist:Tensor, outbuf:Tensor|None=None):
-    x = hevc_tensor[offset:offset+sz*HEVC_ROUNDUP].decode_hevc_frame(pos, out_image_size, opaque[i], hist)
-    if outbuf is not None: outbuf.assign(x).realize()
-    return x.realize()
-  return TinyJit(hevc_decode_frame)
-
-def hevc_decode(hevc_tensor:Tensor, opaque:Tensor, frame_info:list, luma_h:int, luma_w:int,
-                history:list[Tensor]|None=None, preallocated_outputs:list[Tensor]|None=None, warmup=False) -> Iterator[Tensor]:
-  out_image_size = luma_h + (luma_h + 1) // 2, round_up(luma_w, 64)
-  max_hist = max((hs for _, _, _, hs, _ in frame_info), default=0)
-
-  v_pos = Variable("pos", 0, max_hist + 1)
-  v_offset = Variable("offset", 0, hevc_tensor.numel()-1)
-  v_sz = Variable("sz", 1, ceildiv(hevc_tensor.numel(), HEVC_ROUNDUP))
-  v_i = Variable("i", 0, len(frame_info)-1)
-
-  decode_jit = _hevc_jitted_decoder(out_image_size, max_hist, preallocated_outputs is not None)
-  history = history or [Tensor.empty(*out_image_size, dtype=dtypes.uint8, device="NV").contiguous().realize() for _ in range(max_hist)]
-  assert len(history) == max_hist, f"history length {len(history)} does not match max_hist {max_hist}"
-
-  for i, (offset, sz, frame_pos, _, is_hist) in enumerate(frame_info):
-    history = history[-max_hist:] if max_hist > 0 else []
-    img = decode_jit(v_pos.bind(frame_pos), hevc_tensor, v_offset.bind(offset), v_sz.bind(ceildiv(sz, HEVC_ROUNDUP)),
-                     opaque, v_i.bind(i), *history, outbuf=preallocated_outputs[i] if preallocated_outputs else None)
-    res = preallocated_outputs[i] if preallocated_outputs else img.clone().realize()
-    if is_hist: history.append(res)
-    yield res
-
 if __name__ == "__main__":
  parser = argparse.ArgumentParser()
  parser.add_argument("--input_file", type=str, default="")
@@ -53,32 +19,49 @@ if __name__ == "__main__":
  dat_hash = hashlib.md5(dat).hexdigest()

  with Timing("prep infos: "):
+    dat_nv = hevc_tensor.to("NV")
    opaque, frame_info, w, h, luma_w, luma_h, chroma_off = parse_hevc_file_headers(dat)

  frame_info = frame_info[:getenv("MAX_FRAMES", len(frame_info))]

  # move all needed data to gpu
+  #all_slices = []
  with Timing("copy to gpu: "):
    opaque_nv = opaque.to("NV").contiguous().realize()
    hevc_tensor = hevc_tensor.to("NV")

  out_image_size = luma_h + (luma_h + 1) // 2, round_up(luma_w, 64)
+  max_hist = max(history_sz for _, _, _, history_sz, _ in frame_info)

-  # preallocate output/hist buffers
-  max_hist = max((hs for _, _, _, hs, _ in frame_info), default=0)
-  hist = [Tensor.empty(*out_image_size, dtype=dtypes.uint8, device="NV").contiguous().realize() for _ in range(max_hist)]
-  out_images = [Tensor.zeros(*out_image_size, dtype=dtypes.uint8, device="NV").contiguous().realize() for _ in range(len(frame_info))]
+  # define variables
+  v_pos = Variable("pos", 0, max_hist + 1)
+  v_offset = Variable("offset", 0, hevc_tensor.numel()-1)
+  v_sz = Variable("sz", 0, hevc_tensor.numel())
+  v_i = Variable("i", 0, len(frame_info)-1)

-  # warmup decode
-  _ = list(hevc_decode(hevc_tensor, opaque_nv, frame_info[:3], luma_h, luma_w, history=hist, preallocated_outputs=out_images))
-  Device.default.synchronize()
+  @TinyJit
+  def decode_jit(pos:Variable, src:Tensor, data:Tensor, *hist:Tensor):
+    return src.decode_hevc_frame(pos, out_image_size, data, hist).realize()

-  # decode all frames using the iterator
+  # warm up
+  history = [Tensor.empty(*out_image_size, dtype=dtypes.uint8, device="NV") for _ in range(max_hist)]
+  for i in range(3):
+    hevc_frame = hevc_tensor.shrink((((bound_offset:=v_offset.bind(frame_info[0][0])), bound_offset+v_sz.bind(frame_info[0][1])),))
+    decode_jit(v_pos.bind(0), hevc_frame, opaque_nv[v_i.bind(0)], *history)
+
+  out_images = []
  with Timing("decoding whole file: ", on_exit=(lambda et: f", {len(frame_info)} frames, {len(frame_info)/(et/1e9):.2f} fps")):
-    images = list(hevc_decode(hevc_tensor, opaque_nv, frame_info, luma_h, luma_w, history=hist, preallocated_outputs=out_images))
+    for i, (offset, sz, frame_pos, history_sz, is_hist) in enumerate(frame_info):
+      history = history[-max_hist:] if max_hist > 0 else []
+      # TODO: this shrink should work as a slice
+      hevc_frame = hevc_tensor.shrink((((bound_offset:=v_offset.bind(offset)), bound_offset+v_sz.bind(sz)),))
+
+      outimg = decode_jit(v_pos.bind(frame_pos), hevc_frame, opaque_nv[v_i.bind(i)], *history).clone()
+      out_images.append(outimg)
+      if is_hist: history.append(outimg)
+
    Device.default.synchronize()

-  # validation
  if getenv("VALIDATE", 0):
    import pickle
    if dat_hash == "b813bfdbec194fd17fdf0e3ceb8cea1c":
@@ -87,7 +70,7 @@ if __name__ == "__main__":
    else: decoded_frames = pickle.load(open(f"extra/hevc/decoded_frames_{dat_hash}.pkl", "rb"))
  else: import cv2

-  for i, img in tqdm(enumerate(images)):
+  for i, img in tqdm(enumerate(out_images)):
    if getenv("VALIDATE", 0):
      if i < len(decoded_frames) and len(decoded_frames[i]) > 0:
        img = untile_nv12(img, h, w, luma_w, chroma_off).realize()
@@ -129,7 +129,7 @@ class LSTM:
      return self.do_step(x_, hc_)

    if hc is None:
-      hc = Tensor.zeros(self.layers, 2 * x.shape[1], self.hidden_size, requires_grad=False).contiguous().realize()
+      hc = Tensor.zeros(self.layers, 2 * x.shape[1], self.hidden_size, requires_grad=False)

    output = None
    for t in range(x.shape[0]):
@@ -1,13 +1,9 @@
 import unittest
 import numpy as np

-from tinygrad.helpers import BEAM, Timing, CI, prod
-from tinygrad import Variable, Device, Tensor
+from tinygrad.helpers import BEAM, Timing, CI, Context
+from tinygrad import Variable, Tensor
 from tinygrad.nn import Conv2d
-from tinygrad.uop.ops import AxisType
-from tinygrad.codegen.opt import Opt, OptOps
-from tinygrad.codegen.opt.postrange import Scheduler
-from tinygrad.codegen.opt.search import get_kernel_actions

 def rand(*shape):
  return Tensor(np.random.rand(*shape).astype(np.float32))
@@ -79,27 +75,5 @@ class TestBeamSearch(unittest.TestCase):
        a = (a + a) * a
    a.realize()

-  @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores")
-  def test_tc_up(self):
-    tc = Device[Device.DEFAULT].renderer.tensor_cores[0]
-    size = max(tc.dims[0], tc.dims[1]) * 8
-    a, b = Tensor.rand(size, size, dtype=tc.dtype_in), Tensor.rand(size, size, dtype=tc.dtype_in)
-    ast = a.matmul(b, dtype=tc.dtype_out).schedule()[-1].ast
-    s = Scheduler(ast, Device[Device.DEFAULT].renderer)
-    s.apply_opt(Opt(OptOps.TC, 0, (-1, 0, 1)))
-    up = prod([x for x, t in zip(s.full_shape, s.axis_types) if t in (AxisType.UPCAST, AxisType.UNROLL)])
-    actions = get_kernel_actions(s, include_0=False, max_up=int(up))
-    upcasted = [s for s in actions.values() if any(opt.op in (OptOps.UPCAST, OptOps.UNROLL) for opt in s.applied_opts)]
-    assert len(upcasted) > 0, f"expected upcast/unroll actions after TC with max_up={up}, but got none"
-
-  def test_max_up(self):
-    a = Tensor.rand(16, 16)
-    ast = a.schedule()[-1].ast
-    s = Scheduler(ast, Device[Device.DEFAULT].renderer)
-    for max_up in (2, 4):
-      actions = get_kernel_actions(s, include_0=False, max_up=max_up)
-      for up_opts in [s.applied_opts for s in actions.values() if any(opt.op in (OptOps.UPCAST, OptOps.UNROLL) for opt in s.applied_opts)]:
-        assert len([opt for opt in up_opts if opt.arg > max_up]) == 0 and len([op for op in up_opts if op.arg <= max_up]) > 0
-
 if __name__ == '__main__':
  unittest.main()
@@ -3,18 +3,21 @@

 import numpy as np
 import unittest
-import subprocess, struct, math, functools
-from tinygrad import Tensor, dtypes, Device
+import subprocess, struct, math, textwrap
+from tinygrad import Tensor, dtypes, Device, UOp
+from tinygrad.uop.ops import Ops
 from tinygrad.helpers import getenv
+from tinygrad.runtime.support.compiler_amd import amdgpu_disassemble
+from tinygrad.renderer import ProgramSpec
+from tinygrad.engine.realize import CompiledRunner

 from extra.assembly.amd.autogen.rdna3.ins import *
 from extra.assembly.amd.asm import waitcnt
-
-from test.testextra.test_cfg_viz import asm_kernel
+from test.testextra.test_cfg_viz import template

 def get_output(asm:list, n_threads:int=1, vdst:VGPR=v[1]):
  out = Tensor([0]*n_threads, dtype=dtypes.uint32).realize()
-  insts = [
+  src = "\n".join(inst.disasm() for inst in [
    s_load_b64(s[0:1], s[0:1], NULL),
    *asm,
    v_lshlrev_b32_e32(v[0], 2, v[0]),
@@ -22,9 +25,12 @@ def get_output(asm:list, n_threads:int=1, vdst:VGPR=v[1]):
    #global_store_b32(v[0], v[1], s[0:1]),
    global_store_b32(addr=v[0], data=vdst, saddr=s[0:1]),
    s_endpgm()
-  ]
-  out = Tensor.custom_kernel(out, fxn=functools.partial(asm_kernel, name="test", insts=insts, device=out.device, n_threads=n_threads))[0]
-  out.realize()
+  ])
+  prg = ProgramSpec("test", template.replace("fn_name", "test").replace("INSTRUCTION", textwrap.dedent(src)), Device.DEFAULT, UOp(Ops.SINK),
+                    global_size=[1, 1, 1], local_size=[n_threads, 1, 1], globals=[0])
+  car = CompiledRunner(prg)
+  if getenv("PRINT_ASM"): amdgpu_disassemble(car.lib)
+  car([out.uop.buffer], {}, wait=True)
  return out.tolist()

 def f16_to_bits(x:float) -> int: return struct.unpack('<H', struct.pack('<e', x))[0]
@@ -8,7 +8,7 @@ SQTT is implemented on top of normal tinygrad profiling, `VIZ=1 SQTT=1` to get p

 `SQTT_ITRACE_SE_MASK=X` to select for which shader engines instruction tracing will be enabled, -1 is all, 0 is none (instruction tracing disabled), >0 is
 bitfield/mask for SEs to enable instruction tracing on. Masking shader engines will give smaller file sizes at a cost of less hits and kernels that
-don't have any wavefront on first simd of shader engine with instruction tracing enabled will not have instruction timings.
+don't have any wavefront on first simd of shdaer engine with instruction tracing enabled will not have instruction timings.
 The default is 2 (second shader engine only), only one for file size reasons, second instead of first because dispatch starts from it so there is
 greater chance that kernels with small global size will have instruction tracing data.
 
@@ -113,17 +113,12 @@ def decode(sqtt_evs:list[ProfileSQTTEvent], disasms:dict[str, dict[int, tuple[st

    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS

-  exc:Exception|None = None
  def worker():
-    nonlocal exc
    try: rocprof.rocprof_trace_decoder_parse_data(copy_cb, trace_cb, isa_cb, None)
    except AttributeError as e:
-      exc = RuntimeError("Failed to find rocprof-trace-decoder. Run sudo ./extra/sqtt/install_sqtt_decoder.py to install")
-      exc.__cause__ = e
+      raise RuntimeError("Failed to find rocprof-trace-decoder. Run sudo ./extra/sqtt/install_sqtt_decoder.py to install") from e
  (t:=threading.Thread(target=worker, daemon=True)).start()
  t.join()
-  if exc is not None:
-    raise exc
  return ROCParseCtx

 def print_data(data:dict) -> None:
@@ -45,6 +45,7 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
      k_smem = ker.st((KV_BLOCK_SIZE, D), dtypes.bfloat16)
      v_smem = ker.st((KV_BLOCK_SIZE, D), dtypes.bfloat16)

+      q_reg_fl = ker.rt((Q_BLOCK_SIZE, D), dtypes.float32)
      q_reg = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16)
      q_reg_transposed = ker.rt((D, Q_BLOCK_SIZE), dtypes.bfloat16, TileLayout.COL)
      k_reg = ker.rt((KV_BLOCK_SIZE, D), dtypes.bfloat16)
@@ -68,7 +69,9 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
      scale_vec = warp.ones(scale_vec)

      # load q tile
-      q_reg = warp.load(q_reg, q, (), (batch, q_seq, head, 0), axis=1)
+      q_reg_fl = warp.load(q_reg_fl, q, (), (batch, q_seq, head, 0), axis=1)
+      q_reg_fl *= (1.0 / math.sqrt(D)) * (1.0 / math.log(2))
+      q_reg = warp.copy(q_reg, q_reg_fl)
      q_reg_transposed = warp.transpose(q_reg_transposed, q_reg)

      for kv_idx in ker.range(N // KV_BLOCK_SIZE):
@@ -82,7 +85,6 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
        att_block = warp.zero(att_block.after(kv_idx))
        k_reg_transposed = warp.transpose(k_reg_transposed, k_reg)
        att_block = warp.mma_AtB(att_block, k_reg_transposed, q_reg_transposed)
-        att_block *= (1.0 / math.sqrt(D)) * (1.0 / math.log(2))

        # apply attention mask
        mask_reg = warp.load(mask_reg, mask, (), (batch, 0, q_seq, kv_idx), axis=2)
@@ -215,11 +217,11 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False

      return ker.finish()

-  def custom_backward_k(dku:UOp, dou:UOp, qu:UOp, ku:UOp, vu:UOp, masku:UOp, l_vecu:UOp, delta_vecu:UOp) -> UOp:
-    with Kernel("fa_custom_backward_k", (H_KV, N // (KV_BLOCK_SIZE*NUM_WORKERS), B), NUM_WORKERS * WARP_THREADS) as ker:
+  def custom_backward_kv(dku:UOp, dvu:UOp, dou:UOp, qu:UOp, ku:UOp, vu:UOp, masku:UOp, l_vecu:UOp, delta_vecu:UOp) -> UOp:
+    with Kernel("fa_custom_backward_kv", (H_KV, N // (KV_BLOCK_SIZE*NUM_WORKERS), B), NUM_WORKERS * WARP_THREADS) as ker:
      warp = ker.warp

-      dk, do, q, k, v, mask = GL(dku, ker), GL(dou, ker), GL(qu, ker), GL(ku, ker), GL(vu, ker), GL(masku, ker)
+      dk, dv, do, q, k, v, mask = GL(dku, ker), GL(dvu, ker), GL(dou, ker), GL(qu, ker), GL(ku, ker), GL(vu, ker), GL(masku, ker)
      l_vec, delta_vec = GL(l_vecu, ker), GL(delta_vecu, ker)

      head_kv = ker.blockIdx_x
@@ -240,6 +242,7 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
      mask_reg_transposed = ker.rt((KV_BLOCK_SIZE, Q_BLOCK_SIZE), dtypes.float32, TileLayout.COL)

      dk_reg = ker.rt((KV_BLOCK_SIZE, D), dtypes.float32, TileLayout.COL)
+      dv_reg = ker.rt((KV_BLOCK_SIZE, D), dtypes.float32, TileLayout.COL)
      do_reg = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16)
      do_reg_col = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16, TileLayout.COL)

@@ -253,98 +256,6 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
      delta_vec_reg = ker.rv(Q_BLOCK_SIZE, dtypes.float32)

      dk_reg = warp.zero(dk_reg)
-
-      # load kv tile
-      k_reg = warp.load(k_reg, k, (), (batch, kv_seq, head_kv, 0), axis=1)
-      k_reg_t = warp.transpose(k_reg_t, k_reg)
-      v_reg = warp.load(v_reg, v, (), (batch, kv_seq, head_kv, 0), axis=1)
-
-      for q_idx in ker.range(N // Q_BLOCK_SIZE):
-        for g in ker.range(GROUP_SIZE):
-          head_q = head_kv * GROUP_SIZE + g
-
-          # load q and do
-          q_smem = warp.load(q_smem, q, (), (batch, q_idx, head_q, 0), axis=1)
-          do_smem = warp.load(do_smem, do, (), (batch, q_idx, head_q, 0), axis=1)
-
-          q_reg = warp.load(q_reg, q_smem)
-          q_reg_t = warp.transpose(q_reg_t, q_reg)
-          q_reg_col = warp.load(q_reg_col, q_smem)
-          do_reg = warp.load(do_reg, do_smem)
-          do_reg_col = warp.load(do_reg_col, do_smem)
-
-          # load l_vec and delta_vec
-          l_vec_reg = warp.load(l_vec_reg, l_vec, (), (batch, head_q, 0, q_idx), axis=2)
-          l_vec_reg *= 1.0 / math.log(2)
-          delta_vec_reg = warp.load(delta_vec_reg, delta_vec, (), (batch, head_q, 0, q_idx), axis=2)
-
-          # mma qk^t
-          att_block = warp.zero(att_block.after(g))
-          att_block = warp.mma_AtB(att_block, k_reg_t, q_reg_t)
-
-          # apply attention mask
-          mask_reg = warp.load(mask_reg, mask, (), (batch, 0, q_idx, kv_seq), axis=2)
-          mask_reg_transposed = warp.transpose(mask_reg_transposed, mask_reg)
-          att_block += mask_reg_transposed
-
-          att_block *= (1.0 / math.sqrt(D)) * (1.0 / math.log(2))
-          att_block -= l_vec_reg
-          att_block = att_block.exp2()
-
-          dp_block = warp.zero(dp_block.after(g, q_idx))
-          dp_block = warp.mma_ABt(dp_block, v_reg, do_reg)
-          dp_block -= delta_vec_reg
-          att_block *= dp_block
-
-          att_block_mma = warp.copy(att_block_mma, att_block)
-          att_block_transposed = warp.transpose(att_block_transposed, att_block_mma)
-          att_smem = warp.store(att_smem, att_block_transposed)
-          att_block_row = warp.load(att_block_row, att_smem)
-          dk_reg = warp.mma_AB(dk_reg, att_block_row, q_reg_col)
-      dk_reg = ker.endrange(2)
-
-      dk_reg *= 1.0 / math.sqrt(D)
-
-      dk = warp.store(dk, dk_reg, (batch, kv_seq, head_kv, 0), axis=1)
-
-      return ker.finish()
-
-  def custom_backward_v(dvu:UOp, dou:UOp, qu:UOp, ku:UOp, vu:UOp, masku:UOp, l_vecu:UOp, delta_vecu:UOp) -> UOp:
-    with Kernel("fa_custom_backward_v", (H_KV, N // (KV_BLOCK_SIZE*NUM_WORKERS), B), NUM_WORKERS * WARP_THREADS) as ker:
-      warp = ker.warp
-
-      dv, do, q, k, v, mask = GL(dvu, ker), GL(dou, ker), GL(qu, ker), GL(ku, ker), GL(vu, ker), GL(masku, ker)
-      l_vec, delta_vec = GL(l_vecu, ker), GL(delta_vecu, ker)
-
-      head_kv = ker.blockIdx_x
-      batch = ker.blockIdx_z
-      kv_seq = ker.blockIdx_y * NUM_WORKERS + ker.warpid
-
-      q_smem = ker.st((Q_BLOCK_SIZE, D), dtypes.bfloat16)
-      do_smem = ker.st((Q_BLOCK_SIZE, D), dtypes.bfloat16)
-      att_smem = ker.st((Q_BLOCK_SIZE, KV_BLOCK_SIZE), dtypes.bfloat16)
-
-      q_reg = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16)
-      q_reg_t = ker.rt((D, Q_BLOCK_SIZE), dtypes.bfloat16, TileLayout.COL)
-      q_reg_col = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16, TileLayout.COL)
-      k_reg = ker.rt((KV_BLOCK_SIZE, D), dtypes.bfloat16)
-      k_reg_t = ker.rt((D, KV_BLOCK_SIZE), dtypes.bfloat16, TileLayout.COL)
-      v_reg = ker.rt((KV_BLOCK_SIZE, D), dtypes.bfloat16)
-      mask_reg = ker.rt((Q_BLOCK_SIZE, KV_BLOCK_SIZE), dtypes.float32)
-      mask_reg_transposed = ker.rt((KV_BLOCK_SIZE, Q_BLOCK_SIZE), dtypes.float32, TileLayout.COL)
-
-      dv_reg = ker.rt((KV_BLOCK_SIZE, D), dtypes.float32, TileLayout.COL)
-      do_reg = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16)
-      do_reg_col = ker.rt((Q_BLOCK_SIZE, D), dtypes.bfloat16, TileLayout.COL)
-
-      att_block = ker.rt((KV_BLOCK_SIZE, Q_BLOCK_SIZE), dtypes.float32, TileLayout.COL)
-      att_block_mma = ker.rt((KV_BLOCK_SIZE, Q_BLOCK_SIZE), dtypes.bfloat16, TileLayout.COL)
-      att_block_transposed = ker.rt((Q_BLOCK_SIZE, KV_BLOCK_SIZE), dtypes.bfloat16, TileLayout.COL)
-      att_block_row = ker.rt((Q_BLOCK_SIZE, KV_BLOCK_SIZE), dtypes.bfloat16)
-
-      l_vec_reg = ker.rv(Q_BLOCK_SIZE, dtypes.float32)
-      delta_vec_reg = ker.rv(Q_BLOCK_SIZE, dtypes.float32)
-
      dv_reg = warp.zero(dv_reg)

      # load kv tile
@@ -388,12 +299,27 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
          att_block_transposed = warp.transpose(att_block_transposed, att_block_mma)
          att_smem = warp.store(att_smem, att_block_transposed)
          att_block_row = warp.load(att_block_row, att_smem)
-          dv_reg = warp.mma_AB(dv_reg, att_block_row, do_reg_col)
-      dv_reg = ker.endrange(2)
+          dv_reg_ = warp.mma_AB(dv_reg, att_block_row, do_reg_col)

+          dp_block = warp.zero(dp_block.after(g, q_idx, dv_reg_))
+          dp_block = warp.mma_ABt(dp_block, v_reg, do_reg)
+          dp_block -= delta_vec_reg
+          att_block *= dp_block
+
+          att_block_mma = warp.copy(att_block_mma, att_block)
+          att_block_transposed = warp.transpose(att_block_transposed, att_block_mma)
+          att_smem = warp.store(att_smem, att_block_transposed)
+          att_block_row = warp.load(att_block_row, att_smem)
+          dk_reg = warp.mma_AB(dk_reg, att_block_row, q_reg_col)
+      dk_reg = ker.endrange(2)
+      dv_reg = dv_reg.after(dk_reg)
+
+      dk_reg *= 1.0 / math.sqrt(D)
+
+      dk = warp.store(dk, dk_reg, (batch, kv_seq, head_kv, 0), axis=1)
      dv = warp.store(dv, dv_reg, (batch, kv_seq, head_kv, 0), axis=1)

-      return ker.finish()
+      return ker.finish(2)

  if is_causal:
    if attn_mask is not None: raise RuntimeError("cannot set attn_mask when is_causal=True")
@@ -413,11 +339,11 @@ def flash_attention(xq, xk, xv, attn_mask:Tensor|None=None, is_causal:bool=False
    grad_v = Tensor.empty_like(v := Tensor(kernel.src[4]))
    mask = Tensor(kernel.src[5])

-    delta_vec = (grad * attn).sum(-1, dtype=dtypes.float32).transpose(1, 2).unsqueeze(-2).detach()
+    delta_vec = (grad * attn).sum(-1).transpose(1, 2).unsqueeze(-2).detach()
+    print(l_vec.shape, delta_vec.shape, grad.shape, attn.shape, grad_q.shape, grad_k.shape, grad_v.shape)

    grad_q = Tensor.custom_kernel(grad_q, grad, q, k, v, mask, l_vec, delta_vec, fxn=custom_backward_q)[0]
-    grad_k = Tensor.custom_kernel(grad_k, grad, q, k, v, mask, l_vec, delta_vec, fxn=custom_backward_k)[0]
-    grad_v = Tensor.custom_kernel(grad_v, grad, q, k, v, mask, l_vec, delta_vec, fxn=custom_backward_v)[0]
+    grad_k, grad_v = Tensor.custom_kernel(grad_k, grad_v, grad, q, k, v, mask, l_vec, delta_vec, fxn=custom_backward_kv)[:2]
    return (None, None, grad_q.uop, grad_k.uop, grad_v.uop, None)

  attn, l_vec = Tensor.custom_kernel(attn, l_vec, xq, xk, xv, attn_mask, fxn=custom_forward, grad_fxn=grad)[:2]
@@ -24,11 +24,13 @@ class Group:

  # ops that only work on a single warp

+  clear_rid = 1000
  def clear(self, reg:ALL_TILES, value:float=0):
    reg = cast(UOp, reg)
    assert self.warps == 1

-    rngs_for_shape = tuple(self.ker.raw_range(dim) for dim in reg.shape)
+    rngs_for_shape = tuple(UOp.range(dim, Group.clear_rid + i) for i, dim in enumerate(reg.shape))
+    Group.clear_rid += len(reg.shape)

    reg_store = reg[*rngs_for_shape].store(value).end(*rngs_for_shape)

@@ -39,12 +41,14 @@ class Group:
  def ones(self, reg:ALL_TILES): return self.clear(reg, 1)
  def neg_inf(self, reg:ALL_TILES): return self.clear(reg, -math.inf)

+  copy_rid = 300
  def copy(self, dst:ALL_TILES, src:ALL_TILES):
    dst, src = cast(UOp, dst), cast(UOp, src)
    assert self.warps == 1
    assert dst.shape == src.shape

-    rngs_for_shape = tuple(self.ker.raw_range(dim) for dim in dst.shape)
+    rngs_for_shape = tuple(UOp.range(dim, Group.copy_rid + i) for i, dim in enumerate(dst.shape))
+    Group.copy_rid += len(dst.shape)

    src_load = src[*rngs_for_shape]
    if src.dtype.base != dst.dtype.base:
@@ -215,7 +219,8 @@ class Group:
    red_reg = self.ker.alloc((1,), src.dtype.base, AddrSpace.REG)

    for height in self.ker.range(src.shape[-3], track=False):
-      i = self.ker.raw_range(red_reg.size)
+      i = UOp.range(red_reg.size, Group.clear_rid)
+      Group.clear_rid += 1
      red_reg = red_reg.after(height, *[tkr._rng for tkr in self.ker.range_stack])
      reg_store = red_reg.flatten()[i].store(init_value).end(i)
      red_reg = red_reg.after(reg_store).reshape(red_reg.shape)
@@ -249,7 +254,8 @@ class Group:
    red_reg = self.ker.alloc((1,), src.dtype.base, AddrSpace.REG)

    for width in self.ker.range(src.shape[-2], track=False):
-      i = self.ker.raw_range(red_reg.size)
+      i = UOp.range(red_reg.size, Group.clear_rid)
+      Group.clear_rid += 1
      red_reg = red_reg.after(width, *[tkr._rng for tkr in self.ker.range_stack])
      reg_store = red_reg.flatten()[i].store(init_value).end(i)
      red_reg = red_reg.after(reg_store).reshape(red_reg.shape)
@@ -296,20 +302,9 @@ class Group:
              row = laneid % rt.base_shape.rows
              col = rt.base_shape.stride * (laneid // rt.base_shape.rows) + inner

-            sheight = height
-            swidth = width
-            if len(idxs) == 2:
-              row_idx = idxs[0] * dst.shape[-3] * rt.base_shape.rows
-              col_idx = idxs[1] * dst.shape[-2] * rt.base_shape.cols
-
-              row += row_idx % st.base_shape.rows
-              col += col_idx % st.base_shape.cols
-              sheight += row_idx // st.base_shape.rows
-              swidth += col_idx // st.base_shape.cols
-
            srow, scol = cast(ST, src).swizzle(row, col)

-            src_load = src[*idxs[:-2], sheight, swidth, srow, scol]
+            src_load = src[*idxs[:-2], height, width, srow, scol]
            if src.dtype.base != dst.dtype.base:
              src_load = src_load.cast(dst.dtype.base)
            dst_store = dst[*dst_idxs, height, width, inner].store(src_load)
@@ -323,31 +318,28 @@ class Group:
      idxs = tuple(idx * st.cols if i == 3 else idx for i, idx in enumerate(idxs))
      src_i = ((idxs[0] * src.shape[-3] + idxs[1]) * src.shape[-2] + idxs[2]) * src.shape[-1] + idxs[3]

-      elements_per_thread = st.base_shape.elements_per_thread
-      memcpy_per_row = st.cols // elements_per_thread
-      total_calls = (dst.shape[-4] * dst.shape[-3] * st.base_shape.num_elements) // (self.group_threads * elements_per_thread)
+      for height in self.ker.range(dst.shape[-4], track=False):
+        for width in self.ker.range(dst.shape[-3], track=False):
+          elements_per_thread = st.base_shape.elements_per_thread
+          memcpy_per_row = st.base_shape.cols // elements_per_thread
+          total_calls = st.base_shape.num_elements // (self.group_threads * elements_per_thread)

-      for outer in self.ker.range(total_calls, track=False):
-        for inner in self.ker.range(elements_per_thread, axis_type=AxisType.UPCAST, track=False):
-          load_idx = outer * self.group_threads + self.laneid
-          row = load_idx // memcpy_per_row
-          col = (load_idx * elements_per_thread) % st.cols + inner
-          height = row // st.base_shape.rows
-          width = col // st.base_shape.cols
+          for outer in self.ker.range(total_calls, track=False):
+            for inner in self.ker.range(elements_per_thread, axis_type=AxisType.UPCAST, track=False):
+              load_idx = outer * self.group_threads + self.laneid
+              row = load_idx // memcpy_per_row
+              col = (load_idx * elements_per_thread) % st.base_shape.cols + inner

-          row = row % st.base_shape.rows
-          col = col % st.base_shape.cols
+              srow, scol = cast(ST, dst).swizzle(row, col)

-          srow, scol = cast(ST, dst).swizzle(row, col)
+              src_i += height * st.base_shape.rows * row_stride + width * st.base_shape.cols
+              src_i += row * row_stride + col

-          src_i += height * st.base_shape.rows * row_stride + width * st.base_shape.cols
-          src_i += row * row_stride + col
-
-          src_load = srcf[src_i]
-          if src.dtype.base != dst.dtype.base:
-            src_load = src_load.cast(dst.dtype.base)
-          dst_store = dst[*dst_idxs, height, width, srow, scol].store(src_load)
-          dst_store = dst_store.end(height, width, outer, inner).barrier()
+              src_load = srcf[src_i]
+              if src.dtype.base != dst.dtype.base:
+                src_load = src_load.cast(dst.dtype.base)
+              dst_store = dst[*dst_idxs, height, width, srow, scol].store(src_load)
+              dst_store = dst_store.end(height, width, outer, inner).barrier()
    elif dst_dtype.addrspace == AddrSpace.REG and src_dtype.addrspace == AddrSpace.GLOBAL and isinstance(dst, RT):
      srcf = src.flatten()
      row_stride = prod(src.shape[axis+1:])
@@ -479,7 +471,7 @@ class Group:
      idxs = tuple(idx * rv.length if i == 3 else idx for i, idx in enumerate(idxs))
      dst_i = ((idxs[0] * dst.shape[-3] + idxs[1]) * dst.shape[-2] + idxs[2]) * dst.shape[-1] + idxs[3]

-      for outer in self.ker.range(src.shape[-2], track=False):
+      for outer in self.ker.range(src.shape[-2]):
        dst_i += outer * reductions + (laneid % reductions)

        src_load = src[outer, 0]
@@ -55,11 +55,6 @@ class Kernel(AbstractContextManager):
    if track: self.range_stack.append(rng)
    return rng

-  def raw_range(self, end:int=0, axis_type:AxisType=AxisType.LOOP):
-    rng = UOp.range(end, self.range_id, axis_type=axis_type)
-    self.range_id += 1
-    return rng
-
  def alloc(self, shape, dtype, addrspace:AddrSpace, name:str|None=None):
    match addrspace:
      case AddrSpace.GLOBAL:
@@ -1,38 +0,0 @@
-#!/usr/bin/env python3
-import argparse, pathlib
-from typing import Iterator
-from tinygrad.viz import serve as viz
-from tinygrad.uop.ops import RewriteTrace
-from tinygrad.helpers import temp, ansistrip, colored
-
-def optional_eq(val:dict, arg:str|None) -> bool: return arg is None or ansistrip(val["name"]) == arg
-
-def print_data(data:dict) -> None:
-  if isinstance(data.get("value"), Iterator):
-    for m in data["value"]:
-      if not m["diff"]: continue
-      fp = pathlib.Path(m["upat"][0][0])
-      print(f"{fp.parent.name}/{fp.name}:{m['upat'][0][1]}")
-      print(m["upat"][1])
-      for line in m["diff"]:
-        color = "red" if line.startswith("-") else "green" if line.startswith("+") else None
-        print(colored(line, color))
-  if data.get("src") is not None: print(data["src"])
-
-if __name__ == "__main__":
-  parser = argparse.ArgumentParser()
-  parser.add_argument('--kernel', type=str, default=None, metavar="NAME", help='Select a kernel by name (optional name, default: only list names)')
-  parser.add_argument('--select', type=str, default=None, metavar="NAME",
-                      help='Select an item within the chosen kernel (optional name, default: only list names)')
-  args = parser.parse_args()
-
-  viz.trace = viz.load_pickle(pathlib.Path(temp("rewrites.pkl", append_user=True)), default=RewriteTrace([], [], {}))
-  viz.ctxs = viz.get_rewrites(viz.trace)
-  for k in viz.ctxs:
-    if not optional_eq(k, args.kernel): continue
-    print(k["name"])
-    if args.kernel is None: continue
-    for s in k["steps"]:
-      if not optional_eq(s, args.select): continue
-      print(" "*s["depth"]+s['name']+(f" - {s['match_count']}" if s.get('match_count') is not None else ''))
-      if args.select is not None: print_data(viz.get_render(s['query']))
@@ -1,6 +1,6 @@
 [project]
 name = "tinygrad"
-version = "0.12.0"
+version = "0.11.0"
 description = "You like pytorch? You like micrograd? You love tinygrad! <3"
 authors = [{ name = "George Hotz" }]

@@ -66,10 +66,10 @@ testing_minimal = [
  "pytest-xdist",
  "pytest-timeout",
  "pytest-split",
-  "hypothesis>=6.148.9",
+  "hypothesis",
  "z3-solver",
 ]
-testing_unit = ["tinygrad[testing_minimal]", "tqdm", "safetensors", "tabulate", "openai", "ggml-python"]
+testing_unit = ["tinygrad[testing_minimal]", "tqdm", "safetensors", "tabulate", "openai"]
 testing = [
  "tinygrad[testing_unit]",
  "pillow",
@@ -87,6 +87,7 @@ testing = [
  "networkx",
  "nibabel",
  "bottle",
+  "ggml-python",
  "capstone",
  "pycocotools",
  "boto3",
@@ -134,14 +135,9 @@ check_untyped_defs = true
 explicit_package_bases = true
 warn_unreachable = true
 warn_redundant_casts = true
-strict_equality = true
 # NOTE: had to comment this out to make mypy pass on both CI and OSX
 #warn_unused_ignores = true

-[[tool.mypy.overrides]]
-module = "extra.*"
-follow_imports = "skip"
-
 [tool.pytest.ini_options]
 norecursedirs = [
  "extra",
@@ -0,0 +1,28 @@
+from tinygrad import Tensor, dtypes, GlobalCounters
+from tinygrad.engine.realize import get_program
+
+if __name__ == "__main__":
+  t = Tensor.empty(81920, 4096, dtype=dtypes.half)
+  GlobalCounters.reset()
+  t.softmax(-1, dtype="half").realize()
+  GlobalCounters.reset()
+  t.softmax(-1, dtype="half", _single_kernel=True).realize()
+
+  from tinygrad.codegen.opt.kernel import Kernel, Opt, OptOps
+  from tinygrad.helpers import get_single_element
+  GlobalCounters.reset()
+  si = get_single_element(t.softmax(-1, dtype="half", _single_kernel=True).schedule())
+  k = Kernel(si.ast)
+  #k.apply_opt(Opt(OptOps.UPCAST, 0, 4))
+  k.apply_opt(Opt(OptOps.UPCAST, 1, 4))
+  k.apply_opt(Opt(OptOps.LOCAL, 1, 32))
+  #k.apply_opt(Opt(OptOps.LOCAL, 0, 8))
+  k.apply_opt(Opt(OptOps.UNROLL, 1, 4))
+  k.apply_opt(Opt(OptOps.UNROLL, 0, 4))
+  #k.apply_opt(Opt(OptOps.GROUP, 1, 256))
+  #k.apply_opt(Opt(OptOps.GROUP, 0, 32))
+  #k.apply_opt(Opt(OptOps.GROUP, 1, 32))
+  #k.apply_opt(Opt(OptOps.GROUP, 0, 32))
+  from tinygrad.engine.realize import CompiledRunner, ExecItem
+  run = CompiledRunner(prg:=get_program(k.ast, k.opts, k.applied_opts))
+  ExecItem(k.ast, list(si.bufs), prg=run).run()
@@ -0,0 +1,56 @@
+# ruff: noqa: E501
+from tinygrad import dtypes
+from tinygrad.helpers import Timing, getenv
+from tinygrad.codegen.opt.kernel import Opt, OptOps
+from tinygrad.engine.realize import get_program, CompiledRunner
+from tinygrad.uop.ops import UOp, Ops, AxisType
+
+if __name__ == "__main__":
+  if getenv("TC", 0) == 0:
+    c0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1179648), arg=0, src=())
+    c1 = UOp.range(UOp.const(dtypes.int, 512), 0, AxisType.GLOBAL)
+    c2 = UOp.range(UOp.const(dtypes.int, 64), 1, AxisType.GLOBAL)
+    c3 = UOp.range(UOp.const(dtypes.int, 6), 2, AxisType.GLOBAL)
+    c4 = UOp.range(UOp.const(dtypes.int, 6), 3, AxisType.GLOBAL)
+    c5 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(2097152), arg=1, src=())
+    c6 = UOp.range(UOp.const(dtypes.int, 64), 1004, AxisType.REDUCE)
+    c7 = UOp.range(UOp.const(dtypes.int, 3), 1005, AxisType.REDUCE)
+    c8 = UOp.range(UOp.const(dtypes.int, 3), 1006, AxisType.REDUCE)
+    c9 = c5.index(((((((c1*UOp.const(dtypes.int, 4096))+(c3*UOp.const(dtypes.int, 8)))+c4)+(c6*UOp.const(dtypes.int, 64)))+(c7*UOp.const(dtypes.int, 8)))+c8), UOp.const(dtypes.bool, True)).load()
+    c10 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(36864), arg=2, src=())
+    c11 = c10.index(((((c2*UOp.const(dtypes.int, 576))+(c6*UOp.const(dtypes.int, 9)))+(c7*UOp.const(dtypes.int, 3)))+c8), UOp.const(dtypes.bool, True)).load()
+    c12 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=3, src=())
+    c13 = c12.index(c2, UOp.const(dtypes.bool, True)).load()
+    c14 = ((c9*c11).reduce(c6, c7, c8, arg=Ops.ADD)+c13)
+    c15 = c0.index(((((c1*UOp.const(dtypes.int, 2304))+(c2*UOp.const(dtypes.int, 36)))+(c3*UOp.const(dtypes.int, 6)))+c4), UOp.const(dtypes.bool, True)).store(c14, c1, c2, c3, c4)
+    ast = c15.sink()
+
+    # this does have tons of locals
+    opts = [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.UPCAST, axis=3, arg=0),
+            Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=3, arg=2),
+            Opt(op=OptOps.GROUPTOP, axis=0, arg=16)]
+  else:
+    c0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(10616832), arg=0, src=())
+    c1 = UOp.range(UOp.const(dtypes.int, 512), 0, AxisType.GLOBAL)
+    c2 = UOp.range(UOp.const(dtypes.int, 64), 1, AxisType.GLOBAL)
+    c3 = UOp.range(UOp.const(dtypes.int, 36), 2, AxisType.GLOBAL)
+    c4 = UOp.range(UOp.const(dtypes.int, 9), 3, AxisType.GLOBAL)
+    c5 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(36864), arg=1, src=())
+    c6 = UOp.range(UOp.const(dtypes.int, 64), 1004, AxisType.REDUCE)
+    c7 = c5.index((((c2*UOp.const(dtypes.int, 9))+c4)+(c6*UOp.const(dtypes.int, 576))), UOp.const(dtypes.bool, True)).load()
+    c8 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1179648), arg=2, src=())
+    c9 = c8.index((((c1*UOp.const(dtypes.int, 2304))+c3)+(c6*UOp.const(dtypes.int, 36))), UOp.const(dtypes.bool, True)).load()
+    c10 = (c7*c9).reduce(c6, arg=Ops.ADD)
+    c11 = c0.index(((((c1*UOp.const(dtypes.int, 20736))+(c2*UOp.const(dtypes.int, 324)))+(c3*UOp.const(dtypes.int, 9)))+c4), UOp.const(dtypes.bool, True)).store(c10, c1, c2, c3, c4)
+    ast = c11.sink()
+
+    opts = [Opt(op=OptOps.TC, axis=0, arg=(0, 0, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=4),
+            Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=0)]
+
+  prg = get_program(ast, opts=opts)
+  print(prg.src)
+  for i in range(10):
+    with Timing(f"try {i}: "):
+      # NOTE: this doesn't even run the kernel
+      try: CompiledRunner(prg)
+      except RuntimeError: pass
@@ -64,6 +64,8 @@ backend_test.exclude('test_qlinearmatmul_2D_int8_float32_cpu')
 backend_test.exclude('test_qlinearmatmul_3D_int8_float32_cpu')
 # tested in external_test_onnx_ops.py::TestMainOnnxOps.test_maxunpool_export_with_output_shape
 backend_test.exclude('test_maxunpool_export_with_output_shape_cpu')
+# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True
+backend_test.exclude('test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True_cpu')
 # tested in external_test_onnx_ops.py::TestMainOnnxOps.test_resize_downsample_scales_linear_align_corners
 backend_test.exclude('test_resize_downsample_scales_linear_align_corners_cpu')
 # tested in external_test_onnx_ops.py::TestMainOnnxOps.test_resize_downsample_scales_cubic_align_corners
@@ -140,11 +142,17 @@ backend_test.exclude('test_affine_grid_3d_expanded_cpu')
 backend_test.exclude('test_range_int32_type_negative_delta_expanded_cpu')

 # unsupported (strange) ops
+backend_test.exclude('test_blackmanwindow_*')
 backend_test.exclude('test_bernoulli_*')
 backend_test.exclude('test_det_*')
 backend_test.exclude('test_col2im_*')
+backend_test.exclude('test_hammingwindow_*')
+backend_test.exclude('test_hannwindow_*')
+backend_test.exclude('test_hardmax_*')
 backend_test.exclude('test_gridsample_*')
 backend_test.exclude('test_dft_*')
+backend_test.exclude('test_einsum_batch_diagonal_cpu*') # TODO: equation = '...ii ->...i'
+backend_test.exclude('test_einsum_inner_prod_cpu*') # TODO: equation = 'i,i'
 backend_test.exclude('test_unique_*')
 backend_test.exclude('test_sequence_*')
 backend_test.exclude('test_nonmaxsuppression_*')
@@ -162,11 +170,17 @@ backend_test.exclude('test_scan_*')
 backend_test.exclude('test_split_to_sequence_*')
 backend_test.exclude('test_ai_onnx_ml_tree_ensemble_*') # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/aionnxml/op_tree_ensemble.py#L121

-backend_test.exclude('test_attention_4d_diff_heads_mask4d_padded_kv_cpu')  # needs nonpad_kv_seqlen handling
-backend_test.exclude('test_attention_4d_fp16_cpu')  # fp16 numerical issues
-backend_test.exclude('test_attention_4d_fp16_expanded_cpu')  # fp16 numerical issues
-backend_test.exclude('test_attention_4d_gqa_with_past_and_present_fp16_cpu')  # fp16 numerical issues
-backend_test.exclude('test_attention_4d_gqa_with_past_and_present_fp16_expanded_cpu')  # fp16 numerical issues
+# TODO: not yet implemented
+backend_test.exclude('test_tensorscatter_*')
+backend_test.exclude('test_l1normalization_*')
+backend_test.exclude('test_l2normalization_*')
+backend_test.exclude('test_lpnormalization_*')
+backend_test.exclude('test_einsum_scalar_cpu')
+backend_test.exclude('test_mod_mixed_sign_float16_cpu')
+backend_test.exclude('test_qlinearmatmul_2D_uint8_float16_cpu')
+backend_test.exclude('test_qlinearmatmul_3D_uint8_float16_cpu')
+backend_test.exclude('test_attention_3d_*')
+backend_test.exclude('test_attention_4d_*')


 # rest of the failing tests
@@ -183,6 +197,16 @@ backend_test.exclude('test_ai_onnx_ml_label_encoder_tensor_mapping_cpu') # bad d
 backend_test.exclude('test_if_opt_cpu') # ValueError: 13 is not a valid AttributeType
 backend_test.exclude('test_if_seq_cpu') # NotImplementedError: op='SequenceConstruct' is not supported

+# regression from removing StrEnum in Domain
+backend_test.exclude('test_adam_cpu')
+backend_test.exclude('test_gradient_of_add_and_mul_cpu')
+backend_test.exclude('test_gradient_of_add_cpu')
+
+if Device.DEFAULT in ['CL', 'METAL']:
+  backend_test.exclude('test_resize_upsample_sizes_nearest_axes_2_3_cpu')
+  backend_test.exclude('test_resize_upsample_sizes_nearest_axes_3_2_cpu')
+  backend_test.exclude('test_resize_upsample_sizes_nearest_cpu')
+
 if Device.DEFAULT == "METAL" or (OSX and Device.DEFAULT == "CL"):
  # numerical inaccuracy
  backend_test.exclude('test_mish_cpu')
@@ -477,21 +477,18 @@ class TestContribOnnxOps(TestOnnxOps):

  def test_qlinear_global_average_pool(self):
    for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]:
-      for channels_last in [0, 1]:
-        with self.subTest(dtype=dtype, zero_point=zero_point, channels_last=channels_last):
-          dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max
-          # NCHW for channels_last=0, NHWC for channels_last=1
-          shape = [1, 3, 32, 32] if channels_last == 0 else [1, 32, 32, 3]
-          inputs = {
-            "X": np.random.randint(dtype_min, dtype_max + 1, shape, dtype=dtype),
-            "x_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32),
-            "x_zero_point": np.array(zero_point, dtype=dtype),
-            "y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32),
-            "y_zero_point": np.array(zero_point, dtype=dtype)
-          }
-          attributes = {"channels_last": channels_last}
-          outputs = ["C"]
-          self.helper_test_single_op("QLinearGlobalAveragePool", inputs, attributes, outputs)
+      with self.subTest(dtype=dtype, zero_point=zero_point):
+        dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max
+        inputs = {
+          "X": np.random.randint(dtype_min, dtype_max + 1, [1, 3, 32, 32], dtype=dtype),
+          "x_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32),
+          "x_zero_point": np.array(zero_point, dtype=dtype),
+          "y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32),
+          "y_zero_point": np.array(zero_point, dtype=dtype)
+        }
+        attributes = {"channels_last": 0}
+        outputs = ["C"]
+        self.helper_test_single_op("QLinearGlobalAveragePool", inputs, attributes, outputs)

 if __name__ == "__main__":
  unittest.main()
@@ -54,7 +54,7 @@ def replay_get_rangeify_map(ret:dict[UOp, UOp], big_sink:UOp) -> tuple[str, str,
 def replay_get_program(p:ProgramSpec, ast:UOp, renderer:Renderer, opts:list[Opt]|None=None) -> tuple[str, str, tuple[Any, ...]]:
  # the ast.arg is non None if we are inside of search.py
  sink_arg = ast.arg or KernelInfo(opts_to_apply=tuple(opts) if opts is not None else p.applied_opts if BEAM>=1 else None)
-  input_ast = ast if ast.op is Ops.PROGRAM else ast.replace(arg=replace(sink_arg, name=p.name))
+  input_ast = ast.replace(arg=replace(sink_arg, name=p.name))
  p2 = get_program(input_ast, renderer=renderer)
  def to_str(ret:ProgramSpec) -> str:
    # PYTHON renderer pickles UOps, first unpickle and decode here
@@ -12,10 +12,10 @@ libc.mmap.restype = ctypes.c_void_p
 drivers = [AMDDriver(), NVDriver()]
 tracked_fds = {}

-original_memoryview = builtins.memoryview
+orignal_memoryview = builtins.memoryview
 class TrackedMemoryView:
  def __init__(self, data, rcb, wcb):
-    self.mv = original_memoryview(data)
+    self.mv = orignal_memoryview(data)
    self.rcb, self.wcb = rcb, wcb

  def __getitem__(self, index):
@@ -41,7 +41,7 @@ def _memoryview(cls, mem):
    for d in drivers:
      for st,en,rcb,wcb in d.tracked_addresses:
        if st <= addr <= en: return TrackedMemoryView(mem, rcb, wcb)
-  return original_memoryview(mem)
+  return orignal_memoryview(mem)
 builtins.memoryview = type("memoryview", (), {'__new__': _memoryview}) # type: ignore

 def _open(path, flags):
@@ -8,9 +8,9 @@ import torch

 def get_question_samp(bsz, seq_len, vocab_size, seed):
  np.random.seed(seed)
-  in_ids = np.random.randint(vocab_size, size=(bsz, seq_len), dtype=np.int32)
+  in_ids= np.random.randint(vocab_size, size=(bsz, seq_len))
  mask = np.random.choice([True, False], size=(bsz, seq_len))
-  seg_ids = np.random.randint(2, size=(bsz, seq_len), dtype=np.int32)  # type_vocab_size
+  seg_ids = np.random.randint(2, size=(bsz, seq_len))  # type_vocab_size
  return in_ids, mask, seg_ids

 def set_equal_weights(mdl, torch_mdl):
@@ -1,10 +1,6 @@
 import unittest
 from extra.models import resnet
-from tinygrad import dtypes
-from tinygrad.device import is_dtype_supported

-# pretrained weights contain num_batches_tracked as int64
-@unittest.skipUnless(is_dtype_supported(dtypes.int64), "need int64 support")
 class TestResnet(unittest.TestCase):
  def test_model_load(self):
    model = resnet.ResNet18()
@@ -52,8 +52,6 @@ def wer_helper(result: str, reference: str)->float:

@unittest.skipIf(Device.DEFAULT in ["CPU"], "slow")
@unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support")
-# TODO: WEBGPU GPU dispatch dimensions limit
-@unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU GPU dispatch dimensions limit")
 class TestWhisper(unittest.TestCase):
  @classmethod
  def setUpClass(cls):
@@ -11,7 +11,6 @@ from tinygrad.helpers import AMX, AMD_LLVM, CPU_LLVM, Context
 from test.helpers import slow
 from tinygrad.engine.realize import CompiledRunner, get_program
 from tinygrad.codegen.opt import Opt, OptOps, KernelOptError
-from tinygrad.codegen.opt.tc import amd_cdna_1616128

 # TODO: write a clean version of this
 from test.test_linearizer import helper_realized_ast, helper_linearizer_opt
@@ -121,7 +120,7 @@ class TestTensorCores(unittest.TestCase):
      # check excessive padding doesn't trigger padded TC in TC_OPT=2
      helper_tc_ensure_uops_and_opts_count(tc.dims[0]//4, tc.dims[1], tc.dims[2], tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False)
      helper_tc_ensure_uops_and_opts_count(tc.dims[0], tc.dims[1]//4, tc.dims[2], tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False)
-      if not AMX and tc not in amd_cdna_1616128: # AMX tc.dims[2] == 1
+      if not AMX: # AMX tc.dims[2] == 1
        helper_tc_ensure_uops_and_opts_count(tc.dims[0], tc.dims[1], tc.dims[2]//8, tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False)

  @Context(ALLOW_TF32=1)
@@ -94,9 +94,10 @@ class TestIndexing(unittest.TestCase):
      X = dataset[idxs]
      assert X.shape == (4,DDIM)
      sched = X.schedule()
-      self.assertEqual(len(sched), 1)
+      # TODO: enable these asserts when the scheduler can handle this
+      #self.assertEqual(len(sched), 1)
      run_schedule(sched)
-      assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops}"
+      #assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops}"
    np.testing.assert_allclose(real_index, X.numpy())

  def test_index_fused(self, noopt=1):
@@ -308,7 +308,6 @@ class TestTautologicalCompare(unittest.TestCase):
    np.testing.assert_equal((Tensor(True) < Tensor(False)).numpy(), False)
    np.testing.assert_equal((Tensor(True) < Tensor(True)).numpy(), False)

-  @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU doesn't support NaN comparison correctly")
  def test_a_eq_a(self):
    # self eq is always true for int or bool
    a = Tensor([1, 2, 3])
@@ -43,13 +43,16 @@ def _test_cast(a:Tensor, target_dtype:DType):
  if a.is_floating_point() and dtypes.is_unsigned(target_dtype):
    # converting negative float to unsigned integer is undefined
    a = a.abs()
+  if target_dtype == dtypes.half and Device.DEFAULT == "PYTHON":
+    # TODO: struct.pack cannot pack value > 65504 (max of half) into e format
+    a = (a > 65504).where(65504, a)

  expected = list(a.numpy().astype(_to_np_dtype(target_dtype)))
-  if target_dtype in dtypes.fp8s: expected = [truncate[target_dtype](x) for x in expected]
+  if target_dtype in dtypes.fp8s: expected = list(map(lambda x: truncate[target_dtype](x), expected))
  _test_op(lambda: a.cast(target_dtype), target_dtype, expected)
 def _test_bitcast(a:Tensor, target_dtype:DType, target=None):
  expected = torch.tensor(a.tolist(), dtype=_to_torch_storage_type(a.dtype)).view(_to_torch_dtype(target_dtype)).tolist()
-  if target_dtype in dtypes.fp8s: expected = [fp8_to_float(x, target_dtype) for x in expected]
+  if target_dtype in dtypes.fp8s: expected = list(map(lambda x: fp8_to_float(x, target_dtype), expected))
  _test_op(lambda: a.bitcast(target_dtype), target_dtype, target or expected)

 class TestDType(unittest.TestCase):
@@ -65,34 +68,37 @@ class TestDType(unittest.TestCase):
  def test_to_np(self):
    _test_to_np(Tensor(self.DATA, dtype=self.DTYPE), _to_np_dtype(self.DTYPE), np.array(self.DATA, dtype=_to_np_dtype(self.DTYPE)))

-  def test_casts_to(self):
-    for dtype in get_available_cast_dtypes(self.DTYPE):
-      _test_cast(Tensor(self.DATA, dtype=dtype), self.DTYPE)
-
-  def test_casts_from(self):
-    for dtype in get_available_cast_dtypes(self.DTYPE):
-      _test_cast(Tensor(self.DATA, dtype=self.DTYPE), dtype)
+  def test_casts_to(self): list(map(
+    lambda dtype: _test_cast(Tensor(self.DATA, dtype=dtype), self.DTYPE),
+    get_available_cast_dtypes(self.DTYPE)
+  ))
+  def test_casts_from(self): list(map(
+    lambda dtype: _test_cast(Tensor(self.DATA, dtype=self.DTYPE), dtype),
+    get_available_cast_dtypes(self.DTYPE)
+  ))

  def test_same_size_ops(self):
-    for dtype in get_available_cast_dtypes(self.DTYPE):
-      if dtype.itemsize == self.DTYPE.itemsize:
-        _test_ops(a_dtype=self.DTYPE, b_dtype=dtype)
-
+    list(map(
+      lambda dtype: _test_ops(a_dtype=self.DTYPE, b_dtype=dtype) if dtype.itemsize == self.DTYPE.itemsize else None,
+      get_available_cast_dtypes(self.DTYPE)
+    ))
  def test_upcast_ops(self):
-    for dtype in get_available_cast_dtypes(self.DTYPE):
-      if dtype.itemsize > self.DTYPE.itemsize:
-        _test_ops(a_dtype=self.DTYPE, b_dtype=dtype)
-
+    list(map(
+      lambda dtype: _test_ops(a_dtype=self.DTYPE, b_dtype=dtype) if dtype.itemsize > self.DTYPE.itemsize else None,
+      get_available_cast_dtypes(self.DTYPE)
+  ))
  def test_upcast_to_ops(self):
-    for dtype in get_available_cast_dtypes(self.DTYPE):
-      if dtype.itemsize < self.DTYPE.itemsize:
-        _test_ops(a_dtype=dtype, b_dtype=self.DTYPE)
-
+    list(map(
+      lambda dtype: _test_ops(a_dtype=dtype, b_dtype=self.DTYPE) if dtype.itemsize < self.DTYPE.itemsize else None,
+      get_available_cast_dtypes(self.DTYPE)
+  ))
  def test_bitcast(self):
    if self.DTYPE == dtypes.bool: raise unittest.SkipTest("no bools in bitcast")
-    for dtype in get_available_cast_dtypes(self.DTYPE):
-      if dtype != dtypes.bool:
-        _test_bitcast(Tensor(self.DATA[:8], dtype=self.DTYPE), dtype)
+    list(map(
+      lambda dtype:
+        _test_bitcast(Tensor(self.DATA[:8], dtype=self.DTYPE), dtype) if dtype != dtypes.bool else None,
+     get_available_cast_dtypes(self.DTYPE)
+    ))

  @unittest.skipIf(Device.DEFAULT == "PYTHON", "skip for now")
  @unittest.skipIf(isinstance(Device[Device.DEFAULT].renderer, (PTXRenderer, NIRRenderer)), "skip for now")
@@ -125,7 +131,7 @@ class TestDType(unittest.TestCase):
  def test_finfo(self):
    if self.DTYPE not in [dtypes.float16, dtypes.float32, dtypes.float64]: return
    info = np.finfo(_to_np_dtype(self.DTYPE))
-    self.assertEqual(info.bits, self.DTYPE.bitsize)
+    self.assertEqual(info.bits, self.DTYPE.itemsize*8)
    self.assertEqual((info.nexp, info.nmant), dtypes.finfo(self.DTYPE))

 def _test_ops(a_dtype:DType, b_dtype:DType, target_dtype=None):
@@ -213,7 +219,7 @@ class TestBFloat16DType(unittest.TestCase):
    back = t.cast(dtypes.float32)
    assert tuple(back.numpy().tolist()) == (9984., -1, -1000, -9984, 20)

-@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16) and is_dtype_supported(dtypes.float16), "bfloat16 or float16 not supported")
+@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported")
 class TestBFloat16DTypeCast(unittest.TestCase):
  def test_f16_to_bf16_conversion(self):
    original_tensor = Tensor([1.0, 2.0, 3.0], dtype=dtypes.float16)
@@ -301,7 +307,7 @@ class TestBitCast(unittest.TestCase):
    data = rand_for_dtype(dt1, 32).reshape(2, 2, 8)
    expected = torch.tensor(data.tolist(), dtype=_to_torch_storage_type(dt1)).view(_to_torch_dtype(dt2))
    if dt2 in dtypes.fp8s:
-      expected = torch.tensor([fp8_to_float(x, dt2) for x in expected.view(-1).tolist()]).view_as(expected)
+      expected = torch.tensor(list(map(lambda x: fp8_to_float(x, dt2), expected.view(-1).tolist()))).view_as(expected)
    _test_op(lambda: Tensor(data, dtype=dt1).bitcast(dt2), dt2, expected.tolist())

  def test_shape_change_bitcast_exceptions(self):
@@ -423,6 +429,7 @@ class TestDtypeUsage(unittest.TestCase):
 class TestOpsBFloat16(unittest.TestCase):
  def test_cast(self):
    # TODO: helper_test_op breaks in unrelated part
+    # TODO: wrong output with CL=1 on mac
    data = [60000.0, 70000.0, 80000.0]
    np.testing.assert_allclose(Tensor(data).cast("bfloat16").numpy(), torch.tensor(data).type(torch.bfloat16).float().numpy())

@@ -113,7 +113,7 @@ class TestGraph(unittest.TestCase):
  def skip_if_not_multigraph(self):
    graph = g.func if isinstance(g:=(d:=Device[Device.DEFAULT]).graph, functools.partial) else g
    if not issubclass(graph, MultiGraphRunner): self.skipTest("graph is not supported (not MultiGraphRunner)")
-    if not hasattr(d.allocator, '_transfer') or not d.allocator.supports_transfer: self.skipTest("device is not supported (no transfers)")
+    if not hasattr(d.allocator, '_transfer'): self.skipTest("device is not supported (no transfers)")

  def test_order_copy_writed(self):
    self.skip_if_not_multigraph()
@@ -10,25 +10,25 @@ IMAGE_SUPPORTED_DEVICES = ("QCOM", "CL")

@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported")
 class TestImageCopy(unittest.TestCase):
-  def test_image_copyout_1x8(self, img_type=dtypes.imagef):
-    it = Tensor.arange(32).cast(img_type((1,8,4))).realize()
+  def test_image_copyout_1x1(self, img_type=dtypes.imagef):
+    it = Tensor.arange(4).cast(img_type((1,1,4))).realize()
    buf = it.uop.buffer
    out = buf.as_buffer()
-    np.testing.assert_equal(out.cast(it.dtype.fmt).tolist(), np.arange(32))
+    np.testing.assert_equal(out.cast(it.dtype.fmt).tolist(), np.arange(4))

  @unittest.skipUnless(is_dtype_supported(dtypes.half, device="PYTHON"), "need half")
-  def test_imageh_copyout_1x8(self): self.test_image_copyout_1x8(img_type=dtypes.imageh)
+  def test_imageh_copyout_1x1(self): self.test_image_copyout_1x1(img_type=dtypes.imageh)

-  def test_image_numpy_1x8(self, img_type=dtypes.imagef):
-    it = Tensor.arange(32).cast(img_type((1,8,4))).realize()
-    np.testing.assert_equal(it.numpy(), np.arange(32))
-  def test_imageh_numpy_1x8(self): self.test_image_numpy_1x8(img_type=dtypes.imageh)
+  def test_image_numpy_1x1(self, img_type=dtypes.imagef):
+    it = Tensor.arange(4).cast(img_type((1,1,4))).realize()
+    np.testing.assert_equal(it.numpy(), np.arange(4))
+  def test_imageh_numpy_1x1(self): self.test_image_numpy_1x1(img_type=dtypes.imageh)

-  def test_image_copyout_2x4(self):
-    it = Tensor.arange(2*4*4).cast(dtypes.imagef((2,4,4))).realize()
+  def test_image_copyout_2x3(self):
+    it = Tensor.arange(2*3*4).cast(dtypes.imagef((2,3,4))).realize()
    buf = it.uop.buffer
    out = buf.as_buffer()
-    np.testing.assert_equal(out.cast('f').tolist(), np.arange(2*4*4))
+    np.testing.assert_equal(out.cast('f').tolist(), np.arange(2*3*4))

  def test_image_roundtrip(self):
    sz = (4,2,4)
@@ -105,9 +105,9 @@ class TestImageDType(unittest.TestCase):
    __validate(dtypes.imagef((1, 1)), 0x40)

  def test_image_and_back(self):
-    data = Tensor.randn(9*32*4).realize()
+    data = Tensor.randn(9*27*4).realize()
    tst = data.numpy()
-    it = data.cast(dtypes.imagef((9,32,4))).contiguous().realize()
+    it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize()
    assert isinstance(it.uop.base.realized.dtype, ImageDType)
    np.testing.assert_equal(tst, it.numpy())

@@ -127,13 +127,13 @@ class TestImageDType(unittest.TestCase):
    np.testing.assert_equal(tst, it.numpy())

  def test_shrink_load_float(self):
-    it = Tensor.randn(16).cast(dtypes.imagef((1,4,4))).realize()
+    it = Tensor.randn(4).cast(dtypes.imagef((1,1,4))).realize()
    imgv = it.numpy()
    np.testing.assert_equal(imgv[0:2], it[0:2].numpy())

  def test_mul_stays_image(self):
    # NOTE: contiguous is needed otherwise this folds
-    it = Tensor.randn(16).cast(dtypes.imagef((1,4,4))).contiguous().realize()
+    it = Tensor.randn(4).cast(dtypes.imagef((1,1,4))).contiguous().realize()
    out = (it*2).realize()
    assert isinstance(out.uop.base.realized.dtype, ImageDType)

@@ -143,7 +143,7 @@ class TestImageDType(unittest.TestCase):
    np.testing.assert_allclose(np.sum(itn), it.sum().numpy(), rtol=1e-6)

  def test_shrink_max(self):
-    it = Tensor.randn(16).cast(dtypes.imagef((1,4,4))).realize()
+    it = Tensor.randn(8).cast(dtypes.imagef((1,2,4))).realize()
    imgv = it.numpy()
    np.testing.assert_equal(np.maximum(imgv[0:3], 0), it[0:3].relu().numpy())

@@ -162,19 +162,19 @@ class TestImageDType(unittest.TestCase):
    assert it.uop.base.realized._buf == b1

  def test_no_lru_alloc(self):
-    data = Tensor.randn(9*32*4).realize()
-    it = data.cast(dtypes.imagef((9,32,4))).contiguous().realize()
+    data = Tensor.randn(9*27*4).realize()
+    it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize()
    b1 = it.uop.base.realized._buf
    del it
-    it = data.reshape(9,32,4).pad_to(10, None, None).cast(dtypes.imagef((10,32,4))).contiguous().realize()
+    it = data.cast(dtypes.imagef((10,27,4))).contiguous().realize()
    assert it.uop.base.realized._buf != b1

  def test_no_lru_alloc_dtype(self):
-    data = Tensor.randn(9*32*4).realize()
-    it = data.cast(dtypes.imagef((9,32,4))).contiguous().realize()
+    data = Tensor.randn(9*27*4).realize()
+    it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize()
    b1 = it.uop.base.realized._buf
    del it
-    it = data.cast(dtypes.imageh((9,32,4))).realize()
+    it = data.cast(dtypes.imageh((9,27,4))).realize()
    assert it.uop.base.realized._buf != b1

  # issue caused by: don't realize image to image casts. this is part of a larger problem
@@ -194,7 +194,7 @@ class TestImageDType(unittest.TestCase):
          lst = s.bufs[0].as_buffer().cast("f").tolist()
          print(lst)
          assert not np.any(np.isnan(lst))
-      # NOTE: the w1 grad must realize to a separate kernel
+      # NOTE: the w1 grad must realize to a seperate kernel
      assert w1.grad.uop.is_realized, f"never realized {w1.grad}"
      self.assertEqual(w1.grad.uop.base.buffer.dtype, dtypes.float32)
      self.assertEqual(len(sched), 9)
@@ -202,36 +202,36 @@ class TestImageDType(unittest.TestCase):
@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported")
 class TestImageRealization(unittest.TestCase):
  def test_image_dtype_expand(self):
-    data = Tensor.randn(9*32*4).realize()
-    it = data.cast(dtypes.imagef((9,32,4))).contiguous().realize()
-    self.assertEqual(it.dtype, dtypes.imagef((9,32,4)))
-    it_expanded = it.reshape((9,32,4,1)).expand((9,32,4,4)).contiguous().realize()
+    data = Tensor.randn(9*27*4).realize()
+    it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize()
+    self.assertEqual(it.dtype, dtypes.imagef((9,27,4)))
+    it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)).contiguous().realize()
    self.assertEqual(it_expanded.dtype, dtypes.float32)

  def test_image_dtype_expand_and_back(self):
-    data = Tensor.randn(9*32*4).realize()
-    it = data.cast(dtypes.imagef((9,32,4))).contiguous().realize()
-    self.assertEqual(it.dtype, dtypes.imagef((9,32,4)))
-    it_expanded = it.reshape((9,32,4,1)).expand((9,32,4,4))
+    data = Tensor.randn(9*27*4).realize()
+    it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize()
+    self.assertEqual(it.dtype, dtypes.imagef((9,27,4)))
+    it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4))
    it2 = it_expanded.sum(3).realize()
-    self.assertEqual(it2.dtype, dtypes.imagef((9,32,4)))
+    self.assertEqual(it2.dtype, dtypes.imagef((9,27,4)))

  def test_image_alu_children(self):
-    data = Tensor.randn(9*32*4).realize()
-    it = data.cast(dtypes.imagef((9,32,4))).contiguous().realize()
-    self.assertEqual(it.dtype, dtypes.imagef((9,32,4)))
-    it_expanded = it.reshape((9,32,4,1)).expand((9,32,4,4)).contiguous()
+    data = Tensor.randn(9*27*4).realize()
+    it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize()
+    self.assertEqual(it.dtype, dtypes.imagef((9,27,4)))
+    it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)).contiguous()
    alu1 = it_expanded+1
    alu2 = it_expanded.sum(3)
    it_expanded.realize()
    # NOTE: the parent becomes float, but the alu child will stay image until its output cannot fit the image
-    self.assertEqual(alu1.dtype, dtypes.imagef((9,32,4)))
+    self.assertEqual(alu1.dtype, dtypes.imagef((9,27,4)))
    alu1.realize()
    self.assertEqual(alu1.dtype, dtypes.float32)
    # alu2 is back in image because it fits the dtype again
-    self.assertEqual(alu2.dtype, dtypes.imagef((9,32,4)))
+    self.assertEqual(alu2.dtype, dtypes.imagef((9,27,4)))
    alu2.realize()
-    self.assertEqual(alu2.dtype, dtypes.imagef((9,32,4)))
+    self.assertEqual(alu2.dtype, dtypes.imagef((9,27,4)))

 if __name__ == '__main__':
  unittest.main()
@@ -5,7 +5,7 @@ import numpy as np
 from hypothesis import given, settings, strategies as strat
 from test.helpers import assert_jit_cache_len, not_support_multi_device, REAL_DEV, needs_second_gpu
 from tinygrad.tensor import Tensor
-from tinygrad.engine.jit import TinyJit, JitError, GraphRunner, MultiGraphRunner, graph_class
+from tinygrad.engine.jit import TinyJit, GraphRunner, MultiGraphRunner, graph_class
 from tinygrad.engine.realize import CompiledRunner, BufferCopy, BufferXfer
 from tinygrad.device import Device
 from tinygrad.helpers import Context, JIT, GlobalCounters, getenv
@@ -76,7 +76,7 @@ class TestJit(unittest.TestCase):
  def test_nothing_jitted(self):
    @TinyJit
    def add(a, b): return None
-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      for _ in range(5):
        a = Tensor.randn(10, 10)
        b = Tensor.randn(10, 10)
@@ -125,13 +125,13 @@ class TestJit(unittest.TestCase):
      b = Tensor.randn(10, 10)
      add(a, b)
    bad = Tensor.randn(20, 20)
-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      add(a, bad)

  def test_jit_shape_views_mismatch(self):
    @TinyJit
    def add(a): return (a+1).realize()
-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      for i in range(1,5):
        # a has an offset that the kernel doesn't know about
        a = Tensor.randn(10, 10).realize()[:, i:i+2]
@@ -142,7 +142,7 @@ class TestJit(unittest.TestCase):
    @TinyJit
    def add(a, b): return (a+b).realize()
    a = Tensor.randn(10, 10)
-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      add(a, a)

  def test_jit_assign(self, dtype=dtypes.float32):
@@ -184,9 +184,16 @@ class TestJit(unittest.TestCase):
  def test_array_jit(self):
    @TinyJit
    def add_array(a, arr): return (a+arr[0]).realize()
-    for _ in range(5):
-      a, b = Tensor.randn(10, 10).realize(), Tensor.randn(10, 10).realize()
-      np.testing.assert_allclose(add_array(a, [b]).numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5)
+    for i in range(5):
+      a = Tensor.randn(10, 10)
+      b = Tensor.randn(10, 10)
+      a.realize(), b.realize()
+      c = add_array(a, [b])
+      if i >= 2:
+        # should fail once jitted since jit can't handle arrays
+        np.testing.assert_allclose(np.any(np.not_equal(c.numpy(),a.numpy()+b.numpy())), True, atol=1e-4, rtol=1e-5)
+      else:
+        np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5)
    assert_jit_cache_len(add_array, 1)

  def test_jit_copyin(self):
@@ -223,9 +230,20 @@ class TestJit(unittest.TestCase):
  def test_jit_output_non_tensor_fail(self):
    @TinyJit
    def f(a, b, i): return (a+b).realize(), i
-    with self.assertRaises(JitError):
-      for i in range(3):
-        f(Tensor.randn(10, 10), Tensor.randn(10, 10), i)
+    output1, output2 = [], []
+    expect1, expect2 = [], []
+    for i in range(5):
+      a = Tensor.randn(10, 10)
+      b = Tensor.randn(10, 10)
+      o1, o2 = f(a, b, i)
+      output1.append(o1.numpy().copy())
+      output2.append(o2)
+      expect1.append(a.numpy().copy()+b.numpy().copy())
+      expect2.append(i)
+    np.testing.assert_allclose(output1, expect1, atol=1e-4, rtol=1e-5)
+    # the jit only works with Tensor outputs
+    assert output2 != expect2
+    assert_jit_cache_len(f, 1)

  def test_jit_random_regen(self):
    def f(a, b):
@@ -407,6 +425,12 @@ class TestJit(unittest.TestCase):
    assert isinstance(jf.jit_cache[0].prg, graph_t)
    assert isinstance(jf.jit_cache[1].prg, graph_t)

+  def test_jit_const_inputs(self):
+    @TinyJit
+    def g(x,y,z): return (x+y+z).realize()
+    for i in range(5):
+      np.testing.assert_equal(g(Tensor([i]*3), Tensor.ones(3), Tensor.zeros(3)).numpy(), np.array([i+1]*3))
+
  def test_jitted_clone(self):
    def f(a): return a.clone().realize()
    jf = TinyJit(f)
@@ -483,11 +507,10 @@ class TestJit(unittest.TestCase):

    f(Tensor.empty(1))
    f(Tensor.empty(1))
-    # scalar const input is not allowed
-    with self.assertRaises(JitError):
-      f(Tensor(2.0)).item()
-    # list input has different view structure than empty(1)
-    with self.assertRaises(JitError):
+    # TODO: this should fail since input has a different size
+    f(Tensor(2.0)).item()
+    # TODO: this should not fail, and should return 3
+    with self.assertRaises(AssertionError):
      f(Tensor([2.0])).item()

@unittest.skip("Pending multioutput implementation #3607")
@@ -6,14 +6,14 @@ Each test shows behavior that works without JIT but changes with JIT.
 Comments marked "should be X!" indicate the intuitively expected value.

 SILENT MISMATCHES (highest priority - wrong results, no error):
+  tensors_in_containers_ignored      EASY   only checks t.__class__ is Tensor, could scan lists/dicts
+  non_tensor_outputs_frozen          EASY   could warn/error if return contains non-Tensor values
  class_method_shared_across_instances EASY could check if first arg is self and warn
  output_buffer_reuse                MED    performance tradeoff, could add option or better docs
  python_constants_frozen            HARD   inherent to tracing JITs
  conditional_branches_frozen        HARD   inherent to tracing JITs

 ERRORS RAISED (lower priority - at least users know):
-  unrealized_const_input_error       EASY   raises JitError for unrealized const inputs
-  non_tensor_outputs_error           EASY   raises JitError if return contains non-Tensor values
  positional_kwargs_cannot_mix       EASY   normalize positional args to kwargs using function signature
  duplicate_inputs_fail              MED    would need to handle aliasing in input_replace
  nested_jit_fails_on_second_call    MED    could fail on first call instead of second
@@ -21,7 +21,6 @@ ERRORS RAISED (lower priority - at least users know):
 import unittest
 import numpy as np
 from tinygrad import Tensor, TinyJit
-from tinygrad.engine.jit import JitError

 class TestJitFootguns(unittest.TestCase):

@@ -49,11 +48,21 @@ class TestJitFootguns(unittest.TestCase):

    self.assertEqual([r1.item(), r2.item(), r3.item()], [2, 4, 6])

-  def test_non_tensor_outputs_error(self):
+  def test_non_tensor_outputs_frozen(self):
+    """Non-tensor return values are frozen at capture time."""
    @TinyJit
    def f(x, mult): return (x * 2).realize(), mult * 10
-    with self.assertRaises(JitError):
-      for i in range(3): f(Tensor([i]), i)
+
+    # collect results, copying tensor values immediately (buffer reuse!)
+    results = []
+    for i in range(5):
+      t, s = f(Tensor([i]), i)
+      results.append((t.item(), s))
+
+    # tensor outputs work correctly
+    self.assertEqual([r[0] for r in results[2:]], [4, 6, 8])
+    # scalar outputs frozen at capture (i=1) - should be 20, 30, 40!
+    self.assertEqual([r[1] for r in results[2:]], [10, 10, 10])

  def test_duplicate_inputs_fail(self):
    """JIT cannot handle the same tensor passed as multiple arguments."""
@@ -61,15 +70,23 @@ class TestJitFootguns(unittest.TestCase):
    def f(a, b): return (a + b).realize()

    x = Tensor([1, 2, 3])
-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      f(x, x)

-  def test_tensors_in_containers(self):
+  def test_tensors_in_containers_ignored(self):
+    """Tensors inside lists/dicts are not tracked as inputs."""
    @TinyJit
    def f(a, arr): return (a + arr[0]).realize()
+
+    results = []
    for i in range(4):
      a, b = Tensor([1, 1, 1]).realize(), Tensor([i, i, i]).realize()
-      np.testing.assert_array_equal(f(a, [b]).numpy(), [1+i, 1+i, 1+i])
+      results.append(f(a, [b]).numpy().copy())
+
+    np.testing.assert_array_equal(results[0], [1, 1, 1])  # warmup
+    np.testing.assert_array_equal(results[1], [2, 2, 2])  # capture
+    np.testing.assert_array_equal(results[2], [2, 2, 2])  # should be [3,3,3]!
+    np.testing.assert_array_equal(results[3], [2, 2, 2])  # should be [4,4,4]!

  def test_nested_jit_fails_on_second_call(self):
    """Nested JIT works on first call but fails on second."""
@@ -99,7 +116,7 @@ class TestJitFootguns(unittest.TestCase):
    def f(a): return (a + 1).realize()

    base = Tensor.randn(10, 10).realize()
-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      for i in range(1, 5):
        f(base[:, i:i+2])  # different offset each time

@@ -111,7 +128,7 @@ class TestJitFootguns(unittest.TestCase):
    f(Tensor.randn(10, 10), Tensor.randn(10, 10))  # warmup
    f(Tensor.randn(10, 10), Tensor.randn(10, 10))  # capture

-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      f(Tensor.randn(20, 20), Tensor.randn(20, 20))

  def test_python_constants_frozen(self):
@@ -131,21 +148,6 @@ class TestJitFootguns(unittest.TestCase):
    self.assertEqual(results[2], 20)   # should be 30!
    self.assertEqual(results[3], 20)   # should be 40!

-  def test_unrealized_const_input_error(self):
-    """Const tensors have no buffer to replace, so JIT raises an error. Even explicit .realize() doesn't help."""
-    @TinyJit
-    def f(a, b): return (a * b).realize()
-
-    # unrealized const fails
-    with self.assertRaises(JitError):
-      f(Tensor([1, 2, 3]).realize(), Tensor(2))
-
-    # explicit .realize() on const still fails - const cannot be realized to have a buffer
-    @TinyJit
-    def g(a, b): return (a * b).realize()
-    with self.assertRaises(JitError):
-      g(Tensor([1, 2, 3]).realize(), Tensor(2).realize())
-
  def test_conditional_branches_frozen(self):
    """Only the branch taken during capture runs thereafter."""
    @TinyJit
@@ -168,7 +170,7 @@ class TestJitFootguns(unittest.TestCase):
    f(Tensor([1]), Tensor([2]))  # warmup with positional
    f(Tensor([1]), Tensor([2]))  # capture with positional

-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      f(a=Tensor([3]), b=Tensor([4]))  # kwargs fail

  def test_class_method_shared_across_instances(self):
@@ -211,39 +213,10 @@ class TestJitFootguns(unittest.TestCase):
    @TinyJit
    def f(a, b): return None

-    with self.assertRaises(JitError):
+    with self.assertRaises(AssertionError):
      for _ in range(3):
        f(Tensor([1]), Tensor([2]))

-  def test_item_creates_unrealized_return(self):
-    """.item() in shape computation creates unrealized return with baked-in shape."""
-    @TinyJit
-    def f(x): return Tensor.zeros(x.sum().item())
-
-    for _ in range(3): f(Tensor([1, 1, 1]))  # captures with sum=3
-    result = f(Tensor([2, 2, 2]))  # sum=6, but shape is baked in
-    assert result.shape == (3,)  # should be (6,)!
-
-  def test_item_bakes_in_values(self):
-    """.item() value is baked in, causing wrong output shapes (silent failure)."""
-    @TinyJit
-    def f(x, mask): return x.masked_select(mask)
-
-    mask_2 = Tensor([True, False, True, False])
-    for _ in range(3): f(Tensor([1, 2, 3, 4]), mask_2)
-    mask_3 = Tensor([True, True, True, False])
-    result = f(Tensor([1, 2, 3, 4]), mask_3)
-    assert result.shape == (2,)  # should be (3,)!
-
-  def test_tolist_bakes_in_values(self):
-    """.tolist() returns Python values that get baked in (silent failure)."""
-    @TinyJit
-    def f(x): return Tensor(x.tolist())
-
-    for _ in range(3): f(Tensor([1, 2, 3]))
-    result = f(Tensor([4, 5, 6]))
-    np.testing.assert_equal(result.numpy(), [1, 2, 3])  # should be [4,5,6]!
-

 class TestJitCorrectBehavior(unittest.TestCase):
  """Behaviors that work correctly - documented for clarity."""
@@ -399,7 +399,8 @@ class TestLinearizer(unittest.TestCase):
      assert len(set([u.op for u in uops if u.op in {Ops.RANGE, Ops.SPECIAL}])) == 1, "has either specials or ranges, not both"
      reg_stores = [u for u in uops if u.op is Ops.STORE and isinstance(dt:=u.src[0].dtype, PtrDType) and dt.addrspace == AddrSpace.REG]
      assert len(reg_stores) == 0, "STORE to reg should have been simplified"
-      assert len([u for u in uops if u.op is Ops.MAX]) <= max_ops, "no unnecessary MAX ops"
+      # TODO: once uops track min/max this will be fixed
+      #assert len([u for u in uops if u.op is Ops.MAX]) <= max_ops, "no unnecessary MAX ops"

    helper(Tensor.arange(5.5, (3.5*300), 3.5), max_ops=2)
    helper(Tensor.arange(-1, -100, -5), max_ops=2)
@@ -541,37 +541,6 @@ class TestMultiTensor(unittest.TestCase):
      np.testing.assert_allclose(r.numpy(), np.ones(256)+np.ones(256), atol=1e-4, rtol=1e-5)
    assert len(jf.jit_cache) > 0

-  def test_multitensor_jit_in_list(self):
-    # test MULTI tensor inside a list container - exercises the container unpacking + MULTI unpacking
-    @TinyJit
-    def f(a, arr): return (a + arr[0]).realize()
-    for i in range(5):
-      a = Tensor.full((4,), i).contiguous().realize().shard(devices_2, 0).realize()
-      b = Tensor.ones(4).contiguous().realize().shard(devices_2, 0).realize()
-      out = f(a, [b])
-      np.testing.assert_allclose(out.numpy(), np.full(4, i) + np.ones(4), atol=1e-4, rtol=1e-5)
-
-  def test_multitensor_jit_multiple_inputs(self):
-    # test multiple MULTI tensors as inputs - each gets unpacked to component UOps
-    @TinyJit
-    def f(a, b, c): return (a + b + c).realize()
-    for i in range(5):
-      a = Tensor.full((4,), i).contiguous().realize().shard(devices_2, 0).realize()
-      b = Tensor.full((4,), i*2).contiguous().realize().shard(devices_2, 0).realize()
-      c = Tensor.ones(4).contiguous().realize().shard(devices_2, 0).realize()
-      out = f(a, b, c)
-      np.testing.assert_allclose(out.numpy(), np.full(4, i) + np.full(4, i*2) + np.ones(4), atol=1e-4, rtol=1e-5)
-
-  def test_multitensor_jit_different_sharding(self):
-    # test MULTI tensors with different sharding - one sharded on axis 0, one broadcast (axis=None)
-    @TinyJit
-    def f(a, b): return (a + b).realize()
-    for i in range(5):
-      a = Tensor.full((4, 4), i).contiguous().realize().shard(devices_2, 0).realize()
-      b = Tensor.full((4, 4), i*2).contiguous().realize().shard(devices_2, None).realize()
-      out = f(a, b)
-      np.testing.assert_allclose(out.numpy(), np.full((4, 4), i) + np.full((4, 4), i*2), atol=1e-4, rtol=1e-5)
-
  @unittest.skip("test broken")
  def test_multi_device_jit_graph(self):
    if Device[d0].graph is None or Device[d1].graph is None: raise unittest.SkipTest("only test graphs")
@@ -1015,6 +984,7 @@ class TestShrinkMultiTensorShardedAxis(unittest.TestCase):
    np.testing.assert_equal((a+a).numpy(), na+na)
    np.testing.assert_equal((b+b).numpy(), nb+nb)

+  # @unittest.skip("why didn't this work?")
  def test_add_two_partitions(self):
    t = Tensor.arange(64).reshape(8, 8).contiguous().realize()
    t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0)
@@ -2,7 +2,7 @@ import time, math, unittest, functools, platform, warnings
 import numpy as np
 from typing import List, Callable
 import torch
-from tinygrad.helpers import getenv, IMAGE, DEBUG, CI, Context, CPU_LLVM, AMD_LLVM, EMULATE
+from tinygrad.helpers import getenv, IMAGE, DEBUG, CI, Context, CPU_LLVM, CPU_LVP, AMD_LLVM, EMULATE
 from tinygrad import Tensor, Device, dtypes
 from tinygrad.tensor import _to_np_dtype
 from tinygrad.device import is_dtype_supported
@@ -235,7 +235,8 @@ class TestOps(unittest.TestCase):
  def test_unfold(self):
    helper_test_op([(8,)], lambda x: x.unfold(0, 2, 1))
    helper_test_op([(8,)], lambda x: x.unfold(0, 2, 2))
-    helper_test_op([(8,)], lambda x: x.unfold(0, 7, 3))
+    # TODO: something is wrong with unfold
+    if not getenv("TINY_BACKEND"): helper_test_op([(8,)], lambda x: x.unfold(0, 7, 3))
    helper_test_op([(3,3,3)], lambda x: x.unfold(2, 2, 8))
    helper_test_op([(3,3,3)], lambda x: x.unfold(1, 0, 8))
    helper_test_op([(3,3,3,3,3)], lambda x: x.unfold(-1, 2, 2))
@@ -639,8 +640,6 @@ class TestOps(unittest.TestCase):
    helper_test_op([(45,65), (45,65)], lambda x,y: x**y)
    helper_test_op([(45,65), (45,65)], lambda x,y: x.pow(y))

-  # TODO: WEBGPU NaN handling in pow operations
-  @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU NaN handling differs")
  def test_pow(self):
    helper_test_op([(45,65)], lambda x: x**0)
    helper_test_op([(45,65)], lambda x: x**1)
@@ -702,14 +701,10 @@ class TestOps(unittest.TestCase):

  def test_pow_zero_tensor(self):
    helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [0.0]])
-    # TODO: fix WEBGPU
-    if Device.DEFAULT != "WEBGPU":
+    # TODO: fix WEBGPU and LVP
+    if Device.DEFAULT != "WEBGPU" and not CPU_LVP:
      helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [0.3]])
      helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [-0.3]])
-  @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU issue")
-  def test_exp2_log2_zero_times_negative(self):
-    # gallivm's exp2/log2 have "undefined behavior with infs, 0s and nans", so exp2(log2(0)*y) returns 0 instead of inf
-    helper_test_op(None, lambda x,y: (x.log2()*y).exp2(), lambda x,y: (x.log2()*y).exp2(), vals=[[0.0], [-0.7]], forward_only=True)
  def test_pow_zero_const(self):
    helper_test_op(None, lambda x: x**0.3, vals=[[0.0]])
    helper_test_op(None, lambda x: x**0.0, vals=[[0.0]])
@@ -1092,7 +1087,7 @@ class TestOps(unittest.TestCase):
    helper_test_op([(2,3,0)], lambda x: torch.cummax(x, dim=2).values, lambda x: Tensor.cummax(x, axis=2))

  def test_argmax(self):
-    # check if it returns the first index for multiple occurrences
+    # check if it returns the first index for multiple occurences
    helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[2, 2]])
    helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[1, 2, 2]])
    if not COMPILE_ONLY:
@@ -1112,7 +1107,7 @@ class TestOps(unittest.TestCase):
    helper_test_op(None, lambda x: x.type(torch.int32).argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[True, False]])

  def test_argmin(self):
-    # check if it returns the first index for multiple occurrences
+    # check if it returns the first index for multiple occurences
    helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[2, 2]])
    helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[3, 2, 2]])
    if not COMPILE_ONLY:
@@ -1176,8 +1171,6 @@ class TestOps(unittest.TestCase):

  @slow_test
  def test_einsum(self):
-    # scalar
-    helper_test_op([()], lambda a: torch.einsum('->', a), lambda a: Tensor.einsum('->', a))
    # matrix transpose
    helper_test_op([(10,10)], lambda a: torch.einsum('ij->ji', a), lambda a: Tensor.einsum('ij->ji', a))
    helper_test_op([(10,10)], lambda a: torch.einsum('ij -> ji', a), lambda a: Tensor.einsum('ij -> ji', a))
@@ -1246,18 +1239,6 @@ class TestOps(unittest.TestCase):
    self.helper_test_exception([(2, 3, 4), (2, 3, 4)], lambda a, b: torch.einsum('i...j,ji...->...', [a, b]),
                lambda a, b: Tensor.einsum('i...j,ji...->...', [a, b]), expected=RuntimeError)

-  def test_einsum_trace(self):
-    # inner product
-    helper_test_op([(5,), (5,)], lambda a, b: torch.einsum('i,i', a, b), lambda a, b: Tensor.einsum('i,i', a, b))
-    # simple diagonal
-    helper_test_op([(4, 4)], lambda a: torch.einsum('ii->i', a), lambda a: Tensor.einsum('ii->i', a))
-    # trace (sum of diagonal)
-    helper_test_op([(4, 4)], lambda a: torch.einsum('ii->', a), lambda a: Tensor.einsum('ii->', a))
-    # batch diagonal
-    helper_test_op([(3, 5, 5)], lambda a: torch.einsum('...ii->...i', a), lambda a: Tensor.einsum('...ii->...i', a))
-    # batch trace
-    helper_test_op([(3, 5, 5)], lambda a: torch.einsum('...ii->...', a), lambda a: Tensor.einsum('...ii->...', a))
-
  def test_einsum_shape_check(self):
    self.helper_test_exception([(3,8,10,5), (11,5,13,16,8)], lambda a, b: torch.einsum('pqrs,tuqvr->pstuv', [a, b]),
                lambda a, b: Tensor.einsum('pqrs,tuqvr->pstuv', [a, b]), expected=RuntimeError)
@@ -1467,9 +1448,6 @@ class TestOps(unittest.TestCase):
    helper_test_op([(3,4,5,6)], lambda x: x.all(axis=(1,2)), forward_only=True)
  def test_all_zero_axis(self):
    helper_test_op([(1,0,3,0,5)], lambda x: x.all(axis=(1,3)), forward_only=True)
-  def test_all_large(self):
-    for exp in [15, 16, 20]:
-      helper_test_op(None, lambda: torch.ones(2**exp).bool().all(), lambda: Tensor.ones(2**exp).bool().all(), vals=[], forward_only=True)

  def test_isclose(self):
    helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x), forward_only=True)
@@ -118,7 +118,7 @@ class TestSchedule(unittest.TestCase):
    a = Tensor.randn(4, 2, 1).realize().permute((1, 0, 2))
    b = a.cast(dtypes.half).expand((2, 4, 4))+2
    run_schedule(check_schedule(b, 1))
-    np.testing.assert_allclose(b.numpy(), np.broadcast_to(a.numpy().astype(np.float16), (2, 4, 4))+2, rtol=1e-3)
+    np.testing.assert_allclose(b.numpy(), np.broadcast_to(a.numpy().astype(np.float16), (2, 4, 4))+2)

  def test_indexing_scalars_simple(self):
    X = Tensor.randn(2, 2).realize()
@@ -1,7 +1,7 @@
 import unittest
 import random
 from os import getenv
-from tinygrad import Tensor, TinyJit, Variable, dtypes, Device
+from tinygrad import Tensor, TinyJit, Variable, dtypes
 from tinygrad.helpers import Context
 import numpy as np

@@ -81,6 +81,8 @@ class TestSetitem(unittest.TestCase):
    t[1] ^= 5
    np.testing.assert_allclose(t.numpy(), [[0, 1], [7, 6]])

+  #@unittest.expectedFailure
+  # update: passing after delete_forced_realize
  def test_setitem_consecutive_inplace_operator(self):
    t = Tensor.arange(4).reshape(2, 2).contiguous()
    t[1] += 2
@@ -157,8 +159,6 @@ class TestSetitem(unittest.TestCase):
    t[:-1] = t[1:]
    self.assertEqual(t.tolist(), [[2.0], [1.0], [1.0]])

-  # TODO: WEBGPU pipeline validation error
-  @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU pipeline validation error")
  def test_setitem_big(self):
    idx_size, val = 256, 4
    t = Tensor.arange(0, idx_size+1)
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
geohot	aec4d65241	ds compiled	2025-12-31 15:43:44 -05:00
geohot	f022a7d8a7	assembly/amd: move more instructions to pcode	2025-12-31 15:42:59 -05:00
				`@@ -1 +0,0 @@`
				`"""Hardware-validated emulator tests for RDNA3 instructions."""`