fix

test/backend/test_encodings.py

@@ -1,10 +1,12 @@
 import unittest
+from tinygrad import Device
 from tinygrad.uop.ops import UOp, Ops
 from tinygrad.dtype import dtypes
 from tinygrad.renderer.isa.x86 import X86Ops, X86Renderer, RBP, RDI, RSP, RSI, RAX, RDX, XMM, GPR, imm, def_reg
 
 def ins(op, dt, src, tag=None): return UOp(Ops.INS, arg=op, dtype=dt, src=src, tag=tag)
 
+@unittest.skipUnless(isinstance(Device[Device.DEFAULT].renderer, X86Renderer), "only on x86")
 class TestEncodingsX86(unittest.TestCase):
   # NOTE: x86 supports a single displacement as memory address and index without base memory address
   # these have no use cases so they aren't supported

test/backend/test_isel.py

@@ -1,10 +1,12 @@
 import unittest
+from tinygrad import Device
 from tinygrad.uop import Ops
 from tinygrad.uop.ops import UOp, dtypes, graph_rewrite
 from tinygrad.renderer.isa.x86 import X86Renderer, X86Ops
 from tinygrad.renderer.isa import IselContext
 
 # these tests are to catch changes that don't cause incorrect codegen but cause worse codegen
+@unittest.skipUnless(isinstance(Device[Device.DEFAULT].renderer, X86Renderer), "only x86")
 class TestIselX86(unittest.TestCase):
   def isel_rewrite(self, x:UOp): return graph_rewrite(x, X86Renderer().isel_matcher, IselContext(x), bottom_up=True)
 
@@ -12,8 +14,8 @@ class TestIselX86(unittest.TestCase):
     nargs = expr.__code__.co_argcount
     for dt,op in dt_op:
       with self.subTest(dtype=dt):
-        vars = [UOp.variable(str(i), 0, 0, dt) for i in range(nargs)]
-        n = self.isel_rewrite(expr(*vars))
+        v = [UOp.variable(str(i), 0, 0, dt) for i in range(nargs)]
+        n = self.isel_rewrite(expr(*v))
         self.assertIs(n.arg, op)
 
   def test_cmove(self):

tinygrad/codegen/late/regalloc.py

@@ -55,7 +55,7 @@ class LinearScanRegallocContext:
       if u.op in PSEUDO_OPS: continue
       # allocate uses
       for j,s in enumerate(u.src):
-        # HACK
+        # HACK: cause of later hacks to lower range
         if u.op is Ops.END: continue
         # allocate srcs, if src was spilled it's replaced by a load, if it's live the load was already emitted otherwise alloc and emit one
         if isinstance(v:=s.reg, Register) and v in self.spills:
@@ -74,7 +74,8 @@ class LinearScanRegallocContext:
             ins = tuple(live.get(s.reg) for s in u.src)
             cons = ((ins[0],) if ins[0] in cons else ()) + tuple(r for r in cons if r not in ins)
             assert cons
-          self.real_defs[v] = live[v] = alloc(cons, i+1)
+          # HACK: cause the range is missing the comparison
+          self.real_defs[v] = live[v] = alloc(cons, i+1 if u.op is not Ops.RANGE else i)
 
       # loop prologue, avoid loading inside the loop
       if u.op is Ops.RANGE: