forked from tinygrad/tinygrad
more llvm asm tests
This commit is contained in:
File diff suppressed because it is too large
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+169
-388
@@ -1,36 +1,20 @@
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# library for RDNA3 assembly DSL
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from __future__ import annotations
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import re
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from enum import IntEnum
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from typing import overload, Annotated, TypeVar, Generic
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# Bit field DSL
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class BitField:
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def __init__(self, hi: int, lo: int, name: str | None = None): self.hi, self.lo, self.name = hi, lo, name
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def __set_name__(self, owner, name): self.name, self._owner = name, owner
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def __set_name__(self, owner, name): self.name = name
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def __eq__(self, val: int) -> tuple[BitField, int]: return (self, val) # type: ignore
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def mask(self) -> int: return (1 << (self.hi - self.lo + 1)) - 1
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@property
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def marker(self) -> type | None:
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# Get marker from Annotated type hint if present
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import typing
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if hasattr(self, '_owner') and self.name:
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hints = typing.get_type_hints(self._owner, include_extras=True)
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if self.name in hints:
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hint = hints[self.name]
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if typing.get_origin(hint) is Annotated:
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args = typing.get_args(hint)
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return args[1] if len(args) > 1 else None
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return None
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@overload
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def __get__(self, obj: None, objtype: type) -> BitField: ...
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@overload
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def __get__(self, obj: object, objtype: type | None = None) -> int: ...
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def __get__(self, obj, objtype=None):
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if obj is None: return self
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val = unwrap(obj._values.get(self.name, 0))
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# Convert to IntEnum if marker is an IntEnum subclass
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if self.marker and isinstance(self.marker, type) and issubclass(self.marker, IntEnum):
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try: return self.marker(val)
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ann = getattr(type(obj), '__annotations__', {}).get(self.name)
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if ann and isinstance(ann, type) and issubclass(ann, IntEnum):
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try: return ann(val)
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except ValueError: pass
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return val
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@@ -40,77 +24,54 @@ bits = _Bits()
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# Register types
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class Reg:
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def __init__(self, idx: int, count: int = 1, hi: bool = False, neg: bool = False): self.idx, self.count, self.hi, self.neg = idx, count, hi, neg
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def __init__(self, idx: int, count: int = 1, hi: bool = False): self.idx, self.count, self.hi = idx, count, hi
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def __repr__(self): return f"{self.__class__.__name__.lower()[0]}[{self.idx}]" if self.count == 1 else f"{self.__class__.__name__.lower()[0]}[{self.idx}:{self.idx + self.count}]"
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def __neg__(self): return self.__class__(self.idx, self.count, self.hi, neg=not self.neg)
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T = TypeVar('T', bound=Reg)
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class _RegFactory(Generic[T]):
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def __init__(self, cls: type[T], name: str): self._cls, self._name = cls, name
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@overload
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def __getitem__(self, key: int) -> Reg: ...
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@overload
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def __getitem__(self, key: slice) -> Reg: ...
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def __getitem__(self, key: int | slice) -> Reg:
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return self._cls(key.start, key.stop - key.start + 1) if isinstance(key, slice) else self._cls(key)
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def __repr__(self): return f"<{self._name} factory>"
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@classmethod
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def __class_getitem__(cls, key): return cls(key.start, key.stop - key.start) if isinstance(key, slice) else cls(key)
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class SGPR(Reg): pass
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class VGPR(Reg): pass
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class TTMP(Reg): pass
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s: _RegFactory[SGPR] = _RegFactory(SGPR, "SGPR")
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v: _RegFactory[VGPR] = _RegFactory(VGPR, "VGPR")
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ttmp: _RegFactory[TTMP] = _RegFactory(TTMP, "TTMP")
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s, v = SGPR, VGPR
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# Field type markers (runtime classes for validation)
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class _SSrc: pass
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class _Src: pass
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class _Imm: pass
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class _SImm: pass
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class _VDSTYEnc: pass # VOPD vdsty: encoded = actual >> 1, actual = (encoded << 1) | ((vdstx & 1) ^ 1)
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class _SGPRField: pass
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class _VGPRField: pass
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# Type aliases for annotations - tells mypy it's a BitField while preserving marker info
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SSrc = Annotated[BitField, _SSrc]
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Src = Annotated[BitField, _Src]
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Imm = Annotated[BitField, _Imm]
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SImm = Annotated[BitField, _SImm]
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VDSTYEnc = Annotated[BitField, _VDSTYEnc]
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SGPRField = Annotated[BitField, _SGPRField]
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VGPRField = Annotated[BitField, _VGPRField]
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# Field type markers
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class SSrc: pass
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class Src: pass
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class Imm: pass
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class SImm: pass
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class RawImm:
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def __init__(self, val: int): self.val = val
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def __repr__(self): return f"RawImm({self.val})"
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def __eq__(self, other): return isinstance(other, RawImm) and self.val == other.val
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def unwrap(val) -> int:
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return val.val if isinstance(val, RawImm) else val.value if hasattr(val, 'value') else val.idx if hasattr(val, 'idx') else val
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# Encoding helpers
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FLOAT_ENC = {0.5: 240, -0.5: 241, 1.0: 242, -1.0: 243, 2.0: 244, -2.0: 245, 4.0: 246, -4.0: 247}
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SRC_FIELDS = {'src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'soffset', 'srcx0', 'srcy0'}
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SRC_FIELDS = {'src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'soffset'}
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RAW_FIELDS = {'vdata', 'vdst', 'vaddr', 'addr', 'data', 'data0', 'data1', 'sdst', 'sdata'}
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def _encode_reg(val) -> int:
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if isinstance(val, TTMP): return 108 + val.idx
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return val.idx | (0x80 if val.hi else 0)
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def encode_src(val) -> int:
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if isinstance(val, VGPR): return 256 + _encode_reg(val)
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if isinstance(val, Reg): return _encode_reg(val)
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if isinstance(val, SGPR): return val.idx | (0x80 if val.hi else 0)
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if isinstance(val, VGPR): return 256 + val.idx + (0x80 if val.hi else 0) # .h sets bit 7 of VGPR encoding
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if isinstance(val, TTMP): return 108 + val.idx
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if hasattr(val, 'value'): return val.value
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if isinstance(val, float): return 128 if val == 0.0 else FLOAT_ENC.get(val, 255)
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if isinstance(val, float): return FLOAT_ENC.get(val, 255)
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return 128 + val if isinstance(val, int) and 0 <= val <= 64 else 192 + (-val) if isinstance(val, int) and -16 <= val <= -1 else 255
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SPECIAL_DEC = {106: "vcc_lo", 107: "vcc_hi", 124: "null", 125: "m0", 126: "exec_lo", 127: "exec_hi", **{v: str(k) for k, v in FLOAT_ENC.items()}}
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def decode_src(val: int) -> str:
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if val <= 105: return f"s{val}"
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if val in SPECIAL_DEC: return SPECIAL_DEC[val]
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if 108 <= val <= 123: return f"ttmp{val - 108}"
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if 128 <= val <= 192: return str(val - 128)
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if 193 <= val <= 208: return str(-(val - 192))
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if 256 <= val <= 511: return f"v{val - 256}"
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return "lit" if val == 255 else f"?{val}"
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# Instruction base class
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class Inst:
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_fields: dict[str, BitField]
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_encoding: tuple[BitField, int] | None = None
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_defaults: dict[str, int] = {}
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_values: dict[str, int | RawImm]
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_words: int # size in 32-bit words, set by decode_program
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_literal: int | None
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_defaults: dict[str, int] = {} # field defaults
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def __init_subclass__(cls, **kwargs):
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super().__init_subclass__(**kwargs)
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@@ -118,82 +79,18 @@ class Inst:
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if 'encoding' in cls._fields and isinstance(cls.__dict__.get('encoding'), tuple): cls._encoding = cls.__dict__['encoding']
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def __init__(self, *args, literal: int | None = None, **kwargs):
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self._values, self._literal = dict(self._defaults), literal
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# Map positional args to field names
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field_names = [n for n in self._fields if n != 'encoding']
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orig_args = dict(zip(field_names, args))
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orig_args.update(kwargs)
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self._values.update(orig_args)
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# Validate register counts for SMEM instructions (before encoding)
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if self.__class__.__name__ == 'SMEM':
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op_val = orig_args.get(field_names[0]) if args else orig_args.get('op')
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if op_val is not None:
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if hasattr(op_val, 'value'): op_val = op_val.value
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expected_cnt = {0:1, 1:2, 2:4, 3:8, 4:16, 8:1, 9:2, 10:4, 11:8, 12:16}.get(op_val)
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sdata_val = orig_args.get('sdata')
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if expected_cnt is not None and isinstance(sdata_val, Reg) and sdata_val.count != expected_cnt:
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raise ValueError(f"SMEM op {op_val} expects {expected_cnt} registers, got {sdata_val.count}")
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# Validate register counts for SOP1 instructions (b32 = 1 reg, b64 = 2 regs)
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if self.__class__.__name__ == 'SOP1':
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op_val = orig_args.get(field_names[0]) if args else orig_args.get('op')
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if op_val is not None and hasattr(op_val, 'name'):
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expected = 2 if op_val.name.endswith('_B64') else 1
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sdst_val, ssrc0_val = orig_args.get('sdst'), orig_args.get('ssrc0')
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if isinstance(sdst_val, Reg) and sdst_val.count != expected:
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raise ValueError(f"SOP1 {op_val.name} expects {expected} destination register(s), got {sdst_val.count}")
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if isinstance(ssrc0_val, Reg) and ssrc0_val.count != expected:
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raise ValueError(f"SOP1 {op_val.name} expects {expected} source register(s), got {ssrc0_val.count}")
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# Type check and encode values
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for name, val in list(self._values.items()):
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if name == 'encoding': continue
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# For RawImm, only process RAW_FIELDS to unwrap to int
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if isinstance(val, RawImm):
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if name in RAW_FIELDS: self._values[name] = val.val
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continue
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field = self._fields.get(name)
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marker = field.marker if field else None
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# Type validation
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if marker is _SGPRField:
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if isinstance(val, VGPR): raise TypeError(f"field '{name}' requires SGPR, got VGPR")
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if not isinstance(val, (SGPR, TTMP, int, RawImm)): raise TypeError(f"field '{name}' requires SGPR, got {type(val).__name__}")
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if marker is _VGPRField:
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if not isinstance(val, VGPR): raise TypeError(f"field '{name}' requires VGPR, got {type(val).__name__}")
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if marker is _SSrc and isinstance(val, VGPR): raise TypeError(f"field '{name}' requires scalar source, got VGPR")
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# Encode source fields as RawImm for consistent disassembly
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if name in SRC_FIELDS:
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encoded = encode_src(val)
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self._values[name] = RawImm(encoded)
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# Handle negation modifier for VOP3 instructions
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if isinstance(val, Reg) and val.neg and 'neg' in self._fields:
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neg_bit = {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0)
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cur_neg = self._values.get('neg', 0)
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self._values['neg'] = (cur_neg.val if isinstance(cur_neg, RawImm) else cur_neg) | neg_bit
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# Track literal value if needed (encoded as 255)
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# For 64-bit ops, store literal in high 32 bits (to match from_bytes decoding and to_bytes encoding)
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if encoded == 255 and self._literal is None and isinstance(val, int) and not isinstance(val, IntEnum):
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self._literal = (val << 32) if self._is_64bit_op() else val
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elif encoded == 255 and self._literal is None and isinstance(val, float):
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import struct
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lit32 = struct.unpack('<I', struct.pack('<f', val))[0]
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self._literal = (lit32 << 32) if self._is_64bit_op() else lit32
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# Encode raw register fields for consistent repr
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elif name in RAW_FIELDS:
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if isinstance(val, Reg): self._values[name] = _encode_reg(val)
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elif hasattr(val, 'value'): self._values[name] = val.value # IntEnum like SrcEnum.NULL
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# Encode sbase (divided by 2) and srsrc/ssamp (divided by 4)
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elif name == 'sbase' and isinstance(val, Reg):
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self._values[name] = val.idx // 2
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elif name in {'srsrc', 'ssamp'} and isinstance(val, Reg):
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self._values[name] = val.idx // 4
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# VOPD vdsty: encode as actual >> 1 (constraint: vdsty parity must be opposite of vdstx)
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elif marker is _VDSTYEnc and isinstance(val, VGPR):
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self._values[name] = val.idx >> 1
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self._values, self._literal = dict(self._defaults), literal # start with defaults
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self._values.update(zip([n for n in self._fields if n != 'encoding'], args))
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self._values.update(kwargs)
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def _encode_field(self, name: str, val) -> int:
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if isinstance(val, RawImm): return val.val
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if name in {'srsrc', 'ssamp'}: return val.idx // 4 if isinstance(val, Reg) else val
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if name == 'sbase': return val.idx // 2 if isinstance(val, Reg) else val
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if name in RAW_FIELDS: return _encode_reg(val) if isinstance(val, Reg) else val
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if name in RAW_FIELDS:
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if isinstance(val, TTMP): return 108 + val.idx
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if isinstance(val, Reg): return val.idx | (0x80 if val.hi else 0) # .h sets bit 7 for vdst
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return val
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if isinstance(val, Reg) or name in SRC_FIELDS: return encode_src(val)
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return val.value if hasattr(val, 'value') else val
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@@ -208,35 +105,13 @@ class Inst:
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if n in self._values and not isinstance(v := self._values[n], RawImm) and isinstance(v, int) and not isinstance(v, IntEnum) and not (0 <= v <= 64 or -16 <= v <= -1): return v
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return None
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def _is_64bit_op(self) -> bool:
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"""Check if this instruction uses 64-bit operands (and thus 64-bit literals).
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Exception: V_LDEXP_F64 has 32-bit integer src1, so its literal is 32-bit."""
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op = self._values.get('op')
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if op is None: return False
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# op may be an enum (from __init__) or an int (from from_int)
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op_name = op.name if hasattr(op, 'name') else None
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if op_name is None and self.__class__.__name__ == 'VOP3':
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from extra.assembly.rdna3.autogen import VOP3Op
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try: op_name = VOP3Op(op).name
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except ValueError: pass
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if op_name is None: return False
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# V_LDEXP_F64 has 32-bit integer exponent in src1, so literal is 32-bit
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if op_name == 'V_LDEXP_F64': return False
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return op_name.endswith(('_F64', '_B64', '_I64', '_U64'))
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def to_bytes(self) -> bytes:
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result = self.to_int().to_bytes(self._size(), 'little')
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lit = self._get_literal() or getattr(self, '_literal', None)
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if lit is None: return result
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# For 64-bit ops, literal is stored in high 32 bits internally, but encoded as 4 bytes
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lit32 = (lit >> 32) if self._is_64bit_op() else lit
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return result + (lit32 & 0xffffffff).to_bytes(4, 'little')
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return result + (lit & 0xffffffff).to_bytes(4, 'little') if (lit := self._get_literal() or getattr(self, '_literal', None)) else result
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@classmethod
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def _size(cls) -> int: return 4 if issubclass(cls, Inst32) else 8
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def size(self) -> int:
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# Literal is always 4 bytes in the binary (for 64-bit ops, it's in high 32 bits)
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return self._size() + (4 if self._literal is not None else 0)
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def size(self) -> int: return self._size() + (4 if self._literal is not None else 0)
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@classmethod
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def from_int(cls, word: int):
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@@ -250,240 +125,146 @@ class Inst:
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inst = cls.from_int(int.from_bytes(data[:cls._size()], 'little'))
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op_val = inst._values.get('op', 0)
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has_literal = cls.__name__ == 'VOP2' and op_val in (44, 45, 55, 56)
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has_literal = has_literal or (cls.__name__ == 'SOP2' and op_val in (69, 70))
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has_literal = has_literal or (cls.__name__ == 'SOP2' and op_val in (69, 70)) # S_FMAAK_F32, S_FMAMK_F32
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for n in SRC_FIELDS:
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if n in inst._values and isinstance(inst._values[n], RawImm) and inst._values[n].val == 255: has_literal = True
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if has_literal:
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# For 64-bit ops, the literal is 32 bits placed in the HIGH 32 bits of the 64-bit value
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# (low 32 bits are zero). This is how AMD hardware interprets 32-bit literals for 64-bit ops.
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if len(data) >= cls._size() + 4:
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lit32 = int.from_bytes(data[cls._size():cls._size()+4], 'little')
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inst._literal = (lit32 << 32) if inst._is_64bit_op() else lit32
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if has_literal and len(data) >= cls._size() + 4: inst._literal = int.from_bytes(data[cls._size():cls._size()+4], 'little')
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return inst
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def __repr__(self):
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# Use _fields order and exclude fields that are 0/default (for consistent repr after roundtrip)
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def is_zero(v): return (isinstance(v, int) and v == 0) or (isinstance(v, VGPR) and v.idx == 0 and v.count == 1)
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items = [(k, self._values[k]) for k in self._fields if k in self._values and k != 'encoding'
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and not (is_zero(self._values[k]) and k not in {'op'})]
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lit = f", literal={hex(self._literal)}" if self._literal is not None else ""
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return f"{self.__class__.__name__}({', '.join(f'{k}={v}' for k, v in items)}{lit})"
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def __eq__(self, other):
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if not isinstance(other, Inst): return NotImplemented
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return self.__class__ == other.__class__ and self._values == other._values and self._literal == other._literal
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def __hash__(self): return hash((self.__class__.__name__, tuple(sorted((k, repr(v)) for k, v in self._values.items())), self._literal))
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def __repr__(self): return f"{self.__class__.__name__}({', '.join(f'{k}={v}' for k, v in self._values.items())})"
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def disasm(self) -> str:
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from extra.assembly.rdna3.asm import disasm
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return disasm(self)
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op_val = unwrap(self._values.get('op', 0))
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try:
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from extra.assembly.rdna3 import autogen
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op_name = getattr(autogen, f"{self.__class__.__name__}Op")(op_val).name.lower() if hasattr(autogen, f"{self.__class__.__name__}Op") else f"op_{op_val}"
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except (ValueError, KeyError): op_name = f"op_{op_val}"
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def fmt(n, v):
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v = unwrap(v)
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if n in SRC_FIELDS: return f"0x{self._literal:x}" if v == 255 and getattr(self, '_literal', None) else decode_src(v) if v != 255 else "0xff"
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if n in ('sdst', 'vdst'): return f"{'s' if n == 'sdst' else 'v'}{v}"
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return f"v{v}" if n == 'vsrc1' else f"0x{v:x}" if n == 'simm16' else str(v)
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ops = [fmt(n, self._values.get(n, 0)) for n in self._fields if n not in ('encoding', 'op')]
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if self.__class__.__name__ == 'VOP2' and getattr(self, '_literal', None) and op_val in (44, 45, 55, 56):
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lit_str = f"0x{self._literal:x}"
|
||||
ops.insert(2, lit_str) if op_val in (44, 55) else ops.append(lit_str)
|
||||
return f"{op_name} {', '.join(ops)}" if ops else op_name
|
||||
|
||||
class Inst32(Inst): pass
|
||||
class Inst64(Inst): pass
|
||||
class Inst64(Inst):
|
||||
def to_bytes(self) -> bytes:
|
||||
result = self.to_int().to_bytes(8, 'little')
|
||||
return result + (lit & 0xffffffff).to_bytes(4, 'little') if (lit := self._get_literal() or getattr(self, '_literal', None)) else result
|
||||
@classmethod
|
||||
def from_bytes(cls, data: bytes): return cls.from_int(int.from_bytes(data[:8], 'little'))
|
||||
|
||||
# ═══════════════════════════════════════════════════════════════════════════════
|
||||
# CODE GENERATION: generates autogen/__init__.py by parsing the AMD RDNA3.5 ISA PDF
|
||||
# ═══════════════════════════════════════════════════════════════════════════════
|
||||
# Waitcnt helpers
|
||||
def waitcnt(vmcnt: int = 0x7f, expcnt: int = 0x7, lgkmcnt: int = 0x3f) -> int:
|
||||
return (vmcnt & 0xf) | ((expcnt & 0x7) << 4) | (((vmcnt >> 4) & 0x7) << 7) | ((lgkmcnt & 0x3f) << 10)
|
||||
def decode_waitcnt(val: int) -> tuple[int, int, int]:
|
||||
return (val & 0xf) | (((val >> 7) & 0x7) << 4), (val >> 4) & 0x7, (val >> 10) & 0x3f
|
||||
|
||||
PDF_URL = "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content"
|
||||
FIELD_TYPES = {'SSRC0': 'SSrc', 'SSRC1': 'SSrc', 'SOFFSET': 'SSrc', 'SADDR': 'SSrc', 'SRC0': 'Src', 'SRC1': 'Src', 'SRC2': 'Src',
|
||||
'SDST': 'SGPRField', 'SBASE': 'SGPRField', 'SDATA': 'SGPRField', 'SRSRC': 'SGPRField', 'VDST': 'VGPRField', 'VSRC1': 'VGPRField', 'VDATA': 'VGPRField',
|
||||
'VADDR': 'VGPRField', 'ADDR': 'VGPRField', 'DATA': 'VGPRField', 'DATA0': 'VGPRField', 'DATA1': 'VGPRField', 'SIMM16': 'SImm', 'OFFSET': 'Imm',
|
||||
'OPX': 'VOPDOp', 'OPY': 'VOPDOp', 'SRCX0': 'Src', 'SRCY0': 'Src', 'VSRCX1': 'VGPRField', 'VSRCY1': 'VGPRField', 'VDSTX': 'VGPRField', 'VDSTY': 'VDSTYEnc'}
|
||||
FIELD_ORDER = {
|
||||
'SOP2': ['op', 'sdst', 'ssrc0', 'ssrc1'], 'SOP1': ['op', 'sdst', 'ssrc0'], 'SOPC': ['op', 'ssrc0', 'ssrc1'],
|
||||
'SOPK': ['op', 'sdst', 'simm16'], 'SOPP': ['op', 'simm16'], 'VOP1': ['op', 'vdst', 'src0'], 'VOPC': ['op', 'src0', 'vsrc1'],
|
||||
'VOP2': ['op', 'vdst', 'src0', 'vsrc1'], 'VOP3SD': ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2', 'clmp'],
|
||||
'SMEM': ['op', 'sdata', 'sbase', 'soffset', 'offset', 'glc', 'dlc'], 'DS': ['op', 'vdst', 'addr', 'data0', 'data1'],
|
||||
'VOP3': ['op', 'vdst', 'src0', 'src1', 'src2', 'omod', 'neg', 'abs', 'clmp', 'opsel'],
|
||||
'VOP3P': ['op', 'vdst', 'src0', 'src1', 'src2', 'neg', 'neg_hi', 'opsel', 'opsel_hi', 'clmp'],
|
||||
'FLAT': ['op', 'vdst', 'addr', 'data', 'saddr', 'offset', 'seg', 'dlc', 'glc', 'slc'],
|
||||
'MUBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
|
||||
'MTBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
|
||||
'MIMG': ['op', 'vdata', 'vaddr', 'srsrc', 'ssamp', 'dmask', 'dim', 'unrm', 'dlc', 'glc', 'slc'],
|
||||
'EXP': ['en', 'target', 'vsrc0', 'vsrc1', 'vsrc2', 'vsrc3', 'done', 'row'],
|
||||
'VINTERP': ['op', 'vdst', 'src0', 'src1', 'src2', 'waitexp', 'clmp', 'opsel', 'neg'],
|
||||
'VOPD': ['opx', 'opy', 'vdstx', 'vdsty', 'srcx0', 'vsrcx1', 'srcy0', 'vsrcy1'],
|
||||
'LDSDIR': ['op', 'vdst', 'attr', 'attr_chan', 'wait_va']}
|
||||
SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'}
|
||||
FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO',
|
||||
'4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'}
|
||||
# Assembler
|
||||
SPECIAL_REGS = {'vcc_lo': RawImm(106), 'vcc_hi': RawImm(107), 'null': RawImm(124), 'off': RawImm(124), 'm0': RawImm(125), 'exec_lo': RawImm(126), 'exec_hi': RawImm(127), 'scc': RawImm(253)}
|
||||
FLOAT_CONSTS = {'0.5': 0.5, '-0.5': -0.5, '1.0': 1.0, '-1.0': -1.0, '2.0': 2.0, '-2.0': -2.0, '4.0': 4.0, '-4.0': -4.0}
|
||||
REG_MAP = {'s': SGPR, 'v': VGPR, 't': TTMP, 'ttmp': TTMP}
|
||||
|
||||
def _parse_bits(s: str) -> tuple[int, int] | None:
|
||||
import re
|
||||
return (int(m.group(1)), int(m.group(2) or m.group(1))) if (m := re.match(r'\[(\d+)(?::(\d+))?\]', s)) else None
|
||||
def parse_operand(op: str) -> tuple:
|
||||
op = op.strip().lower()
|
||||
neg = op.startswith('-') and not op[1:2].isdigit(); op = op[1:] if neg else op
|
||||
abs_ = op.startswith('|') and op.endswith('|') or op.startswith('abs(') and op.endswith(')')
|
||||
op = op[1:-1] if op.startswith('|') else op[4:-1] if op.startswith('abs(') else op
|
||||
# Handle .l/.h suffix (16-bit register halves)
|
||||
hi_half = op.endswith('.h')
|
||||
op = re.sub(r'\.[lh]$', '', op)
|
||||
if op in FLOAT_CONSTS: return (FLOAT_CONSTS[op], neg, abs_, hi_half)
|
||||
if re.match(r'^-?\d+$', op): return (int(op), neg, abs_, hi_half)
|
||||
if m := re.match(r'^-?0x([0-9a-f]+)$', op):
|
||||
v = -int(m.group(1), 16) if op.startswith('-') else int(m.group(1), 16)
|
||||
return (v, neg, abs_, hi_half)
|
||||
if op in SPECIAL_REGS: return (SPECIAL_REGS[op], neg, abs_, hi_half)
|
||||
if m := re.match(r'^([svt](?:tmp)?)\[(\d+):(\d+)\]$', op): return (REG_MAP[m.group(1)][int(m.group(2)):int(m.group(3))+1], neg, abs_, hi_half)
|
||||
if m := re.match(r'^([svt](?:tmp)?)(\d+)$', op):
|
||||
reg_cls = REG_MAP[m.group(1)]
|
||||
return (reg_cls(int(m.group(2)), 1, hi_half), neg, abs_, hi_half)
|
||||
raise ValueError(f"cannot parse operand: {op}")
|
||||
|
||||
def _parse_fields_table(table: list, fmt: str, enums: set[str]) -> list[tuple]:
|
||||
import re
|
||||
fields = []
|
||||
for row in table[1:]:
|
||||
if not row or not row[0]: continue
|
||||
name, bits_str = row[0].split('\n')[0].strip(), (row[1] or '').split('\n')[0].strip()
|
||||
if not (bits := _parse_bits(bits_str)): continue
|
||||
enc_val, hi, lo = None, bits[0], bits[1]
|
||||
if name == 'ENCODING' and row[2] and (m := re.search(r"'b([01_]+)", row[2])):
|
||||
enc_bits = m.group(1).replace('_', '')
|
||||
enc_val = int(enc_bits, 2)
|
||||
declared_width, actual_width = hi - lo + 1, len(enc_bits)
|
||||
if actual_width > declared_width: lo = hi - actual_width + 1
|
||||
ftype = f"{fmt}Op" if name == 'OP' and f"{fmt}Op" in enums else FIELD_TYPES.get(name.upper())
|
||||
fields.append((name, hi, lo, enc_val, ftype))
|
||||
return fields
|
||||
SMEM_OPS = {'s_load_b32', 's_load_b64', 's_load_b128', 's_load_b256', 's_load_b512',
|
||||
's_buffer_load_b32', 's_buffer_load_b64', 's_buffer_load_b128', 's_buffer_load_b256', 's_buffer_load_b512'}
|
||||
SOP1_SRC_ONLY = {'s_setpc_b64', 's_rfe_b64'} # instructions with ssrc0 only, no sdst
|
||||
SOP1_MSG_IMM = {'s_sendmsg_rtn_b32', 's_sendmsg_rtn_b64'} # instructions with raw immediate in ssrc0
|
||||
SOPK_IMM_ONLY = {'s_version'} # instructions with simm16 only, no sdst
|
||||
SOPK_IMM_FIRST = {'s_setreg_b32'} # instructions where simm16 comes before sdst
|
||||
SOPK_UNSUPPORTED = {'s_setreg_imm32_b32'} # special 64-bit SOPK format
|
||||
|
||||
def generate(output_path: str | None = None) -> dict:
|
||||
"""Generate RDNA3.5 instruction definitions from the AMD ISA PDF. Returns dict with formats for testing."""
|
||||
import re, pdfplumber, pathlib
|
||||
from tinygrad.helpers import fetch
|
||||
|
||||
pdf = pdfplumber.open(fetch(PDF_URL))
|
||||
pages = pdf.pages[150:200]
|
||||
page_texts = [p.extract_text() or '' for p in pages]
|
||||
page_tables = [[t.extract() for t in p.find_tables()] for p in pages]
|
||||
full_text = '\n'.join(page_texts)
|
||||
|
||||
# parse SSRC encoding from first page with VCC_LO
|
||||
src_enum = dict(SRC_EXTRAS)
|
||||
for text in page_texts[:10]:
|
||||
if 'SSRC0' in text and 'VCC_LO' in text:
|
||||
for m in re.finditer(r'^(\d+)\s+(\S+)', text, re.M):
|
||||
val, name = int(m.group(1)), m.group(2).rstrip('.:')
|
||||
if name in FLOAT_MAP: src_enum[val] = FLOAT_MAP[name]
|
||||
elif re.match(r'^[A-Z][A-Z0-9_]*$', name): src_enum[val] = name
|
||||
break
|
||||
|
||||
# parse opcode tables
|
||||
enums: dict[str, dict[int, str]] = {}
|
||||
for m in re.finditer(r'Table \d+\. (\w+) Opcodes(.*?)(?=Table \d+\.|\n\d+\.\d+\.\d+\.\s+\w+\s*\nDescription|$)', full_text, re.S):
|
||||
if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+([A-Z][A-Z0-9_]+)', m.group(2))}:
|
||||
enums[m.group(1) + "Op"] = ops
|
||||
if vopd_m := re.search(r'Table \d+\. VOPD Y-Opcodes\n(.*?)(?=Table \d+\.|15\.\d)', full_text, re.S):
|
||||
if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+(V_DUAL_\w+)', vopd_m.group(1))}:
|
||||
enums["VOPDOp"] = ops
|
||||
enum_names = set(enums.keys())
|
||||
|
||||
def is_fields_table(t) -> bool: return t and len(t) > 1 and t[0] and 'Field' in str(t[0][0] or '')
|
||||
def has_encoding(fields) -> bool: return any(f[0] == 'ENCODING' for f in fields)
|
||||
def has_header_before_fields(text) -> bool:
|
||||
return (pos := text.find('Field Name')) != -1 and bool(re.search(r'\d+\.\d+\.\d+\.\s+\w+\s*\n', text[:pos]))
|
||||
|
||||
# find format headers with their page indices
|
||||
format_headers = [] # (fmt_name, page_idx)
|
||||
for i, text in enumerate(page_texts):
|
||||
for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n?Description', text): format_headers.append((m.group(1), i, m.start()))
|
||||
for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n', text):
|
||||
if m.start() > len(text) - 200 and 'Description' not in text[m.end():] and i + 1 < len(page_texts):
|
||||
next_text = page_texts[i + 1].lstrip()
|
||||
if next_text.startswith('Description') or (next_text.startswith('"RDNA') and 'Description' in next_text[:200]):
|
||||
format_headers.append((m.group(1), i, m.start()))
|
||||
|
||||
# parse instruction formats
|
||||
formats: dict[str, list] = {}
|
||||
for fmt_name, page_idx, header_pos in format_headers:
|
||||
if fmt_name in formats: continue
|
||||
text, tables = page_texts[page_idx], page_tables[page_idx]
|
||||
field_pos = text.find('Field Name', header_pos)
|
||||
|
||||
# find fields table with ENCODING (same page or up to 2 pages ahead)
|
||||
fields = None
|
||||
for offset in range(3):
|
||||
if page_idx + offset >= len(pages): break
|
||||
if offset > 0 and has_header_before_fields(page_texts[page_idx + offset]): break
|
||||
for t in page_tables[page_idx + offset] if offset > 0 or field_pos > header_pos else []:
|
||||
if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)) and has_encoding(f):
|
||||
fields = f
|
||||
break
|
||||
if fields: break
|
||||
|
||||
# for modifier formats (no ENCODING), accept first fields table on same page
|
||||
if not fields and field_pos > header_pos:
|
||||
for t in tables:
|
||||
if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)):
|
||||
fields = f
|
||||
break
|
||||
|
||||
if not fields: continue
|
||||
field_names = {f[0] for f in fields}
|
||||
|
||||
# check next pages for continuation fields (tables without ENCODING)
|
||||
for pg_offset in range(1, 3):
|
||||
if page_idx + pg_offset >= len(pages) or has_header_before_fields(page_texts[page_idx + pg_offset]): break
|
||||
for t in page_tables[page_idx + pg_offset]:
|
||||
if is_fields_table(t) and (extra := _parse_fields_table(t, fmt_name, enum_names)) and not has_encoding(extra):
|
||||
for ef in extra:
|
||||
if ef[0] not in field_names:
|
||||
fields.append(ef)
|
||||
field_names.add(ef[0])
|
||||
break
|
||||
formats[fmt_name] = fields
|
||||
|
||||
# fix known PDF errors (verified against LLVM test vectors)
|
||||
# SMEM: PDF says DLC=bit14, GLC=bit16 but actual encoding is DLC=bit13, GLC=bit14
|
||||
if 'SMEM' in formats:
|
||||
formats['SMEM'] = [(n, 13 if n == 'DLC' else 14 if n == 'GLC' else h, 13 if n == 'DLC' else 14 if n == 'GLC' else l, e, t)
|
||||
for n, h, l, e, t in formats['SMEM']]
|
||||
|
||||
# generate output
|
||||
def enum_lines(name, items):
|
||||
return [f"class {name}(IntEnum):"] + [f" {n} = {v}" for v, n in sorted(items.items())] + [""]
|
||||
def field_key(f): return order.index(f[0].lower()) if f[0].lower() in order else 1000
|
||||
lines = ["# autogenerated from AMD RDNA3.5 ISA PDF by lib.py - do not edit", "from enum import IntEnum",
|
||||
"from typing import Annotated",
|
||||
"from extra.assembly.rdna3.lib import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField",
|
||||
"import functools", ""]
|
||||
lines += enum_lines("SrcEnum", src_enum) + sum([enum_lines(n, ops) for n, ops in sorted(enums.items())], [])
|
||||
# Format-specific field defaults (verified against LLVM test vectors)
|
||||
format_defaults = {'VOP3P': {'opsel_hi': 3, 'opsel_hi2': 1}}
|
||||
lines.append("# instruction formats")
|
||||
for fmt_name, fields in sorted(formats.items()):
|
||||
base = "Inst64" if max(f[1] for f in fields) > 31 or fmt_name == 'VOP3SD' else "Inst32"
|
||||
order = FIELD_ORDER.get(fmt_name, [])
|
||||
lines.append(f"class {fmt_name}({base}):")
|
||||
if enc := next((f for f in fields if f[0] == 'ENCODING'), None):
|
||||
enc_str = f"bits[{enc[1]}:{enc[2]}] == 0b{enc[3]:b}" if enc[1] != enc[2] else f"bits[{enc[1]}] == {enc[3]}"
|
||||
lines.append(f" encoding = {enc_str}")
|
||||
if defaults := format_defaults.get(fmt_name):
|
||||
lines.append(f" _defaults = {defaults}")
|
||||
for name, hi, lo, _, ftype in sorted([f for f in fields if f[0] != 'ENCODING'], key=field_key):
|
||||
# Wrap IntEnum types (ending in Op) with Annotated[BitField, ...] for correct typing
|
||||
if ftype and ftype.endswith('Op'):
|
||||
ann = f":Annotated[BitField, {ftype}]"
|
||||
else:
|
||||
ann = f":{ftype}" if ftype else ""
|
||||
lines.append(f" {name.lower()}{ann} = bits[{hi}]" if hi == lo else f" {name.lower()}{ann} = bits[{hi}:{lo}]")
|
||||
lines.append("")
|
||||
lines.append("# instruction helpers")
|
||||
for cls_name, ops in sorted(enums.items()):
|
||||
fmt = cls_name[:-2]
|
||||
for op_val, name in sorted(ops.items()):
|
||||
seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=2"}.get(fmt, "")
|
||||
tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt, f"{fmt}, {cls_name}")
|
||||
if fmt in formats or fmt in ("GLOBAL", "SCRATCH"):
|
||||
# VOP1/VOP2/VOPC get _e32 suffix, VOP3 promoted ops (< 512) get _e64 suffix
|
||||
if fmt in ("VOP1", "VOP2", "VOPC"):
|
||||
suffix = "_e32"
|
||||
elif fmt == "VOP3" and op_val < 512:
|
||||
suffix = "_e64"
|
||||
else:
|
||||
suffix = ""
|
||||
# FMAMK/FMAAK have a literal constant K that must be passed via literal= kwarg
|
||||
# FMAMK: D = S0.f * K + S1.f (K is 3rd operand in assembly syntax)
|
||||
# FMAAK: D = S0.f * S1.f + K (K is 4th operand in assembly syntax)
|
||||
if name in ('V_FMAMK_F32', 'V_FMAMK_F16'):
|
||||
lines.append(f"def {name.lower()}{suffix}(vdst, src0, K, vsrc1): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
|
||||
elif name in ('V_FMAAK_F32', 'V_FMAAK_F16'):
|
||||
lines.append(f"def {name.lower()}{suffix}(vdst, src0, vsrc1, K): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
|
||||
else:
|
||||
lines.append(f"{name.lower()}{suffix} = functools.partial({tgt}.{name}{seg})")
|
||||
# export SrcEnum values, but skip DPP8/DPP16 which conflict with class names
|
||||
skip_exports = {'DPP8', 'DPP16'}
|
||||
lines += [""] + [f"{name} = SrcEnum.{name}" for _, name in sorted(src_enum.items()) if name not in skip_exports] + ["OFF = NULL\n"]
|
||||
|
||||
if output_path is not None:
|
||||
import pathlib
|
||||
pathlib.Path(output_path).write_text('\n'.join(lines))
|
||||
return {"formats": formats, "enums": enums, "src_enum": src_enum}
|
||||
|
||||
if __name__ == "__main__":
|
||||
result = generate("extra/assembly/rdna3/autogen/__init__.py")
|
||||
print(f"generated SrcEnum ({len(result['src_enum'])}) + {len(result['enums'])} opcode enums + {len(result['formats'])} format classes")
|
||||
def asm(text: str) -> Inst:
|
||||
from extra.assembly.rdna3 import autogen
|
||||
text = text.strip()
|
||||
clamp = 'clamp' in text.lower()
|
||||
if clamp: text = re.sub(r'\s+clamp\s*$', '', text, flags=re.I)
|
||||
# Parse modifiers like wait_exp:N
|
||||
modifiers = {}
|
||||
if m := re.search(r'\s+wait_exp:(\d+)', text, re.I): modifiers['waitexp'] = int(m.group(1)); text = text[:m.start()] + text[m.end():]
|
||||
parts = text.replace(',', ' ').split()
|
||||
if not parts: raise ValueError("empty instruction")
|
||||
mnemonic, op_str = parts[0].lower(), text[len(parts[0]):].strip()
|
||||
operands, current, depth, in_pipe = [], "", 0, False
|
||||
for ch in op_str:
|
||||
if ch == '[': depth += 1
|
||||
elif ch == ']': depth -= 1
|
||||
elif ch == '|': in_pipe = not in_pipe
|
||||
if ch == ',' and depth == 0 and not in_pipe: operands.append(current.strip()); current = ""
|
||||
else: current += ch
|
||||
if current.strip(): operands.append(current.strip())
|
||||
parsed = [parse_operand(op) for op in operands]
|
||||
values = [p[0] for p in parsed]
|
||||
neg_bits = sum((1 << (i-1)) for i, p in enumerate(parsed) if i > 0 and p[1])
|
||||
abs_bits = sum((1 << (i-1)) for i, p in enumerate(parsed) if i > 0 and p[2])
|
||||
# Compute opsel bits for VOP3: bit0=src0.h, bit1=src1.h, bit2=src2.h, bit3=vdst.h
|
||||
opsel_bits = (8 if len(parsed) > 0 and parsed[0][3] else 0) | sum((1 << i) for i, p in enumerate(parsed[1:4]) if p[3])
|
||||
lit = None
|
||||
if mnemonic in ('v_fmaak_f32', 'v_fmaak_f16') and len(values) == 4: lit, values = unwrap(values[3]), values[:3]
|
||||
elif mnemonic in ('v_fmamk_f32', 'v_fmamk_f16') and len(values) == 4: lit, values = unwrap(values[2]), [values[0], values[1], values[3]]
|
||||
# VCC-using VOP2 instructions: skip implicit VCC operands (format: vdst, vcc_dst, src0, src1, vcc_src)
|
||||
vcc_ops = {'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32', 'v_add_co_u32', 'v_sub_co_u32', 'v_subrev_co_u32'}
|
||||
if mnemonic.replace('_e32', '') in vcc_ops and len(values) >= 5: values = [values[0], values[2], values[3]]
|
||||
# VOPC: skip implicit VCC destination operand (format: vcc_dst, src0, src1)
|
||||
if mnemonic.startswith('v_cmp') and len(values) >= 3 and operands[0].strip().lower() in ('vcc_lo', 'vcc_hi', 'vcc'):
|
||||
values = values[1:] # skip vcc destination
|
||||
# VOP3SD (v_div_scale_*): has vdst, sdst, then 3 sources - neg/abs apply to sources (operands 2,3,4)
|
||||
vop3sd_ops = {'v_div_scale_f32', 'v_div_scale_f64'}
|
||||
if mnemonic in vop3sd_ops and len(parsed) >= 5:
|
||||
neg_bits = sum((1 << i) for i, p in enumerate(parsed[2:5]) if p[1])
|
||||
abs_bits = sum((1 << i) for i, p in enumerate(parsed[2:5]) if p[2])
|
||||
# Unsupported instructions
|
||||
if mnemonic in SOPK_UNSUPPORTED: raise ValueError(f"unsupported instruction: {mnemonic}")
|
||||
# SOP1 source-only instructions (no destination)
|
||||
elif mnemonic in SOP1_SRC_ONLY:
|
||||
return getattr(autogen, mnemonic)(ssrc0=values[0])
|
||||
# SOP1 instructions with raw immediate message ID
|
||||
elif mnemonic in SOP1_MSG_IMM:
|
||||
return getattr(autogen, mnemonic)(sdst=values[0], ssrc0=RawImm(unwrap(values[1])))
|
||||
# SOPK immediate-only instructions (no destination)
|
||||
elif mnemonic in SOPK_IMM_ONLY:
|
||||
return getattr(autogen, mnemonic)(simm16=values[0])
|
||||
# SOPK instructions with simm16 before sdst
|
||||
elif mnemonic in SOPK_IMM_FIRST:
|
||||
return getattr(autogen, mnemonic)(simm16=values[0], sdst=values[1])
|
||||
# SMEM: when third operand is immediate, use it as offset with soffset=NULL
|
||||
elif mnemonic in SMEM_OPS and len(operands) >= 3 and re.match(r'^-?[0-9]|^-?0x', operands[2].strip().lower()):
|
||||
return getattr(autogen, mnemonic)(sdata=values[0], sbase=values[1], offset=values[2], soffset=RawImm(124))
|
||||
# MUBUF: when vaddr is 'off', use 0 instead of NULL
|
||||
elif mnemonic.startswith('buffer_') and len(operands) >= 2 and operands[1].strip().lower() == 'off':
|
||||
return getattr(autogen, mnemonic)(vdata=values[0], vaddr=0, srsrc=values[2], soffset=RawImm(unwrap(values[3])) if len(values) > 3 else RawImm(0))
|
||||
for suffix in (['_e32', ''] if not (neg_bits or abs_bits or clamp) else ['', '_e32']):
|
||||
if hasattr(autogen, name := mnemonic.replace('.', '_') + suffix):
|
||||
use_opsel = 'opsel' in getattr(autogen, name).func._fields
|
||||
# For VOP3+, clear hi flags from registers (opsel handles hi half selection)
|
||||
vals = [type(v)(v.idx, v.count, False) if isinstance(v, Reg) and v.hi and use_opsel else v for v in values]
|
||||
inst = getattr(autogen, name)(*vals, literal=lit, **modifiers)
|
||||
if neg_bits and 'neg' in inst._fields: inst._values['neg'] = neg_bits
|
||||
if opsel_bits and use_opsel: inst._values['opsel'] = opsel_bits
|
||||
if abs_bits and 'abs' in inst._fields: inst._values['abs'] = abs_bits
|
||||
if clamp and 'clmp' in inst._fields: inst._values['clmp'] = 1
|
||||
return inst
|
||||
raise ValueError(f"unknown instruction: {mnemonic}")
|
||||
|
||||
Reference in New Issue
Block a user