ds compiled

assembly/amd: move more instructions to pcode
2025-12-31 15:43:44 -05:00 · 2025-12-31 15:42:59 -05:00
400 changed files with 166394 additions and 195600 deletions
@@ -11,5 +11,5 @@ runs:
        git fetch origin $CURRENT_SHA
        export COMMIT_MESSAGE=$(git show -s --format=%B "$CURRENT_SHA")
        export CURRENT_HEAD=$(git rev-parse HEAD)
-        cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && CHECK_OOB=0 PYTHONPATH=. python3 process_replay.py
+        cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && IGNORE_OOB=1 PYTHONPATH=. python3 process_replay.py
        git checkout $CURRENT_HEAD  # restore to branch
@@ -56,15 +56,7 @@ runs:

    # **** Caching packages ****

-    - name: Cache Python packages (PR)
-      if: github.event_name == 'pull_request'
-      id: restore-venv-pr
-      uses: actions/cache/restore@v4
-      with:
-        path: ${{ github.workspace }}/.venv
-        key: venv-${{ runner.os }}-python-${{ steps.setup-python.outputs.python-version }}-${{ inputs.deps }}-${{ inputs.pydeps }}-${{ env.CACHE_VERSION }}
    - name: Cache Python packages
-      if: github.event_name != 'pull_request'
      id: restore-venv
      uses: actions/cache@v4
      with:
@@ -73,23 +65,23 @@ runs:

    # **** Caching downloads ****

-    - name: Cache downloads (PR)
-      if: inputs.key != '' && github.event_name == 'pull_request'
-      uses: actions/cache/restore@v4
-      with:
-        path: ${{ runner.os == 'Linux' && '~/.cache/tinygrad/downloads/' || '~/Library/Caches/tinygrad/downloads/' }}
-        key: downloads-${{ github.job }}-${{ inputs.key }}-${{ env.CACHE_VERSION }}
-    - name: Cache downloads
-      if: inputs.key != '' && github.event_name != 'pull_request'
+    - name: Cache downloads (Linux)
+      if: inputs.key != '' && runner.os == 'Linux'
      uses: actions/cache@v4
      with:
-        path: ${{ runner.os == 'Linux' && '~/.cache/tinygrad/downloads/' || '~/Library/Caches/tinygrad/downloads/' }}
+        path: ~/.cache/tinygrad/downloads/
+        key: downloads-${{ github.job }}-${{ inputs.key }}-${{ env.CACHE_VERSION }}
+    - name: Cache downloads (macOS)
+      if: inputs.key != '' && runner.os == 'macOS'
+      uses: actions/cache@v4
+      with:
+        path: ~/Library/Caches/tinygrad/downloads/
        key: downloads-${{ github.job }}-${{ inputs.key }}-${{ env.CACHE_VERSION }}

    # **** Python deps ****

    - name: Install dependencies in venv (with extra)
-      if: inputs.deps != '' && steps.restore-venv-pr.outputs.cache-hit != 'true' && steps.restore-venv.outputs.cache-hit != 'true'
+      if: inputs.deps != '' && steps.restore-venv.outputs.cache-hit != 'true'
      shell: bash
      run: |
        python -m venv .venv
@@ -100,7 +92,7 @@ runs:
        fi
        python -m pip install -e ".[${{ inputs.deps }}]" ${{ inputs.pydeps }} --extra-index-url https://download.pytorch.org/whl/cpu --extra-index-url https://aiinfra.pkgs.visualstudio.com/PublicPackages/_packaging/Triton-Nightly/pypi/simple/
    - name: Install dependencies in venv (without extra)
-      if: inputs.deps == '' && steps.restore-venv-pr.outputs.cache-hit != 'true' && steps.restore-venv.outputs.cache-hit != 'true'
+      if: inputs.deps == '' && steps.restore-venv.outputs.cache-hit != 'true'
      shell: bash
      run: |
        python -m venv .venv
@@ -190,14 +182,8 @@ runs:
        echo "pkgs=$pkgs" >> "$GITHUB_OUTPUT"
        echo "hash=$(echo -n "$pkgs" | sha256sum | cut -d' ' -f1)" >> "$GITHUB_OUTPUT"

-    - name: Cache apt (PR)
-      if: runner.os == 'Linux' && (inputs.opencl == 'true' || inputs.amd == 'true' || inputs.cuda == 'true' || inputs.webgpu == 'true' || inputs.llvm == 'true') && github.event_name == 'pull_request'
-      uses: actions/cache/restore@v4
-      with:
-        path: /var/cache/apt/archives/
-        key: ${{ runner.os }}-apt-${{ steps.apt-pkgs.outputs.hash }}-${{ env.CACHE_VERSION }}
    - name: Cache apt
-      if: runner.os == 'Linux' && (inputs.opencl == 'true' || inputs.amd == 'true' || inputs.cuda == 'true' || inputs.webgpu == 'true' || inputs.llvm == 'true') && github.event_name != 'pull_request'
+      if: runner.os == 'Linux' && (inputs.opencl == 'true' || inputs.amd == 'true' || inputs.cuda == 'true' || inputs.webgpu == 'true' || inputs.llvm == 'true')
      uses: actions/cache@v4
      with:
        path: /var/cache/apt/archives/
@@ -253,17 +239,8 @@ runs:
        ln -s /opt/homebrew/opt/[email protected] /opt/homebrew/opt/boost || true
        ln -s /opt/homebrew/opt/boost/lib/libboost_atomic-mt.dylib /opt/homebrew/opt/boost/lib/libboost_atomic.dylib || true
        ln -s /opt/homebrew/opt/boost/lib/libboost_thread-mt.dylib /opt/homebrew/opt/boost/lib/libboost_thread.dylib || true
-    - name: Cache gpuocelot (PR)
-      if: inputs.ocelot == 'true' && github.event_name == 'pull_request'
-      id: cache-build-pr
-      uses: actions/cache/restore@v4
-      env:
-        cache-name: cache-gpuocelot-build-1
-      with:
-        path: ${{ github.workspace }}/gpuocelot/ocelot
-        key: ${{ runner.os }}-gpuocelot-b16039dc940dc6bc4ea0a98380495769ff35ed99-rebuild-${{ env.CACHE_VERSION }}
    - name: Cache gpuocelot
-      if: inputs.ocelot == 'true' && github.event_name != 'pull_request'
+      if: inputs.ocelot == 'true'
      id: cache-build
      uses: actions/cache@v4
      env:
@@ -272,7 +249,7 @@ runs:
        path: ${{ github.workspace }}/gpuocelot/ocelot
        key: ${{ runner.os }}-gpuocelot-b16039dc940dc6bc4ea0a98380495769ff35ed99-rebuild-${{ env.CACHE_VERSION }}
    - name: Clone/compile gpuocelot
-      if: inputs.ocelot == 'true' && steps.cache-build-pr.outputs.cache-hit != 'true' && steps.cache-build.outputs.cache-hit != 'true'
+      if: inputs.ocelot == 'true' && steps.cache-build.outputs.cache-hit != 'true'
      shell: bash
      run: |
        git clone --recurse-submodules https://github.com/gpuocelot/gpuocelot.git ${{ github.workspace }}/gpuocelot
@@ -14,12 +14,10 @@ on:
    paths:
    - 'tinygrad/runtime/autogen/**/*'
    - 'tinygrad/runtime/support/autogen.py'
-    - '.github/workflows/autogen.yml'
  workflow_dispatch:
    paths:
    - 'tinygrad/runtime/autogen/**/*'
    - 'tinygrad/runtime/support/autogen.py'
-    - '.github/workflows/autogen.yml'

 jobs:
  autogen:
@@ -40,36 +38,103 @@ jobs:
        mesa: 'true'
        pydeps: 'pyyaml mako'
    - name: Install autogen support packages
-      run: sudo apt-get install -y --no-install-recommends libclang-20-dev llvm-20-dev hip-dev libusb-1.0-0-dev libdrm-dev
-    - name: Regenerate autogen files
+      run: sudo apt-get install -y --no-install-recommends libclang-20-dev llvm-20-dev hip-dev libusb-1.0-0-dev
+    - name: Verify OpenCL autogen
      run: |
-        find tinygrad/runtime/autogen -type f -name "*.py" -not -name "__init__.py" -not -name "comgr_3.py" -not -name "metal.py" -not -name "iokit.py" -not -name "corefoundation.py" -not -name "libclang.py" -delete
+        mv tinygrad/runtime/autogen/opencl.py /tmp/opencl.py.bak
        python3 -c "from tinygrad.runtime.autogen import opencl"
-        python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv_580, nv"
-        python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof, amdgpu_kd, amdgpu_drm"
-        python3 -c "from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v13_0_6, smu_v14_0_2"
-        python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio"
-        python3 -c "from tinygrad.runtime.autogen import llvm"
-        python3 -c "from tinygrad.runtime.autogen import webgpu"
-        python3 -c "from tinygrad.runtime.autogen import kgsl, qcom_dsp"
-        python3 -c "from tinygrad.runtime.autogen import libusb"
-        python3 -c "from tinygrad.runtime.autogen import mesa"
-        python3 -c "from tinygrad.runtime.autogen import avcodec"
-        REGEN=1 python3 -c "from tinygrad.runtime.autogen import libclang"
-    - name: Check for differences
+        diff /tmp/opencl.py.bak tinygrad/runtime/autogen/opencl.py
+    - name: Verify CUDA autogen
      run: |
-        if ! git diff --quiet; then
-          git diff > autogen-ubuntu.patch
-          echo "Autogen files out of date. Apply patch from: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}#artifacts"
-          exit 1
-        fi
-    - name: Upload patch artifact
-      if: failure()
-      uses: actions/upload-artifact@v4
-      with:
-        name: autogen-ubuntu-patch
-        path: autogen-ubuntu.patch
-
+        mv tinygrad/runtime/autogen/cuda.py /tmp/cuda.py.bak
+        mv tinygrad/runtime/autogen/nvrtc.py /tmp/nvrtc.py.bak
+        mv tinygrad/runtime/autogen/nvjitlink.py /tmp/nvjitlink.py.bak
+        mv tinygrad/runtime/autogen/nv_570.py /tmp/nv_570.py.bak
+        mv tinygrad/runtime/autogen/nv.py /tmp/nv.py.bak
+        python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv"
+        diff /tmp/cuda.py.bak tinygrad/runtime/autogen/cuda.py
+        diff /tmp/nvrtc.py.bak tinygrad/runtime/autogen/nvrtc.py
+        diff /tmp/nvjitlink.py.bak tinygrad/runtime/autogen/nvjitlink.py
+        diff /tmp/nv_570.py.bak tinygrad/runtime/autogen/nv_570.py
+        diff /tmp/nv.py.bak tinygrad/runtime/autogen/nv.py
+    - name: Verify AMD autogen
+      run: |
+        mv tinygrad/runtime/autogen/comgr.py /tmp/comgr.py.bak
+        mv tinygrad/runtime/autogen/hsa.py /tmp/hsa.py.bak
+        mv tinygrad/runtime/autogen/hip.py /tmp/hip.py.bak
+        mv tinygrad/runtime/autogen/amd_gpu.py /tmp/amd_gpu.py.bak
+        mv tinygrad/runtime/autogen/sqtt.py /tmp/sqtt.py.bak
+        mv tinygrad/runtime/autogen/rocprof.py /tmp/rocprof.py.bak
+        mv tinygrad/runtime/autogen/am/am.py /tmp/am_am.py.bak
+        mv tinygrad/runtime/autogen/am/pm4_soc15.py /tmp/am_pm4_soc15.py.bak
+        mv tinygrad/runtime/autogen/am/pm4_nv.py /tmp/am_pm4_nv.py.bak
+        mv tinygrad/runtime/autogen/am/sdma_4_0_0.py /tmp/am_sdma_4_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/sdma_5_0_0.py /tmp/am_sdma_5_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/sdma_6_0_0.py /tmp/am_sdma_6_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/smu_v13_0_0.py /tmp/am_smu_v13_0_0.py.bak
+        mv tinygrad/runtime/autogen/am/smu_v14_0_2.py /tmp/am_smu_v14_0_2.py.bak
+        python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof; from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v14_0_2"
+        diff /tmp/comgr.py.bak tinygrad/runtime/autogen/comgr.py
+        diff /tmp/hsa.py.bak tinygrad/runtime/autogen/hsa.py
+        diff /tmp/hip.py.bak tinygrad/runtime/autogen/hip.py
+        diff /tmp/amd_gpu.py.bak tinygrad/runtime/autogen/amd_gpu.py
+        diff /tmp/sqtt.py.bak tinygrad/runtime/autogen/sqtt.py
+        diff /tmp/rocprof.py.bak tinygrad/runtime/autogen/rocprof.py
+        diff /tmp/am_am.py.bak tinygrad/runtime/autogen/am/am.py
+        diff /tmp/am_pm4_soc15.py.bak tinygrad/runtime/autogen/am/pm4_soc15.py
+        diff /tmp/am_pm4_nv.py.bak tinygrad/runtime/autogen/am/pm4_nv.py
+        diff /tmp/am_sdma_4_0_0.py.bak tinygrad/runtime/autogen/am/sdma_4_0_0.py
+        diff /tmp/am_sdma_5_0_0.py.bak tinygrad/runtime/autogen/am/sdma_5_0_0.py
+        diff /tmp/am_sdma_6_0_0.py.bak tinygrad/runtime/autogen/am/sdma_6_0_0.py
+        diff /tmp/am_smu_v13_0_0.py.bak tinygrad/runtime/autogen/am/smu_v13_0_0.py
+        diff /tmp/am_smu_v14_0_2.py.bak tinygrad/runtime/autogen/am/smu_v14_0_2.py
+    - name: Verify Linux autogen
+      run: |
+        mv tinygrad/runtime/autogen/libc.py /tmp/libc.py.bak
+        mv tinygrad/runtime/autogen/kfd.py /tmp/kfd.py.bak
+        mv tinygrad/runtime/autogen/io_uring.py /tmp/io_uring.py.bak
+        mv tinygrad/runtime/autogen/ib.py /tmp/ib.py.bak
+        mv tinygrad/runtime/autogen/pci.py /tmp/pci.py.bak
+        mv tinygrad/runtime/autogen/vfio.py /tmp/vfio.py.bak
+        python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio"
+        diff /tmp/libc.py.bak tinygrad/runtime/autogen/libc.py
+        diff /tmp/kfd.py.bak tinygrad/runtime/autogen/kfd.py
+        diff /tmp/io_uring.py.bak tinygrad/runtime/autogen/io_uring.py
+        diff /tmp/ib.py.bak tinygrad/runtime/autogen/ib.py
+        diff /tmp/pci.py.bak tinygrad/runtime/autogen/pci.py
+        diff /tmp/vfio.py.bak tinygrad/runtime/autogen/vfio.py
+    - name: Verify LLVM autogen
+      run: |
+        mv tinygrad/runtime/autogen/llvm.py /tmp/llvm.py.bak
+        python3 -c "from tinygrad.runtime.autogen import llvm"
+        diff /tmp/llvm.py.bak tinygrad/runtime/autogen/llvm.py
+    - name: Verify WebGPU autogen
+      run: |
+        mv tinygrad/runtime/autogen/webgpu.py /tmp/webgpu.py.bak
+        python3 -c "from tinygrad.runtime.autogen import webgpu"
+        diff /tmp/webgpu.py.bak tinygrad/runtime/autogen/webgpu.py
+    - name: Verify Qualcomm autogen
+      run: |
+        mv tinygrad/runtime/autogen/kgsl.py /tmp/kgsl.py.bak
+        mv tinygrad/runtime/autogen/qcom_dsp.py /tmp/qcom_dsp.py.bak
+        python3 -c "from tinygrad.runtime.autogen import kgsl, qcom_dsp"
+        diff /tmp/kgsl.py.bak tinygrad/runtime/autogen/kgsl.py
+        diff /tmp/qcom_dsp.py.bak tinygrad/runtime/autogen/qcom_dsp.py
+    - name: Verify libusb autogen
+      run: |
+        mv tinygrad/runtime/autogen/libusb.py /tmp/libusb.py.bak
+        python3 -c "from tinygrad.runtime.autogen import libusb"
+        diff /tmp/libusb.py.bak tinygrad/runtime/autogen/libusb.py
+    - name: Verify mesa autogen
+      run: |
+        mv tinygrad/runtime/autogen/mesa.py /tmp/mesa.py.bak
+        python3 -c "from tinygrad.runtime.autogen import mesa"
+        diff /tmp/mesa.py.bak tinygrad/runtime/autogen/mesa.py
+    - name: Verify libclang autogen
+      run: |
+        cp tinygrad/runtime/autogen/libclang.py /tmp/libclang.py.bak
+        REGEN=1 python3 -c "from tinygrad.runtime.autogen import libclang"
+        diff /tmp/libclang.py.bak tinygrad/runtime/autogen/libclang.py
  autogen-mac:
    name: In-tree Autogen (macos)
    runs-on: macos-14
@@ -81,24 +146,11 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        llvm: 'true'
-    - name: Regenerate autogen files
+    - name: Verify macos autogen
      run: |
-        rm tinygrad/runtime/autogen/metal.py tinygrad/runtime/autogen/iokit.py tinygrad/runtime/autogen/corefoundation.py
-        python3 -c "from tinygrad.runtime.autogen import metal, iokit, corefoundation"
-    - name: Check for differences
-      run: |
-        if ! git diff --quiet; then
-          git diff > autogen-macos.patch
-          echo "Autogen files out of date. Apply patch from: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}#artifacts"
-          exit 1
-        fi
-    - name: Upload patch artifact
-      if: failure()
-      uses: actions/upload-artifact@v4
-      with:
-        name: autogen-macos-patch
-        path: autogen-macos.patch
-
+        mv tinygrad/runtime/autogen/metal.py /tmp/metal.py.bak
+        LIBCLANG_PATH=/opt/homebrew/opt/llvm@20/lib/libclang.dylib python3 -c "from tinygrad.runtime.autogen import metal"
+        diff /tmp/metal.py.bak tinygrad/runtime/autogen/metal.py
  autogen-comgr-3:
    name: In-tree Autogen (comgr 3)
    runs-on: ubuntu-24.04
@@ -117,20 +169,8 @@ jobs:
        echo -e 'Package: *\nPin: release o=repo.radeon.com\nPin-Priority: 600' | sudo tee /etc/apt/preferences.d/rocm-pin-600
        sudo apt -qq update || true
        sudo apt-get install -y --no-install-recommends libclang-20-dev comgr
-    - name: Regenerate autogen files
+    - name: Verify comgr (3) autogen
      run: |
-        rm tinygrad/runtime/autogen/comgr_3.py
+        mv tinygrad/runtime/autogen/comgr_3.py /tmp/comgr_3.py.bak
        python3 -c "from tinygrad.runtime.autogen import comgr_3"
-    - name: Check for differences
-      run: |
-        if ! git diff --quiet; then
-          git diff > autogen-comgr3.patch
-          echo "Autogen files out of date. Apply patch from: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}#artifacts"
-          exit 1
-        fi
-    - name: Upload patch artifact
-      if: failure()
-      uses: actions/upload-artifact@v4
-      with:
-        name: autogen-comgr3-patch
-        path: autogen-comgr3.patch
+        diff /tmp/comgr_3.py.bak tinygrad/runtime/autogen/comgr_3.py
@@ -16,36 +16,6 @@ on:
  workflow_dispatch:

 jobs:
-  # the goal of this test is to replicate a normal person on a laptop running the test
-  # no process replay, no benchmarks, no CI, just a normal laptop person
-  # the 3 minute timeout should not be raised
-  testmacpytest:
-    name: Mac pytest
-    runs-on: [self-hosted, macOS]
-    timeout-minutes: 3
-    defaults:
-      run:
-        shell: bash -e -o pipefail {0}
-    if: github.repository_owner == 'tinygrad'
-    steps:
-    - name: Checkout Code
-      uses: actions/checkout@v4
-    # brew install uv
-    - name: setup python environment
-      run: |
-        rm -rf /tmp/tinygrad_pytest_ci
-        uv venv /tmp/tinygrad_pytest_ci
-        source /tmp/tinygrad_pytest_ci/bin/activate
-        uv pip install .[testing]
-    - name: setup staging db
-      run: |
-        echo "CACHEDB=/tmp/pytest-db-ci.db" >> $GITHUB_ENV
-        rm -f /tmp/pytest-db-ci*
-    - name: Run pytest -nauto
-      run: |
-        source /tmp/tinygrad_pytest_ci/bin/activate
-        pytest -nauto
-
  testmacbenchmark:
    name: Mac Benchmark
    env:
@@ -79,19 +49,19 @@ jobs:
    - name: Print macOS version
      run: sw_vers
    - name: Run Stable Diffusion
-      run: BENCHMARK_LOG=stable_diffusion JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    - name: Run Stable Diffusion without fp16
-      run: BENCHMARK_LOG=stable_diffusion_fp32 JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_fp32 JIT=1 ASSERT_MIN_STEP_TIME=720 python3.11 examples/stable_diffusion.py --seed 0 --noshow --timing | tee sd_no_fp16.txt
    - name: Run Stable Diffusion v2
      # TODO: very slow step time
-      run: BENCHMARK_LOG=stable_diffusion_v2 JIT=1 ASSERT_MIN_STEP_TIME=4500 python3.11 examples/sdv2.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_v2 JIT=1 ASSERT_MIN_STEP_TIME=4500 python3.11 examples/sdv2.py --fp16 --seed 0 --noshow --timing | tee sdv2.txt
    # process replay can't capture this, the graph is too large
    - name: Run SDXL
-      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=5000 CAPTURE_PROCESS_REPLAY=0 JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=5000 CAPTURE_PROCESS_REPLAY=0 JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run model inference benchmark
      run: METAL=1 NOCLANG=1 python3.11 test/external/external_model_benchmark.py
    - name: Test speed vs torch
-      run: BIG=2 MPS=1 python3.11 test/speed/external_test_speed_v_torch.py
+      run: BIG=2 MPS=1 python3.11 test/speed/external_test_speed_v_torch.py | tee torch_speed.txt
    - name: Test tensor cores
      run: METAL=1 python3.11 test/opt/test_tensor_cores.py
    - name: Test AMX tensor cores
@@ -101,59 +71,84 @@ jobs:
        DEBUG=2 CPU=1 CPU_LLVM=0 AMX=1 python3.11 test/opt/test_gen_float4.py TestFloat4.test_float4_multidim_amx TestFloat4.test_float4_multidim_unaligned_load_amx
        DEBUG=2 CPU=1 CPU_LLVM=1 AMX=1 python3.11 test/opt/test_gen_float4.py TestFloat4.test_float4_multidim_amx TestFloat4.test_float4_multidim_unaligned_load_amx
    - name: Run Tensor Core GEMM (float)
-      run: DEBUG=2 SHOULD_USE_TC=1 python3.11 extra/gemm/simple_matmul.py
+      run: DEBUG=2 SHOULD_USE_TC=1 python3.11 extra/gemm/simple_matmul.py | tee matmul.txt
    - name: Run Tensor Core GEMM (half)
-      run: DEBUG=2 SHOULD_USE_TC=1 HALF=1 python3.11 extra/gemm/simple_matmul.py
+      run: DEBUG=2 SHOULD_USE_TC=1 HALF=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_half.txt
    - name: Run Tensor Core GEMM (bfloat16)
-      run: DEBUG=2 SHOULD_USE_TC=1 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py
+      run: DEBUG=2 SHOULD_USE_TC=1 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
    - name: Fuzz Padded Tensor Core GEMM
      run: METAL=1 M_START=6 M_STOP=10 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=6 K_STOP=24 K_STEP=1 TC_OPT=2 DEBUG=2 python3.11 ./extra/gemm/fuzz_matmul.py
    - name: Run LLaMA
      run: |
-        BENCHMARK_LOG=llama_nojit JIT=0 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=llama JIT=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=llama_nojit JIT=0 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
+        BENCHMARK_LOG=llama JIT=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt
    - name: Run LLaMA with BEAM
-      run: BENCHMARK_LOG=llama_beam JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=llama_beam JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt
    - name: Run quantized LLaMA
      run: |
-        BENCHMARK_LOG=llama_int8 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize int8
-        BENCHMARK_LOG=llama_nf4 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize nf4
+        BENCHMARK_LOG=llama_int8 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize int8 | tee llama_int8.txt
+        BENCHMARK_LOG=llama_nf4 python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize nf4 | tee llama_nf4.txt
    - name: Run quantized LLaMA3
      run: |
-        BENCHMARK_LOG=llama3_int8 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize int8
-        BENCHMARK_LOG=llama3_nf4 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize nf4
+        BENCHMARK_LOG=llama3_int8 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize int8 | tee llama3_int8.txt
+        BENCHMARK_LOG=llama3_nf4 python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize nf4 | tee llama3_nf4.txt
    #- name: Run LLaMA 7B on 4 (virtual) GPUs
-    #  run: python3.11 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing
+    #  run: python3.11 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    - name: Run GPT2
      run: |
-        BENCHMARK_LOG=gpt2_nojit JIT=0 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=gpt2 JIT=1 ASSERT_MIN_STEP_TIME=13 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=gpt2_nojit JIT=0 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt
+        BENCHMARK_LOG=gpt2 JIT=1 ASSERT_MIN_STEP_TIME=13 python3.11 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt
    - name: Run GPT2 w HALF
-      run: BENCHMARK_LOG=gpt2_half HALF=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half HALF=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
-      run: BENCHMARK_LOG=gpt2_half_beam HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half_beam HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
    - name: Run OLMoE
      run: BENCHMARK_LOG=olmoe python3.11 examples/olmoe.py
    - name: Train MNIST
-      run: time PYTHONPATH=. TARGET_EVAL_ACC_PCT=96.0 python3.11 examples/beautiful_mnist.py
+      run: time PYTHONPATH=. TARGET_EVAL_ACC_PCT=96.0 python3.11 examples/beautiful_mnist.py | tee beautiful_mnist.txt

    # NOTE: this is failing in CI. it is not failing on my machine and I don't really have a way to debug it
    # the error is "RuntimeError: Internal Error (0000000e:Internal Error)"
    #- name: Run 10 CIFAR training steps
-    #  run: BENCHMARK_LOG=cifar_10steps JIT=1 ASSERT_MIN_STEP_TIME=3000 STEPS=10 python3.11 examples/hlb_cifar10.py
+    #  run: BENCHMARK_LOG=cifar_10steps JIT=1 ASSERT_MIN_STEP_TIME=3000 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar.txt
    #- name: Run 10 CIFAR training steps w HALF
-    #  run: BENCHMARK_LOG=cifar_10steps_half JIT=2 ASSERT_MIN_STEP_TIME=3000 STEPS=10 DEFAULT_FLOAT=HALF python3.11 examples/hlb_cifar10.py
+    #  run: BENCHMARK_LOG=cifar_10steps_half JIT=2 ASSERT_MIN_STEP_TIME=3000 STEPS=10 DEFAULT_FLOAT=HALF python3.11 examples/hlb_cifar10.py | tee train_cifar_half.txt

    #- name: Run 10 CIFAR training steps w BF16
-    #  run: STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3.11 examples/hlb_cifar10.py
+    #  run: STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3.11 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    # TODO: too slow
    # - name: Run 10 CIFAR training steps w winograd
-    #   run: BENCHMARK_LOG=cifar_10steps_wino JIT=1 ASSERT_MIN_STEP_TIME=150 WINO=1 STEPS=10 python3.11 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_wino JIT=1 ASSERT_MIN_STEP_TIME=150 WINO=1 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar_wino.txt
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (Mac)
        path: |
          onnx_inference_speed.csv
+          torch_speed.txt
+          llama_unjitted.txt
+          llama_jitted.txt
+          llama_beam.txt
+          llama_int8.txt
+          llama_nf4.txt
+          llama3_int8.txt
+          llama3_nf4.txt
+          llama_four_gpu.txt
+          gpt2_unjitted.txt
+          gpt2_jitted.txt
+          gpt2_half.txt
+          gpt2_half_beam.txt
+          matmul.txt
+          matmul_half.txt
+          matmul_bfloat16.txt
+          sd.txt
+          sd_no_fp16.txt
+          sdv2.txt
+          sdxl.txt
+          beautiful_mnist.txt
+          train_cifar.txt
+          train_cifar_half.txt
+          train_cifar_bf16.txt
+          train_cifar_wino.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3.11 process_replay.py

@@ -175,10 +170,6 @@ jobs:
      run: |
        echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV
        rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal
-    - name: Kill stale pids
-      run: |
-        PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
-        PYTHONPATH=. ./extra/hcq/hcq_smi.py nv kill_pids
    - name: UsbGPU boot time
      run: sudo -E PYTHONPATH=. DEBUG=2 AM_RESET=1 AMD=1 AMD_IFACE=USB time python3.11 test/test_tiny.py TestTiny.test_plus
    - name: UsbGPU tiny tests
@@ -224,7 +215,7 @@ jobs:
    - name: Run model inference benchmark
      run: NV=1 CAPTURE_PROCESS_REPLAY=0 NOCLANG=1 python3 test/external/external_model_benchmark.py
    - name: Test speed vs torch
-      run: NV=1 CAPTURE_PROCESS_REPLAY=0 HALF=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py
+      run: NV=1 CAPTURE_PROCESS_REPLAY=0 HALF=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py | tee torch_speed.txt
    - name: Test speed vs theoretical
      run: NV=1 IGNORE_BEAM_CACHE=1 CCACHE=0 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20
    - name: Test benchmark allreduce
@@ -235,58 +226,79 @@ jobs:
        NV=1 NV_PTX=1 ALLOW_TF32=1 python3 test/opt/test_tensor_cores.py
    - name: Run Tensor Core GEMM (CUDA)
      run: |
-        CUDA=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
-        CUDA=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
-        CUDA=1 SHOULD_USE_TC=1 ALLOW_TF32=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py
-        CUDA=1 SHOULD_USE_TC=1 FP8E4M3=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
+        CUDA=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul.txt
+        CUDA=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
+        CUDA=1 SHOULD_USE_TC=1 ALLOW_TF32=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_tf32.txt
+        CUDA=1 SHOULD_USE_TC=1 FP8E4M3=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_fp8.txt
    - name: Run Tensor Core GEMM (PTX)
-      run: NV=1 NV_PTX=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
+      run: NV=1 NV_PTX=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_ptx.txt
    - name: Run Tensor Core GEMM (NV)
-      run: NV=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
+      run: NV=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_nv.txt
    - name: Test NV=1
      run: DEBUG=2 NV=1 python -m pytest -rA test/test_tiny.py
    - name: Test CUDA=1
      run: DEBUG=2 CUDA=1 python -m pytest -rA test/test_tiny.py
    - name: Run Stable Diffusion
-      run: BENCHMARK_LOG=stable_diffusion NV=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion NV=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    # TODO: too slow
    # - name: Run SDXL
-    #   run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=2000 CAPTURE_PROCESS_REPLAY=0 NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing
+    #   run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=2000 CAPTURE_PROCESS_REPLAY=0 NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run LLaMA
      run: |
-        BENCHMARK_LOG=llama_nojit NV=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=llama NV=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=llama_nojit NV=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
+        BENCHMARK_LOG=llama NV=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt
    - name: Run LLaMA with BEAM
-      run: BENCHMARK_LOG=llama_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=llama_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt
    # - name: Run LLaMA 7B on 4 GPUs
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    # - name: Run LLaMA 7B on 6 GPUs
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_six_gpu.txt
    - name: Run LLaMA-3 8B BEAM
-      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_beam.txt
    - name: Run LLaMA-3 8B on 4 GPUs with BEAM
-      run: BENCHMARK_LOG=llama3_beam_4gpu NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam_4gpu NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_four_gpu.txt
    - name: Run quantized LLaMA3
-      run: BENCHMARK_LOG=llama3_fp8 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --temperature 0 --benchmark --quantize fp8
+      run: BENCHMARK_LOG=llama3_fp8 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --temperature 0 --benchmark --quantize fp8 | tee llama3_fp8.txt
    # - name: Run LLaMA-3 8B on 6 GPUs
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_six_gpu.txt
    # - name: Run LLaMA-2 70B
-    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 MAX_CONTEXT=256 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: NV=1 CAPTURE_PROCESS_REPLAY=0 MAX_CONTEXT=256 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_2_70B.txt
    - name: Run Mixtral 8x7B
-      run: time BENCHMARK_LOG=mixtral NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/mixtral.py --temperature 0 --count 10 --timing
+      run: time BENCHMARK_LOG=mixtral NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/mixtral.py --temperature 0 --count 10 --timing | tee mixtral.txt
    - name: Run GPT2
      run: |
-        BENCHMARK_LOG=gpt2_nojit NV=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=gpt2 NV=1 JIT=1 ASSERT_MIN_STEP_TIME=4 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=gpt2_nojit NV=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt
+        BENCHMARK_LOG=gpt2 NV=1 JIT=1 ASSERT_MIN_STEP_TIME=4 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt
    - name: Run GPT2 w HALF
-      run: BENCHMARK_LOG=gpt2_half NV=1 HALF=1 ASSERT_MIN_STEP_TIME=6 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half NV=1 HALF=1 ASSERT_MIN_STEP_TIME=6 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
-      run: BENCHMARK_LOG=gpt2_half_beam NV=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half_beam NV=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (NVIDIA)
        path: |
          onnx_inference_speed.csv
+          torch_speed.txt
+          matmul.txt
+          matmul_bfloat16.txt
+          matmul_tf32.txt
+          matmul_ptx.txt
+          matmul_nv.txt
+          sd.txt
+          sdxl.txt
+          llama_unjitted.txt
+          llama_jitted.txt
+          llama_beam.txt
+          llama3_beam.txt
+          llama3_four_gpu.txt
+          llama3_six_gpu.txt
+          llama3_fp8.txt
+          llama_2_70B.txt
+          mixtral.txt
+          gpt2_unjitted.txt
+          gpt2_jitted.txt
+          gpt2_half.txt
+          gpt2_half_beam.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -325,30 +337,44 @@ jobs:
    # - name: Fuzz Padded Tensor Core GEMM (PTX)
    #   run: NV=1 NV_PTX=1 M_START=12 M_STOP=20 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=28 K_STOP=36 K_STEP=1 HALF=1 TC_OPT=2 python3 ./extra/gemm/fuzz_matmul.py
    - name: HEVC Decode Benchmark
-      run: VALIDATE=1 MAX_FRAMES=100 JITBEAM=1 NV=1 PYTHONPATH=. python3 extra/hevc/decode.py
+      run: VALIDATE=1 MAX_FRAMES=100 NV=1 PYTHONPATH=. python3 extra/hevc/decode.py
    - name: Train MNIST
-      run: time PYTHONPATH=. NV=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py
+      run: time PYTHONPATH=. NV=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py | tee beautiful_mnist.txt
    - name: Run 10 CIFAR training steps
-      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 python3 examples/hlb_cifar10.py | tee train_cifar.txt
    - name: Run 10 CIFAR training steps w HALF
-      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=110 NV=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=110 NV=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_half.txt
    - name: Run 10 CIFAR training steps w BF16
-      run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=120 NV=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    # - name: Run 10 CIFAR training steps w winograd
-    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=350 NV=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=350 NV=1 CAPTURE_PROCESS_REPLAY=0 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_wino.txt
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_one_gpu.txt
    - name: Run full CIFAR training steps w 6 GPUS
-      run: time BENCHMARK_LOG=cifar_6gpu CAPTURE_PROCESS_REPLAY=0 NV=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar_6gpu CAPTURE_PROCESS_REPLAY=0 NV=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu.txt
    - name: Run MLPerf resnet eval on training data
      run: time BENCHMARK_LOG=resnet_eval NV=1 MODEL=resnet python3 examples/mlperf/model_eval.py
    - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-      run: BENCHMARK_LOG=resnet_10steps NV=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps NV=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet_one_gpu.txt
    - name: Run 10 MLPerf ResNet50 training steps (6 gpu)
-      run: BENCHMARK_LOG=resnet_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt
    - name: Run 10 MLPerf Bert training steps (6 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps_6gpu NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (NVIDIA Training)
+        path: |
+          beautiful_mnist.txt
+          train_cifar.txt
+          train_cifar_half.txt
+          train_cifar_bf16.txt
+          train_cifar_wino.txt
+          train_cifar_one_gpu.txt
+          train_cifar_six_gpu.txt
+          train_resnet.txt
+          train_resnet_one_gpu.txt
+          train_bert.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -363,12 +389,10 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Setcap to python
-      run: ./extra/amdpci/setup_python_cap.sh
-    - name: Remove amd modules
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
-    - name: Kill stale pids
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
+    - name: Remove amdgpu
+      run: sudo rmmod amdgpu || true
+    - name: Cleanup running AM processes
+      run: python extra/amdpci/am_smi.py --pids --kill
    #- name: Insert amdgpu
    #  run: sudo modprobe amdgpu
    - name: Symlink models and datasets
@@ -402,7 +426,7 @@ jobs:
    #- name: Test speed vs torch
    #  run: |
    #    python3 -c "import torch; print(torch.__version__)"
-    #    LD_PRELOAD="/opt/rocm/lib/libhsa-runtime64.so" HSA=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py
+    #    LD_PRELOAD="/opt/rocm/lib/libhsa-runtime64.so" HSA=1 BIG=2 TORCHCUDA=1 python3 test/speed/external_test_speed_v_torch.py | tee torch_speed.txt
    - name: Test speed vs theoretical
      run: AMD=1 IGNORE_BEAM_CACHE=1 CCACHE=0 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20
    - name: Test tensor cores AMD_LLVM=0
@@ -413,7 +437,7 @@ jobs:
    - name: Run Tensor Core GEMM (AMD)
      run: |
        AMD=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
-        AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py
+        AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_amd.txt
    - name: Test AMD=1
      run: DEBUG=2 AMD=1 python -m pytest -rA test/test_tiny.py
    #- name: Test HIP=1
@@ -428,39 +452,61 @@ jobs:
    - name: Test AM warm start time
      run: time AMD=1 python3 test/test_tiny.py TestTiny.test_plus
    - name: Run Stable Diffusion
-      run: BENCHMARK_LOG=stable_diffusion ASSERT_MIN_STEP_TIME=550 AMD=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion ASSERT_MIN_STEP_TIME=550 AMD=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    - name: Run SDXL
-      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=3200 CAPTURE_PROCESS_REPLAY=0 AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing
+      run: BENCHMARK_LOG=stable_diffusion_xl ASSERT_MIN_STEP_TIME=3200 CAPTURE_PROCESS_REPLAY=0 AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run LLaMA 7B
      run: |
-        BENCHMARK_LOG=llama_nojit AMD=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=llama AMD=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=llama_nojit AMD=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
+        BENCHMARK_LOG=llama AMD=1 JIT=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_jitted.txt
    - name: Run LLaMA 7B with BEAM
-      run: BENCHMARK_LOG=llama_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=llama_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_beam.txt
    # - name: Run LLaMA 7B on 4 GPUs
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    # - name: Run LLaMA 7B on 6 GPUs
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 1 --size 7B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_six_gpu.txt
    - name: Run LLaMA-3 8B BEAM
-      run: BENCHMARK_LOG=llama3_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_beam.txt
    - name: Run LLaMA-3 8B on 4 GPUs with BEAM
-      run: BENCHMARK_LOG=llama3_beam_4gpu AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam_4gpu AMD=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 4 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_four_gpu.txt
    # - name: Run LLaMA-3 8B on 6 GPUs
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama3.py --size 8B --shard 6 --model weights/LLaMA-3/8B-SF-DPO/ --benchmark --temperature 0 | tee llama3_six_gpu.txt
    #- name: Restore amdgpu
    #  run: sudo modprobe amdgpu
    # - name: Run LLaMA-2 70B
-    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing
+    #   run: AMD=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/llama.py --gen 2 --size 70B --shard 6 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_2_70B.txt
    - name: Run Mixtral 8x7B
-      run: time BENCHMARK_LOG=mixtral AMD=1 python3 examples/mixtral.py --temperature 0 --count 10 --timing
+      run: time BENCHMARK_LOG=mixtral AMD=1 python3 examples/mixtral.py --temperature 0 --count 10 --timing | tee mixtral.txt
    - name: Run GPT2
      run: |
-        BENCHMARK_LOG=gpt2_nojit AMD=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
-        BENCHMARK_LOG=gpt2 AMD=1 JIT=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing
+        BENCHMARK_LOG=gpt2_nojit AMD=1 JIT=0 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_unjitted.txt
+        BENCHMARK_LOG=gpt2 AMD=1 JIT=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --prompt "Hello." --count 10 --temperature 0 --timing | tee gpt2_jitted.txt
    - name: Run GPT2 w HALF
-      run: BENCHMARK_LOG=gpt2_half AMD=1 HALF=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half AMD=1 HALF=1 ASSERT_MIN_STEP_TIME=5 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
-      run: BENCHMARK_LOG=gpt2_half_beam AMD=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing
+      run: BENCHMARK_LOG=gpt2_half_beam AMD=1 HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AMD)
+        path: |
+          onnx_inference_speed.csv
+          torch_speed.txt
+          llama_unjitted.txt
+          llama_jitted.txt
+          llama_beam.txt
+          llama3_beam.txt
+          llama3_four_gpu.txt
+          llama3_six_gpu.txt
+          llama_2_70B.txt
+          gpt2_unjitted.txt
+          gpt2_jitted.txt
+          gpt2_half.txt
+          gpt2_half_beam.txt
+          matmul.txt
+          matmul_amd.txt
+          sd.txt
+          sdxl.txt
+          mixtral.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -475,12 +521,10 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Setcap to python
-      run: ./extra/amdpci/setup_python_cap.sh
-    - name: Remove amd modules
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
-    - name: Kill stale pids
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
+    - name: Remove amdgpu
+      run: sudo rmmod amdgpu || true
+    - name: Cleanup running AM processes
+      run: python extra/amdpci/am_smi.py --pids --kill
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -499,20 +543,31 @@ jobs:
    - name: reset process replay
      run: test/external/process_replay/reset.py
    - name: Train MNIST
-      run: time PYTHONPATH=. AMD=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py
+      run: time PYTHONPATH=. AMD=1 TARGET_EVAL_ACC_PCT=96.0 python3 examples/beautiful_mnist.py | tee beautiful_mnist.txt
    - name: Run 10 CIFAR training steps
-      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 python3 examples/hlb_cifar10.py | tee train_cifar.txt
    - name: Run 10 CIFAR training steps w HALF
-      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+      run: BENCHMARK_LOG=cifar_10steps_half ASSERT_MIN_STEP_TIME=200 AMD=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_half.txt
    # - name: Run 10 CIFAR training steps w BF16
-    #   run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=288 AMD=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_bf16 ASSERT_MIN_STEP_TIME=288 AMD=1 STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    # TODO: too slow
    # - name: Run 10 CIFAR training steps w winograd
-    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=66 AMD=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py
+    #   run: BENCHMARK_LOG=cifar_10steps_half_wino ASSERT_MIN_STEP_TIME=66 AMD=1 WINO=1 STEPS=10 DEFAULT_FLOAT=HALF python3 examples/hlb_cifar10.py | tee train_cifar_wino.txt
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_one_gpu.txt
    - name: Run full CIFAR training steps w 6 GPUS
-      run: time BENCHMARK_LOG=cifar_6gpu AMD=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar_6gpu AMD=1 DEFAULT_FLOAT=HALF STEPS=350 BS=1536 GPUS=6 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee train_cifar_six_gpu.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AMD Training)
+        path: |
+          beautiful_mnist.txt
+          train_cifar.txt
+          train_cifar_half.txt
+          train_cifar_bf16.txt
+          train_cifar_wino.txt
+          train_cifar_one_gpu.txt
+          train_cifar_six_gpu.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -527,12 +582,10 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Setcap to python
-      run: ./extra/amdpci/setup_python_cap.sh
-    - name: Remove amd modules
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
-    - name: Kill stale pids
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
+    - name: Remove amdgpu
+      run: sudo rmmod amdgpu || true
+    - name: Cleanup running AM processes
+      run: python extra/amdpci/am_smi.py --pids --kill
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -553,12 +606,19 @@ jobs:
    - name: Run MLPerf resnet eval
      run: time BENCHMARK_LOG=resnet_eval AMD=1 MODEL=resnet python3 examples/mlperf/model_eval.py
    - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-      run: BENCHMARK_LOG=resnet_10steps AMD=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps AMD=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet_one_gpu.txt
    - name: Run 10 MLPerf ResNet50 training steps (6 gpu)
-      run: BENCHMARK_LOG=resnet_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt
    - name: Run 10 MLPerf Bert training steps (6 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps_6gpu AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=72 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AMD MLPerf)
+        path: |
+          train_resnet.txt
+          train_resnet_one_gpu.txt
+          train_bert.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -581,21 +641,19 @@ jobs:
    - name: reset process replay
      run: test/external/process_replay/reset.py
    - name: openpilot compile3 0.10.0 driving_policy
-      run: BENCHMARK_LOG=openpilot_0_10_0_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=3 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.10.0/selfdrive/modeld/models/driving_policy.onnx
+      run: BENCHMARK_LOG=openpilot_0_10_0_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=4 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.10.0/selfdrive/modeld/models/driving_policy.onnx
    - name: openpilot compile3 0.10.0 dmonitoring
      run: BENCHMARK_LOG=openpilot_0_10_0_dmonitoring PYTHONPATH="." ASSERT_MIN_STEP_TIME=11 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.10.0/selfdrive/modeld/models/dmonitoring_model.onnx
    - name: DEBUG=2 openpilot compile3 0.10.1 driving_vision
      run: PYTHONPATH="." DEBUG=2 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: DEBUG=2 IMAGE=1 openpilot compile3 0.10.1 driving_vision
      run: PYTHONPATH="." DEBUG=2 DEV=QCOM FLOAT16=1 IMAGE=1 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
-    - name: IMAGE=1 openpilot compile3 0.10.1 driving_vision
-      run: BENCHMARK_LOG=image_1_openpilot_0_10_1_vision PYTHONPATH="." DEV=QCOM FLOAT16=1 IMAGE=1 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: openpilot compile3 0.10.1 driving_vision
      run: BENCHMARK_LOG=openpilot_0_10_1_vision PYTHONPATH="." ASSERT_MIN_STEP_TIME=17 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: openpilot compile3 0.10.1 driving_policy
-      run: BENCHMARK_LOG=openpilot_0_10_1_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=3 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_policy.onnx
+      run: BENCHMARK_LOG=openpilot_0_10_1_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=4 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_policy.onnx
    - name: openpilot compile3 0.10.1 dmonitoring
-      run: BENCHMARK_LOG=openpilot_0_10_1_dmonitoring PYTHONPATH="." ASSERT_MIN_STEP_TIME=11 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/dmonitoring_model.onnx
+      run: BENCHMARK_LOG=openpilot_0_10_1_dmonitoring PYTHONPATH="." ASSERT_MIN_STEP_TIME=10 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/dmonitoring_model.onnx
    - name: benchmark MobileNetV2 on DSP
      run: |
        # generate quantized weights
@@ -618,12 +676,10 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Setcap to python
-      run: ./extra/amdpci/setup_python_cap.sh
    - name: Remove amd modules
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
+      run: ./extra/hcq/hcq_smi.py amd rmmod
    - name: Kill stale pids
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
+      run: ./extra/hcq/hcq_smi.py amd kill_pids
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -652,7 +708,7 @@ jobs:
    #     AMD=1 AMD_LLVM=1 python3 test/test_linearizer.py test/opt/test_tensor_cores.py
    #     AMD=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
    - name: Run Tensor Core GEMM (AMD)
-      run: AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py
+      run: AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee am_matmul_amd.txt
    - name: Test AMD=1
      run: DEBUG=2 AMD=1 python -m pytest -rA test/test_tiny.py
    - name: Test DISK copy time
@@ -662,12 +718,20 @@ jobs:
        AMD=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyDefaulttoCPUJit
        AMD=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyCPUtoDefaultJit
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar AMD=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee am_train_cifar_one_gpu.txt
    # - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-    #   run: BENCHMARK_LOG=resnet_10steps AMD=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+    #   run: BENCHMARK_LOG=resnet_10steps AMD=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee am_train_resnet_one_gpu.txt
    - name: Run 10 MLPerf Bert training steps (1 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee am_train_bert_one_gpu.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (AM Driver)
+        path: |
+          am_matmul_amd.txt
+          am_train_cifar_one_gpu.txt
+          am_train_resnet_one_gpu.txt
+          am_train_bert_one_gpu.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py

@@ -682,12 +746,10 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Setcap to python
-      run: ./extra/amdpci/setup_python_cap.sh
    - name: Remove nv modules
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py nv rmmod
+      run: ./extra/hcq/hcq_smi.py nv rmmod
    - name: Kill stale pids
-      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py nv kill_pids
+      run: ./extra/hcq/hcq_smi.py nv kill_pids
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -716,13 +778,21 @@ jobs:
        NV=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyDefaulttoCPUJit
        NV=1 GRAPH_ONE_KERNEL=1 PYTHONPATH=. NSZ=8192 python3 test/speed/external_test_copy_speed.py TestCopySpeed.testCopyCPUtoDefaultJit
    - name: Test LLAMA-3
-      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --benchmark --temperature 0
+      run: BENCHMARK_LOG=llama3_beam NV=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3 examples/llama3.py --size 8B --benchmark --temperature 0 | tee nv_llama3_beam.txt
    - name: Run full CIFAR training w 1 GPU
-      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py
+      run: time BENCHMARK_LOG=cifar NV=1 DEFAULT_FLOAT=HALF STEPS=1000 TARGET_EVAL_ACC_PCT=93.0 python3 examples/hlb_cifar10.py | tee nv_train_cifar_one_gpu.txt
    - name: Run 10 MLPerf ResNet50 training steps (1 gpu)
-      run: BENCHMARK_LOG=resnet_10steps NV=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=resnet_10steps NV=1 MNISTMOCK=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=256 GPUS=1 MODEL=resnet python3 examples/mlperf/model_train.py | tee nv_train_resnet_one_gpu.txt
    - name: Run 10 MLPerf Bert training steps (1 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: BENCHMARK_LOG=bert_10steps NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: BENCHMARK_LOG=bert_10steps NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee nv_train_bert_one_gpu.txt
+    - uses: actions/upload-artifact@v4
+      with:
+        name: Speed (NV Driver)
+        path: |
+          nv_llama3_beam.txt
+          nv_train_cifar_one_gpu.txt
+          nv_train_resnet_one_gpu.txt
+          nv_train_bert_one_gpu.txt
    - name: Run process replay tests
      run: cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && PYTHONPATH=. python3 process_replay.py
@@ -5,7 +5,7 @@ env:
  CAPTURE_PROCESS_REPLAY: 1
  GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}
  PYTHONPATH: ${{ github.workspace }}
-  CHECK_OOB: 1
+  IGNORE_OOB: 0

 on:
  push:
@@ -26,7 +26,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: llvm-speed
-        deps: testing_unit
+        deps: testing_minimal
        llvm: 'true'
    - name: Speed Test
      run: CPU=1 CPU_LLVM=1 python3 test/speed/external_test_speed_v_torch.py
@@ -38,7 +38,7 @@ jobs:
    runs-on: ubuntu-22.04
    timeout-minutes: 10
    env:
-      CHECK_OOB: 0
+      IGNORE_OOB: 1
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -98,7 +98,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: torch-backend-pillow-torchvision-et-pt
-        deps: testing_unit
+        deps: testing_minimal
        pydeps: "pillow torchvision expecttest"
        llvm: 'true'
    - name: Install ninja
@@ -110,7 +110,7 @@ jobs:
    - name: Test ResNet-18
      run: DEBUG=2 python3 extra/torch_backend/example.py
    - name: custom tests
-      run: python3 -m pytest -n auto extra/torch_backend/test.py --durations=20
+      run: python3 extra/torch_backend/test.py
    - name: Test one op in torch tests
      run: DEBUG=2 python3 extra/torch_backend/torch_tests.py TestTinyBackendPRIVATEUSE1.test_unary_log_tiny_float32
    - name: Test Ops with TINY_BACKEND
@@ -134,7 +134,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: torch-backend-pillow-torchvision-et-pt
-        deps: testing_unit
+        deps: testing_minimal
        llvm: 'true'
    - name: Install ninja
      run: |
@@ -156,7 +156,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: be-minimal
-        deps: testing_unit
+        deps: testing_minimal
    - name: Test dtype with Python emulator
      run: DEBUG=1 PYTHON=1 python3 -m pytest -n=auto test/test_dtype.py test/test_dtype_alu.py
    - name: Test ops with Python emulator
@@ -218,6 +218,7 @@ jobs:
    runs-on: ubuntu-latest
    timeout-minutes: 10

+    # TODO: run the pre-commit hook to replace a lot of this
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -229,20 +230,19 @@ jobs:
        deps: linting
    - name: Lint bad-indentation and trailing-whitespace with pylint
      run: python -m pylint --disable=all -e W0311 -e C0303 --jobs=0 --indent-string='  ' --recursive=y .
-    - name: Run pre-commit linting hooks
-      run: SKIP=tiny,tests,example pre-commit run --all-files
-    - name: Lint additional files with ruff
+    - name: Lint with ruff
      run: |
+        pip3 install --upgrade --force-reinstall ruff==0.14.10
+        python3 -m ruff check .
        python3 -m ruff check examples/mlperf/ --ignore E501
        python3 -m ruff check extra/thunder/tiny/ --ignore E501 --ignore F841 --ignore E722
        python3 -m ruff check extra/torch_backend/backend.py
-    - name: Run mypy with lineprecision report
+    - name: Run mypy
      run: |
-        python -m mypy --lineprecision-report .
-        grep -v autogen lineprecision.txt | awk 'NR>2 {lines+=$2; precise+=$3; imprecise+=$4; any+=$5; empty+=$6} END {t=lines-empty; printf "TOTAL: %d lines, %d precise (%.1f%%), %d imprecise (%.1f%%), %d any (%.1f%%)\n", t, precise, 100*precise/t, imprecise, 100*imprecise/t, any, 100*any/t}'
+        python -m mypy --strict-equality --lineprecision-report .
        cat lineprecision.txt
    - name: Run TYPED=1
-      run: CHECK_OOB=0 DEV=CPU TYPED=1 python test/test_tiny.py
+      run: TYPED=1 python -c "import tinygrad"

  unittest:
    name: Unit Tests
@@ -255,13 +255,9 @@ jobs:
    - name: Setup Environment
      uses: ./.github/actions/setup-tinygrad
      with:
-        key: unittest-13
-        pydeps: "pillow ftfy regex pre-commit"
+        key: unittest-12
+        pydeps: "pillow numpy ftfy regex"
        deps: testing_unit
-        llvm: 'true'
-        amd: 'true'
-    - name: Run pre-commit test hooks
-      run: SKIP=ruff,mypy pre-commit run --all-files
    - name: Check Device.DEFAULT
      run: python -c "from tinygrad import Device; assert Device.DEFAULT == 'CPU', Device.DEFAULT"
    - name: Run unit tests
@@ -314,7 +310,7 @@ jobs:
        deps: testing_unit
        python-version: '3.14'
    - name: Test SPEC=2
-      run: SPEC=2 pytest --maxfail=10 -n auto --durations=30 --ignore=test/models --ignore test/test_custom_kernel.py --ignore test/unit/test_hashing.py --ignore test/unit/test_autogen.py --timeout 60 -k "not test_setitem_big" --splits 2 --group ${{ matrix.group }}
+      run: SPEC=2 pytest --maxfail=10 -n auto --durations=30 --ignore=test/models --ignore test/test_custom_kernel.py --ignore test/unit/test_hashing.py --timeout 60 -k "not test_setitem_big" --splits 2 --group ${{ matrix.group }}

  fuzzing:
    name: Fuzzing
@@ -348,7 +344,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: gpu-image
-          deps: testing_unit
+          deps: testing_minimal
          opencl: 'true'
      - name: Test CL IMAGE=2 ops
        run: |
@@ -369,7 +365,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: gen-dataset
-          deps: testing
+          deps: testing_minimal
          opencl: 'true'
      - name: Generate Dataset
        run: CL=1 extra/optimization/generate_dataset.sh
@@ -424,7 +420,7 @@ jobs:
        with:
          key: onnxoptc
          deps: testing
-          python-version: '3.12'
+          python-version: '3.11'
          llvm: 'true'
      - name: Test ONNX (CPU)
        run: CPU=1 CPU_LLVM=0 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
@@ -452,7 +448,7 @@ jobs:
          key: onnxoptl
          deps: testing
          pydeps: "tensorflow==2.19"
-          python-version: '3.12'
+          python-version: '3.11'
          opencl: 'true'
      - name: Test ONNX (CL)
        run: CL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
@@ -478,7 +474,7 @@ jobs:
    runs-on: ubuntu-24.04
    timeout-minutes: 15
    env:
-      CHECK_OOB: 0
+      IGNORE_OOB: 1
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -526,7 +522,7 @@ jobs:
      with:
        key: metal
        deps: testing
-        python-version: '3.12'
+        python-version: '3.11'
    - name: Test models (Metal)
      run: METAL=1 python -m pytest -n=auto test/models --durations=20
    - name: Test LLaMA compile speed
@@ -545,7 +541,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: devectorize-minimal
-        deps: testing_unit
+        deps: testing_minimal
        pydeps: "pillow"
        llvm: "true"
    - name: Test LLVM=1 DEVECTORIZE=0
@@ -566,8 +562,8 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: dsp-minimal
-        deps: testing_unit
-        pydeps: "onnx==1.18.0 onnxruntime"
+        deps: testing_minimal
+        pydeps: "onnx==1.18.0 onnxruntime pillow"
        llvm: "true"
    - name: Set up Docker Buildx
      uses: docker/setup-buildx-action@v3
@@ -600,8 +596,8 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: webgpu-minimal
-        deps: testing_unit
-        python-version: '3.12'
+        deps: testing_minimal
+        python-version: '3.11'
        webgpu: 'true'
    - name: Check Device.DEFAULT (WEBGPU) and print some source
      run: |
@@ -609,7 +605,9 @@ jobs:
        WEBGPU=1 DEBUG=4 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
    - name: Run selected webgpu tests
      run: |
-          WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
+          WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit \
+          --ignore=test/test_copy_speed.py --ignore=test/test_rearrange_einops.py \
+          --ignore=test/test_fuzz_shape_ops.py --durations=20
    - name: Run process replay tests
      uses: ./.github/actions/process-replay

@@ -634,7 +632,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_unit
+          deps: testing_minimal
          amd: 'true'
          llvm: ${{ matrix.backend == 'amdllvm' && 'true' }}
      - name: Check Device.DEFAULT and print some source
@@ -652,23 +650,16 @@ jobs:
        run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20
      - name: Run TestOps.test_add with SQTT
        run: |
-          VIZ=-2 DEBUG=5 python3 test/test_ops.py TestOps.test_add
+          VIZ=1 PMC=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add
+          VIZ=1 SQTT=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add
          extra/sqtt/rgptool.py create "/tmp/profile.pkl.$USER" -o /tmp/gpu0.rgp
-      - name: Run AMD emulated mmapeak on NULL backend
-        env:
-          AMD: 0
-        run: PYTHONPATH=. NULL=1 EMULATE=AMD python extra/mmapeak/mmapeak.py
      - name: Run process replay tests
        uses: ./.github/actions/process-replay

  testamdasm:
    name: AMD ASM IDE
    runs-on: ubuntu-24.04
-    timeout-minutes: 20
-    env:
-      AMD: 1
-      PYTHON_REMU: 1
-      MOCKGPU: 1
+    timeout-minutes: 10
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -676,13 +667,8 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: rdna3-emu
-          deps: testing_unit
+          deps: testing_minimal
          amd: 'true'
-          python-version: '3.14'
-      - name: Verify AMD autogen is up to date
-        run: |
-          python -m extra.assembly.amd.generate
-          git diff --exit-code extra/assembly/amd/autogen/
      - name: Install LLVM 21
        run: |
          wget -qO- https://apt.llvm.org/llvm-snapshot.gpg.key | sudo tee /etc/apt/trusted.gpg.d/apt.llvm.org.asc
@@ -691,21 +677,31 @@ jobs:
          sudo apt-get install llvm-21 llvm-21-tools cloc
      - name: RDNA3 Line Count
        run: cloc --by-file extra/assembly/amd/*.py
-      - name: Install rocprof-trace-decoder
-        run: sudo PYTHONPATH="." ./extra/sqtt/install_sqtt_decoder.py
      - name: Run RDNA3 emulator tests
-        run: AMD_LLVM=0 python -m pytest -n=auto extra/assembly/amd/ --durations 20
+        run: python -m pytest -n=auto extra/assembly/amd/ --durations 20
      - name: Run RDNA3 emulator tests (AMD_LLVM=1)
        run: AMD_LLVM=1 python -m pytest -n=auto extra/assembly/amd/ --durations 20
      - name: Run RDNA3 dtype tests
-        run: AMD_LLVM=0 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py --durations 20
+        run: AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py
      - name: Run RDNA3 dtype tests (AMD_LLVM=1)
-        run: AMD_LLVM=1 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py --durations 20
-      # TODO: run all once emulator is faster
-      - name: Run RDNA3 ops tests
-        run: SKIP_SLOW_TEST=1 AMD_LLVM=0 pytest -n=auto test/test_ops.py -k "test_sparse_categorical_crossentropy or test_tril or test_nonzero or test_softmax_argmax" --durations 20
-      - name: Run RDNA4 emulator tests
-        run: MOCKGPU_ARCH=rdna4 python -m pytest test/test_tiny.py -v --durations 20
+        run: AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py
+
+  testamdautogen:
+    name: AMD autogen
+    runs-on: ubuntu-24.04
+    timeout-minutes: 10
+    steps:
+      - name: Checkout Code
+        uses: actions/checkout@v4
+      - name: Setup Environment
+        uses: ./.github/actions/setup-tinygrad
+        with:
+          key: rdna3-autogen
+          pydeps: "pdfplumber"
+      - name: Verify AMD autogen is up to date
+        run: |
+          python -m extra.assembly.amd.pdf --arch all
+          git diff --exit-code extra/assembly/amd/autogen/

  testnvidia:
    strategy:
@@ -726,7 +722,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_unit
+          deps: testing_minimal
          cuda: 'true'
          ocelot: 'true'
      - name: Set env
@@ -738,8 +734,6 @@ jobs:
      - name: Run pytest (cuda)
        # skip multitensor because it's slow
        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore test/test_gc.py --ignore test/test_multitensor.py --durations=20
-      - name: Run TestOps.test_add with PMA
-        run: VIZ=-1 PMA=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add
      - name: Run process replay tests
        uses: ./.github/actions/process-replay

@@ -759,7 +753,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_unit
+          deps: testing_minimal
          opencl: ${{ matrix.backend == 'opencl' && 'true' }}
          llvm: ${{ matrix.backend == 'llvm' || matrix.backend == 'lvp' }}
          mesa: ${{ matrix.backend == 'lvp' && 'true' }}
@@ -790,7 +784,7 @@ jobs:
      with:
        key: metal
        deps: testing
-        python-version: '3.12'
+        python-version: '3.11'
        amd: 'true'
        cuda: 'true'
        ocelot: 'true'
@@ -888,7 +882,8 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: macos-${{ matrix.backend }}-minimal
-          deps: testing_unit
+          deps: testing_minimal
+          pydeps: "capstone"
          llvm: ${{ matrix.backend == 'llvm' || matrix.backend == 'lvp' }}
          mesa: ${{ matrix.backend == 'lvp' && 'true' }}
      - name: Set env
@@ -955,7 +950,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: compile-${{ matrix.backend }}
-          deps: testing_unit
+          deps: testing_minimal
          mesa: ${{ (matrix.backend == 'ir3' || matrix.backend == 'nak') && 'true' }}
          python-version: '3.14'
      - name: Set env
@@ -58,11 +58,10 @@ weights
 *.lprof
 comgr_*
 *.pkl
-!extra/sqtt/examples/**/*.pkl
 site/
 profile_stats
 *.log
 target
 .mypy_cache
 mutants
-.mutmut-cache
+.mutmut-cache
@@ -16,7 +16,7 @@ repos:
        pass_filenames: false
      - id: mypy
        name: mypy
-        entry: python3 -m mypy
+        entry: python3 -m mypy tinygrad/ --strict-equality
        language: system
        always_run: true
        pass_filenames: false
@@ -28,7 +28,7 @@ repos:
        pass_filenames: false
      - id: tests
        name: comprehensive test suite
-        entry: env OMP_NUM_THREADS=1 SKIP_SLOW_TEST=1 PYTHONPATH="." python3 -m pytest -n=6 test/test_ops.py test/test_schedule.py test/unit/test_assign.py test/test_tensor.py test/test_jit.py test/unit/test_schedule_cache.py test/unit/test_pattern_matcher.py test/unit/test_uop_symbolic.py test/unit/test_helpers.py
+        entry: env OMP_NUM_THREADS=1 SKIP_SLOW_TEST=1 PYTHONPATH="." python3 -m pytest -n=6 test/test_ops.py test/test_schedule.py test/test_assign.py test/test_tensor.py test/test_jit.py test/unit/test_schedule_cache.py test/unit/test_pattern_matcher.py test/unit/test_uop_symbolic.py test/unit/test_helpers.py
        language: system
        always_run: true
        pass_filenames: false
@@ -192,12 +192,9 @@ When optimizing tinygrad internals:

 9. **Avoid creating intermediate objects in hot paths** - For example, `any(x.op in ops for x in self.backward_slice)` is faster than `any(x.op in ops for x in {self:None, **self.backward_slice})` because it avoids dict creation.

-## Pattern Matching Analysis
+## Pattern Matching Profiling

-**Use the right tool:**
-
- `TRACK_MATCH_STATS=2` - **Profiling**: identify expensive patterns
- `VIZ=-1` - **Inspection**: see all transformations, what every match pattern does, the before/after diffs
+Use `TRACK_MATCH_STATS=2` to identify expensive patterns:

 ```bash
 TRACK_MATCH_STATS=2 PYTHONPATH="." python3 test/external/external_benchmark_schedule.py
@@ -212,14 +209,6 @@ Key patterns to watch (from ResNet50 benchmark):

 Patterns with 0% match rate are workload-specific overhead. They may be useful in other workloads, so don't remove them without understanding their purpose.

-```bash
-# Save the trace
-VIZ=-1 python test/test_tiny.py TestTiny.test_gemm
-
-# Explore it
-./extra/viz/cli.py --help
-```
-
 ## AMD Performance Counter Profiling

 Set VIZ to `-2` to save performance counters traces for the AMD backend.
@@ -70,7 +70,7 @@ AMD backend supports several interfaces for communicating with devices:

 * `KFD`: uses the amdgpu driver
 * `PCI`: uses the [AM driver](developer/am.md)
-* `USB`: USB3 interface for asm24xx chips.
+* `USB`: USB3 interafce for asm24xx chips.

 You can force an interface by setting `AMD_IFACE` to one of these values. In the case of `AMD_IFACE=PCI`, this may unbind your GPU from the amdgpu driver.

@@ -6,7 +6,6 @@ Elementwise ops operate on a per element basis. They don't change the shape of t
 ::: tinygrad.Tensor.neg
 ::: tinygrad.Tensor.log
 ::: tinygrad.Tensor.log2
-::: tinygrad.Tensor.log10
 ::: tinygrad.Tensor.exp
 ::: tinygrad.Tensor.exp2
 ::: tinygrad.Tensor.sqrt
@@ -88,8 +87,4 @@ Elementwise ops operate on a per element basis. They don't change the shape of t
 ::: tinygrad.Tensor.float
 ::: tinygrad.Tensor.half
 ::: tinygrad.Tensor.int
-::: tinygrad.Tensor.bool
-::: tinygrad.Tensor.bfloat16
-::: tinygrad.Tensor.double
-::: tinygrad.Tensor.long
-::: tinygrad.Tensor.short
+::: tinygrad.Tensor.bool
@@ -27,6 +27,5 @@
 ::: tinygrad.Tensor.flatten
 ::: tinygrad.Tensor.unflatten
 ::: tinygrad.Tensor.diag
-::: tinygrad.Tensor.diagonal
 ::: tinygrad.Tensor.roll
 ::: tinygrad.Tensor.rearrange
@@ -7,7 +7,6 @@
 ::: tinygrad.Tensor.any
 ::: tinygrad.Tensor.all
 ::: tinygrad.Tensor.isclose
-::: tinygrad.Tensor.allclose
 ::: tinygrad.Tensor.mean
 ::: tinygrad.Tensor.var
 ::: tinygrad.Tensor.var_mean
@@ -31,9 +30,7 @@
 ::: tinygrad.Tensor.matmul
 ::: tinygrad.Tensor.einsum
 ::: tinygrad.Tensor.cumsum
-::: tinygrad.Tensor.cumprod
 ::: tinygrad.Tensor.cummax
-::: tinygrad.Tensor.cummin
 ::: tinygrad.Tensor.triu
 ::: tinygrad.Tensor.tril
 ::: tinygrad.Tensor.interpolate
@@ -41,9 +38,7 @@
 ::: tinygrad.Tensor.scatter_reduce
 ::: tinygrad.Tensor.masked_select
 ::: tinygrad.Tensor.masked_fill
-::: tinygrad.Tensor.nonzero
 ::: tinygrad.Tensor.sort
-::: tinygrad.Tensor.argsort
 ::: tinygrad.Tensor.topk
 ::: tinygrad.Tensor.multinomial

@@ -61,8 +56,3 @@
 ::: tinygrad.Tensor.sparse_categorical_crossentropy
 ::: tinygrad.Tensor.cross_entropy
 ::: tinygrad.Tensor.nll_loss
-
-## Linear Algebra
-
-::: tinygrad.Tensor.qr
-::: tinygrad.Tensor.svd
@@ -1,196 +0,0 @@
-from tinygrad import Tensor, dtypes, Context, getenv, UOp, fetch
-from tinygrad.uop.ops import Ops, PatternMatcher, UPat
-from tinygrad.uop.symbolic import symbolic
-from tinygrad.codegen import Renderer
-from tinygrad.codegen.opt import Opt, OptOps
-
-# ************************* implementation of the problem ************************
-
-def myhash(a: Tensor) -> Tensor:
-  a = (a + 0x7ED55D16) + (a << 12)
-  a = (a ^ 0xC761C23C) ^ (a >> 19)
-  a = (a + 0x165667B1) + (a << 5)
-  a = (a + 0xD3A2646C) ^ (a << 9)
-  a = (a + 0xFD7046C5) + (a << 3)
-  a = (a ^ 0xB55A4F09) ^ (a >> 16)
-  return a
-
-def select_with_where_tree(values: Tensor, relative_idx: Tensor) -> Tensor:
-  n = values.shape[0]
-  if n == 1: return values[0].expand(relative_idx.shape)
-
-  mid = n // 2
-  left = select_with_where_tree(values[:mid], relative_idx)
-  right = select_with_where_tree(values[mid:], relative_idx - mid)
-
-  go_left = relative_idx < mid
-  return go_left.where(left, right)
-
-def tree_traversal(forest: Tensor, val: Tensor, height: int, rounds: int, where_tree_threshold=3) -> Tensor:
-  # All walkers start at idx=0
-  idx = Tensor.zeros(val.shape, device=val.device, dtype=dtypes.uint32)
-
-  for r in range(rounds):
-    level = r % (height + 1)
-    level_start = (1 << level) - 1
-    level_size = 1 << level
-
-    if level == 0:
-      # At root (level 0), all walkers are at idx=0
-      # No gather needed, just broadcast the root value
-      node_val = forest[0].expand(val.shape)
-      idx = idx * 0  # Reset to 0
-    elif level <= where_tree_threshold:
-      # Small level: use where-tree
-      level_values = forest[level_start : level_start + level_size]
-      relative_idx = (idx - level_start)
-      node_val = select_with_where_tree(level_values, relative_idx)
-    else:
-      # Large level: use gather
-      node_val = forest.gather(0, idx)
-
-    val = myhash(val ^ node_val)
-    idx = (idx << 1) + (1 + (val & 1))
-
-    # No wrap check needed! At round 10 (level becomes 0), we reset idx above.
-
-  return val.contiguous(arg=(Opt(OptOps.UPCAST, 0, 8),))
-
-# ************************* renderer for VLIW machine *************************
-
-def loop_unrolling(sink:UOp):
-  rng = [x for x in sink.toposort() if x.op is Ops.RANGE]
-  if len(rng) == 0: return None
-  print(f"unrolling loop with size {rng[0].vmax+1}")
-  unrolled_sinks = [sink.substitute({rng[0]:rng[0].const_like(i)}).src[0] for i in range(rng[0].vmax+1)]
-  return UOp.sink(*unrolled_sinks, arg=sink.arg)
-
-global_addrs = []
-vliw_prepare = PatternMatcher([
-  # loop unrolling (should be a part of tinygrad)
-  (UPat(Ops.SINK, name="sink"), loop_unrolling),
-  # cast is fake
-  (UPat(Ops.CAST, name="c"), lambda c: c.src[0]),
-  # rewrites to hardcode the addresses in memory
-  (UPat(Ops.DEFINE_GLOBAL, name="dg"), lambda dg: UOp.const(dtypes.uint, global_addrs[dg.arg])),
-  # INDEX is just plus
-  (UPat(Ops.INDEX, name="i"), lambda i: i.src[0]+i.src[1]),
-])+symbolic
-
-class VLIWRenderer(Renderer):
-  has_local = False  # TODO: this should be the default / cleaned up
-  # this says this backend supports MULACC + more. decompositions uses this
-  code_for_op: dict = {Ops.MULACC: None, Ops.ADD: "+", Ops.MUL: "*",
-                       Ops.XOR: "^", Ops.AND: "&", Ops.OR: "|",
-                       Ops.SHL: "<<", Ops.SHR: ">>", Ops.CMPLT: "<"}
-  # this matcher runs while still in graph form
-  pre_matcher = vliw_prepare
-
-  def render(self, uops:list[UOp]):
-
-    # TODO: this is a minimal renderer. for low cycle count, make it good
-    # to get speed, you need to add VLIW packing
-    # to get under 1536 regs, you need to add a register allocator
-    # we left the fun parts to you
-
-    print(f"rendering with {len(uops)} uops")
-    reg, inst = 0, []
-    r: dict[UOp, int] = {}
-    for u in uops:
-      assert u.dtype.count in (1,8), "dtype count must be 1 or 8"
-
-      # dumb register allocator
-      if u.op not in {Ops.STORE, Ops.SINK, Ops.GEP}:
-        r[u] = reg
-        reg += u.dtype.count
-
-      # render UOps to instructions
-      match u.op:
-        case Ops.SINK:
-          inst.append({"flow": [("halt",)]})
-        case Ops.CONST:
-          inst.append({"load": [("const", r[u], u.arg)]})
-        case Ops.GEP:
-          # a GEP is just an alias to a special register in the vector
-          r[u] = r[u.src[0]] + u.arg[0]
-        case Ops.VECTORIZE:
-          if all(s == u.src[0] for s in u.src):
-            # if all sources are the same, we can broadcast
-            inst.append({"valu": [("vbroadcast", r[u], r[u.src[0]])]})
-          else:
-            # this is a copy into a contiguous chunk of registers
-            inst.extend({"flow": [("add_imm", r[u]+i, r[s], 0)]} for i,s in enumerate(u.src) if r[s] != r[u]+i)
-        case Ops.LOAD:
-          op = "vload" if u.dtype.count > 1 else "load"
-          inst.append({"load": [(op, r[u], r[u.src[0]])]})
-        case Ops.STORE:
-          op = "vstore" if u.src[1].dtype.count > 1 else "store"
-          inst.append({"store": [(op, r[u.src[0]], r[u.src[1]])]})
-        case Ops.MULACC:
-          assert u.dtype.count == 8
-          inst.append({"valu": [("multiply_add", r[u], r[u.src[0]], r[u.src[1]], r[u.src[2]])]})
-        case Ops.WHERE:
-          assert u.dtype.count == 8
-          inst.append({"flow": [("vselect", r[u], r[u.src[0]], r[u.src[1]], r[u.src[2]])]})
-        case _ if u.op in self.code_for_op:
-          cat = "valu" if u.dtype.count > 1 else "alu"
-          inst.append({cat: [(self.code_for_op[u.op], r[u], r[u.src[0]], r[u.src[1]])]})
-        case _:
-          raise NotImplementedError(f"unhandled op {u.op}")
-    return repr(inst)
-
-# ************************* test and render *************************
-
-import sys, types
-PROBLEM_URL = "https://raw.githubusercontent.com/anthropics/original_performance_takehome/refs/heads/main/tests/frozen_problem.py"
-sys.modules["problem"] = problem = types.ModuleType("problem")
-exec(fetch(PROBLEM_URL).read_text(), problem.__dict__)
-
-if __name__ == "__main__":
-  batch_size = getenv("BS", 256)
-  height = 10
-  rounds = getenv("ROUNDS", 16)
-
-  # build problem
-  tree = problem.Tree.generate(height)
-  inp = problem.Input.generate(tree, batch_size, rounds)
-  mem = problem.build_mem_image(tree, inp)
-  global_addrs.extend([mem[6], mem[6], mem[4]])  # output, input, forest
-
-  # *** verify the kernel in tinygrad compared to reference ***
-
-  forest_t = Tensor(tree.values, dtype=dtypes.uint32)
-  val_t = Tensor(inp.values, dtype=dtypes.uint32)
-
-  if getenv("VERIFY", 1):
-    # verify on normal tinygrad device
-    with Context(PCONTIG=2):
-      out = tree_traversal(forest_t, val_t, height, rounds)
-      val_out = out.tolist()
-    problem.reference_kernel(tree, inp)
-    assert val_out == inp.values
-    print("verification passed")
-
-  # *** render to device ***
-
-  from tinygrad.codegen import get_program
-  with Context(PCONTIG=2, DEVECTORIZE=2, SPEC=0):
-    out = tree_traversal(forest_t, val_t, height, rounds)
-    sink = out.schedule()[-1].ast
-    prg = get_program(sink, VLIWRenderer())
-
-  # *** run on Machine and compare ***
-
-  # NOTE: the scratch size needs to be reduced to 1536 when you have a register allocator
-  src = eval(prg.src)
-  max_regs = max(t[1] for instr in src for v in instr.values() for t in v if len(t) > 1) + 8
-  print(f"{max_regs:5d} regs used" + ("" if max_regs <= 1536 else "       <-- WARNING: TOO MANY REGISTERS, MUST BE <= 1536"))
-  machine = problem.Machine(mem, src, problem.DebugInfo(scratch_map={}), n_cores=1, trace=False, scratch_size=max_regs)
-  machine.run()
-  print(f"ran for {machine.cycle:5d} cycles" + ("" if machine.cycle <= 1363 else "  <-- EVEN CLAUDE GOT 1363"))
-
-  # compare to reference
-  ref_mem = mem.copy()
-  for _ in problem.reference_kernel2(ref_mem, {}): pass
-  assert machine.mem[mem[6]:mem[6]+mem[2]] == ref_mem[mem[6]:mem[6]+mem[2]]
-  print("compare passed!")
@@ -1,79 +0,0 @@
-from typing import Optional
-from tinygrad import Tensor
-from tinygrad.dtype import DTypeLike, dtypes
-import math
-
-# rewritten from numpy
-def rfftfreq(n: int, d: float = 1.0, device=None) -> Tensor:
-  val = 1.0 / (n * d)
-  N = n // 2 + 1
-  results = Tensor.arange(N, device=device)
-  return results * val
-
-# just like in librosa
-def fft_frequencies(sr: float, n_fft: int) -> Tensor:
-  return rfftfreq(n=n_fft, d=1.0 / sr)
-
-def hz_to_mel(freq: Tensor) -> Tensor:
-  # linear part
-  f_min = 0.0
-  f_sp = 200.0 / 3
-  mels = (freq - f_min) / f_sp
-
-  # log-scale part
-  min_log_hz = 1000.0  # beginning of log region (Hz)
-  mask = freq >= min_log_hz
-  return mask.where(((min_log_hz - f_min) / f_sp) + (freq / min_log_hz).log() / (math.log(6.4) / 27.0), mels)
-
-def mel_to_hz(mels: Tensor) -> Tensor:
-  # linear scale
-  f_min = 0.0
-  f_sp = 200.0 / 3
-  freqs = f_min + f_sp * mels
-
-  # nonlinear scale
-  min_log_hz = 1000.0  # beginning of log region (Hz)
-  min_log_mel = (min_log_hz - f_min) / f_sp  # same (Mels)
-  logstep = math.log(6.4) / 27.0  # step size for log region
-
-  log_t = mels >= min_log_mel
-  freqs = log_t.where(min_log_hz * ((logstep * (mels - min_log_mel)).exp()), freqs)
-  return freqs
-
-def mel_frequencies(n_mels: int = 128, *, fmin: float = 0.0, fmax: float = 11025.0) -> Tensor:
-  # center freqs of mel bands - uniformly spaced between limits
-  min_max_mel = hz_to_mel(Tensor([fmin, fmax]))
-
-  mels = Tensor.linspace(min_max_mel[0], min_max_mel[1], n_mels)
-  hz = mel_to_hz(mels)
-  return hz
-
-def mel(
-  *,
-  sr: float,
-  n_fft: int,
-  n_mels: int = 128,
-  fmin: float = 0.0,
-  fmax: Optional[float] = None,
-  dtype: DTypeLike = dtypes.default_float,
-) -> Tensor:
-  if fmax is None:
-    fmax = float(sr) / 2
-
-  n_mels = int(n_mels)
-
-  fftfreqs = fft_frequencies(sr=sr, n_fft=n_fft)  # center freqs of each FFT bin
-  mel_f = mel_frequencies(n_mels + 2, fmin=fmin, fmax=fmax)  # center freqs of mel bands
-
-  fdiff = mel_f[1:] - mel_f[:-1]
-  ramps = mel_f[None].T.expand(-1, fftfreqs.shape[-1]) - fftfreqs
-
-  lower = -ramps[:n_mels] / fdiff[:n_mels][None].T
-  upper = ramps[2 : n_mels + 2] / fdiff[1 : n_mels + 1][None].T
-  weights = lower.minimum(upper).maximum(0)
-
-  # Slaney-style mel is scaled to be approx constant energy per channel
-  enorm = 2.0 / (mel_f[2 : n_mels + 2] - mel_f[:n_mels])
-  weights *= enorm[:, None]
-
-  return weights
@@ -213,13 +213,12 @@ class InterleavedDataset:
    self.queues[queue_index].queue.extend(load_file(file))

 # Reference: https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/run_pretraining.py, Line 394
-def batch_load_train_bert(BS:int, seed:int|None=None):
+def batch_load_train_bert(BS:int):
  from extra.datasets.wikipedia import get_wiki_train_files
-  rng = random.Random(seed)
  fs = sorted(get_wiki_train_files())
  train_files = []
  while fs: # TF shuffle
-    rng.shuffle(fs)
+    random.shuffle(fs)
    train_files.append(fs.pop(0))

  cycle_length = min(getenv("NUM_CPU_THREADS", min(os.cpu_count(), 8)), len(train_files))
@@ -219,18 +219,7 @@ def get_mlperf_bert_model():
  config = get_mlperf_bert_config()
  if getenv("DISABLE_DROPOUT", 0):
    config["hidden_dropout_prob"] = config["attention_probs_dropout_prob"] = 0.0
-  model = BertForPretraining(**config)
-  if getenv("FP8_TRAIN"):
-    from extra.fp8.fp8_linear import convert_to_float8_training
-    def module_filter_fn(mod, fqn):
-      if isinstance(mod, LinearBert):
-        skip_layers = [] if (ln:=config["num_hidden_layers"]) <= 2 else ["bert.encoder.layer.0.", f"bert.encoder.layer.{ln-1}"]
-        if mod.weight.shape[-1] >= 1024 and "encoder" in fqn and not any(name in fqn for name in skip_layers):
-          print(f"replacing linear with fp8: {fqn} {mod.weight.shape}")
-          return True
-      return False
-    convert_to_float8_training(model, module_filter_fn)
-  return model
+  return BertForPretraining(**config)

 def get_fake_data_bert(BS:int):
  return {
@@ -3,7 +3,7 @@ from pathlib import Path
 import multiprocessing

 from tinygrad import Device, GlobalCounters, Tensor, TinyJit, dtypes
-from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, Profiling, profile_marker
+from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, Profiling
 from tinygrad.nn.state import get_parameters, get_state_dict, load_state_dict, safe_load, safe_save
 from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, Adam, AdamW

@@ -1008,7 +1008,6 @@ def train_bert():
  config["DISABLE_DROPOUT"] = getenv("DISABLE_DROPOUT", 0)
  config["TRAIN_BEAM"]    = TRAIN_BEAM = getenv("TRAIN_BEAM", BEAM.value)
  config["EVAL_BEAM"]     = EVAL_BEAM  = getenv("EVAL_BEAM", BEAM.value)
-  config["FP8_TRAIN"]     = getenv("FP8_TRAIN", 0)

  Tensor.manual_seed(seed)  # seed for weight initialization

@@ -1086,7 +1085,7 @@ def train_bert():
  if RUNMLPERF:
    # only load real data with RUNMLPERF
    eval_it = iter(batch_load_val_bert(EVAL_BS))
-    train_it = iter(tqdm(batch_load_train_bert(BS, seed=seed), total=train_steps, disable=BENCHMARK))
+    train_it = iter(tqdm(batch_load_train_bert(BS), total=train_steps, disable=BENCHMARK))
    for _ in range(start_step): next(train_it) # Fast forward
  else:
    # repeat fake data
@@ -1148,7 +1147,7 @@ def train_bert():

        device_str = parameters[0].device if isinstance(parameters[0].device, str) else f"{parameters[0].device[0]} * {len(parameters[0].device)}"
        loss = loss.item()
-        if not getenv("FP8_TRAIN"): assert not math.isnan(loss)
+        assert not math.isnan(loss)
        lr = lr.item()

      cl = time.perf_counter()
@@ -1161,7 +1160,7 @@ def train_bert():
      if WANDB:
        wandb.log({"lr": lr, "train/loss": loss, "train/global_norm": global_norm.item(), "train/step_time": cl - st,
                    "train/python_time": pt - st, "train/data_time": dt - pt, "train/cl_time": cl - dt,
-                    "train/mem":GlobalCounters.mem_used / 1e9, "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": (i+1)*GBS})
+                    "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": (i+1)*GBS})

      train_data, next_data = next_data, None
      i += 1
@@ -1286,23 +1285,17 @@ def train_llama3():
  from examples.llama3 import MODEL_PARAMS
  from examples.mlperf.lr_schedulers import CosineAnnealingLRWithWarmup

-  BENCHMARK = getenv("BENCHMARK")
-
  config = {}
  BASEDIR            = config["BASEDIR"]                = Path(getenv("BASEDIR", "/raid/datasets/c4/"))
  BS                 = config["BS"]                     = getenv("BS", 16)
  grad_acc           = config["GRADIENT_ACC_STEPS"]     = getenv("GRADIENT_ACC_STEPS", 1)
+  assert grad_acc == 1, f"{grad_acc=} is not supported"
  GBS                = config["GLOBAL_BATCH_SIZE"]      = BS * grad_acc
  SEED               = config["SEED"]                   = getenv("SEED", 5760)
  SEQLEN             = config["SEQLEN"]                 = getenv("SEQLEN", 8192)
  TRAIN_ON_VAL       = config["TRAIN_ON_VAL"]           = getenv("TRAIN_ON_VAL", 0)
  SMALL              = config["SMALL"]                  = getenv("SMALL", 0)
  SAMPLES            = config["SAMPLES"]                = getenv("SAMPLES", 5_760 if TRAIN_ON_VAL else 1_200_000 * 1152)
-  EVAL_SAMPLES       = config["EVAL_SAMPLES"]           = getenv("EVAL_SAMPLES", 5760 if not SMALL else 1024)
-  MAX_STEPS          = config["MAX_STEPS"]              = getenv("MAX_STEPS", math.ceil(1_200_000 * 1152 / GBS))
-  WARMUP_STEPS       = config["WARMUP_STEPS"]           = getenv("WARMUP_STEPS", math.ceil(8000 * 1152 / GBS))
-  LR                 = config["LR"]                     = getenv("LR", 8e-5 * GBS / 1152)
-  END_LR             = config["END_LR"]                 = getenv("END_LR", 8e-7)
  EVAL_FREQ          = config["EVAL_FREQ"]              = getenv("EVAL_FREQ", 46080)
  EVAL_BS            = config["EVAL_BS"]                = getenv("EVAL_BS", 16)
  EVAL_TARGET        = config["EVAL_TARGET"]            = getenv("EVAL_TARGET", 5.6)
@@ -1316,12 +1309,10 @@ def train_llama3():
  opt_adamw_weight_decay = 0.1

  opt_gradient_clip_norm = 1.0
-  opt_learning_rate_warmup_steps = WARMUP_STEPS
-  opt_learning_rate_decay_steps = MAX_STEPS - opt_learning_rate_warmup_steps
-  opt_base_learning_rate = LR
-  opt_end_learning_rate = END_LR
-
-  Tensor.manual_seed(SEED)  # seed for weight initialization
+  opt_learning_rate_warmup_steps = getenv("WARMUP_STEPS", math.ceil(8000 * 1152 / GBS))
+  opt_learning_rate_decay_steps = getenv("MAX_STEPS", math.ceil(1_200_000 * 1152 / GBS)) - opt_learning_rate_warmup_steps
+  opt_base_learning_rate = getenv("LR", 8e-5 * GBS / 1152)  # NOTE: cannot change for benchmark
+  opt_end_learning_rate = getenv("END_LR", 8e-7)

  # ** init wandb **
  WANDB = getenv("WANDB")
@@ -1334,8 +1325,6 @@ def train_llama3():
  # vocab_size from the mixtral tokenizer
  if not SMALL: model_params |= {"vocab_size": 32000}
  if (llama_layers:=getenv("LLAMA_LAYERS")) != 0: model_params['n_layers'] = llama_layers
-  print(f"model parameters: {model_params}")
-
  model = Transformer(**model_params, max_context=SEQLEN, jit=False, disable_kv_cache=True)
  params = get_parameters(model)
  # weights are all bfloat16 for now
@@ -1371,12 +1360,6 @@ def train_llama3():

  optim = AdamW(get_parameters(model), lr=0.0,
                b1=opt_adamw_beta_1, b2=opt_adamw_beta_2, eps=opt_adamw_epsilon, weight_decay=opt_adamw_weight_decay)
-
-  # init grads
-  for p in optim.params:
-    p.grad = p.zeros_like().contiguous().realize()
-  grads = [p.grad for p in optim.params]
-
  scheduler = CosineAnnealingLRWithWarmup(optim, opt_base_learning_rate, opt_end_learning_rate, opt_learning_rate_warmup_steps, opt_learning_rate_decay_steps)

  if resume_ckpt := getenv("RESUME_CKPT"):
@@ -1389,7 +1372,9 @@ def train_llama3():
    load_state_dict(scheduler, safe_load(fn), realize=False)

  @TinyJit
-  def minibatch(tokens:Tensor):
+  @Tensor.train()
+  def train_step(model, tokens:Tensor):
+    optim.zero_grad()
    if (DP := getenv("DP", 1)) > 1:
      device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP))
      tokens = tokens.shard(device, 0)
@@ -1399,40 +1384,27 @@ def train_llama3():
    logits:Tensor = model(tokens[:, :-1], start_pos=0, temperature=math.nan)
    loss = logits.sparse_categorical_crossentropy(tokens[:, 1:])
    loss.backward()
-    assert all(p.grad is g for p,g in zip(optim.params, grads))
-    Tensor.realize(loss, *grads)
-    return loss
-
-  @TinyJit
-  def optim_step():
-    for p in optim.params:
-      p.grad.assign(p.grad / grad_acc)
-
    # L2 norm grad clip
    # https://github.com/NVIDIA/NeMo/blob/3368c3fc0b4a186ab33a1d68a504315100c0b2a6/nemo/collections/nlp/modules/common/megatron/clip_grads.py#L57
    # https://docs.pytorch.org/docs/stable/generated/torch.nn.utils.clip_grad_norm_.html
    if not getenv("DISABLE_GRAD_CLIP_NORM"):
      total_norm = Tensor(0.0, dtype=dtypes.float32, device=optim.params[0].device)
-      for g in grads:
-        total_norm += g.float().square().sum()
-      total_norm = total_norm.sqrt().contiguous().realize()
-      for g in grads:
-        g.assign((g * (opt_gradient_clip_norm / (total_norm + 1e-6)).clamp(max_=1.0)).cast(g.dtype)).realize()
+      for p in optim.params:
+        total_norm += p.grad.float().square().sum()
+      total_norm = total_norm.sqrt().contiguous()
+      for p in optim.params:
+        p.grad = p.grad * (opt_gradient_clip_norm / (total_norm + 1e-6)).clamp(max_=1.0)

    optim.step()
    scheduler.step()

-    for g in grads:
-      g.assign(g.zeros_like().contiguous()).realize()
-
    lr = optim.lr
-    Tensor.realize(lr, *grads)
-
-    return lr
+    loss.realize(lr)
+    return loss, lr

  @TinyJit
  @Tensor.train(False)
-  def eval_step(tokens:Tensor):
+  def eval_step(model, tokens:Tensor):
    if (DP := getenv("DP", 1)) > 1:
      device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP))
      tokens = tokens.shard(device, 0)
@@ -1459,73 +1431,39 @@ def train_llama3():
    eval_dataset = None
  else:
    from examples.mlperf.dataloader import get_llama3_dataset
-    eval_dataset = get_llama3_dataset(EVAL_SAMPLES, SEQLEN, BASEDIR, val=True, small=bool(SMALL))
+    eval_dataset = get_llama3_dataset(5760, SEQLEN, BASEDIR, val=True, small=bool(SMALL))

  def get_eval_iter():
    if eval_dataset is None:
-      return fake_data(EVAL_BS, EVAL_SAMPLES)
+      return fake_data(EVAL_BS, 5760)
    from examples.mlperf.dataloader import iterate_llama3_dataset
    return iterate_llama3_dataset(eval_dataset, EVAL_BS)

-  num_params = sum(p.numel() for p in params) - model_params["vocab_size"]*model_params["dim"]
-  train_iter = get_train_iter()
+  iter = get_train_iter()
  i, sequences_seen = resume_ckpt, 0
-  step_times = []
-  while i < MAX_STEPS:
+  for tokens in tqdm(iter, total=SAMPLES//GBS):
    GlobalCounters.reset()
    if getenv("TRAIN", 1):
-      profile_marker(f"train @ {i}")
-      st = time.perf_counter()
-
-      stopped = False
-      for _ in range(grad_acc):
-        ist = time.perf_counter()
-        try: tokens = next(train_iter)
-        except StopIteration:
-          stopped = True
-          break
-        dt = time.perf_counter()
-        loss = minibatch(tokens)
-      if stopped: break
-
-      gt = time.perf_counter()
-      lr = optim_step()
-      ot = time.perf_counter()
-
+      t = time.perf_counter()
+      loss, lr = train_step(model, tokens)
      loss = loss.float().item()
      lr = lr.item()

-      et = time.perf_counter()
-      step_time = et - st
-      gbs_time = gt - st
-      optim_time = ot - gt
-      data_time = dt - ist
-      dev_time = step_time - data_time * grad_acc
-      if BENCHMARK: step_times.append(step_time)
-
      i += 1
-      sequences_seen += GBS
+      sequences_seen += tokens.shape[0]

+      sec = time.perf_counter()-t
      mem_gb = GlobalCounters.mem_used / 1e9
-      gflops = GlobalCounters.global_ops / 1e9 / dev_time
-      mfu = ((6 * num_params * SEQLEN * GBS) / (dev_time * max(getenv("DP", 1), getenv("MP", 1)) * 2.3e15)) * 100
+      gflops = GlobalCounters.global_ops / 1e9 / sec
      tqdm.write(
-          f"{i:5} {step_time:.3f} s step, {gbs_time:.3f} s gbs, {optim_time:.3f} s optim, {data_time:.3f} s data, {loss:.4f} loss, " \
-          f"{lr:.12f} LR, {mem_gb:.2f} GB used, {gflops:9.2f} GFLOPS, {mfu:5.2f}% MFU")
+        f"{i:5} {sec:.2f} s run, {loss:.4f} loss, {lr:.12f} LR, {mem_gb:.2f} GB used, {gflops:9.2f} GFLOPS")
+
+      if (fname:=getenv("LOSS_FILE", "")):
+        with open(fname, "a") as f:
+          f.write(f"{i} {loss:.4f} {lr:.12f} {mem_gb:.2f}\n")

      if WANDB:
-        wandb.log({
-          "lr": lr, "train/loss": loss,
-          "train/step_time": step_time,
-          "train/gbs_time": gbs_time,
-          "train/optim_time": optim_time,
-          "train/dev_time": dev_time,
-          "train/data_time": data_time,
-          "train/mem": mem_gb,
-          "train/GFLOPS": gflops,
-          "train/MFU": mfu,
-          "train/sequences_seen": sequences_seen
-        })
+        wandb.log({"lr": lr, "train/loss": loss, "train/step_time": sec, "train/GFLOPS": gflops, "train/sequences_seen": sequences_seen})

      if (ckpt_freq := getenv("CKPT")) and (i % ckpt_freq == 0 and (i != 1 or ckpt_freq == 1)):
        tqdm.write("saving checkpoint")
@@ -1537,29 +1475,16 @@ def train_llama3():
        fn = f"{ckpt_dir}/llama3_{i}_optim.safe"
        safe_save(get_state_dict(scheduler), fn)

-      if i == BENCHMARK:
-        median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2]
-        estimated_total_minutes = int(median_step_time * (SAMPLES // GBS) / 60)
-        print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m")
-        print(f"epoch global_ops: {GlobalCounters.global_ops:_}, "
-              f"epoch global_mem: {GlobalCounters.global_mem:_}")
-
-    if (sequences_seen % EVAL_FREQ == 0 and (i != 1 or EVAL_FREQ == 1)) or (BENCHMARK and i == BENCHMARK):
-      if EVAL_BS == 0: return
+    if sequences_seen % EVAL_FREQ == 0 and (i != 1 or EVAL_FREQ == 1):
      tqdm.write(f"evaluating after {sequences_seen} sequences")
-      profile_marker(f"eval @ {i}")

      # run eval
      eval_losses = []
      eval_iter = get_eval_iter()
      tqdm.write(f"evaluating {5760//EVAL_BS} batches of {EVAL_BS} sequences")

-      for j,tokens in tqdm(enumerate(eval_iter), total=EVAL_SAMPLES//EVAL_BS):
-        eval_losses += eval_step(tokens).tolist()
-
-        if BENCHMARK and (j+1) == min(BENCHMARK, EVAL_SAMPLES//EVAL_BS):
-          return
-
+      for tokens in tqdm(eval_iter, total=5760//EVAL_BS):
+        eval_losses += eval_step(model, tokens).tolist()
      log_perplexity = Tensor(eval_losses).mean().float().item()

      tqdm.write(f"eval log perplexity: {log_perplexity:.4f}")
@@ -1645,7 +1570,7 @@ def train_stable_diffusion():
    loss, out_lr = loss.detach().to("CPU"), optimizer.lr.to("CPU")
    Tensor.realize(loss, out_lr)
    return loss, out_lr
-
+    
  # checkpointing takes ~9 minutes without this, and ~1 minute with this
  @TinyJit
  def ckpt_to_cpu():
@@ -1684,7 +1609,7 @@ def train_stable_diffusion():
    if i == 3:
      for _ in range(3): ckpt_to_cpu() # do this at the beginning of run to prevent OOM surprises when checkpointing
      print("BEAM COMPLETE", flush=True) # allows wrapper script to detect BEAM search completion and retry if it failed
-
+      
    total_train_time = time.perf_counter() - train_start_time
    if WANDB:
      wandb.log({"train/loss": loss_item, "train/lr": lr_item, "train/loop_time_prev": loop_time, "train/dl_time": dl_time, "train/step": i,
@@ -4,7 +4,7 @@ export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" GPUS=1 BS=128 EVAL_BS=128

-export CHECK_OOB=0
+export IGNORE_OOB=1

 export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
@@ -5,7 +5,7 @@ export MODEL="bert"
 export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -8,7 +8,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -11,7 +11,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -1,20 +0,0 @@
-#!/bin/bash
-
-export PYTHONPATH="." AMD=1 DEBUG=0 JIT=1 FLASH_ATTENTION=1
-export MODEL="bert"
-export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
-
-# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54
-export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
-export TRAIN_STEPS=3900
-
-export CHECK_OOB=0
-export REWRITE_STACK_LIMIT=5000000
-
-export BEAM=0 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
-export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
-export BASEDIR="/raid/datasets/wiki"
-
-export WANDB=1 PARALLEL=0
-
-RUNMLPERF=1 python3 examples/mlperf/model_train.py
@@ -1,24 +0,0 @@
-#!/bin/bash
-
-export PYTHONPATH="." AMD=1
-export MODEL="bert"
-export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
-
-# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54
-export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
-export TRAIN_STEPS=3900
-
-export CHECK_OOB=0
-export REWRITE_STACK_LIMIT=5000000
-
-export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
-export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
-export BASEDIR="/raid/datasets/wiki"
-export BEAM_TIMEOUT_SEC=15
-export FP8_TRAIN=1
-# search
-IGNORE_BEAM_CACHE=1 BENCHMARK=10 BERT_LAYERS=2 RUNMLPERF=0 python3 examples/mlperf/model_train.py
-
-export WANDB=1 PARALLEL=0
-
-RUNMLPERF=1 python3 examples/mlperf/model_train.py
@@ -11,7 +11,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=5000000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." NV=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=72 EVAL_BS=72

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." NV=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=72 EVAL_BS=72

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -7,7 +7,7 @@ export MODEL="bert"
 export SUBMISSION_PLATFORM="tinybox_green"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=72 EVAL_BS=72

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -7,7 +7,7 @@ export MODEL="bert"
 export SUBMISSION_PLATFORM="tinybox_red"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export CHECK_OOB=0
+export IGNORE_OOB=1
 export REWRITE_STACK_LIMIT=500000

 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -1,32 +0,0 @@
-#!/usr/bin/env bash
-
-export PYTHONPATH="."
-export DEV=${DEV:-AMD}
-export CHECK_OOB=0
-export REWRITE_STACK_LIMIT=5000000 HCQDEV_WAIT_TIMEOUT_MS=240000
-
-export DEBUG=${DEBUG:-2}
-export FLASH_ATTENTION=${FLASH_ATTENTION:-1}
-export ALL2ALL=${ALL2ALL:-1}
-
-export DEFAULT_FLOAT="bfloat16" OPTIM_DTYPE="bfloat16"
-export DP=8 BS=8 EVAL_BS=8 GRADIENT_ACC_STEPS=2
-export GBS=$((BS * GRADIENT_ACC_STEPS))
-
-export MODEL="llama3"
-export BASEDIR="/raid/datasets/c4-8b/"
-export SMALL=1
-export LLAMA3_SIZE=${LLAMA3_SIZE:-"8B"}
-export EVAL_TARGET=3.3 EVAL_FREQ=12288
-export LR="2.5e-4" END_LR="2.5e-5" WARMUP_SAMPLES=256 MAX_STEPS=1200000
-export WARMUP_STEPS=$((WARMUP_SAMPLES / GBS))
-export SAMPLES=$((MAX_STEPS * GBS))
-
-export SEED=5760
-
-export JITBEAM=3
-export BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
-
-export FAKEDATA=1 BENCHMARK=10 LLAMA_LAYERS=2
-
-python3 examples/mlperf/model_train.py
@@ -1,33 +0,0 @@
-#!/usr/bin/env bash
-
-export PYTHONPATH="."
-export DEV=${DEV:-AMD}
-export EMULATE="AMD_CDNA4"
-export CHECK_OOB=0
-export REWRITE_STACK_LIMIT=5000000 HCQDEV_WAIT_TIMEOUT_MS=240000
-
-export DEBUG=${DEBUG:-0}
-export FLASH_ATTENTION=${FLASH_ATTENTION:-1}
-export ALL2ALL=${ALL2ALL:-1}
-export USE_ATOMICS=${USE_ATOMICS:-1}
-export ASM_GEMM=${ASM_GEMM:-1}
-
-export DEFAULT_FLOAT="bfloat16" OPTIM_DTYPE="bfloat16"
-export DP=${DP:-8} BS=${BS:-8} EVAL_BS=${EVAL_BS:-8} GRADIENT_ACC_STEPS=${GRADIENT_ACC_STEPS:-2}
-export GBS=$((BS * GRADIENT_ACC_STEPS))
-
-export MODEL="llama3"
-export BASEDIR="/raid/datasets/c4-8b/"
-export SMALL=1
-export LLAMA3_SIZE=${LLAMA3_SIZE:-"8B"}
-export EVAL_TARGET=3.3 EVAL_FREQ=12288
-export LR="2.5e-4" END_LR="2.5e-5" WARMUP_SAMPLES=256 MAX_STEPS=1200000
-export WARMUP_STEPS=$((WARMUP_SAMPLES / GBS))
-export SAMPLES=$((MAX_STEPS * GBS))
-
-export SEED=${SEED:-5760}
-
-export JITBEAM=${JITBEAM:-3}
-export BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
-
-python3 examples/mlperf/model_train.py
@@ -1,9 +0,0 @@
-#!/bin/bash
-export BENCHMARK=5
-export EVAL_BS=0
-export FAKEDATA=1
-export HIP_VISIBLE_DEVICES=""
-export DEV=NULL
-export JITBEAM=0
-export LLAMA_LAYERS=${LLAMA_LAYERS:-"2"}
-time examples/mlperf/training_submission_v6.0/tinycorp/benchmarks/llama8b/implementations/tinybox_8xMI350X/dev_run.sh
@@ -7,7 +7,7 @@ if __name__ == "__main__":
  with open(fetch(sys.argv[1]), "rb") as f:
    run_onnx_jit = pickle.load(f)
  input_name = run_onnx_jit.captured.expected_names[0]
-  device = run_onnx_jit.captured.expected_input_info[0][-1]
+  device = run_onnx_jit.captured.expected_st_vars_dtype_device[0][-1]
  print(f"input goes into {input_name=} on {device=}")
  hit = 0
  for i,(img,y) in enumerate(imagenet_dataloader(cnt=getenv("CNT", 100))):
@@ -93,7 +93,7 @@ if __name__ == "__main__":
    forward: Any = None

  sub_steps = [
-    Step(name = "textModel", input = [Tensor.randint(1, 77, low=0, high=49408, dtype=dtypes.int32)], forward = model.cond_stage_model.transformer.text_model),
+    Step(name = "textModel", input = [Tensor.randn(1, 77)], forward = model.cond_stage_model.transformer.text_model),
    Step(name = "diffusor", input = [Tensor.randn(1, 77, 768), Tensor.randn(1, 77, 768), Tensor.randn(1,4,64,64), Tensor.rand(1), Tensor.randn(1), Tensor.randn(1), Tensor.randn(1)], forward = model),
    Step(name = "decoder", input = [Tensor.randn(1,4,64,64)], forward = model.decode),
    Step(name = "f16tof32", input = [Tensor.randn(2097120, dtype=dtypes.uint32)], forward = u32_to_f16)
@@ -7,7 +7,6 @@ from tinygrad import Tensor, TinyJit, Variable, nn, dtypes
 from tinygrad.nn.state import torch_load, load_state_dict
 from tinygrad.helpers import getenv, fetch

-from examples.audio_helpers import mel
 import numpy as np
 import librosa

@@ -160,7 +159,7 @@ def prep_audio(waveforms: List[np.ndarray], batch_size: int, truncate=False) ->

  stft = librosa.stft(waveforms, n_fft=N_FFT, hop_length=HOP_LENGTH, window='hann', dtype=np.csingle)
  magnitudes = np.absolute(stft[..., :-1]) ** 2
-  mel_spec = mel(sr=RATE, n_fft=N_FFT, n_mels=N_MELS).numpy() @ magnitudes
+  mel_spec = librosa.filters.mel(sr=RATE, n_fft=N_FFT, n_mels=N_MELS) @ magnitudes

  log_spec = np.log10(np.clip(mel_spec, 1e-10, None))
  log_spec = np.maximum(log_spec, log_spec.max((1,2), keepdims=True) - 8.0)
@@ -153,7 +153,8 @@ class SMICtx:
    tables = {}
    for dev in self.devs:
      match dev.ip_ver[am.MP1_HWIP]:
-        case (13,0,6)|(13,0,12): table_t = dev.smu.smu_mod.MetricsTableX_t
+        case (13,0,6): table_t = dev.smu.smu_mod.MetricsTableX_t
+        case (13,0,12): table_t = dev.smu.smu_mod.MetricsTableV2_t
        case _: table_t = dev.smu.smu_mod.SmuMetricsExternal_t
      tables[dev] = dev.smu.read_table(table_t, dev.smu.smu_mod.SMU_TABLE_SMU_METRICS) if dev.pci_state == "D0" else None
    return tables
@@ -164,17 +165,17 @@ class SMICtx:

  def get_gfx_activity(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return max(0, min(100, self._smuq10_round(metrics.SocketGfxBusy)))
+      case (13,0,6): return max(0, min(100, self._smuq10_round(metrics.SocketGfxBusy)))
      case _: return metrics.SmuMetrics.AverageGfxActivity

  def get_mem_activity(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return max(0, min(100, self._smuq10_round(metrics.DramBandwidthUtilization)))
+      case (13,0,6): return max(0, min(100, self._smuq10_round(metrics.DramBandwidthUtilization)))
      case _: return metrics.SmuMetrics.AverageUclkActivity

  def get_temps(self, dev, metrics, compact=False):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12):
+      case (13,0,6):
        temps = {
          "Hotspot": self._smuq10_round(metrics.MaxSocketTemperature),
          "HBM": self._smuq10_round(metrics.MaxHbmTemperature),
@@ -190,7 +191,7 @@ class SMICtx:

  def get_voltage(self, dev, metrics, compact=False):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return {}
+      case (13,0,6): return {}
      case _:
        voltage_keys = [(k, name) for k, name in dev.smu.smu_mod.SVI_PLANE_e.items()
                        if k < dev.smu.smu_mod.SVI_PLANE_COUNT and metrics.SmuMetrics.AvgVoltage[k] != 0]
@@ -204,33 +205,33 @@ class SMICtx:
  def get_gfx_freq(self, dev, metrics):
    if metrics is None: return 0
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.GfxclkFrequency[0])
+      case (13,0,6): return self._smuq10_round(metrics.GfxclkFrequency[0])
      case _:
        return metrics.SmuMetrics.AverageGfxclkFrequencyPostDs if self.get_gfx_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
               metrics.SmuMetrics.AverageGfxclkFrequencyPreDs

  def get_mem_freq(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.UclkFrequency)
+      case (13,0,6): return self._smuq10_round(metrics.UclkFrequency)
      case _:
        return metrics.SmuMetrics.AverageMemclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
               metrics.SmuMetrics.AverageMemclkFrequencyPreDs

  def get_fckl_freq(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.FclkFrequency)
+      case (13,0,6): return self._smuq10_round(metrics.FclkFrequency)
      case _:
        return metrics.SmuMetrics.AverageFclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
               metrics.SmuMetrics.AverageFclkFrequencyPreDs

  def get_fan_rpm_pwm(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return None, None
+      case (13,0,6): return None, None
      case _: return metrics.SmuMetrics.AvgFanRpm, metrics.SmuMetrics.AvgFanPwm

  def get_power(self, dev, metrics):
    match dev.ip_ver[am.MP1_HWIP]:
-      case (13,0,6)|(13,0,12): return self._smuq10_round(metrics.SocketPower), self._smuq10_round(metrics.MaxSocketPowerLimit)
+      case (13,0,6): return self._smuq10_round(metrics.SocketPower), self._smuq10_round(metrics.MaxSocketPowerLimit)
      case _: return metrics.SmuMetrics.AverageSocketPower, metrics.SmuMetrics.dGPU_W_MAX

  def get_mem_usage(self, dev):
@@ -3,16 +3,14 @@ An integrated environment for AMD GPU assembly and emulation
 Test with `PYTHONPATH="." pytest -n12 extra/assembly/amd/`
 `AMD_LLVM=1 PYTHONPATH="." pytest -n12 extra/assembly/amd/`

-* pdf.py -- extract assembly format + instruction pseudocode from AMD PDF
+* pdf.py -- extract assembly format + instruction psuedocode from AMD PDF
 * dsl.py -- helpers for the autogen instruction classes in `__init__.py`. should be standalone with init
-* pcode.py -- pseudocode execution environment. pseudocode should be transformed as little as possible.
+* pcode.py -- psuedocode execution environment. psuedocode should be transformed as little as possible.
 * asm.py -- an asm/disasm function to transform to and from AMD assembly syntax
 * emu.py -- an emulator for RDNA that runs in tinygrad with `AMD=1 MOCKGPU=1 PYTHON_REMU=1`

 The code should be as readable and deduplicated as possible. asm and emu shouldn't be required for dsl.

-The autogen folder is autogenerated from the AMD PDFs with `python3 -m extra.assembly.amd.pdf --arch all`
-
 test_emu.py has a good set of instruction tests for the emulation, with USE_HW=1 it will compare to real hardware.
 Whenever an instruction is fixed, regression tests should be added here and confirmed with real hardware.

@@ -28,12 +26,6 @@ The ops tests also pass, but they are very slow, so you should run them one at a
 `SKIP_SLOW_TEST=1 PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=12 test/test_ops.py`
 `SKIP_SLOW_TEST=1 PYTHONPATH="." AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=12 test/test_ops.py`

-When something is caught by main tinygrad tests, a local regression test should be added to `extra/assembly/amd/test`.
-While working with tinygrad, you can dump the assembly with `DEBUG=7`. These tests all pass on real hardware
-If a test is failing with `AMD=1 PYTHON_REMU=1 MOCKGPU=1` it's because an instruction is emulated incorrectly.
-You can test without `MOCKGPU=1` to test on real hardware, if it works on real hardware there's a bug in the emulator.
-IMPORTANT: if a test is failing in the emulator, it's an instruction bug. Use DEBUG=7, get the instructions, and debug.
-
-Currently, only RDNA3 is well supported, but when finished, this will support RDNA3+RDNA4+CDNA in ~2000 lines.
-Get line count with `cloc --by-file extra/assembly/amd/*.py`
+When something is caught by main tinygrad tests, a local regression test should be added to `extra/assembly/amd/test`. While working with tinygrad, you can dump the assembly with `DEBUG=7`. These tests all pass on real hardware, so if a test is failing with `AMD=1 PYTHON_REMU=1 MOCKGPU=1` it's likely because an instruction is emulated incorrectly. You can test without `MOCKGPU=1` to test on real hardware, if it works on real hardware there's a bug in the emulator.

+Currently, only RDNA3 is well supported, but when finished, this will support RDNA3+RDNA4+CDNA in ~2000 lines. Count lines with `cloc --by-file extra/assembly/amd/*.py`
@@ -1,67 +0,0 @@
-# Instruction format detection and decoding
-from __future__ import annotations
-from extra.assembly.amd.dsl import Inst, FixedBitField, EnumBitField
-
-# SDWA/DPP variant detection: src0 field (bits 0-8) encodes the variant
-# 0xf9 (249) = SDWA, 0xfa (250) = DPP16 for CDNA (GFX9)
-_VARIANT_SRC0 = {"_SDWA_SDST": 0xf9, "_SDWA": 0xf9, "_DPP16": 0xfa}
-
-def _matches(data: bytes, cls: type[Inst]) -> bool:
-  """Check if data matches all FixedBitFields and op is in allowed."""
-  for _, field in cls._fields:
-    dword_idx = field.lo // 32
-    if len(data) < (dword_idx + 1) * 4: return False
-    word = int.from_bytes(data[dword_idx*4:(dword_idx+1)*4], 'little')
-    field_lo = field.lo % 32
-    if isinstance(field, FixedBitField):
-      if ((word >> field_lo) & field.mask) != field.default: return False
-    if isinstance(field, EnumBitField) and field.allowed is not None:
-      try: opcode = field.decode((word >> field_lo) & field.mask)
-      except ValueError: return False  # opcode not in enum
-      if opcode not in field.allowed: return False
-  # Check SDWA/DPP variant based on src0 field (bits 0-8) - only for variant classes
-  name = cls.__name__
-  word = int.from_bytes(data[:4], 'little')
-  for suffix, expected_src0 in _VARIANT_SRC0.items():
-    if name.endswith(suffix): return (word & 0x1ff) == expected_src0
-  return True
-
-# Import instruction classes for each architecture
-from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP1_SDST, VOP1_LIT, VOP2, VOP2_LIT, VOP3, VOP3_SDST, VOP3SD, VOP3P, VOPC, VOPD, VINTERP,
-  SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPK, SOPK_LIT, SOPP, SMEM, DS, FLAT, GLOBAL, SCRATCH)
-from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP1_SDST as R4_VOP1_SDST, VOP1_LIT as R4_VOP1_LIT,
-  VOP2 as R4_VOP2, VOP2_LIT as R4_VOP2_LIT, VOP3 as R4_VOP3, VOP3_SDST as R4_VOP3_SDST, VOP3SD as R4_VOP3SD, VOP3P as R4_VOP3P,
-  VOPC as R4_VOPC, VOPD as R4_VOPD, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP1_LIT as R4_SOP1_LIT,
-  SOP2 as R4_SOP2, SOP2_LIT as R4_SOP2_LIT, SOPC as R4_SOPC, SOPC_LIT as R4_SOPC_LIT,
-  SOPK as R4_SOPK, SOPK_LIT as R4_SOPK_LIT, SOPP as R4_SOPP,
-  SMEM as R4_SMEM, DS as R4_DS, VFLAT as R4_FLAT, VGLOBAL as R4_GLOBAL, VSCRATCH as R4_SCRATCH)
-from extra.assembly.amd.autogen.cdna.ins import (VOP1 as C_VOP1, VOP1_SDWA as C_VOP1_SDWA, VOP1_DPP16 as C_VOP1_DPP16,
-  VOP2 as C_VOP2, VOP2_LIT as C_VOP2_LIT, VOP2_SDWA as C_VOP2_SDWA, VOP2_DPP16 as C_VOP2_DPP16,
-  VOPC as C_VOPC, VOPC_SDWA_SDST as C_VOPC_SDWA_SDST,
-  VOP3 as C_VOP3, VOP3_SDST as C_VOP3_SDST, VOP3SD as C_VOP3SD, VOP3P as C_VOP3P, VOP3P_MFMA as C_VOP3P_MFMA, VOP3PX2 as C_VOP3PX2,
-  SOP1 as C_SOP1, SOP2 as C_SOP2, SOPC as C_SOPC, SOPK as C_SOPK, SOPK_LIT as C_SOPK_LIT, SOPP as C_SOPP, SMEM as C_SMEM, DS as C_DS,
-  FLAT as C_FLAT, GLOBAL as C_GLOBAL, SCRATCH as C_SCRATCH, MUBUF as C_MUBUF)
-
-# Order matters: more specific encodings first, catch-alls (SOP2, VOP2) last
-# Order: base before _LIT (base matches regular ops, _LIT catches lit-only ops excluded from base)
-_FORMATS = {
-  "rdna3": [VOPD, VOP3P, VINTERP, VOP3SD, VOP3_SDST, VOP3, DS, GLOBAL, SCRATCH, FLAT, SMEM,
-            SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPK, SOPK_LIT, SOPP, VOPC, VOP1_SDST, VOP1, VOP1_LIT, VOP2, VOP2_LIT],
-  "rdna4": [R4_VOPD, R4_VOP3P, R4_VINTERP, R4_VOP3SD, R4_VOP3_SDST, R4_VOP3, R4_DS, R4_GLOBAL, R4_SCRATCH, R4_FLAT, R4_SMEM,
-            R4_SOP1, R4_SOP1_LIT, R4_SOPC, R4_SOPC_LIT, R4_SOPP, R4_SOPK, R4_SOPK_LIT, R4_VOPC, R4_VOP1_SDST, R4_VOP1, R4_VOP1_LIT,
-            R4_SOP2, R4_SOP2_LIT, R4_VOP2, R4_VOP2_LIT],
-  "cdna": [C_VOP3PX2, C_VOP3P_MFMA, C_VOP3P, C_VOP3SD, C_VOP3_SDST, C_VOP3, C_DS, C_GLOBAL, C_SCRATCH, C_FLAT, C_MUBUF, C_SMEM,
-            C_SOP1, C_SOPC, C_SOPP, C_SOPK, C_SOPK_LIT, C_VOPC_SDWA_SDST, C_VOPC,
-            C_VOP1_DPP16, C_VOP1_SDWA, C_VOP1, C_VOP2_DPP16, C_VOP2_SDWA, C_SOP2, C_VOP2, C_VOP2_LIT],
-}
-
-def detect_format(data: bytes, arch: str = "rdna3") -> type[Inst]:
-  """Detect instruction format from machine code bytes."""
-  assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}"
-  for cls in _FORMATS[arch]:
-    if _matches(data, cls): return cls
-  raise ValueError(f"unknown {arch} format word={int.from_bytes(data[:4], 'little'):#010x}")
-
-def decode_inst(data: bytes, arch: str = "rdna3") -> Inst:
-  """Decode machine code bytes into an instruction."""
-  return detect_format(data, arch).from_bytes(data)
@@ -0,0 +1,581 @@
+# RDNA3 assembler and disassembler
+from __future__ import annotations
+import re
+from extra.assembly.amd.dsl import Inst, RawImm, Reg, SrcMod, SGPR, VGPR, TTMP, s, v, ttmp, _RegFactory
+from extra.assembly.amd.dsl import VCC_LO, VCC_HI, VCC, EXEC_LO, EXEC_HI, EXEC, SCC, M0, NULL, OFF
+from extra.assembly.amd.dsl import SPECIAL_GPRS, SPECIAL_PAIRS, FLOAT_DEC, FLOAT_ENC, decode_src
+from extra.assembly.amd.autogen.rdna3 import ins
+from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP2, VOP3, VOP3SD, VOP3P, VOPC, VOPD, VINTERP, SOP1, SOP2, SOPC, SOPK, SOPP, SMEM, DS, FLAT, MUBUF, MTBUF, MIMG, EXP,
+  VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOPDOp, SOP1Op, SOPKOp, SOPPOp, SMEMOp, DSOp, MUBUFOp)
+
+def _matches_encoding(word: int, cls: type[Inst]) -> bool:
+  """Check if word matches the encoding pattern of an instruction class."""
+  if cls._encoding is None: return False
+  bf, val = cls._encoding
+  return ((word >> bf.lo) & bf.mask()) == val
+
+# Order matters: more specific encodings first, VOP2 last (it's a catch-all for bit31=0)
+_FORMATS_64 = [VOPD, VOP3P, VINTERP, VOP3, DS, FLAT, MUBUF, MTBUF, MIMG, SMEM, EXP]
+_FORMATS_32 = [SOP1, SOPC, SOPP, SOPK, VOPC, VOP1, SOP2, VOP2]  # SOP2/VOP2 are catch-alls
+
+def detect_format(data: bytes) -> type[Inst]:
+  """Detect instruction format from machine code bytes."""
+  assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}"
+  word = int.from_bytes(data[:4], 'little')
+  # Check 64-bit formats first (bits[31:30] == 0b11)
+  if (word >> 30) == 0b11:
+    for cls in _FORMATS_64:
+      if _matches_encoding(word, cls):
+        return VOP3SD if cls is VOP3 and ((word >> 16) & 0x3ff) in Inst._VOP3SD_OPS else cls
+    raise ValueError(f"unknown 64-bit format word={word:#010x}")
+  # 32-bit formats
+  for cls in _FORMATS_32:
+    if _matches_encoding(word, cls): return cls
+  raise ValueError(f"unknown 32-bit format word={word:#010x}")
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# CONSTANTS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+HWREG = {1: 'HW_REG_MODE', 2: 'HW_REG_STATUS', 3: 'HW_REG_TRAPSTS', 4: 'HW_REG_HW_ID', 5: 'HW_REG_GPR_ALLOC',
+         6: 'HW_REG_LDS_ALLOC', 7: 'HW_REG_IB_STS', 15: 'HW_REG_SH_MEM_BASES', 18: 'HW_REG_PERF_SNAPSHOT_PC_LO',
+         19: 'HW_REG_PERF_SNAPSHOT_PC_HI', 20: 'HW_REG_FLAT_SCR_LO', 21: 'HW_REG_FLAT_SCR_HI', 22: 'HW_REG_XNACK_MASK',
+         23: 'HW_REG_HW_ID1', 24: 'HW_REG_HW_ID2', 25: 'HW_REG_POPS_PACKER', 28: 'HW_REG_IB_STS2'}
+HWREG_IDS = {v.lower(): k for k, v in HWREG.items()}
+MSG = {128: 'MSG_RTN_GET_DOORBELL', 129: 'MSG_RTN_GET_DDID', 130: 'MSG_RTN_GET_TMA',
+       131: 'MSG_RTN_GET_REALTIME', 132: 'MSG_RTN_SAVE_WAVE', 133: 'MSG_RTN_GET_TBA'}
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# HELPERS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _reg(p: str, b: int, n: int = 1) -> str: return f"{p}{b}" if n == 1 else f"{p}[{b}:{b+n-1}]"
+def _sreg(b: int, n: int = 1) -> str: return _reg("s", b, n)
+def _vreg(b: int, n: int = 1) -> str: return _reg("v", b, n)
+def _ttmp(b: int, n: int = 1) -> str: return _reg("ttmp", b - 108, n) if 108 <= b <= 123 else None
+def _sreg_or_ttmp(b: int, n: int = 1) -> str: return _ttmp(b, n) or _sreg(b, n)
+
+def _fmt_sdst(v: int, n: int = 1) -> str:
+  if v == 124: return "null"
+  if t := _ttmp(v, n): return t
+  if n > 1: return SPECIAL_PAIRS.get(v) or _sreg(v, n)
+  return SPECIAL_GPRS.get(v, f"s{v}")
+
+def _fmt_src(v: int, n: int = 1) -> str:
+  if n == 1: return decode_src(v)
+  if v >= 256: return _vreg(v - 256, n)
+  if v <= 105: return _sreg(v, n)
+  if n == 2 and v in SPECIAL_PAIRS: return SPECIAL_PAIRS[v]
+  if t := _ttmp(v, n): return t
+  return decode_src(v)
+
+def _fmt_v16(v: int, base: int = 256, hi_thresh: int = 384) -> str:
+  return f"v{(v - base) & 0x7f}.{'h' if v >= hi_thresh else 'l'}"
+
+def waitcnt(vmcnt: int = 0x3f, expcnt: int = 0x7, lgkmcnt: int = 0x3f) -> int:
+  return (expcnt & 0x7) | ((lgkmcnt & 0x3f) << 4) | ((vmcnt & 0x3f) << 10)
+
+def _has(op: str, *subs) -> bool: return any(s in op for s in subs)
+def _omod(v: int) -> str: return {1: " mul:2", 2: " mul:4", 3: " div:2"}.get(v, "")
+def _src16(inst, v: int) -> str: return _fmt_v16(v) if v >= 256 else inst.lit(v)  # format 16-bit src: vgpr.h/l or literal
+def _mods(*pairs) -> str: return " ".join(m for c, m in pairs if c)
+def _fmt_bits(label: str, val: int, count: int) -> str: return f"{label}:[{','.join(str((val >> i) & 1) for i in range(count))}]"
+
+def _vop3_src(inst, v: int, neg: int, abs_: int, hi: int, n: int, f16: bool, any_hi: bool) -> str:
+  """Format VOP3 source operand with modifiers."""
+  if n > 1: s = _fmt_src(v, n)
+  elif f16 and v >= 256: s = f"v{v - 256}.h" if hi else (f"v{v - 256}.l" if any_hi else inst.lit(v))
+  else: s = inst.lit(v)
+  if abs_: s = f"|{s}|"
+  return f"-{s}" if neg else s
+
+def _opsel_str(opsel: int, n: int, need: bool, is16_d: bool) -> str:
+  """Format op_sel modifier string."""
+  if not need: return ""
+  if is16_d and (opsel & 8): return f" op_sel:[1,1,1{',1' if n == 3 else ''}]"
+  if n == 3: return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1},{(opsel >> 3) & 1}]"
+  return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1}]"
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# DISASSEMBLER
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _disasm_vop1(inst: VOP1) -> str:
+  name = inst.op_name.lower()
+  if inst.op in (VOP1Op.V_NOP, VOP1Op.V_PIPEFLUSH): return name
+  if inst.op == VOP1Op.V_READFIRSTLANE_B32: return f"v_readfirstlane_b32 {decode_src(inst.vdst)}, v{inst.src0 - 256 if inst.src0 >= 256 else inst.src0}"
+  # 16-bit dst: uses .h/.l suffix (determined by name pattern, not dtype - e.g. sat_pk_u8_i16 outputs 8-bit but uses 16-bit encoding)
+  parts = name.split('_')
+  is_16d = any(p in ('f16','i16','u16','b16') for p in parts[-2:-1]) or (len(parts) >= 2 and parts[-1] in ('f16','i16','u16','b16') and 'cvt' not in name)
+  dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else _fmt_v16(inst.vdst, 0, 128) if is_16d else f"v{inst.vdst}"
+  src = _fmt_src(inst.src0, inst.src_regs(0)) if inst.src_regs(0) > 1 else _src16(inst, inst.src0) if inst.is_src_16(0) and 'sat_pk' not in name else inst.lit(inst.src0)
+  return f"{name}_e32 {dst}, {src}"
+
+def _disasm_vop2(inst: VOP2) -> str:
+  name = inst.op_name.lower()
+  suf = "" if inst.op == VOP2Op.V_DOT2ACC_F32_F16 else "_e32"
+  # fmaak: dst = src0 * vsrc1 + K, fmamk: dst = src0 * K + vsrc1
+  if inst.op in (VOP2Op.V_FMAAK_F32, VOP2Op.V_FMAAK_F16): return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}, 0x{inst._literal:x}"
+  if inst.op in (VOP2Op.V_FMAMK_F32, VOP2Op.V_FMAMK_F16): return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, 0x{inst._literal:x}, v{inst.vsrc1}"
+  if inst.is_16bit(): return f"{name}{suf} {_fmt_v16(inst.vdst, 0, 128)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1, 0, 128)}"
+  return f"{name}{suf} v{inst.vdst}, {inst.lit(inst.src0)}, v{inst.vsrc1}" + (", vcc_lo" if inst.op == VOP2Op.V_CNDMASK_B32 else "")
+
+def _disasm_vopc(inst: VOPC) -> str:
+  name = inst.op_name.lower()
+  s0 = _fmt_src(inst.src0, inst.src_regs(0)) if inst.src_regs(0) > 1 else _src16(inst, inst.src0) if inst.is_16bit() else inst.lit(inst.src0)
+  s1 = _vreg(inst.vsrc1, inst.src_regs(1)) if inst.src_regs(1) > 1 else _fmt_v16(inst.vsrc1, 0, 128) if inst.is_16bit() else f"v{inst.vsrc1}"
+  return f"{name}_e32 {s0}, {s1}" if inst.op.value >= 128 else f"{name}_e32 vcc_lo, {s0}, {s1}"
+
+NO_ARG_SOPP = {SOPPOp.S_ENDPGM, SOPPOp.S_BARRIER, SOPPOp.S_WAKEUP, SOPPOp.S_ICACHE_INV,
+               SOPPOp.S_WAIT_IDLE, SOPPOp.S_ENDPGM_SAVED, SOPPOp.S_CODE_END, SOPPOp.S_ENDPGM_ORDERED_PS_DONE}
+
+def _disasm_sopp(inst: SOPP) -> str:
+  name = inst.op_name.lower()
+  if inst.op in NO_ARG_SOPP: return name
+  if inst.op == SOPPOp.S_WAITCNT:
+    vm, exp, lgkm = (inst.simm16 >> 10) & 0x3f, inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x3f
+    p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0x3f else ""]
+    return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
+  if inst.op == SOPPOp.S_DELAY_ALU:
+    deps, skips = ['VALU_DEP_1','VALU_DEP_2','VALU_DEP_3','VALU_DEP_4','TRANS32_DEP_1','TRANS32_DEP_2','TRANS32_DEP_3','FMA_ACCUM_CYCLE_1','SALU_CYCLE_1','SALU_CYCLE_2','SALU_CYCLE_3'], ['SAME','NEXT','SKIP_1','SKIP_2','SKIP_3','SKIP_4']
+    id0, skip, id1 = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 7) & 0xf
+    dep = lambda v: deps[v-1] if 0 < v <= len(deps) else str(v)
+    p = [f"instid0({dep(id0)})" if id0 else "", f"instskip({skips[skip]})" if skip else "", f"instid1({dep(id1)})" if id1 else ""]
+    return f"s_delay_alu {' | '.join(x for x in p if x) or '0'}"
+  return f"{name} {inst.simm16}" if name.startswith(('s_cbranch', 's_branch')) else f"{name} 0x{inst.simm16:x}"
+
+def _disasm_smem(inst: SMEM) -> str:
+  name = inst.op_name.lower()
+  if inst.op in (SMEMOp.S_GL1_INV, SMEMOp.S_DCACHE_INV): return name
+  off_s = f"{decode_src(inst.soffset)} offset:0x{inst.offset:x}" if inst.offset and inst.soffset != 124 else f"0x{inst.offset:x}" if inst.offset else decode_src(inst.soffset)
+  sbase_idx, sbase_count = inst.sbase * 2, 4 if (8 <= inst.op.value <= 12 or name == 's_atc_probe_buffer') else 2
+  sbase_str = _fmt_src(sbase_idx, sbase_count) if sbase_count == 2 else _sreg(sbase_idx, sbase_count) if sbase_idx <= 105 else _reg("ttmp", sbase_idx - 108, sbase_count)
+  if name in ('s_atc_probe', 's_atc_probe_buffer'): return f"{name} {inst.sdata}, {sbase_str}, {off_s}"
+  return f"{name} {_fmt_sdst(inst.sdata, inst.dst_regs())}, {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (inst.dlc, " dlc"))
+
+def _disasm_flat(inst: FLAT) -> str:
+  name = inst.op_name.lower()
+  seg = ['flat', 'scratch', 'global'][inst.seg] if inst.seg < 3 else 'flat'
+  instr = f"{seg}_{name.split('_', 1)[1] if '_' in name else name}"
+  off_val = inst.offset if seg == 'flat' else (inst.offset if inst.offset < 4096 else inst.offset - 8192)
+  w = inst.dst_regs() * (2 if 'cmpswap' in name else 1)
+  mods = f"{f' offset:{off_val}' if off_val else ''}{' glc' if inst.glc else ''}{' slc' if inst.slc else ''}{' dlc' if inst.dlc else ''}"
+  # saddr
+  if seg == 'flat' or inst.saddr == 0x7F: saddr_s = ""
+  elif inst.saddr == 124: saddr_s = ", off"
+  elif seg == 'scratch': saddr_s = f", {decode_src(inst.saddr)}"
+  elif inst.saddr in SPECIAL_PAIRS: saddr_s = f", {SPECIAL_PAIRS[inst.saddr]}"
+  elif t := _ttmp(inst.saddr, 2): saddr_s = f", {t}"
+  else: saddr_s = f", {_sreg(inst.saddr, 2) if inst.saddr < 106 else decode_src(inst.saddr)}"
+  # addtid: no addr
+  if 'addtid' in name: return f"{instr} v{inst.data if 'store' in name else inst.vdst}{saddr_s}{mods}"
+  # addr width
+  addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(inst.addr, 1 if seg == 'scratch' or (inst.saddr not in (0x7F, 124)) else 2)
+  data_s, vdst_s = _vreg(inst.data, w), _vreg(inst.vdst, w // 2 if 'cmpswap' in name else w)
+  if 'atomic' in name:
+    return f"{instr} {vdst_s}, {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}" if inst.glc else f"{instr} {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}"
+  if 'store' in name: return f"{instr} {addr_s}, {data_s}{saddr_s}{mods}"
+  return f"{instr} {_vreg(inst.vdst, w)}, {addr_s}{saddr_s}{mods}"
+
+def _disasm_ds(inst: DS) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  gds = " gds" if inst.gds else ""
+  off = f" offset:{inst.offset0 | (inst.offset1 << 8)}" if inst.offset0 or inst.offset1 else ""
+  off2 = f" offset0:{inst.offset0} offset1:{inst.offset1}" if inst.offset0 or inst.offset1 else ""
+  w = inst.dst_regs()
+  d0, d1, dst, addr = _vreg(inst.data0, w), _vreg(inst.data1, w), _vreg(inst.vdst, w), f"v{inst.addr}"
+
+  if op == DSOp.DS_NOP: return name
+  if op == DSOp.DS_BVH_STACK_RTN_B32: return f"{name} v{inst.vdst}, {addr}, v{inst.data0}, {_vreg(inst.data1, 4)}{off}{gds}"
+  if 'gws_sema' in name and op != DSOp.DS_GWS_SEMA_BR: return f"{name}{off}{gds}"
+  if 'gws_' in name: return f"{name} {addr}{off}{gds}"
+  if op in (DSOp.DS_CONSUME, DSOp.DS_APPEND): return f"{name} v{inst.vdst}{off}{gds}"
+  if 'gs_reg' in name: return f"{name} {_vreg(inst.vdst, 2)}, v{inst.data0}{off}{gds}"
+  if '2addr' in name:
+    if 'load' in name: return f"{name} {_vreg(inst.vdst, w*2)}, {addr}{off2}{gds}"
+    if 'store' in name and 'xchg' not in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
+    return f"{name} {_vreg(inst.vdst, w*2)}, {addr}, {d0}, {d1}{off2}{gds}"
+  if 'load' in name: return f"{name} v{inst.vdst}{off}{gds}" if 'addtid' in name else f"{name} {dst}, {addr}{off}{gds}"
+  if 'store' in name and not _has(name, 'cmp', 'xchg'):
+    return f"{name} v{inst.data0}{off}{gds}" if 'addtid' in name else f"{name} {addr}, {d0}{off}{gds}"
+  if 'swizzle' in name or op == DSOp.DS_ORDERED_COUNT: return f"{name} v{inst.vdst}, {addr}{off}{gds}"
+  if 'permute' in name: return f"{name} v{inst.vdst}, {addr}, v{inst.data0}{off}{gds}"
+  if 'condxchg' in name: return f"{name} {_vreg(inst.vdst, 2)}, {addr}, {_vreg(inst.data0, 2)}{off}{gds}"
+  if _has(name, 'cmpstore', 'mskor', 'wrap'):
+    return f"{name} {dst}, {addr}, {d0}, {d1}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}, {d1}{off}{gds}"
+  return f"{name} {dst}, {addr}, {d0}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}{off}{gds}"
+
+def _disasm_vop3(inst: VOP3) -> str:
+  op, name = inst.op, inst.op_name.lower()
+
+  # VOP3SD (shared encoding)
+  if isinstance(op, VOP3SDOp):
+    sdst = (inst.clmp << 7) | (inst.opsel << 3) | inst.abs
+    def src(v, neg, n): s = _fmt_src(v, n) if n > 1 else inst.lit(v); return f"-{s}" if neg else s
+    s0, s1, s2 = src(inst.src0, inst.neg & 1, inst.src_regs(0)), src(inst.src1, inst.neg & 2, inst.src_regs(1)), src(inst.src2, inst.neg & 4, inst.src_regs(2))
+    dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else f"v{inst.vdst}"
+    srcs = f"{s0}, {s1}, {s2}" if inst.num_srcs() == 3 else f"{s0}, {s1}"
+    return f"{name} {dst}, {_fmt_sdst(sdst, 1)}, {srcs}" + _omod(inst.omod)
+
+  # Detect 16-bit operand sizes (for .h/.l suffix handling)
+  is16_d = is16_s = is16_s2 = False
+  if 'cvt_pk' in name: is16_s = name.endswith('16')
+  elif m := re.match(r'v_(?:cvt|frexp_exp)_([a-z0-9_]+)_([a-z0-9]+)', name):
+    is16_d, is16_s = _has(m.group(1), 'f16','i16','u16','b16'), _has(m.group(2), 'f16','i16','u16','b16')
+    is16_s2 = is16_s
+  elif re.match(r'v_mad_[iu]32_[iu]16', name): is16_s = True
+  elif 'pack_b32' in name: is16_s = is16_s2 = True
+  else: is16_d = is16_s = is16_s2 = inst.is_16bit()
+
+  any_hi = inst.opsel != 0
+  s0 = _vop3_src(inst, inst.src0, inst.neg&1, inst.abs&1, inst.opsel&1, inst.src_regs(0), is16_s, any_hi)
+  s1 = _vop3_src(inst, inst.src1, inst.neg&2, inst.abs&2, inst.opsel&2, inst.src_regs(1), is16_s, any_hi)
+  s2 = _vop3_src(inst, inst.src2, inst.neg&4, inst.abs&4, inst.opsel&4, inst.src_regs(2), is16_s2, any_hi)
+
+  # Destination
+  dn = inst.dst_regs()
+  if op == VOP3Op.V_READLANE_B32: dst = _fmt_sdst(inst.vdst, 1)
+  elif dn > 1: dst = _vreg(inst.vdst, dn)
+  elif is16_d: dst = f"v{inst.vdst}.h" if (inst.opsel & 8) else f"v{inst.vdst}.l" if any_hi else f"v{inst.vdst}"
+  else: dst = f"v{inst.vdst}"
+
+  cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
+  nonvgpr_opsel = (inst.src0 < 256 and (inst.opsel & 1)) or (inst.src1 < 256 and (inst.opsel & 2)) or (inst.src2 < 256 and (inst.opsel & 4))
+  need_opsel = nonvgpr_opsel or (inst.opsel and not is16_s)
+
+  if inst.op < 256:  # VOPC
+    return f"{name}_e64 {s0}, {s1}" if name.startswith('v_cmpx') else f"{name}_e64 {_fmt_sdst(inst.vdst, 1)}, {s0}, {s1}"
+  if inst.op < 384:  # VOP2
+    n = inst.num_srcs()
+    os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
+    return f"{name}_e64 {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name}_e64 {dst}, {s0}, {s1}{os}{cl}{om}"
+  if inst.op < 512:  # VOP1
+    return f"{name}_e64" if op in (VOP3Op.V_NOP, VOP3Op.V_PIPEFLUSH) else f"{name}_e64 {dst}, {s0}{_opsel_str(inst.opsel, 1, need_opsel, is16_d)}{cl}{om}"
+  # Native VOP3
+  n = inst.num_srcs()
+  os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
+  return f"{name} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{os}{cl}{om}"
+
+def _disasm_vop3sd(inst: VOP3SD) -> str:
+  name = inst.op_name.lower()
+  def src(v, neg, n): s = _fmt_src(v, n) if n > 1 else inst.lit(v); return f"-{s}" if neg else s
+  s0, s1, s2 = src(inst.src0, inst.neg & 1, inst.src_regs(0)), src(inst.src1, inst.neg & 2, inst.src_regs(1)), src(inst.src2, inst.neg & 4, inst.src_regs(2))
+  dst = _vreg(inst.vdst, inst.dst_regs()) if inst.dst_regs() > 1 else f"v{inst.vdst}"
+  srcs = f"{s0}, {s1}, {s2}" if inst.num_srcs() == 3 else f"{s0}, {s1}"
+  suffix = "_e64" if name.startswith('v_') and 'co_' in name else ""
+  return f"{name}{suffix} {dst}, {_fmt_sdst(inst.sdst, 1)}, {srcs}{' clamp' if inst.clmp else ''}{_omod(inst.omod)}"
+
+def _disasm_vopd(inst: VOPD) -> str:
+  lit = inst._literal or inst.literal
+  vdst_y, nx, ny = (inst.vdsty << 1) | ((inst.vdstx & 1) ^ 1), VOPDOp(inst.opx).name.lower(), VOPDOp(inst.opy).name.lower()
+  def half(n, vd, s0, vs1): return f"{n} v{vd}, {inst.lit(s0)}{f', 0x{lit:x}' if lit and _has(n, 'fmaak', 'fmamk') else ''}" if 'mov' in n else f"{n} v{vd}, {inst.lit(s0)}, v{vs1}{f', 0x{lit:x}' if lit and _has(n, 'fmaak', 'fmamk') else ''}"
+  return f"{half(nx, inst.vdstx, inst.srcx0, inst.vsrcx1)} :: {half(ny, vdst_y, inst.srcy0, inst.vsrcy1)}"
+
+def _disasm_vop3p(inst: VOP3P) -> str:
+  name = inst.op_name.lower()
+  is_wmma, n, is_fma_mix = 'wmma' in name, inst.num_srcs(), 'fma_mix' in name
+  if is_wmma:
+    sc = 2 if 'iu4' in name else 4 if 'iu8' in name else 8
+    src0, src1, src2, dst = _fmt_src(inst.src0, sc), _fmt_src(inst.src1, sc), _fmt_src(inst.src2, 8), _vreg(inst.vdst, 8)
+  else: src0, src1, src2, dst = _fmt_src(inst.src0, 1), _fmt_src(inst.src1, 1), _fmt_src(inst.src2, 1), f"v{inst.vdst}"
+  opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
+  if is_fma_mix:
+    def m(s, neg, abs_): return f"-{f'|{s}|' if abs_ else s}" if neg else (f"|{s}|" if abs_ else s)
+    src0, src1, src2 = m(src0, inst.neg & 1, inst.neg_hi & 1), m(src1, inst.neg & 2, inst.neg_hi & 2), m(src2, inst.neg & 4, inst.neg_hi & 4)
+    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi else []) + (["clamp"] if inst.clmp else [])
+  else:
+    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != (7 if n == 3 else 3) else []) + \
+           ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if inst.clmp else [])
+  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
+
+def _disasm_buf(inst: MUBUF | MTBUF) -> str:
+  name = inst.op_name.lower()
+  if inst.op in (MUBUFOp.BUFFER_GL0_INV, MUBUFOp.BUFFER_GL1_INV): return name
+  w = (2 if _has(name, 'xyz', 'xyzw') else 1) if 'd16' in name else \
+      ((2 if _has(name, 'b64', 'u64', 'i64') else 1) * (2 if 'cmpswap' in name else 1)) if 'atomic' in name else \
+      {'b32':1,'b64':2,'b96':3,'b128':4,'b16':1,'x':1,'xy':2,'xyz':3,'xyzw':4}.get(name.split('_')[-1], 1)
+  if inst.tfe: w += 1
+  vaddr = _vreg(inst.vaddr, 2) if inst.offen and inst.idxen else f"v{inst.vaddr}" if inst.offen or inst.idxen else "off"
+  srsrc = _sreg_or_ttmp(inst.srsrc*4, 4)
+  mods = ([f"format:{inst.format}"] if isinstance(inst, MTBUF) else []) + [m for c, m in [(inst.idxen,"idxen"),(inst.offen,"offen"),(inst.offset,f"offset:{inst.offset}"),(inst.glc,"glc"),(inst.dlc,"dlc"),(inst.slc,"slc"),(inst.tfe,"tfe")] if c]
+  return f"{name} {_vreg(inst.vdata, w)}, {vaddr}, {srsrc}, {decode_src(inst.soffset)}{' ' + ' '.join(mods) if mods else ''}"
+
+def _mimg_vaddr_width(name: str, dim: int, a16: bool) -> int:
+  """Calculate vaddr register count for MIMG sample/gather operations."""
+  #                    1d,2d,3d,cube,1d_arr,2d_arr,2d_msaa,2d_msaa_arr
+  base =              [1, 2, 3, 3,   2,     3,     3,      4][dim]  # address coords
+  grad =              [1, 2, 3, 2,   1,     2,     2,      2][dim]  # gradient coords (for derivatives)
+  if 'get_resinfo' in name: return 1  # only mip level
+  packed, unpacked = 0, 0
+  if '_mip' in name: packed += 1
+  elif 'sample' in name or 'gather' in name:
+    if '_o' in name: unpacked += 1                                              # offset
+    if re.search(r'_c(_|$)', name): unpacked += 1                               # compare (not _cl)
+    if '_d' in name: unpacked += (grad + 1) & ~1 if '_g16' in name else grad*2  # derivatives
+    if '_b' in name: unpacked += 1                                              # bias
+    if '_l' in name and '_cl' not in name and '_lz' not in name: packed += 1    # LOD
+    if '_cl' in name: packed += 1                                               # clamp
+  return (base + packed + 1) // 2 + unpacked if a16 else base + packed + unpacked
+
+def _disasm_mimg(inst: MIMG) -> str:
+  name = inst.op_name.lower()
+  srsrc_base = inst.srsrc * 4
+  srsrc_str = _sreg_or_ttmp(srsrc_base, 8)
+  # BVH intersect ray: special case with 4 SGPR srsrc
+  if 'bvh' in name:
+    vaddr = (9 if '64' in name else 8) if inst.a16 else (12 if '64' in name else 11)
+    return f"{name} {_vreg(inst.vdata, 4)}, {_vreg(inst.vaddr, vaddr)}, {_sreg_or_ttmp(srsrc_base, 4)}{' a16' if inst.a16 else ''}"
+  # vdata width from dmask (gather4/msaa_load always 4), d16 packs, tfe adds 1
+  vdata = 4 if 'gather4' in name or 'msaa_load' in name else (bin(inst.dmask).count('1') or 1)
+  if inst.d16: vdata = (vdata + 1) // 2
+  if inst.tfe: vdata += 1
+  # vaddr width
+  dim_names = ['1d', '2d', '3d', 'cube', '1d_array', '2d_array', '2d_msaa', '2d_msaa_array']
+  dim = dim_names[inst.dim] if inst.dim < len(dim_names) else f"dim_{inst.dim}"
+  vaddr = _mimg_vaddr_width(name, inst.dim, inst.a16)
+  vaddr_str = f"v{inst.vaddr}" if vaddr == 1 else _vreg(inst.vaddr, vaddr)
+  # modifiers
+  mods = [f"dmask:0x{inst.dmask:x}"] if inst.dmask and (inst.dmask != 15 or 'atomic' in name) else []
+  mods.append(f"dim:SQ_RSRC_IMG_{dim.upper()}")
+  for flag, mod in [(inst.unrm,"unorm"),(inst.glc,"glc"),(inst.slc,"slc"),(inst.dlc,"dlc"),(inst.r128,"r128"),
+                    (inst.a16,"a16"),(inst.tfe,"tfe"),(inst.lwe,"lwe"),(inst.d16,"d16")]:
+    if flag: mods.append(mod)
+  # ssamp for sample/gather/get_lod
+  ssamp_str = ""
+  if 'sample' in name or 'gather' in name or 'get_lod' in name:
+    ssamp_str = ", " + _sreg_or_ttmp(inst.ssamp * 4, 4)
+  return f"{name} {_vreg(inst.vdata, vdata)}, {vaddr_str}, {srsrc_str}{ssamp_str} {' '.join(mods)}"
+
+def _disasm_sop1(inst: SOP1) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  if op == SOP1Op.S_GETPC_B64: return f"{name} {_fmt_sdst(inst.sdst, 2)}"
+  if op in (SOP1Op.S_SETPC_B64, SOP1Op.S_RFE_B64): return f"{name} {_fmt_src(inst.ssrc0, 2)}"
+  if op == SOP1Op.S_SWAPPC_B64: return f"{name} {_fmt_sdst(inst.sdst, 2)}, {_fmt_src(inst.ssrc0, 2)}"
+  if op in (SOP1Op.S_SENDMSG_RTN_B32, SOP1Op.S_SENDMSG_RTN_B64): return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, sendmsg({MSG.get(inst.ssrc0, str(inst.ssrc0))})"
+  return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, {inst.lit(inst.ssrc0) if inst.src_regs(0) == 1 else _fmt_src(inst.ssrc0, inst.src_regs(0))}"
+
+def _disasm_sop2(inst: SOP2) -> str:
+  return f"{inst.op_name.lower()} {_fmt_sdst(inst.sdst, inst.dst_regs())}, {inst.lit(inst.ssrc0) if inst.ssrc0 == 255 else _fmt_src(inst.ssrc0, inst.src_regs(0))}, {inst.lit(inst.ssrc1) if inst.ssrc1 == 255 else _fmt_src(inst.ssrc1, inst.src_regs(1))}"
+
+def _disasm_sopc(inst: SOPC) -> str:
+  return f"{inst.op_name.lower()} {_fmt_src(inst.ssrc0, inst.src_regs(0))}, {_fmt_src(inst.ssrc1, inst.src_regs(1))}"
+
+def _disasm_sopk(inst: SOPK) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  if op == SOPKOp.S_VERSION: return f"{name} 0x{inst.simm16:x}"
+  if op in (SOPKOp.S_SETREG_B32, SOPKOp.S_GETREG_B32):
+    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
+    hs = f"0x{inst.simm16:x}" if hid in (16, 17) else f"hwreg({HWREG.get(hid, str(hid))}, {hoff}, {hsz})"
+    return f"{name} {hs}, {_fmt_sdst(inst.sdst, 1)}" if op == SOPKOp.S_SETREG_B32 else f"{name} {_fmt_sdst(inst.sdst, 1)}, {hs}"
+  return f"{name} {_fmt_sdst(inst.sdst, inst.dst_regs())}, 0x{inst.simm16:x}"
+
+def _disasm_vinterp(inst: VINTERP) -> str:
+  mods = _mods((inst.waitexp, f"wait_exp:{inst.waitexp}"), (inst.clmp, "clamp"))
+  return f"{inst.op_name.lower()} v{inst.vdst}, {inst.lit(inst.src0, inst.neg & 1)}, {inst.lit(inst.src1, inst.neg & 2)}, {inst.lit(inst.src2, inst.neg & 4)}" + (" " + mods if mods else "")
+
+DISASM_HANDLERS = {VOP1: _disasm_vop1, VOP2: _disasm_vop2, VOPC: _disasm_vopc, VOP3: _disasm_vop3, VOP3SD: _disasm_vop3sd, VOPD: _disasm_vopd, VOP3P: _disasm_vop3p,
+                   VINTERP: _disasm_vinterp, SOPP: _disasm_sopp, SMEM: _disasm_smem, DS: _disasm_ds, FLAT: _disasm_flat, MUBUF: _disasm_buf, MTBUF: _disasm_buf,
+                   MIMG: _disasm_mimg, SOP1: _disasm_sop1, SOP2: _disasm_sop2, SOPC: _disasm_sopc, SOPK: _disasm_sopk}
+
+def disasm(inst: Inst) -> str: return DISASM_HANDLERS[type(inst)](inst)
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# ASSEMBLER
+# ═══════════════════════════════════════════════════════════════════════════════
+
+SPEC_REGS = {'vcc_lo': RawImm(106), 'vcc_hi': RawImm(107), 'vcc': RawImm(106), 'null': RawImm(124), 'off': RawImm(124), 'm0': RawImm(125),
+             'exec_lo': RawImm(126), 'exec_hi': RawImm(127), 'exec': RawImm(126), 'scc': RawImm(253), 'src_scc': RawImm(253)}
+FLOATS = {str(k): k for k in FLOAT_ENC}  # Valid float literal strings: '0.5', '-0.5', '1.0', etc.
+REG_MAP: dict[str, _RegFactory] = {'s': s, 'v': v, 't': ttmp, 'ttmp': ttmp}
+SMEM_OPS = {'s_load_b32', 's_load_b64', 's_load_b128', 's_load_b256', 's_load_b512',
+            's_buffer_load_b32', 's_buffer_load_b64', 's_buffer_load_b128', 's_buffer_load_b256', 's_buffer_load_b512'}
+SPEC_DSL = {'vcc_lo': 'VCC_LO', 'vcc_hi': 'VCC_HI', 'vcc': 'VCC_LO', 'null': 'NULL', 'off': 'OFF', 'm0': 'M0',
+            'exec_lo': 'EXEC_LO', 'exec_hi': 'EXEC_HI', 'exec': 'EXEC_LO', 'scc': 'SCC', 'src_scc': 'SCC'}
+
+def _op2dsl(op: str) -> str:
+  op = op.strip()
+  neg = op.startswith('-') and not (op[1:2].isdigit() or (len(op) > 2 and op[1] == '0' and op[2] in 'xX'))
+  if neg: op = op[1:]
+  abs_ = (op.startswith('|') and op.endswith('|')) or (op.startswith('abs(') and op.endswith(')'))
+  if abs_: op = op[1:-1] if op.startswith('|') else op[4:-1]
+  hi = ".h" if op.endswith('.h') else ".l" if op.endswith('.l') else ""
+  if hi: op = op[:-2]
+  lo = op.lower()
+  def wrap(b): return f"{'-' if neg else ''}abs({b}){hi}" if abs_ else f"-{b}{hi}" if neg else f"{b}{hi}"
+  if lo in SPEC_DSL: return wrap(SPEC_DSL[lo])
+  if op in FLOATS: return wrap(op)
+  rp = {'s': 's', 'v': 'v', 't': 'ttmp', 'ttmp': 'ttmp'}
+  if m := re.match(r'^([svt](?:tmp)?)\[(\d+):(\d+)\]$', lo): return wrap(f"{rp[m.group(1)]}[{m.group(2)}:{m.group(3)}]")
+  if m := re.match(r'^([svt](?:tmp)?)(\d+)$', lo): return wrap(f"{rp[m.group(1)]}[{m.group(2)}]")
+  if re.match(r'^-?\d+$|^-?0x[0-9a-fA-F]+$', op): return f"SrcMod({op}, neg={neg}, abs_={abs_})" if neg or abs_ else op
+  return wrap(op)
+
+def _parse_ops(s: str) -> list[str]:
+  ops, cur, depth, pipe = [], "", 0, False
+  for c in s:
+    if c in '[(': depth += 1
+    elif c in '])': depth -= 1
+    elif c == '|': pipe = not pipe
+    if c == ',' and depth == 0 and not pipe: ops.append(cur.strip()); cur = ""
+    else: cur += c
+  if cur.strip(): ops.append(cur.strip())
+  return ops
+
+def _extract(text: str, pat: str, flags=re.I):
+  if m := re.search(pat, text, flags): return m, text[:m.start()] + text[m.end():]
+  return None, text
+
+def get_dsl(text: str) -> str:
+  text, kw = text.strip(), []
+  # Extract modifiers
+  for pat, val in [(r'\s+mul:2(?:\s|$)', 1), (r'\s+mul:4(?:\s|$)', 2), (r'\s+div:2(?:\s|$)', 3)]:
+    if (m := _extract(text, pat))[0]: kw.append(f'omod={val}'); text = m[1]; break
+  if (m := _extract(text, r'\s+clamp(?:\s|$)'))[0]: kw.append('clmp=1'); text = m[1]
+  opsel, m, text = None, *_extract(text, r'\s+op_sel:\[([^\]]+)\]')
+  if m:
+    bits, mn = [int(x.strip()) for x in m.group(1).split(',')], text.split()[0].lower()
+    is3p = mn.startswith(('v_pk_', 'v_wmma_', 'v_dot'))
+    opsel = (bits[0] | (bits[1] << 1) | (bits[2] << 2)) if len(bits) == 3 and is3p else \
+            (bits[0] | (bits[1] << 1) | (bits[2] << 3)) if len(bits) == 3 else sum(b << i for i, b in enumerate(bits))
+  m, text = _extract(text, r'\s+wait_exp:(\d+)'); waitexp = m.group(1) if m else None
+  m, text = _extract(text, r'\s+offset:(0x[0-9a-fA-F]+|-?\d+)'); off_val = m.group(1) if m else None
+  m, text = _extract(text, r'\s+dlc(?:\s|$)'); dlc = 1 if m else None
+  m, text = _extract(text, r'\s+glc(?:\s|$)'); glc = 1 if m else None
+  m, text = _extract(text, r'\s+slc(?:\s|$)'); slc = 1 if m else None
+  m, text = _extract(text, r'\s+neg_lo:\[([^\]]+)\]'); neg_lo = sum(int(x.strip()) << i for i, x in enumerate(m.group(1).split(','))) if m else None
+  m, text = _extract(text, r'\s+neg_hi:\[([^\]]+)\]'); neg_hi = sum(int(x.strip()) << i for i, x in enumerate(m.group(1).split(','))) if m else None
+  if waitexp: kw.append(f'waitexp={waitexp}')
+
+  parts = text.replace(',', ' ').split()
+  if not parts: raise ValueError("empty instruction")
+  mn, op_str = parts[0].lower(), text[len(parts[0]):].strip()
+  ops, args = _parse_ops(op_str), [_op2dsl(o) for o in _parse_ops(op_str)]
+
+  # s_waitcnt
+  if mn == 's_waitcnt':
+    vm, exp, lgkm = 0x3f, 0x7, 0x3f
+    for p in op_str.replace(',', ' ').split():
+      if m := re.match(r'vmcnt\((\d+)\)', p): vm = int(m.group(1))
+      elif m := re.match(r'expcnt\((\d+)\)', p): exp = int(m.group(1))
+      elif m := re.match(r'lgkmcnt\((\d+)\)', p): lgkm = int(m.group(1))
+      elif re.match(r'^0x[0-9a-f]+$|^\d+$', p): return f"s_waitcnt(simm16={int(p, 0)})"
+    return f"s_waitcnt(simm16={waitcnt(vm, exp, lgkm)})"
+
+  # VOPD
+  if '::' in text:
+    xp, yp = text.split('::')
+    xps, yps = xp.strip().replace(',', ' ').split(), yp.strip().replace(',', ' ').split()
+    xo, yo = [_op2dsl(p) for p in xps[1:]], [_op2dsl(p) for p in yps[1:]]
+    vdx, sx0, vsx1 = xo[0], xo[1] if len(xo) > 1 else '0', xo[2] if len(xo) > 2 else 'v[0]'
+    vdy, sy0, vsy1 = yo[0], yo[1] if len(yo) > 1 else '0', yo[2] if len(yo) > 2 else 'v[0]'
+    lit = xo[3] if 'fmaak' in xps[0].lower() and len(xo) > 3 else yo[3] if 'fmaak' in yps[0].lower() and len(yo) > 3 else None
+    if 'fmamk' in xps[0].lower() and len(xo) > 3: lit, vsx1 = xo[2], xo[3]
+    elif 'fmamk' in yps[0].lower() and len(yo) > 3: lit, vsy1 = yo[2], yo[3]
+    return f"VOPD(VOPDOp.{xps[0].upper()}, VOPDOp.{yps[0].upper()}, vdstx={vdx}, vdsty={vdy}, srcx0={sx0}, vsrcx1={vsx1}, srcy0={sy0}, vsrcy1={vsy1}{f', literal={lit}' if lit else ''})"
+
+  # Special instructions
+  if mn == 's_setreg_imm32_b32': raise ValueError(f"unsupported: {mn}")
+  if mn in ('s_setpc_b64', 's_rfe_b64'): return f"{mn}(ssrc0={args[0]})"
+  if mn in ('s_sendmsg_rtn_b32', 's_sendmsg_rtn_b64'): return f"{mn}(sdst={args[0]}, ssrc0=RawImm({args[1].strip()}))"
+  if mn == 's_version': return f"{mn}(simm16={args[0]})"
+  if mn == 's_setreg_b32': return f"{mn}(simm16={args[0]}, sdst={args[1]})"
+
+  # SMEM
+  if mn in SMEM_OPS:
+    gs, ds = ", glc=1" if glc else "", ", dlc=1" if dlc else ""
+    if len(ops) >= 3 and re.match(r'^-?[0-9]|^-?0x', ops[2].strip().lower()):
+      return f"{mn}(sdata={args[0]}, sbase={args[1]}, offset={args[2]}, soffset=RawImm(124){gs}{ds})"
+    if off_val and len(ops) >= 3: return f"{mn}(sdata={args[0]}, sbase={args[1]}, offset={off_val}, soffset={args[2]}{gs}{ds})"
+    if len(ops) >= 3: return f"{mn}(sdata={args[0]}, sbase={args[1]}, soffset={args[2]}{gs}{ds})"
+
+  # Buffer
+  if mn.startswith('buffer_') and len(ops) >= 2 and ops[1].strip().lower() == 'off':
+    return f"{mn}(vdata={args[0]}, vaddr=0, srsrc={args[2]}, soffset={f'RawImm({args[3].strip()})' if len(args) > 3 else 'RawImm(0)'})"
+
+  # FLAT/GLOBAL/SCRATCH load/store/atomic - saddr needs RawImm(124) for off/null
+  def _saddr(a): return 'RawImm(124)' if a in ('OFF', 'NULL') else a
+  flat_mods = f"{f', offset={off_val}' if off_val else ''}{', glc=1' if glc else ''}{', slc=1' if slc else ''}{', dlc=1' if dlc else ''}"
+  for pre, flds in [('flat_load','vdst,addr,saddr'), ('global_load','vdst,addr,saddr'), ('scratch_load','vdst,addr,saddr'),
+                    ('flat_store','addr,data,saddr'), ('global_store','addr,data,saddr'), ('scratch_store','addr,data,saddr')]:
+    if mn.startswith(pre) and len(args) >= 2:
+      f0, f1, f2 = flds.split(',')
+      return f"{mn}({f0}={args[0]}, {f1}={args[1]}{f', {f2}={_saddr(args[2])}' if len(args) >= 3 else ', saddr=RawImm(124)'}{flat_mods})"
+  for pre in ('flat_atomic', 'global_atomic', 'scratch_atomic'):
+    if mn.startswith(pre):
+      if glc and len(args) >= 3: return f"{mn}(vdst={args[0]}, addr={args[1]}, data={args[2]}{f', saddr={_saddr(args[3])}' if len(args) >= 4 else ', saddr=RawImm(124)'}{flat_mods})"
+      if len(args) >= 2: return f"{mn}(addr={args[0]}, data={args[1]}{f', saddr={_saddr(args[2])}' if len(args) >= 3 else ', saddr=RawImm(124)'}{flat_mods})"
+
+  # DS instructions
+  if mn.startswith('ds_'):
+    off0, off1 = (str(int(off_val, 0) & 0xff), str((int(off_val, 0) >> 8) & 0xff)) if off_val else ("0", "0")
+    gds_s = ", gds=1" if 'gds' in text.lower().split()[-1:] else ""
+    off_kw = f", offset0={off0}, offset1={off1}{gds_s}"
+    if mn == 'ds_nop' or mn in ('ds_gws_sema_v', 'ds_gws_sema_p', 'ds_gws_sema_release_all'): return f"{mn}({off_kw.lstrip(', ')})"
+    if 'gws_' in mn: return f"{mn}(addr={args[0]}{off_kw})"
+    if 'consume' in mn or 'append' in mn: return f"{mn}(vdst={args[0]}{off_kw})"
+    if 'gs_reg' in mn: return f"{mn}(vdst={args[0]}, data0={args[1]}{off_kw})"
+    if '2addr' in mn:
+      if 'load' in mn: return f"{mn}(vdst={args[0]}, addr={args[1]}{off_kw})"
+      if 'store' in mn and 'xchg' not in mn: return f"{mn}(addr={args[0]}, data0={args[1]}, data1={args[2]}{off_kw})"
+      return f"{mn}(vdst={args[0]}, addr={args[1]}, data0={args[2]}, data1={args[3]}{off_kw})"
+    if 'load' in mn: return f"{mn}(vdst={args[0]}{off_kw})" if 'addtid' in mn else f"{mn}(vdst={args[0]}, addr={args[1]}{off_kw})"
+    if 'store' in mn and not _has(mn, 'cmp', 'xchg'):
+      return f"{mn}(data0={args[0]}{off_kw})" if 'addtid' in mn else f"{mn}(addr={args[0]}, data0={args[1]}{off_kw})"
+    if 'swizzle' in mn or 'ordered_count' in mn: return f"{mn}(vdst={args[0]}, addr={args[1]}{off_kw})"
+    if 'permute' in mn: return f"{mn}(vdst={args[0]}, addr={args[1]}, data0={args[2]}{off_kw})"
+    if 'bvh' in mn: return f"{mn}(vdst={args[0]}, addr={args[1]}, data0={args[2]}, data1={args[3]}{off_kw})"
+    if 'condxchg' in mn: return f"{mn}(vdst={args[0]}, addr={args[1]}, data0={args[2]}{off_kw})"
+    if _has(mn, 'cmpstore', 'mskor', 'wrap'):
+      return f"{mn}(vdst={args[0]}, addr={args[1]}, data0={args[2]}, data1={args[3]}{off_kw})" if '_rtn' in mn else f"{mn}(addr={args[0]}, data0={args[1]}, data1={args[2]}{off_kw})"
+    return f"{mn}(vdst={args[0]}, addr={args[1]}, data0={args[2]}{off_kw})" if '_rtn' in mn else f"{mn}(addr={args[0]}, data0={args[1]}{off_kw})"
+
+  # v_fmaak/v_fmamk literal extraction
+  lit_s = ""
+  if mn in ('v_fmaak_f32', 'v_fmaak_f16') and len(args) == 4: lit_s, args = f", literal={args[3].strip()}", args[:3]
+  elif mn in ('v_fmamk_f32', 'v_fmamk_f16') and len(args) == 4: lit_s, args = f", literal={args[2].strip()}", [args[0], args[1], args[3]]
+
+  # VCC ops cleanup
+  vcc_ops = {'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'}
+  if mn.replace('_e32', '') in vcc_ops and len(args) >= 5: mn, args = mn.replace('_e32', '') + '_e32', [args[0], args[2], args[3]]
+  if mn.replace('_e64', '') in vcc_ops and mn.endswith('_e64'): mn = mn.replace('_e64', '')
+  if mn.startswith('v_cmp') and not mn.endswith('_e64') and len(args) >= 3 and ops[0].strip().lower() in ('vcc_lo', 'vcc_hi', 'vcc'): args = args[1:]
+  if 'cmpx' in mn and mn.endswith('_e64') and len(args) == 2: args = ['RawImm(126)'] + args
+
+  fn = mn.replace('.', '_')
+  if opsel is not None: args = [re.sub(r'\.[hl]$', '', a) for a in args]
+
+  # v_fma_mix*: extract inline neg/abs modifiers
+  if 'fma_mix' in mn and neg_lo is None and neg_hi is None:
+    inline_neg, inline_abs, clean_args = 0, 0, [args[0]]
+    for i, op in enumerate(ops[1:4]):
+      op = op.strip()
+      neg = op.startswith('-') and not (op[1:2].isdigit() or (len(op) > 2 and op[1] == '0' and op[2] in 'xX'))
+      if neg: op = op[1:]
+      abs_ = op.startswith('|') and op.endswith('|')
+      if abs_: op = op[1:-1]
+      if neg: inline_neg |= (1 << i)
+      if abs_: inline_abs |= (1 << i)
+      clean_args.append(_op2dsl(op))
+    args = clean_args + args[4:]
+    if inline_neg: neg_lo = inline_neg
+    if inline_abs: neg_hi = inline_abs
+
+  all_kw = list(kw)
+  if lit_s: all_kw.append(lit_s.lstrip(', '))
+  if opsel is not None: all_kw.append(f'opsel={opsel}')
+  if neg_lo is not None: all_kw.append(f'neg={neg_lo}')
+  if neg_hi is not None: all_kw.append(f'neg_hi={neg_hi}')
+  if 'bvh' in mn and 'intersect_ray' in mn: all_kw.extend(['dmask=15', 'unrm=1', 'r128=1'])
+
+  a_str, kw_str = ', '.join(args), ', '.join(all_kw)
+  return f"{fn}({a_str}, {kw_str})" if kw_str and a_str else f"{fn}({kw_str})" if kw_str else f"{fn}({a_str})"
+
+def asm(text: str) -> Inst:
+  dsl = get_dsl(text)
+  ns = {n: getattr(ins, n) for n in dir(ins) if not n.startswith('_')}
+  ns.update({'s': s, 'v': v, 'ttmp': ttmp, 'abs': abs, 'RawImm': RawImm, 'SrcMod': SrcMod, 'VGPR': VGPR, 'SGPR': SGPR, 'TTMP': TTMP,
+             'VCC_LO': VCC_LO, 'VCC_HI': VCC_HI, 'VCC': VCC, 'EXEC_LO': EXEC_LO, 'EXEC_HI': EXEC_HI, 'EXEC': EXEC, 'SCC': SCC, 'M0': M0, 'NULL': NULL, 'OFF': OFF})
+  try: return eval(dsl, ns)
+  except NameError:
+    if m := re.match(r'^(v_\w+)(\(.*\))$', dsl): return eval(f"{m.group(1)}_e32{m.group(2)}", ns)
+    raise
@@ -1,324 +0,0 @@
-# autogenerated from AMD ISA XML - do not edit
-from enum import Enum, auto
-
-class ReprEnum(Enum):
-  """Enum with clean repr that roundtrips with eval()."""
-  def __repr__(self): return f"{type(self).__name__}.{self.name}"
-
-class Fmt(Enum):
-  FMT_ANY = auto()
-  FMT_BUF = auto()
-  FMT_IMG = auto()
-  FMT_IMG_BVH = auto()
-  FMT_NUM_B1 = auto()
-  FMT_NUM_B1024 = auto()
-  FMT_NUM_B128 = auto()
-  FMT_NUM_B16 = auto()
-  FMT_NUM_B256 = auto()
-  FMT_NUM_B32 = auto()
-  FMT_NUM_B512 = auto()
-  FMT_NUM_B64 = auto()
-  FMT_NUM_B8 = auto()
-  FMT_NUM_B96 = auto()
-  FMT_NUM_BF16 = auto()
-  FMT_NUM_BF6 = auto()
-  FMT_NUM_BF8 = auto()
-  FMT_NUM_F16 = auto()
-  FMT_NUM_F32 = auto()
-  FMT_NUM_F64 = auto()
-  FMT_NUM_FP4 = auto()
-  FMT_NUM_FP6 = auto()
-  FMT_NUM_FP8 = auto()
-  FMT_NUM_I16 = auto()
-  FMT_NUM_I24 = auto()
-  FMT_NUM_I32 = auto()
-  FMT_NUM_I4 = auto()
-  FMT_NUM_I64 = auto()
-  FMT_NUM_I8 = auto()
-  FMT_NUM_IU4 = auto()
-  FMT_NUM_IU8 = auto()
-  FMT_NUM_M64 = auto()
-  FMT_NUM_PK16_BF16 = auto()
-  FMT_NUM_PK16_BF8 = auto()
-  FMT_NUM_PK16_F16 = auto()
-  FMT_NUM_PK16_F32 = auto()
-  FMT_NUM_PK16_FP8 = auto()
-  FMT_NUM_PK16_I32 = auto()
-  FMT_NUM_PK16_I8 = auto()
-  FMT_NUM_PK2_B16 = auto()
-  FMT_NUM_PK2_B32 = auto()
-  FMT_NUM_PK2_B64 = auto()
-  FMT_NUM_PK2_BF16 = auto()
-  FMT_NUM_PK2_BF8 = auto()
-  FMT_NUM_PK2_F16 = auto()
-  FMT_NUM_PK2_F32 = auto()
-  FMT_NUM_PK2_FP4 = auto()
-  FMT_NUM_PK2_FP8 = auto()
-  FMT_NUM_PK2_I16 = auto()
-  FMT_NUM_PK2_I8 = auto()
-  FMT_NUM_PK2_U16 = auto()
-  FMT_NUM_PK2_U8 = auto()
-  FMT_NUM_PK32_BF16 = auto()
-  FMT_NUM_PK32_BF6 = auto()
-  FMT_NUM_PK32_BF8 = auto()
-  FMT_NUM_PK32_F16 = auto()
-  FMT_NUM_PK32_F32 = auto()
-  FMT_NUM_PK32_FP6 = auto()
-  FMT_NUM_PK32_FP8 = auto()
-  FMT_NUM_PK32_I32 = auto()
-  FMT_NUM_PK32_I8 = auto()
-  FMT_NUM_PK4_B8 = auto()
-  FMT_NUM_PK4_BF16 = auto()
-  FMT_NUM_PK4_BF8 = auto()
-  FMT_NUM_PK4_F16 = auto()
-  FMT_NUM_PK4_F32 = auto()
-  FMT_NUM_PK4_F64 = auto()
-  FMT_NUM_PK4_FP8 = auto()
-  FMT_NUM_PK4_I32 = auto()
-  FMT_NUM_PK4_I8 = auto()
-  FMT_NUM_PK4_IU8 = auto()
-  FMT_NUM_PK4_U8 = auto()
-  FMT_NUM_PK8_B32 = auto()
-  FMT_NUM_PK8_BF16 = auto()
-  FMT_NUM_PK8_BF8 = auto()
-  FMT_NUM_PK8_F16 = auto()
-  FMT_NUM_PK8_FP8 = auto()
-  FMT_NUM_PK8_I4 = auto()
-  FMT_NUM_PK8_I8 = auto()
-  FMT_NUM_PK8_IU4 = auto()
-  FMT_NUM_PK8_U4 = auto()
-  FMT_NUM_PK8_U8 = auto()
-  FMT_NUM_PK_F16 = auto()
-  FMT_NUM_PK_I16 = auto()
-  FMT_NUM_PK_I8 = auto()
-  FMT_NUM_PK_U16 = auto()
-  FMT_NUM_PK_U8 = auto()
-  FMT_NUM_U16 = auto()
-  FMT_NUM_U24 = auto()
-  FMT_NUM_U32 = auto()
-  FMT_NUM_U4 = auto()
-  FMT_NUM_U64 = auto()
-  FMT_NUM_U8 = auto()
-  FMT_RSRC = auto()
-  FMT_RSRC_SCALAR = auto()
-  FMT_RSRC_SCRATCH = auto()
-  FMT_RSRC_SCRATCH_BYTE = auto()
-  FMT_RSRC_SCRATCH_STRIDE = auto()
-  FMT_RSRC_TYPED = auto()
-  FMT_RSRC_TYPED_BYTE = auto()
-  FMT_RSRC_TYPED_SCRATCH = auto()
-  FMT_RSRC_TYPED_STRIDE = auto()
-  FMT_RSRC_VECTOR = auto()
-  FMT_RSRC_VECTOR_BYTE = auto()
-  FMT_RSRC_VECTOR_STRIDE = auto()
-  FMT_SAMP = auto()
-  FMT_WMMA_AB_16X16_BF16 = auto()
-  FMT_WMMA_AB_16X16_BF8 = auto()
-  FMT_WMMA_AB_16X16_F16 = auto()
-  FMT_WMMA_AB_16X16_FP8 = auto()
-  FMT_WMMA_AB_16X16_IU4 = auto()
-  FMT_WMMA_AB_16X16_IU8 = auto()
-  FMT_WMMA_AB_16X32_BF16 = auto()
-  FMT_WMMA_AB_16X32_BF8 = auto()
-  FMT_WMMA_AB_16X32_F16 = auto()
-  FMT_WMMA_AB_16X32_FP8 = auto()
-  FMT_WMMA_AB_16X32_IU4 = auto()
-  FMT_WMMA_AB_16X32_IU8 = auto()
-  FMT_WMMA_AB_16X64_IU4 = auto()
-  FMT_WMMA_AB_BF16 = auto()
-  FMT_WMMA_AB_F16 = auto()
-  FMT_WMMA_AB_IU4 = auto()
-  FMT_WMMA_AB_IU8 = auto()
-  FMT_WMMA_DC_16X16_BF16 = auto()
-  FMT_WMMA_DC_16X16_F16 = auto()
-  FMT_WMMA_DC_16X16_F32 = auto()
-  FMT_WMMA_DC_16X16_I32 = auto()
-  FMT_WMMA_DC_BF16 = auto()
-  FMT_WMMA_DC_F16 = auto()
-  FMT_WMMA_DC_F32 = auto()
-  FMT_WMMA_DC_I32 = auto()
-  FMT_WMMA_INDEX_SET = auto()
-
-FMT_BITS = {
-  Fmt.FMT_ANY: 1,
-  Fmt.FMT_BUF: 64,
-  Fmt.FMT_IMG: 256,
-  Fmt.FMT_IMG_BVH: 128,
-  Fmt.FMT_NUM_B1: 1,
-  Fmt.FMT_NUM_B1024: 1024,
-  Fmt.FMT_NUM_B128: 128,
-  Fmt.FMT_NUM_B16: 16,
-  Fmt.FMT_NUM_B256: 256,
-  Fmt.FMT_NUM_B32: 32,
-  Fmt.FMT_NUM_B512: 512,
-  Fmt.FMT_NUM_B64: 64,
-  Fmt.FMT_NUM_B8: 8,
-  Fmt.FMT_NUM_B96: 96,
-  Fmt.FMT_NUM_BF16: 16,
-  Fmt.FMT_NUM_BF6: 6,
-  Fmt.FMT_NUM_BF8: 8,
-  Fmt.FMT_NUM_F16: 16,
-  Fmt.FMT_NUM_F32: 32,
-  Fmt.FMT_NUM_F64: 64,
-  Fmt.FMT_NUM_FP4: 4,
-  Fmt.FMT_NUM_FP6: 6,
-  Fmt.FMT_NUM_FP8: 8,
-  Fmt.FMT_NUM_I16: 16,
-  Fmt.FMT_NUM_I24: 24,
-  Fmt.FMT_NUM_I32: 32,
-  Fmt.FMT_NUM_I4: 4,
-  Fmt.FMT_NUM_I64: 64,
-  Fmt.FMT_NUM_I8: 8,
-  Fmt.FMT_NUM_IU4: 4,
-  Fmt.FMT_NUM_IU8: 8,
-  Fmt.FMT_NUM_M64: 64,
-  Fmt.FMT_NUM_PK16_BF16: 256,
-  Fmt.FMT_NUM_PK16_BF8: 128,
-  Fmt.FMT_NUM_PK16_F16: 256,
-  Fmt.FMT_NUM_PK16_F32: 512,
-  Fmt.FMT_NUM_PK16_FP8: 128,
-  Fmt.FMT_NUM_PK16_I32: 512,
-  Fmt.FMT_NUM_PK16_I8: 128,
-  Fmt.FMT_NUM_PK2_B16: 32,
-  Fmt.FMT_NUM_PK2_B32: 64,
-  Fmt.FMT_NUM_PK2_B64: 128,
-  Fmt.FMT_NUM_PK2_BF16: 32,
-  Fmt.FMT_NUM_PK2_BF8: 16,
-  Fmt.FMT_NUM_PK2_F16: 32,
-  Fmt.FMT_NUM_PK2_F32: 64,
-  Fmt.FMT_NUM_PK2_FP4: 8,
-  Fmt.FMT_NUM_PK2_FP8: 16,
-  Fmt.FMT_NUM_PK2_I16: 32,
-  Fmt.FMT_NUM_PK2_I8: 16,
-  Fmt.FMT_NUM_PK2_U16: 32,
-  Fmt.FMT_NUM_PK2_U8: 16,
-  Fmt.FMT_NUM_PK32_BF16: 512,
-  Fmt.FMT_NUM_PK32_BF6: 192,
-  Fmt.FMT_NUM_PK32_BF8: 256,
-  Fmt.FMT_NUM_PK32_F16: 512,
-  Fmt.FMT_NUM_PK32_F32: 1024,
-  Fmt.FMT_NUM_PK32_FP6: 192,
-  Fmt.FMT_NUM_PK32_FP8: 256,
-  Fmt.FMT_NUM_PK32_I32: 1024,
-  Fmt.FMT_NUM_PK32_I8: 256,
-  Fmt.FMT_NUM_PK4_B8: 32,
-  Fmt.FMT_NUM_PK4_BF16: 64,
-  Fmt.FMT_NUM_PK4_BF8: 32,
-  Fmt.FMT_NUM_PK4_F16: 64,
-  Fmt.FMT_NUM_PK4_F32: 128,
-  Fmt.FMT_NUM_PK4_F64: 256,
-  Fmt.FMT_NUM_PK4_FP8: 32,
-  Fmt.FMT_NUM_PK4_I32: 128,
-  Fmt.FMT_NUM_PK4_I8: 32,
-  Fmt.FMT_NUM_PK4_IU8: 32,
-  Fmt.FMT_NUM_PK4_U8: 32,
-  Fmt.FMT_NUM_PK8_B32: 256,
-  Fmt.FMT_NUM_PK8_BF16: 128,
-  Fmt.FMT_NUM_PK8_BF8: 64,
-  Fmt.FMT_NUM_PK8_F16: 128,
-  Fmt.FMT_NUM_PK8_FP8: 64,
-  Fmt.FMT_NUM_PK8_I4: 32,
-  Fmt.FMT_NUM_PK8_I8: 64,
-  Fmt.FMT_NUM_PK8_IU4: 32,
-  Fmt.FMT_NUM_PK8_U4: 32,
-  Fmt.FMT_NUM_PK8_U8: 64,
-  Fmt.FMT_NUM_PK_F16: 32,
-  Fmt.FMT_NUM_PK_I16: 32,
-  Fmt.FMT_NUM_PK_I8: 32,
-  Fmt.FMT_NUM_PK_U16: 32,
-  Fmt.FMT_NUM_PK_U8: 32,
-  Fmt.FMT_NUM_U16: 16,
-  Fmt.FMT_NUM_U24: 24,
-  Fmt.FMT_NUM_U32: 32,
-  Fmt.FMT_NUM_U4: 4,
-  Fmt.FMT_NUM_U64: 64,
-  Fmt.FMT_NUM_U8: 8,
-  Fmt.FMT_RSRC: 128,
-  Fmt.FMT_RSRC_SCALAR: 128,
-  Fmt.FMT_RSRC_SCRATCH: 128,
-  Fmt.FMT_RSRC_SCRATCH_BYTE: 128,
-  Fmt.FMT_RSRC_SCRATCH_STRIDE: 128,
-  Fmt.FMT_RSRC_TYPED: 128,
-  Fmt.FMT_RSRC_TYPED_BYTE: 128,
-  Fmt.FMT_RSRC_TYPED_SCRATCH: 128,
-  Fmt.FMT_RSRC_TYPED_STRIDE: 128,
-  Fmt.FMT_RSRC_VECTOR: 128,
-  Fmt.FMT_RSRC_VECTOR_BYTE: 128,
-  Fmt.FMT_RSRC_VECTOR_STRIDE: 128,
-  Fmt.FMT_SAMP: 128,
-  Fmt.FMT_WMMA_AB_16X16_BF16: 128,
-  Fmt.FMT_WMMA_AB_16X16_BF8: 64,
-  Fmt.FMT_WMMA_AB_16X16_F16: 128,
-  Fmt.FMT_WMMA_AB_16X16_FP8: 64,
-  Fmt.FMT_WMMA_AB_16X16_IU4: 32,
-  Fmt.FMT_WMMA_AB_16X16_IU8: 64,
-  Fmt.FMT_WMMA_AB_16X32_BF16: 256,
-  Fmt.FMT_WMMA_AB_16X32_BF8: 128,
-  Fmt.FMT_WMMA_AB_16X32_F16: 256,
-  Fmt.FMT_WMMA_AB_16X32_FP8: 128,
-  Fmt.FMT_WMMA_AB_16X32_IU4: 64,
-  Fmt.FMT_WMMA_AB_16X32_IU8: 128,
-  Fmt.FMT_WMMA_AB_16X64_IU4: 128,
-  Fmt.FMT_WMMA_AB_BF16: 256,
-  Fmt.FMT_WMMA_AB_F16: 256,
-  Fmt.FMT_WMMA_AB_IU4: 64,
-  Fmt.FMT_WMMA_AB_IU8: 128,
-  Fmt.FMT_WMMA_DC_16X16_BF16: 128,
-  Fmt.FMT_WMMA_DC_16X16_F16: 128,
-  Fmt.FMT_WMMA_DC_16X16_F32: 256,
-  Fmt.FMT_WMMA_DC_16X16_I32: 256,
-  Fmt.FMT_WMMA_DC_BF16: 256,
-  Fmt.FMT_WMMA_DC_F16: 256,
-  Fmt.FMT_WMMA_DC_F32: 256,
-  Fmt.FMT_WMMA_DC_I32: 256,
-  Fmt.FMT_WMMA_INDEX_SET: 32,
-}
-
-class OpType(Enum):
-  OPR_ACCVGPR = auto()
-  OPR_ATTR = auto()
-  OPR_CLAUSE = auto()
-  OPR_DELAY = auto()
-  OPR_EXEC = auto()
-  OPR_HWREG = auto()
-  OPR_LABEL = auto()
-  OPR_SDST = auto()
-  OPR_SDST_NULL = auto()
-  OPR_SENDMSG = auto()
-  OPR_SENDMSG_RTN = auto()
-  OPR_SIMM16 = auto()
-  OPR_SIMM24 = auto()
-  OPR_SIMM4 = auto()
-  OPR_SIMM5 = auto()
-  OPR_SIMM8 = auto()
-  OPR_SLEEP = auto()
-  OPR_SMEM_OFFSET = auto()
-  OPR_SMEM_OFFSET_NOK = auto()
-  OPR_SRC = auto()
-  OPR_SRC_ACCVGPR = auto()
-  OPR_SRC_NOLDS = auto()
-  OPR_SRC_NOLIT = auto()
-  OPR_SRC_SIMPLE = auto()
-  OPR_SRC_VGPR = auto()
-  OPR_SRC_VGPR_OR_ACCVGPR = auto()
-  OPR_SRC_VGPR_OR_ACCVGPR_OR_CONST = auto()
-  OPR_SRC_VGPR_OR_INLINE = auto()
-  OPR_SREG = auto()
-  OPR_SREG_LITERAL = auto()
-  OPR_SREG_M0 = auto()
-  OPR_SREG_M0_INL = auto()
-  OPR_SREG_NOVCC = auto()
-  OPR_SSRC = auto()
-  OPR_SSRC_BARRIER_ID = auto()
-  OPR_SSRC_LANESEL = auto()
-  OPR_SSRC_NOLIT = auto()
-  OPR_TGT = auto()
-  OPR_VERSION = auto()
-  OPR_VGPR = auto()
-  OPR_VGPR_OR_ACCVGPR = auto()
-  OPR_VGPR_OR_LDS = auto()
-  OPR_WAITCNT = auto()
-  OPR_WAITCNT_DEPCTR = auto()
-  OPR_WAIT_ALU = auto()
-  OPR_WAIT_EVENT = auto()
-  OPR_WAIT_MEM_DS = auto()
@@ -1,907 +0,0 @@
-# RDNA3/RDNA4/CDNA disassembler
-from __future__ import annotations
-import re, struct
-from typing import Callable
-from extra.assembly.amd.dsl import Inst, Reg
-
-# Special register mappings for disassembly
-SPECIAL_GPRS = {106: 'vcc_lo', 107: 'vcc_hi', 124: 'null', 125: 'm0', 126: 'exec_lo', 127: 'exec_hi',
-                128: '0', 240: '0.5', 241: '-0.5', 242: '1.0', 243: '-1.0', 244: '2.0', 245: '-2.0', 246: '4.0', 247: '-4.0', 248: '0x3e22f983', 253: 'scc'}
-SPECIAL_GPRS_CDNA = {106: 'vcc_lo', 107: 'vcc_hi', 124: 'm0', 126: 'exec_lo', 127: 'exec_hi',
-                     128: '0', 240: '0.5', 241: '-0.5', 242: '1.0', 243: '-1.0', 244: '2.0', 245: '-2.0', 246: '4.0', 247: '-4.0', 248: '0x3e22f983', 253: 'scc',
-                     102: 'flat_scratch_lo', 103: 'flat_scratch_hi', 104: 'xnack_mask_lo', 105: 'xnack_mask_hi',
-                     251: 'src_vccz', 252: 'src_execz'}
-SPECIAL_PAIRS = {106: 'vcc', 126: 'exec'}
-SPECIAL_PAIRS_CDNA = {106: 'vcc', 126: 'exec', 102: 'flat_scratch', 104: 'xnack_mask'}
-
-def decode_src(v, cdna: bool = False) -> str:
-  """Decode a source operand encoding to its string representation."""
-  v = _unwrap(v)
-  gprs = SPECIAL_GPRS_CDNA if cdna else SPECIAL_GPRS
-  if v in gprs: return gprs[v]
-  if v < 106: return f's{v}'
-  if 108 <= v < 124: return f'ttmp{v - 108}'
-  if 129 <= v <= 192: return str(v - 128)  # positive integers 1-64
-  if 193 <= v <= 208: return str(-(v - 192))  # negative integers -1 to -16
-  if v >= 256: return f'v{v - 256}'
-  return f's{v}'
-
-def _unwrap(v) -> int:
-  """Unwrap Reg to int offset, or return int as-is."""
-  return v.offset if isinstance(v, Reg) else v
-
-def _vi(v) -> int:
-  """Get VGPR index from Reg or int (for v[N] fields that encode as 256+N)."""
-  off = _unwrap(v)
-  return off - 256 if off >= 256 else off
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# LITERAL FORMATTING
-# ═══════════════════════════════════════════════════════════════════════════════
-
-_FLOAT_DEC = {240: 0.5, 241: -0.5, 242: 1.0, 243: -1.0, 244: 2.0, 245: -2.0, 246: 4.0, 247: -4.0}
-
-def _lit(inst, v, neg=0, cdna=None) -> str:
-  """Format literal/inline constant value."""
-  if cdna is None: cdna = _is_cdna(inst)
-  v = _unwrap(v)
-  if v == 255:
-    lit = inst._literal
-    if lit is None: return "0"
-    s = f"0x{lit:x}"
-  elif v in _FLOAT_DEC: s = str(_FLOAT_DEC[v])
-  elif 128 <= v <= 192: s = str(v - 128)
-  elif 193 <= v <= 208: s = str(-(v - 192))
-  elif v < 128: s = decode_src(v, cdna)
-  elif v >= 256: s = f"v{v - 256}"
-  else: s = decode_src(v, cdna)
-  return f"-{s}" if neg else s
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# INSTRUCTION METADATA - fallback functions when inst.num_srcs()/inst.operands unavailable
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def _num_srcs(inst) -> int:
-  """Fallback: get number of source operands from instruction name."""
-  name = getattr(inst, 'op_name', '') or ''
-  n = name.upper()
-  # FMAC/MAC ops are 2-source (dst is implicit accumulator), but FMA/MAD ops are 3-source
-  if 'FMAC' in n or 'V_MAC_' in n: return 2
-  if any(x in n for x in ('FMA', 'MAD', 'CNDMASK', 'BFE', 'BFI', 'LERP', 'MED3', 'SAD', 'DIV_FMAS', 'DIV_FIXUP', 'DIV_SCALE', 'CUBE')): return 3
-  # PERMLANE_VAR ops are 2-source, but PERMLANE (non-VAR) are 3-source
-  if 'PERMLANE' in n and '_VAR' not in n: return 3
-  if any(x in n for x in ('_ADD3', '_LSHL_ADD', '_ADD_LSHL', '_LSHL_OR', '_AND_OR', 'OR3_B32', 'AND_OR_B32', 'ALIGNBIT', 'ALIGNBYTE', 'V_PERM_', 'XOR3', 'XAD', 'MULLIT', 'MINMAX', 'MAXMIN', 'MINIMUMMAXIMUM', 'MAXIMUMMINIMUM', 'MINIMUM3', 'MAXIMUM3', 'MIN3', 'MAX3', 'DOT2', 'CVT_PK_U8_F32', 'DOT4', 'DOT8', 'WMMA', 'SWMMAC')): return 3
-  return 2
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# IMPORTS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP1_SDST, VOP1_SDST_LIT, VOP1_LIT, VOP2, VOP2_LIT, VOP3, VOP3_SDST, VOP3_SDST_LIT,
-  VOP3_LIT, VOP3SD, VOP3SD_LIT, VOP3P, VOP3P_LIT, VOPC, VOPC_LIT, VOPD, VOPD_LIT, VINTERP, SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPC_LIT,
-  SOPK, SOPK_LIT, SOPP, SMEM, DS, FLAT, GLOBAL, SCRATCH, VOP2Op, VOPDOp, SOPPOp, HWREG, MSG)
-from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP1_SDST as R4_VOP1_SDST, VOP1_SDST_LIT as R4_VOP1_SDST_LIT, VOP1_LIT as R4_VOP1_LIT,
-  VOP2 as R4_VOP2, VOP2_LIT as R4_VOP2_LIT, VOP3 as R4_VOP3, VOP3_SDST as R4_VOP3_SDST, VOP3_SDST_LIT as R4_VOP3_SDST_LIT, VOP3_LIT as R4_VOP3_LIT,
-  VOP3SD as R4_VOP3SD, VOP3SD_LIT as R4_VOP3SD_LIT, VOP3P as R4_VOP3P, VOP3P_LIT as R4_VOP3P_LIT, VOPC as R4_VOPC, VOPC_LIT as R4_VOPC_LIT,
-  VOPD as R4_VOPD, VOPD_LIT as R4_VOPD_LIT, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP1_LIT as R4_SOP1_LIT, SOP2 as R4_SOP2, SOP2_LIT as R4_SOP2_LIT,
-  SOPC as R4_SOPC, SOPC_LIT as R4_SOPC_LIT, SOPK as R4_SOPK, SOPK_LIT as R4_SOPK_LIT, SOPP as R4_SOPP, SMEM as R4_SMEM, DS as R4_DS,
-  VOPDOp as R4_VOPDOp, HWREG as HWREG_RDNA4, VFLAT as R4_FLAT, VGLOBAL as R4_GLOBAL, VSCRATCH as R4_SCRATCH)
-from extra.assembly.amd.autogen.cdna.ins import FLAT as C_FLAT, HWREG as HWREG_CDNA
-
-def _is_cdna(inst: Inst) -> bool: return 'cdna' in inst.__class__.__module__
-def _is_r4(inst: Inst) -> bool: return 'rdna4' in inst.__class__.__module__
-
-# CDNA opcode name aliases for disasm (new name -> old name expected by tests)
-_CDNA_DISASM_ALIASES = {'v_fmac_f64': 'v_mul_legacy_f32', 'v_dot2c_f32_bf16': 'v_mac_f32', 'v_fmamk_f32': 'v_madmk_f32', 'v_fmaak_f32': 'v_madak_f32'}
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# HELPERS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def _reg(p: str, b: int, n: int = 1) -> str: return f"{p}{_unwrap(b)}" if n == 1 else f"{p}[{_unwrap(b)}:{_unwrap(b)+n-1}]"
-def _sreg(b: int, n: int = 1) -> str: return _reg("s", _unwrap(b), n)
-def _vreg(b: int, n: int = 1) -> str: b = _unwrap(b); return _reg("v", b - 256 if b >= 256 else b, n)
-def _areg(b: int, n: int = 1) -> str: b = _unwrap(b); return _reg("a", b - 256 if b >= 256 else b, n)  # accumulator registers for GFX90a
-def _ttmp(b, n: int = 1) -> str | None: b = _unwrap(b); return _reg("ttmp", b - 108, n) if 108 <= b <= 123 else None
-
-def _fmt_sdst(v, n: int = 1, cdna: bool = False) -> str:
-  v = _unwrap(v)
-  if t := _ttmp(v, n): return t
-  pairs = SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS
-  gprs = SPECIAL_GPRS_CDNA if cdna else SPECIAL_GPRS
-  if n > 1: return pairs.get(v) or gprs.get(v) or _sreg(v, n)  # also check gprs for null/m0
-  return gprs.get(v, f"s{v}")
-
-def _fmt_src(v, n: int = 1, cdna: bool = False) -> str:
-  v = _unwrap(v)
-  if v == 253: return "src_scc"  # SCC as source operand
-  if n == 1: return decode_src(v, cdna)
-  if v >= 256: return _vreg(v, n)
-  if v <= 101: return _sreg(v, n)  # s0-s101 can be pairs, but 102+ are special on CDNA
-  pairs = SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS
-  if n == 2 and v in pairs: return pairs[v]
-  if v <= 105: return _sreg(v, n)  # s102-s105 regular pairs for RDNA
-  if t := _ttmp(v, n): return t
-  return decode_src(v, cdna)
-
-def _fmt_v16(v, base: int = 256, hi_thresh: int = 384) -> str:
-  v = _unwrap(v)
-  return f"v{(v - base) & 0x7f}.{'h' if v >= hi_thresh else 'l'}"
-
-def _has(op: str, *subs) -> bool: return any(s in op for s in subs)
-def _omod(v: int) -> str: return {1: " mul:2", 2: " mul:4", 3: " div:2"}.get(v, "")
-def _src16(inst, v: int) -> str: v = _unwrap(v); return _fmt_v16(v) if v >= 256 else _lit(inst, v)  # format 16-bit src: vgpr.h/l or literal
-def _mods(*pairs) -> str: return " ".join(m for c, m in pairs if c)
-def _fmt_bits(label: str, val: int, count: int) -> str: return f"{label}:[{','.join(str((val >> i) & 1) for i in range(count))}]"
-
-def _vop3_src(inst, v: int, neg: int, abs_: int, hi: int, n: int, f16: bool) -> str:
-  """Format VOP3 source operand with modifiers."""
-  v = _unwrap(v)
-  if v == 255: s = _lit(inst, v)  # literal constant takes priority
-  elif n > 1: s = _fmt_src(v, n)
-  elif f16 and v >= 256: s = f"v{v - 256}.h" if hi else f"v{v - 256}.l"
-  elif v == 253: s = "src_scc"  # VOP3 sources use src_scc not scc
-  else: s = _lit(inst, v)
-  if abs_: s = f"|{s}|"
-  return f"-{s}" if neg else s
-
-def _opsel_str(opsel: int, n: int, need: bool, is16_d: bool) -> str:
-  """Format op_sel modifier string."""
-  if not need: return ""
-  dst_hi = (opsel >> 3) & 1
-  if n == 1: return f" op_sel:[{opsel & 1},{dst_hi}]"
-  # Use 4-element format if bit 2 is set (src2 selection used) or if 3+ sources
-  if n == 2 and not ((opsel >> 2) & 1): return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{dst_hi}]"
-  return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1},{dst_hi}]"
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# DISASSEMBLER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def _disasm_vop1(inst: VOP1) -> str:
-  name, cdna = inst.op_name.lower() or f'vop1_op_{inst.op}', _is_cdna(inst)
-  name = name.replace('_e32', '')  # Strip _e32 suffix
-  if any(x in name for x in ('v_nop', 'v_pipeflush', 'v_clrexcp')): return name  # no operands
-  if 'readfirstlane' in name:
-    src = inst.src0.fmt() if inst.src0.offset >= 256 else decode_src(inst.src0.offset, cdna)
-    vdst_off = inst.vdst.offset - 256 if inst.vdst.offset >= 256 else inst.vdst.offset
-    return f"{name} {_fmt_sdst(vdst_off, 1, cdna)}, {src}"
-  bits = inst.canonical_op_bits
-  is16_dst, is16_src = not cdna and bits['d'] == 16, not cdna and bits['s0'] == 16
-  # Format dst
-  if is16_dst: dst = _fmt_v16(inst.vdst)
-  else: dst = inst.vdst.fmt()
-  # Format src
-  if inst.src0.offset == 255: src = _lit(inst, inst.src0)
-  elif is16_src and inst.src0.offset >= 256: src = _fmt_v16(inst.src0)
-  elif inst.src0.sz > 1: src = _fmt_src(inst.src0, inst.src0.sz, cdna)
-  else: src = _lit(inst, inst.src0)
-  return f"{name} {dst}, {src}"
-
-_VOP2_CARRY_OUT = {'v_add_co_u32', 'v_sub_co_u32', 'v_subrev_co_u32'}  # carry out only
-_VOP2_CARRY_INOUT = {'v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'}  # carry in and out (CDNA)
-_VOP2_CARRY_INOUT_RDNA = {'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'}  # carry in and out (RDNA)
-def _disasm_vop2(inst: VOP2) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  if cdna: name = _CDNA_DISASM_ALIASES.get(name, name)  # apply CDNA aliases
-  suf = "" if cdna or name.endswith('_e32') or (not cdna and inst.op == VOP2Op.V_DOT2ACC_F32_F16_E32) else "_e32"
-  lit = inst._literal
-  is16 = not cdna and inst.canonical_op_bits['d'] == 16
-  # fmaak/madak: dst = src0 * vsrc1 + K, fmamk/madmk: dst = src0 * K + vsrc1
-  if 'fmaak' in name or 'madak' in name or (not cdna and inst.op in (VOP2Op.V_FMAAK_F32_E32, VOP2Op.V_FMAAK_F16_E32)):
-    if lit is None: return f"op_{inst.op.value if hasattr(inst.op, 'value') else inst.op}"
-    if is16: return f"{name}{suf} {_fmt_v16(inst.vdst)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1)}, 0x{lit:x}"
-    return f"{name}{suf} {inst.vdst.fmt()}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}, 0x{lit:x}"
-  if 'fmamk' in name or 'madmk' in name or (not cdna and inst.op in (VOP2Op.V_FMAMK_F32_E32, VOP2Op.V_FMAMK_F16_E32)):
-    if lit is None: return f"op_{inst.op.value if hasattr(inst.op, 'value') else inst.op}"
-    if is16: return f"{name}{suf} {_fmt_v16(inst.vdst)}, {_src16(inst, inst.src0)}, 0x{lit:x}, {_fmt_v16(inst.vsrc1)}"
-    return f"{name}{suf} {inst.vdst.fmt()}, {_lit(inst, inst.src0)}, 0x{lit:x}, {inst.vsrc1.fmt()}"
-  if is16: return f"{name}{suf} {_fmt_v16(inst.vdst)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1)}"
-  vcc = "vcc" if cdna else "vcc_lo"
-  basename = name.replace('_e32', '')
-  if cdna and basename in _VOP2_CARRY_OUT: return f"{name}{suf} {inst.vdst.fmt()}, {vcc}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}"
-  if cdna and basename in _VOP2_CARRY_INOUT: return f"{name}{suf} {inst.vdst.fmt()}, {vcc}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}, {vcc}"
-  if not cdna and basename in _VOP2_CARRY_INOUT_RDNA: return f"{name}{suf} {inst.vdst.fmt()}, {vcc}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}, {vcc}"
-  sn0 = inst.canonical_op_regs.get('s0', 1)
-  if inst.vdst.sz > 1 or sn0 > 1 or inst.vsrc1.sz > 1:
-    src0 = _lit(inst, inst.src0) if inst.src0.offset == 255 else _fmt_src(inst.src0, sn0, cdna)
-    return f"{name.replace('_e32', '')} {inst.vdst.fmt()}, {src0}, {inst.vsrc1.fmt()}"
-  return f"{name}{suf} {inst.vdst.fmt()}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}" + (f", {vcc}" if name == 'v_cndmask_b32' else "")
-
-def _disasm_vopc(inst: VOPC) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  bits = inst.canonical_op_bits
-  is16 = bits['s0'] == 16
-  if cdna:
-    s0 = _lit(inst, inst.src0) if inst.src0.offset == 255 else _fmt_src(inst.src0, inst.src0.sz, cdna)
-    return f"{name} vcc, {s0}, {inst.vsrc1.fmt()}"  # CDNA VOPC always outputs vcc
-  # RDNA: v_cmpx_* writes to exec (no vcc), v_cmp_* writes to vcc_lo
-  has_vcc = 'cmpx' not in name
-  s0 = _lit(inst, inst.src0) if inst.src0.offset == 255 else inst.src0.fmt() if inst.src0.sz > 1 else _src16(inst, inst.src0.offset) if is16 else _lit(inst, inst.src0)
-  s1 = inst.vsrc1.fmt() if inst.vsrc1.sz > 1 else _fmt_v16(inst.vsrc1) if is16 else inst.vsrc1.fmt()
-  suf = "" if name.endswith('_e32') else "_e32"
-  return f"{name}{suf} vcc_lo, {s0}, {s1}" if has_vcc else f"{name}{suf} {s0}, {s1}"
-
-NO_ARG_SOPP = {SOPPOp.S_BARRIER, SOPPOp.S_WAKEUP, SOPPOp.S_ICACHE_INV,
-               SOPPOp.S_WAIT_IDLE, SOPPOp.S_ENDPGM_SAVED, SOPPOp.S_CODE_END, SOPPOp.S_ENDPGM_ORDERED_PS_DONE, SOPPOp.S_TTRACEDATA}
-
-def _disasm_sopp(inst: SOPP) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  is_rdna4 = _is_r4(inst)
-  # Ops that have no argument when simm16 == 0
-  no_arg_zero = {'s_barrier', 's_wakeup', 's_icache_inv', 's_ttracedata', 's_wait_idle', 's_endpgm_saved',
-                 's_endpgm_ordered_ps_done', 's_code_end'}
-  if name in no_arg_zero: return name if inst.simm16 == 0 else f"{name} {inst.simm16}"
-  if name == 's_endpgm': return name if inst.simm16 == 0 else f"{name} {inst.simm16}"
-  if cdna:
-    if name == 's_waitcnt':
-      # GFX9 format: vmcnt[3:0]=bits[3:0], vmcnt[5:4]=bits[15:14], expcnt=bits[6:4], lgkmcnt=bits[11:8] (4 bits, max 15)
-      vm_lo, exp, lgkm, vm_hi = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 8) & 0xf, (inst.simm16 >> 14) & 0x3
-      vm = vm_lo | (vm_hi << 4)
-      p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0xf else ""]
-      return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
-    if name.startswith(('s_cbranch', 's_branch')): return f"{name} {inst.simm16}"
-    if name == 's_set_gpr_idx_mode':
-      flags = [n for i, n in enumerate(['SRC0', 'SRC1', 'SRC2', 'DST']) if inst.simm16 & (1 << i)]
-      return f"{name} gpr_idx({','.join(flags)})"
-    return f"{name} 0x{inst.simm16:x}" if inst.simm16 else name
-  # RDNA (use name-based checks instead of enum-based for cross-arch compatibility)
-  if name == 's_waitcnt':
-    if is_rdna4:
-      return f"{name} {inst.simm16}" if inst.simm16 else f"{name} 0"
-    vm, exp, lgkm = (inst.simm16 >> 10) & 0x3f, inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x3f
-    p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0x3f else ""]
-    return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
-  if name == 's_delay_alu':
-    deps = ['VALU_DEP_1','VALU_DEP_2','VALU_DEP_3','VALU_DEP_4','TRANS32_DEP_1','TRANS32_DEP_2','TRANS32_DEP_3','FMA_ACCUM_CYCLE_1','SALU_CYCLE_1','SALU_CYCLE_2','SALU_CYCLE_3']
-    skips = ['SAME','NEXT','SKIP_1','SKIP_2','SKIP_3','SKIP_4']
-    id0, skip, id1 = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 7) & 0xf
-    dep = lambda v: deps[v-1] if 0 < v <= len(deps) else str(v)
-    p = [f"instid0({dep(id0)})" if id0 else "", f"instskip({skips[skip]})" if skip else "", f"instid1({dep(id1)})" if id1 else ""]
-    return f"s_delay_alu {' | '.join(x for x in p if x) or '0'}"
-  if name.startswith(('s_cbranch', 's_branch')): return f"{name} {inst.simm16}"
-  return f"{name} 0x{inst.simm16:x}"
-
-def _disasm_smem(inst: SMEM) -> str:
-  name, cdna = inst.op_name.lower(), _is_cdna(inst)
-  if name in ('s_gl1_inv', 's_dcache_inv', 's_dcache_inv_vol', 's_dcache_wb', 's_dcache_wb_vol', 's_icache_inv'): return name
-  soe, imm = getattr(inst, 'soe', 0) or getattr(inst, 'soffset_en', 0), getattr(inst, 'imm', 1)
-  is_rdna4 = _is_r4(inst)
-  offset = inst.ioffset if is_rdna4 else getattr(inst, 'offset', 0)
-  if cdna:
-    if soe and imm: off_s = f"{decode_src(inst.soffset, cdna)} offset:0x{offset:x}"
-    elif imm: off_s = f"0x{offset:x}"
-    elif offset < 256: off_s = decode_src(offset, cdna)
-    else: off_s = decode_src(inst.soffset, cdna)
-  elif offset and inst.soffset != 124: off_s = f"{decode_src(inst.soffset, cdna)} offset:0x{offset:x}"
-  elif offset: off_s = f"0x{offset:x}"
-  else: off_s = decode_src(inst.soffset, cdna)
-  is_buffer = 'buffer' in name or 's_atc_probe_buffer' == name
-  sbase_idx, sbase_count = _unwrap(inst.sbase), 4 if is_buffer else 2
-  sbase_str = _fmt_src(sbase_idx, sbase_count, cdna) if sbase_count == 2 else _sreg(sbase_idx, sbase_count) if sbase_idx <= 105 else _reg("ttmp", sbase_idx - 108, sbase_count)
-  if name in ('s_atc_probe', 's_atc_probe_buffer'): return f"{name} {_unwrap(inst.sdata)}, {sbase_str}, {off_s}"
-  if 'prefetch' in name:
-    off = getattr(inst, 'ioffset', getattr(inst, 'offset', 0))
-    if off >= 0x800000: off = off - 0x1000000
-    off_s = f"0x{off:x}" if off > 255 else str(off)
-    soff_s = decode_src(inst.soffset, cdna) if inst.soffset != 124 else ("m0" if cdna else "null")
-    if 'pc_rel' in name: return f"{name} {off_s}, {soff_s}, {_unwrap(inst.sdata)}"
-    return f"{name} {sbase_str}, {off_s}, {soff_s}, {_unwrap(inst.sdata)}"
-  # Use get_field_bits for register count
-  dst_n = inst.canonical_op_regs.get('d', 1)
-  th, scope = getattr(inst, 'th', 0), getattr(inst, 'scope', 0)
-  if is_rdna4:  # RDNA4 uses th/scope instead of glc/dlc
-    th_names = ['TH_LOAD_RT', 'TH_LOAD_NT', 'TH_LOAD_HT', 'TH_LOAD_LU']
-    scope_names = ['SCOPE_CU', 'SCOPE_SE', 'SCOPE_DEV', 'SCOPE_SYS']
-    mods = (f" th:{th_names[th]}" if th else "") + (f" scope:{scope_names[scope]}" if scope else "")
-    return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}, {sbase_str}, {off_s}{mods}"
-  if th or scope:
-    th_names = ['TH_LOAD_RT', 'TH_LOAD_NT', 'TH_LOAD_HT', 'TH_LOAD_LU']
-    scope_names = ['SCOPE_CU', 'SCOPE_SE', 'SCOPE_DEV', 'SCOPE_SYS']
-    mods = (f" th:{th_names[th]}" if th else "") + (f" scope:{scope_names[scope]}" if scope else "")
-    return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}, {sbase_str}, {off_s}{mods}"
-  if 'discard' in name: return f"{name} {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (getattr(inst, 'dlc', 0), " dlc"))
-  if name in ('s_memrealtime', 's_memtime'): return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}"
-  return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}, {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (getattr(inst, 'dlc', 0), " dlc"))
-
-def _disasm_flat(inst: FLAT) -> str:
-  name, cdna, r4 = inst.op_name.lower(), _is_cdna(inst), _is_r4(inst)
-  acc = getattr(inst, 'acc', 0)
-  reg_fn = _areg if acc else _vreg
-  if r4: seg = 'flat' if (cls_name:=inst.__class__.__name__) == 'VFLAT' else ('global' if cls_name == 'VGLOBAL' else 'scratch')
-  else: seg = ['flat', 'scratch', 'global'][inst.seg] if inst.seg < 3 else 'flat'
-  instr = f"{seg}_{name.split('_', 1)[1] if '_' in name else name}"
-  # Global/scratch uses 13-bit signed offset
-  offset = inst.ioffset if r4 else inst.offset
-  if seg != 'flat':
-    if cdna:
-      # CDNA: bit 12 is sign bit but not in offset field
-      raw = int.from_bytes(inst.to_bytes(), 'little')
-      off_val = offset | ((raw >> 12) & 1) << 12  # get bit 12
-    else:
-      off_val = offset
-    off_val = off_val if off_val < 4096 else off_val - 8192  # sign extend 13-bit
-  else:
-    off_val = offset
-  # Use get_field_bits: data for stores/atomics, d for loads
-  regs = inst.canonical_op_regs
-  w = regs.get('data', regs.get('d', 1)) if 'store' in name or 'atomic' in name else regs.get('d', 1)
-  off_s = f" offset:{off_val}" if off_val else ""
-  if cdna: mods = f"{off_s}{' sc0' if inst.sc0 else ''}{' nt' if inst.nt else ''}{' sc1' if getattr(inst, 'sc1', 0) else ''}"
-  elif r4: mods = f"{off_s}{' scope' if inst.scope else ''}{' th' if inst.th else ''}"
-  else: mods = f"{off_s}{' glc' if inst.glc else ''}{' slc' if inst.slc else ''}{' dlc' if inst.dlc else ''}"
-  if seg == 'flat': saddr_s = ""
-  elif _unwrap(inst.saddr) in (0x7F, 124): saddr_s = ", off"
-  elif seg == 'scratch': saddr_s = f", {decode_src(inst.saddr, cdna)}"
-  elif _unwrap(inst.saddr) in (SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS): saddr_s = f", {(SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS)[_unwrap(inst.saddr)]}"
-  elif t := _ttmp(inst.saddr, 2): saddr_s = f", {t}"
-  else: saddr_s = f", {_sreg(inst.saddr, 2) if _unwrap(inst.saddr) < 106 else decode_src(_unwrap(inst.saddr), cdna)}"
-  if 'addtid' in name: return f"{instr} {reg_fn(inst.data if 'store' in name else inst.vdst)}{saddr_s}{mods}"
-  # RDNA4: vaddr instead of addr, vsrc instead of data
-  addr = inst.vaddr if r4 else inst.addr
-  data = inst.vsrc if r4 else inst.data
-  # load_lds_* instructions: vaddr, saddr (no vdst, data goes to LDS)
-  if 'load_lds' in name:
-    addr_w = 1 if seg == 'scratch' or (_unwrap(inst.saddr) not in (0x7F, 124)) else 2
-    addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(addr, addr_w)
-    return f"{instr} {addr_s}{saddr_s}{mods}"
-  if seg == 'flat': addr_w = 2  # flat always uses 64-bit vaddr
-  elif cdna: addr_w = 1 if seg == 'scratch' or (_unwrap(inst.saddr) not in (0x7F, 124)) else 2
-  else: addr_w = 1 if seg == 'scratch' or (_unwrap(inst.saddr) not in (0x7F, 124)) else 2
-  addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(addr, addr_w)
-  data_s, vdst_s = reg_fn(data, w), reg_fn(inst.vdst, w // 2 if 'cmpswap' in name else w)
-  if 'atomic' in name:
-    glc_or_sc0 = inst.sc0 if cdna else inst.glc
-    return f"{instr} {vdst_s}, {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}" if glc_or_sc0 else f"{instr} {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}"
-  if 'store' in name: return f"{instr} {addr_s}, {data_s}{saddr_s}{mods}"
-  return f"{instr} {reg_fn(inst.vdst, w)}, {addr_s}{saddr_s}{mods}"
-
-def _disasm_ds(inst: DS) -> str:
-  op, name = inst.op, inst.op_name.lower()
-  acc = getattr(inst, 'acc', 0)
-  reg_fn = _areg if acc else _vreg
-  gds = " gds" if getattr(inst, 'gds', 0) else ""
-  off = f" offset:{inst.offset0 | (inst.offset1 << 8)}" if inst.offset0 or inst.offset1 else ""
-  off2 = (" offset0:" + str(inst.offset0) if inst.offset0 else "") + (" offset1:" + str(inst.offset1) if inst.offset1 else "")
-  # Use get_field_bits: data for stores/writes/atomics, d for loads
-  regs = inst.canonical_op_regs
-  w = regs.get('data', regs.get('d', 1)) if 'store' in name or 'write' in name or ('load' not in name and 'read' not in name) else regs.get('d', 1)
-  d0, d1, dst, addr = reg_fn(inst.data0, w), reg_fn(inst.data1, w), reg_fn(inst.vdst, w), _vreg(inst.addr)
-
-  if name == 'ds_nop': return name
-  if name == 'ds_bvh_stack_rtn_b32': return f"{name} {_vreg(inst.vdst)}, {addr}, {_vreg(inst.data0)}, {_vreg(inst.data1, 4)}{off}{gds}"
-  if 'bvh_stack_push' in name:
-    d1_regs = 8 if 'push8' in name else 4
-    vdst_regs = 2 if 'pop2' in name else 1
-    vdst_s = _vreg(inst.vdst, vdst_regs) if vdst_regs > 1 else _vreg(inst.vdst)
-    return f"{name} {vdst_s}, {addr}, {_vreg(inst.data0)}, {_vreg(inst.data1, d1_regs)}{off}{gds}"
-  if 'gws_sema' in name and 'sema_br' not in name: return f"{name}{off}{gds}"
-  if 'gws_' in name: return f"{name} {addr}{off}{gds}"
-  if name in ('ds_consume', 'ds_append'): return f"{name} {reg_fn(inst.vdst)}{off}{gds}"
-  if 'gs_reg' in name: return f"{name} {reg_fn(inst.vdst, 2)}, {reg_fn(inst.data0)}{off}{gds}"
-  if '2addr' in name:
-    if 'load' in name: return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}{off2}{gds}"
-    if 'store' in name and 'xchg' not in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
-    return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}, {d0}, {d1}{off2}{gds}"
-  if 'write2' in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
-  if 'read2' in name: return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}{off2}{gds}"
-  if 'xchg2' in name: return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}, {d0}, {d1}{off2}{gds}"
-  if 'load' in name or ('read' in name and 'read2' not in name): return f"{name} {reg_fn(inst.vdst)}{off}{gds}" if 'addtid' in name else f"{name} {dst}, {addr}{off}{gds}"
-  if ('store' in name or 'write' in name) and not _has(name, 'cmp', 'xchg', 'write2'):
-    return f"{name} {reg_fn(inst.data0)}{off}{gds}" if 'addtid' in name else f"{name} {addr}, {d0}{off}{gds}"
-  if 'swizzle' in name or name == 'ds_ordered_count': return f"{name} {reg_fn(inst.vdst)}, {addr}{off}{gds}"
-  if 'permute' in name: return f"{name} {reg_fn(inst.vdst)}, {addr}, {reg_fn(inst.data0)}{off}{gds}"
-  if 'condxchg' in name: return f"{name} {reg_fn(inst.vdst, 2)}, {addr}, {reg_fn(inst.data0, 2)}{off}{gds}"
-  if _has(name, 'cmpst', 'mskor', 'wrap'):
-    return f"{name} {dst}, {addr}, {d0}, {d1}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}, {d1}{off}{gds}"
-  return f"{name} {dst}, {addr}, {d0}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}{off}{gds}"
-
-def _disasm_vop3(inst: VOP3) -> str:
-  op, name = inst.op, inst.op_name.lower()
-  n_up = name.upper()
-  bits = inst.canonical_op_bits
-
-  # RDNA4 v_s_* scalar VOP3 instructions - vdst is SGPR (VGPRField adds 256)
-  if name.startswith('v_s_'):
-    src = _lit(inst, inst.src0) if _unwrap(inst.src0) == 255 else ("src_scc" if _unwrap(inst.src0) == 253 else _fmt_src(inst.src0, max(1, bits['s0'] // 32)))
-    if inst.neg & 1: src = f"-{src}"
-    if inst.abs & 1: src = f"|{src}|"
-    clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
-    vdst_raw = _unwrap(inst.vdst)
-    return f"{name} s{vdst_raw - 256 if vdst_raw >= 256 else vdst_raw}, {src}" + (" clamp" if clamp else "") + _omod(inst.omod)
-
-  # Use get_field_bits for register sizes and 16-bit detection
-  r0, r1, r2 = max(1, bits['s0'] // 32), max(1, bits['s1'] // 32), max(1, bits['s2'] // 32)
-  dn = max(1, bits['d'] // 32)
-  is16_d, is16_s, is16_s2 = bits['d'] == 16, bits['s0'] == 16, bits['s2'] == 16
-
-  s0 = _vop3_src(inst, inst.src0, inst.neg&1, inst.abs&1, inst.opsel&1, r0, is16_s)
-  s1 = _vop3_src(inst, inst.src1, inst.neg&2, inst.abs&2, inst.opsel&2, r1, is16_s)
-  s2 = _vop3_src(inst, inst.src2, inst.neg&4, inst.abs&4, inst.opsel&4, r2, is16_s2)
-
-  # Format destination
-  if 'readlane' in name:
-    vdst_off = inst.vdst.offset - 256 if inst.vdst.offset >= 256 else inst.vdst.offset
-    dst = _fmt_sdst(vdst_off, 1)
-  elif is16_d: dst = f"{inst.vdst.fmt()}.h" if (inst.opsel & 8) else f"{inst.vdst.fmt()}.l"
-  else: dst = inst.vdst.fmt()
-
-  clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
-  cl, om = " clamp" if clamp else "", _omod(inst.omod)
-  nonvgpr_opsel = (inst.src0.offset < 256 and (inst.opsel & 1)) or (inst.src1.offset < 256 and (inst.opsel & 2)) or (inst.src2.offset < 256 and (inst.opsel & 4))
-  need_opsel = nonvgpr_opsel or (inst.opsel and not is16_s)
-
-  op_val = inst.op.value if hasattr(inst.op, 'value') else inst.op
-  e64 = "" if name.endswith('_e64') else "_e64"
-  if op_val < 256:  # VOPC
-    vdst_off = inst.vdst.offset - 256 if inst.vdst.offset >= 256 else inst.vdst.offset
-    return f"{name}{e64} {s0}, {s1}{cl}" if name.startswith('v_cmpx') else f"{name}{e64} {_fmt_sdst(vdst_off, 1)}, {s0}, {s1}{cl}"
-  if op_val < 384:  # VOP2
-    n = inst.num_srcs() or 2
-    os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
-    return f"{name}{e64} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name}{e64} {dst}, {s0}, {s1}{os}{cl}{om}"
-  if op_val < 512:  # VOP1
-    if re.match(r'v_cvt_f32_(bf|fp)8', name) and inst.opsel:
-      os = f" byte_sel:{((inst.opsel & 1) << 1) | ((inst.opsel >> 1) & 1)}"
-    else:
-      os = _opsel_str(inst.opsel, 1, need_opsel, is16_d)
-    if 'v_nop' in name or 'v_pipeflush' in name: return f"{name}{e64}"
-    return f"{name}{e64} {dst}, {s0}{os}{cl}{om}"
-  # Native VOP3
-  n = inst.num_srcs() or 2
-  os = f" byte_sel:{inst.opsel >> 2}" if 'cvt_sr' in name and inst.opsel else _opsel_str(inst.opsel, n, need_opsel, is16_d)
-  return f"{name} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{os}{cl}{om}"
-
-def _disasm_vop3sd(inst: VOP3SD) -> str:
-  name = inst.op_name.lower()
-  def src(reg, neg):
-    s = _lit(inst, reg.offset) if reg.offset == 255 else ("src_scc" if reg.offset == 253 else (reg.fmt() if reg.sz > 1 else _lit(inst, reg.offset)))
-    return f"neg({s})" if neg and reg.offset == 255 else (f"-{s}" if neg else s)
-  s0, s1, s2 = src(inst.src0, inst.neg & 1), src(inst.src1, inst.neg & 2), src(inst.src2, inst.neg & 4)
-  # VOP3SD: _co_ ops (add/sub) without _ci_ have only 2 sources, all others (mad, div_scale, _co_ci_) have 3 sources
-  has_only_two_srcs = '_co_' in name and '_ci_' not in name and 'mad' not in name
-  srcs = f"{s0}, {s1}" if has_only_two_srcs else f"{s0}, {s1}, {s2}"
-  clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
-  return f"{name} {inst.vdst.fmt()}, {_fmt_sdst(inst.sdst, 1)}, {srcs}{' clamp' if clamp else ''}{_omod(inst.omod)}"
-
-def _disasm_vopd(inst: VOPD) -> str:
-  lit = inst._literal
-  op_enum = R4_VOPDOp if _is_r4(inst) else VOPDOp
-  nx, ny = op_enum(inst.opx).name.lower(), op_enum(inst.opy).name.lower()
-  def half(n, vd, s0, vs1):
-    vd, vs1 = _vi(vd), _vi(vs1)
-    if 'mov' in n: return f"{n} v{vd}, {_lit(inst, s0)}"
-    if 'fmamk' in n and lit: return f"{n} v{vd}, {_lit(inst, s0)}, 0x{lit:x}, v{vs1}"
-    if 'fmaak' in n and lit: return f"{n} v{vd}, {_lit(inst, s0)}, v{vs1}, 0x{lit:x}"
-    return f"{n} v{vd}, {_lit(inst, s0)}, v{vs1}"
-  return f"{half(nx, inst.vdstx, inst.srcx0, inst.vsrcx1)} :: {half(ny, inst.vdsty, inst.srcy0, inst.vsrcy1)}"
-
-def _disasm_vop3p(inst: VOP3P) -> str:
-  name = inst.op_name.lower()
-  is_wmma, is_swmmac, n, is_fma_mix = 'wmma' in name, 'swmmac' in name, inst.num_srcs() or 2, 'fma_mix' in name
-  def get_src(reg):
-    return _lit(inst, reg.offset) if reg.offset == 255 else reg.fmt()
-  src0, src1, src2, dst = get_src(inst.src0), get_src(inst.src1), get_src(inst.src2), inst.vdst.fmt()
-  opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
-  clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
-  if is_fma_mix:
-    def m(s, neg, abs_): return f"-{f'|{s}|' if abs_ else s}" if neg else (f"|{s}|" if abs_ else s)
-    src0, src1, src2 = m(src0, inst.neg & 1, inst.neg_hi & 1), m(src1, inst.neg & 2, inst.neg_hi & 2), m(src2, inst.neg & 4, inst.neg_hi & 4)
-    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi else []) + (["clamp"] if clamp else [])
-  elif is_swmmac:
-    mods = ([f"index_key:{inst.opsel}"] if inst.opsel else []) + ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + \
-           ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if clamp else [])
-  else:
-    opsel_hi_default = 7 if n == 3 else 3
-    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != opsel_hi_default else []) + \
-           ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if clamp else [])
-  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
-
-def _disasm_sop1(inst: SOP1) -> str:
-  op, name, cdna = inst.op, inst.op_name.lower(), _is_cdna(inst)
-  # Use get_field_bits for register sizes
-  regs = inst.canonical_op_regs
-  dst_regs, src_regs = regs.get('d', 1), regs.get('s0', 1)
-  src = _lit(inst, inst.ssrc0) if _unwrap(inst.ssrc0) == 255 else _fmt_src(inst.ssrc0, src_regs, cdna)
-  if not cdna:
-    if 'getpc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2)}"
-    if 'setpc_b64' in name or 'rfe_b64' in name: return f"{name} {src}"
-    if 'swappc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2)}, {src}"
-    if 'sendmsg_rtn' in name:
-      v = _unwrap(inst.ssrc0)
-      try: msg_str = MSG(v).name if v != 255 else None  # MSG_RTN_ILLEGAL_MSG (255) not supported by LLVM
-      except ValueError: msg_str = None
-      return f"{name} {_fmt_sdst(inst.sdst, dst_regs)}, sendmsg({msg_str})" if msg_str else f"{name} {_fmt_sdst(inst.sdst, dst_regs)}, 0x{v:x}"
-  sop1_src_only = ('S_ALLOC_VGPR', 'S_SLEEP_VAR', 'S_BARRIER_SIGNAL', 'S_BARRIER_SIGNAL_ISFIRST', 'S_BARRIER_INIT', 'S_BARRIER_JOIN', 'S_SET_GPR_IDX_IDX',
-                   'S_CBRANCH_JOIN')
-  if inst.op_name in sop1_src_only: return f"{name} {src}"
-  if cdna:
-    if 'getpc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2, cdna)}"
-    if 'setpc_b64' in name or 'rfe_b64' in name: return f"{name} {src}"
-    if 'swappc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2, cdna)}, {src}"
-  return f"{name} {_fmt_sdst(inst.sdst, dst_regs, cdna)}, {src}"
-
-def _disasm_sop2(inst: SOP2) -> str:
-  cdna, name = _is_cdna(inst), inst.op_name.lower()
-  lit = inst._literal
-  # Use get_field_bits for register sizes
-  regs = inst.canonical_op_regs
-  dn, s0n, s1n = regs['d'], regs['s0'], regs['s1']
-  s0 = _lit(inst, inst.ssrc0) if _unwrap(inst.ssrc0) == 255 else _fmt_src(inst.ssrc0, s0n, cdna)
-  s1 = _lit(inst, inst.ssrc1) if _unwrap(inst.ssrc1) == 255 else _fmt_src(inst.ssrc1, s1n, cdna)
-  dst = _fmt_sdst(inst.sdst, dn, cdna)
-  if 'fmamk' in name and lit is not None: return f"{name} {dst}, {s0}, 0x{lit:x}, {s1}"
-  if 'fmaak' in name and lit is not None: return f"{name} {dst}, {s0}, {s1}, 0x{lit:x}"
-  if name in ('s_cbranch_g_fork', 's_rfe_restore_b64'): return f"{name} {s0}, {s1}"  # no destination
-  return f"{name} {dst}, {s0}, {s1}"
-
-def _disasm_sopc(inst: SOPC) -> str:
-  cdna, regs, name = _is_cdna(inst), inst.canonical_op_regs, inst.op_name.lower()
-  s0 = _lit(inst, inst.ssrc0) if _unwrap(inst.ssrc0) == 255 else _fmt_src(inst.ssrc0, regs['s0'], cdna)
-  if name == 's_set_gpr_idx_on':
-    imm = _unwrap(inst.ssrc1) & 0xf
-    flags = [n for i, n in enumerate(['SRC0', 'SRC1', 'SRC2', 'DST']) if imm & (1 << i)]
-    return f"{name} {s0}, gpr_idx({','.join(flags)})"
-  s1 = _lit(inst, inst.ssrc1) if _unwrap(inst.ssrc1) == 255 else _fmt_src(inst.ssrc1, regs['s1'], cdna)
-  return f"{name} {s0}, {s1}"
-
-_HWREG_BLACKLIST = {'HW_REG_PC_LO', 'HW_REG_PC_HI', 'HW_REG_IB_DBG1', 'HW_REG_FLUSH_IB', 'HW_REG_SHADER_TBA_LO', 'HW_REG_SHADER_TBA_HI',
-                    'HW_REG_SHADER_FLAT_SCRATCH_LO', 'HW_REG_SHADER_FLAT_SCRATCH_HI', 'HW_REG_SHADER_CYCLES'}
-_HWREG_BLACKLIST_CDNA = {'HW_REG_PC_LO', 'HW_REG_PC_HI', 'HW_REG_IB_DBG1', 'HW_REG_FLUSH_IB', 'HW_REG_SQ_SHADER_TBA_LO', 'HW_REG_SQ_SHADER_TBA_HI',
-                         'HW_REG_SQ_SHADER_TMA_LO', 'HW_REG_SQ_SHADER_TMA_HI', 'HW_REG_SQ_PERF_SNAPSHOT_DATA', 'HW_REG_SQ_PERF_SNAPSHOT_DATA1',
-                         'HW_REG_SQ_PERF_SNAPSHOT_PC_LO', 'HW_REG_SQ_PERF_SNAPSHOT_PC_HI', 'HW_REG_XCC_ID'}
-def _disasm_sopk(inst: SOPK) -> str:
-  op, name, cdna = inst.op, inst.op_name.lower(), _is_cdna(inst)
-  is_rdna4 = _is_r4(inst)
-  hw = HWREG_CDNA if cdna else (HWREG_RDNA4 if is_rdna4 else HWREG)
-  blacklist = _HWREG_BLACKLIST_CDNA if cdna else _HWREG_BLACKLIST
-  def fmt_hwreg(hid, hoff, hsz):
-    try: hr_name = hw(hid).name.replace("HW_REG_WAVE_", "HW_REG_")
-    except ValueError: return f"0x{inst.simm16:x}"
-    if hr_name in blacklist: return f"0x{inst.simm16:x}"
-    return f"hwreg({hr_name})" if hoff == 0 and hsz == 32 else f"hwreg({hr_name}, {hoff}, {hsz})"
-  if name == 's_setreg_imm32_b32':
-    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
-    return f"{name} {fmt_hwreg(hid, hoff, hsz)}, 0x{inst._literal:x}"
-  if name == 's_version': return f"{name} 0x{inst.simm16:x}"
-  if name in ('s_setreg_b32', 's_getreg_b32'):
-    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
-    hs = fmt_hwreg(hid, hoff, hsz)
-    return f"{name} {hs}, {_fmt_sdst(inst.sdst, 1, cdna)}" if 'setreg' in name else f"{name} {_fmt_sdst(inst.sdst, 1, cdna)}, {hs}"
-  if name in ('s_subvector_loop_begin', 's_subvector_loop_end'):
-    return f"{name} {_fmt_sdst(inst.sdst, 1)}, 0x{inst.simm16:x}"
-  return f"{name} {_fmt_sdst(inst.sdst, inst.canonical_op_regs['d'], cdna)}, 0x{inst.simm16:x}"
-
-def _disasm_vinterp(inst: VINTERP) -> str:
-  mods = _mods((inst.waitexp, f"wait_exp:{inst.waitexp}"), (inst.clmp, "clamp"))
-  return f"{inst.op_name.lower()} {inst.vdst.fmt()}, {_lit(inst, inst.src0, inst.neg & 1)}, {_lit(inst, inst.src1, inst.neg & 2)}, {_lit(inst, inst.src2, inst.neg & 4)}" + (" " + mods if mods else "")
-
-DISASM_HANDLERS: dict[type, Callable[..., str]] = {
-  VOP1: _disasm_vop1, VOP1_SDST: _disasm_vop1, VOP1_SDST_LIT: _disasm_vop1, VOP1_LIT: _disasm_vop1,
-  VOP2: _disasm_vop2, VOP2_LIT: _disasm_vop2, VOPC: _disasm_vopc, VOPC_LIT: _disasm_vopc,
-  VOP3: _disasm_vop3, VOP3_SDST: _disasm_vop3, VOP3_SDST_LIT: _disasm_vop3, VOP3_LIT: _disasm_vop3, VOP3SD: _disasm_vop3sd, VOP3SD_LIT: _disasm_vop3sd,
-  VOPD: _disasm_vopd, VOPD_LIT: _disasm_vopd, VOP3P: _disasm_vop3p, VOP3P_LIT: _disasm_vop3p,
-  VINTERP: _disasm_vinterp, SOPP: _disasm_sopp, SMEM: _disasm_smem, DS: _disasm_ds, FLAT: _disasm_flat, GLOBAL: _disasm_flat, SCRATCH: _disasm_flat,
-  SOP1: _disasm_sop1, SOP1_LIT: _disasm_sop1, SOP2: _disasm_sop2, SOP2_LIT: _disasm_sop2,
-  SOPC: _disasm_sopc, SOPC_LIT: _disasm_sopc, SOPK: _disasm_sopk, SOPK_LIT: _disasm_sopk,
-  # RDNA4
-  R4_VOP1: _disasm_vop1, R4_VOP1_SDST: _disasm_vop1, R4_VOP1_SDST_LIT: _disasm_vop1, R4_VOP1_LIT: _disasm_vop1,
-  R4_VOP2: _disasm_vop2, R4_VOP2_LIT: _disasm_vop2, R4_VOPC: _disasm_vopc, R4_VOPC_LIT: _disasm_vopc,
-  R4_VOP3: _disasm_vop3, R4_VOP3_SDST: _disasm_vop3, R4_VOP3_SDST_LIT: _disasm_vop3, R4_VOP3_LIT: _disasm_vop3,
-  R4_VOP3SD: _disasm_vop3sd, R4_VOP3SD_LIT: _disasm_vop3sd, R4_VOP3P: _disasm_vop3p, R4_VOP3P_LIT: _disasm_vop3p,
-  R4_FLAT: _disasm_flat, R4_GLOBAL: _disasm_flat, R4_SCRATCH: _disasm_flat,
-  R4_VOPD: _disasm_vopd, R4_VOPD_LIT: _disasm_vopd, R4_VINTERP: _disasm_vinterp, R4_SOPP: _disasm_sopp, R4_SMEM: _disasm_smem, R4_DS: _disasm_ds,
-  R4_SOP1: _disasm_sop1, R4_SOP1_LIT: _disasm_sop1, R4_SOP2: _disasm_sop2, R4_SOP2_LIT: _disasm_sop2,
-  R4_SOPC: _disasm_sopc, R4_SOPC_LIT: _disasm_sopc, R4_SOPK: _disasm_sopk, R4_SOPK_LIT: _disasm_sopk}
-
-def disasm(inst: Inst) -> str: return DISASM_HANDLERS[type(inst)](inst)
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# CDNA DISASSEMBLER SUPPORT
-# ═══════════════════════════════════════════════════════════════════════════════
-
-from extra.assembly.amd.autogen.cdna.ins import (VOP1 as CDNA_VOP1, VOP1_LIT as CDNA_VOP1_LIT,
-  VOP1_SDWA as CDNA_VOP1_SDWA, VOP1_DPP16 as CDNA_VOP1_DPP16,
-  VOP2 as CDNA_VOP2, VOP2_LIT as CDNA_VOP2_LIT, VOP2_SDWA as CDNA_VOP2_SDWA, VOP2_DPP16 as CDNA_VOP2_DPP16,
-  VOPC as CDNA_VOPC, VOPC_LIT as CDNA_VOPC_LIT, VOPC_SDWA_SDST as CDNA_VOPC_SDWA_SDST,
-  VOP3 as CDNA_VOP3, VOP3_SDST as CDNA_VOP3_SDST, VOP3SD as CDNA_VOP3SD, VOP3P as CDNA_VOP3P, VOP3P_MFMA as CDNA_VOP3P_MFMA, VOP3PX2 as CDNA_VOP3PX2,
-  SOP1 as CDNA_SOP1, SOP1_LIT as CDNA_SOP1_LIT, SOP2 as CDNA_SOP2, SOP2_LIT as CDNA_SOP2_LIT,
-  SOPC as CDNA_SOPC, SOPC_LIT as CDNA_SOPC_LIT, SOPK as CDNA_SOPK, SOPK_LIT as CDNA_SOPK_LIT,
-  SOPP as CDNA_SOPP, SMEM as CDNA_SMEM, DS as CDNA_DS,
-  FLAT as CDNA_FLAT, GLOBAL as CDNA_GLOBAL, SCRATCH as CDNA_SCRATCH, MUBUF as CDNA_MUBUF)
-
-def _cdna_src(inst, v, neg, abs_=0, n=1):
-  s = _lit(inst, v) if v == 255 else _fmt_src(v, n, cdna=True)
-  if abs_: s = f"|{s}|"
-  return f"neg({s})" if neg and v == 255 else (f"-{s}" if neg else s)
-
-_CDNA_VOP3_ALIASES = {'v_fmac_f64': 'v_mul_legacy_f32', 'v_dot2c_f32_bf16': 'v_mac_f32'}
-
-def _disasm_vop3a(inst) -> str:
-  op_val = inst.op.value if hasattr(inst.op, 'value') else inst.op
-  name = inst.op_name.lower() or f'vop3a_op_{op_val}'
-  n = inst.num_srcs() or _num_srcs(inst)
-  cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
-  # _sr_ instructions use 4-element op_sel (src2 for byte selection)
-  opsel_n = 3 if '_sr_' in name and n == 2 else n
-  opsel = _opsel_str(inst.opsel, opsel_n, inst.opsel != 0, False)
-  orig_name = name
-  name = _CDNA_VOP3_ALIASES.get(name, name)
-  if name != orig_name:
-    s0, s1 = _cdna_src(inst, inst.src0, inst.neg&1, inst.abs&1, 1), _cdna_src(inst, inst.src1, inst.neg&2, inst.abs&2, 1)
-    s2 = ""
-    dst = _vreg(inst.vdst)
-  else:
-    regs = inst.canonical_op_regs
-    dregs, r0, r1, r2 = regs['d'], regs['s0'], regs['s1'], regs['s2']
-    s0, s1, s2 = _cdna_src(inst, inst.src0, inst.neg&1, inst.abs&1, r0), _cdna_src(inst, inst.src1, inst.neg&2, inst.abs&2, r1), _cdna_src(inst, inst.src2, inst.neg&4, inst.abs&4, r2)
-    dst = _vreg(inst.vdst, dregs) if dregs > 1 else _vreg(inst.vdst)
-  if op_val >= 512:
-    return f"{name} {dst}, {s0}, {s1}, {s2}{opsel}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{opsel}{cl}{om}"
-  if op_val < 256:
-    # VOPC: vdst is actually sdst (SGPR pair), but VGPRField adds 256 to the offset
-    sdst_val = _unwrap(inst.vdst)
-    if sdst_val >= 256: sdst_val -= 256
-    sdst = _fmt_sdst(sdst_val, 2, cdna=True)
-    return f"{name} {sdst}, {s0}, {s1}{cl}"
-  if 320 <= op_val < 512:
-    if name in ('v_nop', 'v_clrexcp', 'v_nop_e64', 'v_clrexcp_e64'): return name.replace('_e64', '')
-    return f"{name} {dst}, {s0}{cl}{om}"
-  if name == 'v_cndmask_b32':
-    s2 = _fmt_src(inst.src2, 2, cdna=True)
-    return f"{name} {dst}, {s0}, {s1}, {s2}{cl}{om}"
-  return f"{name} {dst}, {s0}, {s1}, {s2}{opsel}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{opsel}{cl}{om}"
-
-def _disasm_vop3b(inst) -> str:
-  op_val = inst.op.value if hasattr(inst.op, 'value') else inst.op
-  name, cdna = inst.op_name.lower() or f'vop3b_op_{op_val}', _is_cdna(inst)
-  n = inst.num_srcs() or _num_srcs(inst)
-  regs = inst.canonical_op_regs
-  dregs, r0, r1, r2 = regs['d'], regs['s0'], regs['s1'], regs['s2']
-  s0, s1, s2 = _cdna_src(inst, inst.src0, inst.neg&1, n=r0), _cdna_src(inst, inst.src1, inst.neg&2, n=r1), _cdna_src(inst, inst.src2, inst.neg&4, n=r2)
-  # CDNA VOP3_SDST uses vdst field for sdst (but vdst adds 256), RDNA uses separate sdst field
-  sdst_val = getattr(inst, 'sdst', None)
-  if sdst_val is None and hasattr(inst, 'vdst'):
-    sdst_val = _unwrap(inst.vdst)
-    if sdst_val >= 256: sdst_val -= 256  # VGPRField adds 256, remove it for SGPR
-  # For CDNA VOP3_SDST (VOPC->VOP3), vdst is the scalar dest (sdst), there's no vdst output
-  if cdna and 'v_cmp' in name:
-    sdst = _fmt_sdst(sdst_val, 2, cdna=True)
-    cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
-    return f"{name} {sdst}, {s0}, {s1}{cl}{om}"
-  dst = _vreg(inst.vdst, dregs) if dregs > 1 else _vreg(inst.vdst)
-  sdst = _fmt_sdst(sdst_val, 2, cdna=cdna)
-  cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
-  if name in ('v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'):
-    s2 = _fmt_src(inst.src2, 2, cdna=cdna)
-  return f"{name} {dst}, {sdst}, {s0}, {s1}, {s2}{cl}{om}" if n == 3 else f"{name} {dst}, {sdst}, {s0}, {s1}{cl}{om}"
-
-def _disasm_cdna_vop3p(inst) -> str:
-  name, n = inst.op_name.lower(), inst.num_srcs() or 2
-  is_mfma = 'mfma' in name or 'smfmac' in name
-  is_accvgpr = 'accvgpr' in name
-  get_src = lambda v, sc: _lit(inst, v) if v == 255 else _fmt_src(v, sc, cdna=True)
-
-  # Handle accvgpr read/write (accumulator register operations)
-  if is_accvgpr:
-    src0_off = _unwrap(inst.src0)
-    vdst_off = _vi(inst.vdst)
-    if 'read' in name:
-      # v_accvgpr_read_b32 vN, aM - reads from accumulator to VGPR
-      return f"{name}_b32 v{vdst_off}, a{src0_off - 256 if src0_off >= 256 else src0_off}"
-    if 'write' in name:
-      # v_accvgpr_write_b32 aM, src - writes to accumulator from source
-      src = _lit(inst, inst.src0) if src0_off == 255 else (f"v{src0_off - 256}" if src0_off >= 256 else decode_src(src0_off, cdna=True))
-      return f"{name}_b32 a{vdst_off}, {src}"
-
-  # Handle v_mfma_ld_scale_b32 - special 2-operand format: v_mfma_ld_scale_b32 src0, src1
-  if 'ld_scale' in name:
-    src0, src1 = get_src(inst.src0, 1), get_src(inst.src1, 1)
-    mods = ([_fmt_bits("op_sel", inst.opsel, 2)] if inst.opsel else []) + \
-           ([_fmt_bits("op_sel_hi", inst.opsel_hi, 2)] if inst.opsel_hi != 3 else [])
-    return f"{name} {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
-
-  # Handle MFMA instructions with accumulator destinations
-  if is_mfma:
-    regs = inst.canonical_op_regs
-    dregs, r0, r1, r2 = regs['d'], regs['s0'], regs['s1'], regs['s2']
-    # Infer register counts from instruction name if not in operands table (e.g., v_mfma_f32_32x32x4_xf32)
-    if dregs == 1:
-      if '32x32' in name: dregs, r0, r1, r2 = 16, 2, 2, 16
-      elif '16x16' in name: dregs, r0, r1, r2 = 4, 2, 2, 4
-    # MFMA reuses VOP3P fields differently: clmp -> acc_cd (dest is acc), opsel_hi -> acc (src1/src2 are acc)
-    # acc field (bits 60-59): bit 0 = src2 is acc (always for MFMA), bit 1 = src1 is acc
-    acc = inst.opsel_hi  # opsel_hi field maps to acc for MFMA
-    acc_cd = inst.clmp   # clmp field maps to acc_cd for MFMA (dest is accumulator)
-    is_smfmac = 'smfmac' in name  # SMFMAC has different operand semantics
-    # Format sources: src0 is always VGPR, src1/src2 depend on acc bits
-    def mfma_src(v, sc, is_acc):
-      v = _unwrap(v)
-      if v == 255: return _lit(inst, v)
-      if 128 <= v <= 208 or 240 <= v <= 248: return _lit(inst, v)
-      base = v - 256 if v >= 256 else v
-      if is_acc: return _areg(base, sc)
-      return _vreg(base, sc)
-    src0 = get_src(inst.src0, r0)  # src0 is always VGPR
-    src1 = mfma_src(inst.src1, r1, acc & 2)  # bit 1 = src1 is acc
-    # For SMFMAC, src2 is always a VGPR index (1 register), not accumulator
-    src2 = _vreg(inst.src2) if is_smfmac else mfma_src(inst.src2, r2, acc_cd)
-    dst = _areg(inst.vdst, dregs) if acc_cd else _vreg(inst.vdst, dregs)
-    # MFMA uses neg:[...] not neg_lo:[...], and doesn't support op_sel_hi or clamp
-    # Only f64 MFMA instructions support neg modifier
-    # f8f6f4 MFMA instructions support cbsz/blgp modifiers
-    mods = []
-    if 'f8f6f4' in name:
-      if inst.neg_hi: mods.append(f"cbsz:{inst.neg_hi}")
-      if inst.neg: mods.append(f"blgp:{inst.neg}")
-    elif inst.neg and 'f64' in name:
-      mods.append(_fmt_bits("neg", inst.neg, n))
-    return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}"
-
-  # Standard VOP3P instructions
-  src0, src1, src2, dst = get_src(inst.src0, 1), get_src(inst.src1, 1), get_src(inst.src2, 1), _vreg(inst.vdst)
-  opsel_hi = inst.opsel_hi  # CDNA VOP3P only has 2 bits for opsel_hi (no opsel_hi2)
-  opsel_hi_default = 3  # CDNA default is 0b11 (2 bits), not 0b111 like RDNA
-  mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != opsel_hi_default else []) + \
-          ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if inst.clmp else [])
-  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
-
-def _disasm_mubuf(inst) -> str:
-  name = inst.op_name.lower()
-  # Determine vdata register count from instruction name
-  nregs = 4 if 'xyzw' in name else 3 if 'xyz' in name else 2 if 'xy' in name or 'x2' in name or 'f64' in name or 'dwordx2' in name else 1
-  vdata = _vreg(inst.vdata, nregs)
-  vaddr = _vreg(inst.vaddr) if inst.offen or inst.idxen else None
-  srsrc = str(inst.srsrc)
-  soffset_val = _unwrap(inst.soffset)
-  soffset = f"s{soffset_val}" if soffset_val < 128 else "off"
-  offset = f" offset:{inst.offset}" if inst.offset else ""
-  offen = " offen" if inst.offen else ""
-  idxen = " idxen" if inst.idxen else ""
-  lds = " lds" if inst.lds else ""
-  sc0 = " sc0" if inst.sc0 else ""
-  sc1 = " sc1" if inst.sc1 else ""
-  nt = " nt" if inst.nt else ""
-  # Handle special cases
-  if name in ('buffer_wbl2', 'buffer_inv'):
-    return f"{name}{sc0}{sc1}"
-  if vaddr:
-    return f"{name} {vdata}, {vaddr}, {srsrc}, {soffset}{offen}{idxen}{offset}{sc0}{nt}{sc1}{lds}"
-  return f"{name} {vdata}, off, {srsrc}, {soffset}{offset}{sc0}{nt}{sc1}{lds}"
-
-_SDWA_SEL = {0: 'BYTE_0', 1: 'BYTE_1', 2: 'BYTE_2', 3: 'BYTE_3', 4: 'WORD_0', 5: 'WORD_1', 6: 'DWORD'}
-
-def _disasm_vop1_sdwa(inst) -> str:
-  name = inst.op_name.lower().replace('_e32', '')
-  regs = inst.canonical_op_regs
-  dst = _vreg(inst.vdst, regs['d'])
-  # When s0=1, vsrc0 is SGPR/constant (VGPRField adds 256, so subtract it back)
-  if inst.s0 == 0: src0 = _vreg(inst.vsrc0, regs['s0'])
-  else:
-    raw = _unwrap(inst.vsrc0) - 256  # VGPRField adds 256
-    src0 = decode_src(raw, cdna=True)  # handles SGPRs, constants, specials
-  src0_sel = _SDWA_SEL.get(inst.src0_sel, f'SEL{inst.src0_sel}')
-  mods = []
-  if inst.clmp: mods.append("clamp")
-  if inst.omod == 1: mods.append("mul:2")
-  elif inst.omod == 2: mods.append("mul:4")
-  elif inst.omod == 3: mods.append("div:2")
-  mods.append(f"src0_sel:{src0_sel}")
-  return f"{name}_sdwa {dst}, {src0} {' '.join(mods)}"
-
-def _decode_dpp(dpp: int) -> str:
-  """Decode DPP control value to string."""
-  if dpp < 0x100: return f"quad_perm:[{dpp&3},{(dpp>>2)&3},{(dpp>>4)&3},{(dpp>>6)&3}]"
-  if 0x100 <= dpp <= 0x10f: return f"row_shl:{dpp & 0xf}"
-  if 0x110 <= dpp <= 0x11f: return f"row_shr:{dpp & 0xf}"
-  if 0x120 <= dpp <= 0x12f: return f"row_ror:{dpp & 0xf}"
-  if dpp == 0x130: return "wave_shl:1"
-  if dpp == 0x134: return "wave_rol:1"
-  if dpp == 0x138: return "wave_shr:1"
-  if dpp == 0x13c: return "wave_ror:1"
-  if dpp == 0x140: return "row_mirror"
-  if dpp == 0x141: return "row_half_mirror"
-  if dpp == 0x142: return "row_bcast:15"
-  if dpp == 0x143: return "row_bcast:31"
-  if 0x150 <= dpp <= 0x15f: return f"row_newbcast:{dpp & 0xf}"
-  if 0x160 <= dpp <= 0x16f: return f"row_share:{dpp & 0xf}"
-  if 0x170 <= dpp <= 0x17f: return f"row_xmask:{dpp & 0xf}"
-  return f"dpp:{dpp:#x}"
-
-def _disasm_vop1_dpp(inst) -> str:
-  name = inst.op_name.lower().replace('_e32', '')
-  regs = inst.canonical_op_regs
-  dst, src0 = _vreg(inst.vdst, regs['d']), _vreg(inst.vsrc0, regs['s0'])
-  dpp_str = _decode_dpp(inst.dpp)
-  mods = [dpp_str]
-  if inst.row_mask != 0xf: mods.append(f"row_mask:{inst.row_mask:#x}")
-  if inst.bank_mask != 0xf: mods.append(f"bank_mask:{inst.bank_mask:#x}")
-  if inst.bc: mods.append("bound_ctrl:1")
-  return f"{name}_dpp {dst}, {src0} {' '.join(mods)}"
-
-def _disasm_vop2_sdwa(inst) -> str:
-  name, cdna = inst.op_name.lower().replace('_e32', ''), _is_cdna(inst)
-  regs = inst.canonical_op_regs
-  dst = _vreg(inst.vdst, regs['d'])
-  # When s0/s1=1, vsrc is SGPR/constant (VGPRField adds 256, so subtract it back)
-  src0 = _vreg(inst.vsrc0, regs['s0']) if inst.s0 == 0 else decode_src(_unwrap(inst.vsrc0) - 256, cdna)
-  src1 = _vreg(inst.vsrc1, regs['s1']) if inst.s1 == 0 else decode_src(_unwrap(inst.vsrc1) - 256, cdna)
-  src0_sel = _SDWA_SEL.get(inst.src0_sel, f'SEL{inst.src0_sel}')
-  src1_sel = _SDWA_SEL.get(inst.src1_sel, f'SEL{inst.src1_sel}')
-  mods = []
-  if inst.clmp: mods.append("clamp")
-  if inst.omod == 1: mods.append("mul:2")
-  elif inst.omod == 2: mods.append("mul:4")
-  elif inst.omod == 3: mods.append("div:2")
-  if inst.src0_sel != 6: mods.append(f"src0_sel:{src0_sel}")
-  if inst.src1_sel != 6: mods.append(f"src1_sel:{src1_sel}")
-  mods_str = ' '.join(mods) if mods else ""
-  # CDNA carry instructions and cndmask need vcc operands
-  if cdna and name in _VOP2_CARRY_OUT: return f"{name}_sdwa {dst}, vcc, {src0}, {src1} {mods_str}".strip()
-  if cdna and name in _VOP2_CARRY_INOUT: return f"{name}_sdwa {dst}, vcc, {src0}, {src1}, vcc {mods_str}".strip()
-  if cdna and name == 'v_cndmask_b32': return f"{name}_sdwa {dst}, {src0}, {src1}, vcc {mods_str}".strip()
-  return f"{name}_sdwa {dst}, {src0}, {src1} {mods_str}".strip()
-
-def _disasm_vop2_dpp(inst) -> str:
-  name, cdna = inst.op_name.lower().replace('_e32', ''), _is_cdna(inst)
-  regs = inst.canonical_op_regs
-  dst, src0, src1 = _vreg(inst.vdst, regs['d']), _vreg(inst.vsrc0, regs['s0']), _vreg(inst.vsrc1, regs['s1'])
-  dpp_str = _decode_dpp(inst.dpp)
-  mods = [dpp_str]
-  if inst.row_mask != 0xf: mods.append(f"row_mask:{inst.row_mask:#x}")
-  if inst.bank_mask != 0xf: mods.append(f"bank_mask:{inst.bank_mask:#x}")
-  if inst.bc: mods.append("bound_ctrl:1")
-  # CDNA carry instructions and cndmask need vcc operands
-  if cdna and name in _VOP2_CARRY_OUT: return f"{name}_dpp {dst}, vcc, {src0}, {src1} {' '.join(mods)}"
-  if cdna and name in _VOP2_CARRY_INOUT: return f"{name}_dpp {dst}, vcc, {src0}, {src1}, vcc {' '.join(mods)}"
-  if cdna and name == 'v_cndmask_b32': return f"{name}_dpp {dst}, {src0}, {src1}, vcc {' '.join(mods)}"
-  return f"{name}_dpp {dst}, {src0}, {src1} {' '.join(mods)}"
-
-def _disasm_vopc_sdwa(inst) -> str:
-  name = inst.op_name.lower().replace('_e32', '')
-  regs = inst.canonical_op_regs
-  sdst = _fmt_sdst(inst.sdst, 2, cdna=True)
-  src0 = _vreg(inst.vsrc0, regs['s0']) if getattr(inst, 's0', 0) == 0 else decode_src(_unwrap(inst.vsrc0) - 256, cdna=True)
-  src1 = _vreg(inst.vsrc1, regs['s1']) if getattr(inst, 's1', 0) == 0 else decode_src(_unwrap(inst.vsrc1) - 256, cdna=True)
-  src0_sel = _SDWA_SEL.get(inst.src0_sel, f'SEL{inst.src0_sel}')
-  src1_sel = _SDWA_SEL.get(inst.src1_sel, f'SEL{inst.src1_sel}')
-  mods = []
-  if inst.src0_sel != 6: mods.append(f"src0_sel:{src0_sel}")
-  if inst.src1_sel != 6: mods.append(f"src1_sel:{src1_sel}")
-  return f"{name}_sdwa {sdst}, {src0}, {src1} {' '.join(mods)}".strip()
-
-def _disasm_vop3px2(inst) -> str:
-  """VOP3PX2 disassembler for scaled MFMA instructions."""
-  name = inst.op_name.lower()
-  regs = inst.canonical_op_regs
-  dregs, r2 = regs['d'], regs['s2']
-  # F8F6F4 MFMA: CBSZ selects matrix A format, BLGP selects matrix B format
-  # VGPRs: FP8/BF8(0,1)=8, FP6/BF6(2,3)=6, FP4(4)=4
-  vgprs = {0: 8, 1: 8, 2: 6, 3: 6, 4: 4}
-  r0, r1 = vgprs.get(inst.cbsz, 8), vgprs.get(inst.blgp, 8)
-  def mfma_src(v, sc, is_acc):
-    v = _unwrap(v)
-    if v == 255: return _lit(inst, v)
-    base = v - 256 if v >= 256 else v
-    return _areg(base, sc) if is_acc else _vreg(base, sc)
-  src0, src1, src2 = mfma_src(inst.src0, r0, False), mfma_src(inst.src1, r1, inst.acc & 2), mfma_src(inst.src2, r2, inst.acc_cd)
-  dst = _areg(inst.vdst, dregs) if inst.acc_cd else _vreg(inst.vdst, dregs)
-  scale_src0, scale_src1 = _vreg(inst.scale_src0), _vreg(inst.scale_src1)
-  mods = []
-  if inst.opsel: mods.append(_fmt_bits("op_sel", inst.opsel, 3))
-  if inst.opsel_hi != 0: mods.append(_fmt_bits("op_sel_hi", inst.opsel_hi, 3))
-  if inst.neg: mods.append(_fmt_bits("neg", inst.neg, 3))
-  if inst.cbsz: mods.append(f"cbsz:{inst.cbsz}")
-  if inst.blgp: mods.append(f"blgp:{inst.blgp}")
-  return f"{name} {dst}, {src0}, {src1}, {src2}, {scale_src0}, {scale_src1}{' ' + ' '.join(mods) if mods else ''}"
-
-DISASM_HANDLERS.update({CDNA_VOP1: _disasm_vop1, CDNA_VOP1_LIT: _disasm_vop1,
-  CDNA_VOP1_SDWA: _disasm_vop1_sdwa, CDNA_VOP1_DPP16: _disasm_vop1_dpp,
-  CDNA_VOP2: _disasm_vop2, CDNA_VOP2_LIT: _disasm_vop2,
-  CDNA_VOP2_SDWA: _disasm_vop2_sdwa, CDNA_VOP2_DPP16: _disasm_vop2_dpp,
-  CDNA_VOPC: _disasm_vopc, CDNA_VOPC_LIT: _disasm_vopc, CDNA_VOPC_SDWA_SDST: _disasm_vopc_sdwa,
-  CDNA_SOP1: _disasm_sop1, CDNA_SOP1_LIT: _disasm_sop1, CDNA_SOP2: _disasm_sop2, CDNA_SOP2_LIT: _disasm_sop2,
-  CDNA_SOPC: _disasm_sopc, CDNA_SOPC_LIT: _disasm_sopc, CDNA_SOPK: _disasm_sopk, CDNA_SOPK_LIT: _disasm_sopk, CDNA_SOPP: _disasm_sopp,
-  CDNA_SMEM: _disasm_smem, CDNA_DS: _disasm_ds, CDNA_FLAT: _disasm_flat, CDNA_GLOBAL: _disasm_flat, CDNA_SCRATCH: _disasm_flat,
-  CDNA_VOP3: _disasm_vop3a, CDNA_VOP3_SDST: _disasm_vop3b, CDNA_VOP3SD: _disasm_vop3b, CDNA_VOP3P: _disasm_cdna_vop3p, CDNA_VOP3P_MFMA: _disasm_cdna_vop3p,
-  CDNA_MUBUF: _disasm_mubuf, CDNA_VOP3PX2: _disasm_vop3px2})
@@ -1,450 +1,533 @@
-# dsl.py - clean DSL for AMD assembly
-from typing import Any
+# library for RDNA3 assembly DSL
+# mypy: ignore-errors
+from __future__ import annotations
+import struct, math, re
+from enum import IntEnum
+from functools import cache, cached_property
+from typing import overload, Annotated, TypeVar, Generic
+from extra.assembly.amd.autogen.rdna3.enum import (VOP1Op, VOP2Op, VOP3Op, VOP3SDOp, VOP3POp, VOPCOp, VOPDOp, SOP1Op, SOP2Op,
+  SOPCOp, SOPKOp, SOPPOp, SMEMOp, DSOp, FLATOp, MUBUFOp, MTBUFOp, MIMGOp, VINTERPOp)

-# ══════════════════════════════════════════════════════════════
-# Registers - unified src encoding space (0-511)
-# ══════════════════════════════════════════════════════════════
+# Common masks and bit conversion functions
+MASK32, MASK64 = 0xffffffff, 0xffffffffffffffff
+_struct_f, _struct_I = struct.Struct("<f"), struct.Struct("<I")
+_struct_e, _struct_H = struct.Struct("<e"), struct.Struct("<H")
+_struct_d, _struct_Q = struct.Struct("<d"), struct.Struct("<Q")
+def _f32(i): return _struct_f.unpack(_struct_I.pack(i & MASK32))[0]
+def _i32(f):
+  if isinstance(f, int): f = float(f)
+  if math.isnan(f): return 0xffc00000 if math.copysign(1.0, f) < 0 else 0x7fc00000
+  if math.isinf(f): return 0x7f800000 if f > 0 else 0xff800000
+  try: return _struct_I.unpack(_struct_f.pack(f))[0]
+  except (OverflowError, struct.error): return 0x7f800000 if f > 0 else 0xff800000
+def _sext(v, b): return v - (1 << b) if v & (1 << (b - 1)) else v
+def _f16(i): return _struct_e.unpack(_struct_H.pack(i & 0xffff))[0]
+def _i16(f):
+  if math.isnan(f): return 0x7e00
+  if math.isinf(f): return 0x7c00 if f > 0 else 0xfc00
+  try: return _struct_H.unpack(_struct_e.pack(f))[0]
+  except (OverflowError, struct.error): return 0x7c00 if f > 0 else 0xfc00
+def _f64(i): return _struct_d.unpack(_struct_Q.pack(i & MASK64))[0]
+def _i64(f):
+  if math.isnan(f): return 0x7ff8000000000000
+  if math.isinf(f): return 0x7ff0000000000000 if f > 0 else 0xfff0000000000000
+  try: return _struct_Q.unpack(_struct_d.pack(f))[0]
+  except (OverflowError, struct.error): return 0x7ff0000000000000 if f > 0 else 0xfff0000000000000

-class Reg:
-  # Register names vary by arch: RDNA has NULL@124/M0@125, CDNA has M0@124/reserved@125
-  # RDNA4 has DPP8@233, CDNA has SDWA@249/DPP@250/VCCZ@251/EXECZ@252
-  _NAMES = {102: "FLAT_SCRATCH_LO", 103: "FLAT_SCRATCH_HI", 104: "XNACK_MASK_LO", 105: "XNACK_MASK_HI",
-            106: "VCC_LO", 107: "VCC_HI", 124: "NULL", 125: "M0", 126: "EXEC_LO", 127: "EXEC_HI",
-            233: "DPP8", 234: "DPP8FI", 235: "SHARED_BASE", 236: "SHARED_LIMIT", 237: "PRIVATE_BASE", 238: "PRIVATE_LIMIT",
-            240: "0.5", 241: "-0.5", 242: "1.0", 243: "-1.0", 244: "2.0", 245: "-2.0", 246: "4.0", 247: "-4.0",
-            248: "INV_2PI", 249: "SDWA", 250: "DPP", 251: "VCCZ", 252: "EXECZ", 253: "SCC", 254: "SRC_LDS_DIRECT", 255: "LIT"}
-  _PAIRS = {106: "VCC", 126: "EXEC"}
+# Instruction spec - register counts and dtypes derived from instruction names
+_REGS = {'B32': 1, 'B64': 2, 'B96': 3, 'B128': 4, 'B256': 8, 'B512': 16,
+         'F32': 1, 'I32': 1, 'U32': 1, 'F64': 2, 'I64': 2, 'U64': 2,
+         'F16': 1, 'I16': 1, 'U16': 1, 'B16': 1, 'I8': 1, 'U8': 1, 'B8': 1}
+_CVT_RE = re.compile(r'CVT_([FIUB]\d+)_([FIUB]\d+)$')
+_MAD_MUL_RE = re.compile(r'(?:MAD|MUL)_([IU]\d+)_([IU]\d+)$')
+_PACK_RE = re.compile(r'PACK_([FIUB]\d+)_([FIUB]\d+)$')
+_DST_SRC_RE = re.compile(r'_([FIUB]\d+)_([FIUB]\d+)$')
+_SINGLE_RE = re.compile(r'_([FIUB](?:32|64|16|8|96|128|256|512))$')
+@cache
+def _suffix(name: str) -> tuple[str | None, str | None]:
+  name = name.upper()
+  if m := _CVT_RE.search(name): return m.group(1), m.group(2)
+  if m := _MAD_MUL_RE.search(name): return m.group(1), m.group(2)
+  if m := _PACK_RE.search(name): return m.group(1), m.group(2)
+  if m := _DST_SRC_RE.search(name): return m.group(1), m.group(2)
+  if m := _SINGLE_RE.search(name): return m.group(1), m.group(1)
+  return None, None
+_SPECIAL_REGS = {
+  'V_LSHLREV_B64': (2, 1, 2, 1), 'V_LSHRREV_B64': (2, 1, 2, 1), 'V_ASHRREV_I64': (2, 1, 2, 1),
+  'S_LSHL_B64': (2, 2, 1, 1), 'S_LSHR_B64': (2, 2, 1, 1), 'S_ASHR_I64': (2, 2, 1, 1),
+  'S_BFE_U64': (2, 2, 1, 1), 'S_BFE_I64': (2, 2, 1, 1), 'S_BFM_B64': (2, 1, 1, 1),
+  'S_BITSET0_B64': (2, 1, 1, 1), 'S_BITSET1_B64': (2, 1, 1, 1),
+  'S_BITCMP0_B64': (1, 2, 1, 1), 'S_BITCMP1_B64': (1, 2, 1, 1),
+  'V_LDEXP_F64': (2, 2, 1, 1), 'V_TRIG_PREOP_F64': (2, 2, 1, 1),
+  'V_CMP_CLASS_F64': (1, 2, 1, 1), 'V_CMPX_CLASS_F64': (1, 2, 1, 1),
+  'V_CMP_CLASS_F32': (1, 1, 1, 1), 'V_CMPX_CLASS_F32': (1, 1, 1, 1),
+  'V_CMP_CLASS_F16': (1, 1, 1, 1), 'V_CMPX_CLASS_F16': (1, 1, 1, 1),
+  'V_MAD_U64_U32': (2, 1, 1, 2), 'V_MAD_I64_I32': (2, 1, 1, 2),
+  'V_QSAD_PK_U16_U8': (2, 2, 1, 2), 'V_MQSAD_PK_U16_U8': (2, 2, 1, 2), 'V_MQSAD_U32_U8': (4, 2, 1, 4),
+}
+_SPECIAL_DTYPE = {
+  'V_LSHLREV_B64': ('B64', 'U32', 'B64', None), 'V_LSHRREV_B64': ('B64', 'U32', 'B64', None), 'V_ASHRREV_I64': ('I64', 'U32', 'I64', None),
+  'S_LSHL_B64': ('B64', 'B64', 'U32', None), 'S_LSHR_B64': ('B64', 'B64', 'U32', None), 'S_ASHR_I64': ('I64', 'I64', 'U32', None),
+  'S_BFE_U64': ('U64', 'U64', 'U32', None), 'S_BFE_I64': ('I64', 'I64', 'U32', None),
+  'S_BFM_B64': ('B64', 'U32', 'U32', None), 'S_BITSET0_B64': ('B64', 'U32', None, None), 'S_BITSET1_B64': ('B64', 'U32', None, None),
+  'S_BITCMP0_B64': ('SCC', 'B64', 'U32', None), 'S_BITCMP1_B64': ('SCC', 'B64', 'U32', None),
+  'V_LDEXP_F64': ('F64', 'F64', 'I32', None), 'V_TRIG_PREOP_F64': ('F64', 'F64', 'U32', None),
+  'V_CMP_CLASS_F64': ('VCC', 'F64', 'U32', None), 'V_CMPX_CLASS_F64': ('EXEC', 'F64', 'U32', None),
+  'V_CMP_CLASS_F32': ('VCC', 'F32', 'U32', None), 'V_CMPX_CLASS_F32': ('EXEC', 'F32', 'U32', None),
+  'V_CMP_CLASS_F16': ('VCC', 'F16', 'U32', None), 'V_CMPX_CLASS_F16': ('EXEC', 'F16', 'U32', None),
+  'V_MAD_U64_U32': ('U64', 'U32', 'U32', 'U64'), 'V_MAD_I64_I32': ('I64', 'I32', 'I32', 'I64'),
+  'V_QSAD_PK_U16_U8': ('B64', 'B64', 'B64', 'B64'), 'V_MQSAD_PK_U16_U8': ('B64', 'B64', 'B64', 'B64'),
+  'V_MQSAD_U32_U8': ('B128', 'B64', 'B64', 'B128'),
+}
+@cache
+def spec_regs(name: str) -> tuple[int, int, int, int]:
+  uname = name.upper()
+  if uname in _SPECIAL_REGS: return _SPECIAL_REGS[uname]
+  if 'SAD' in uname and 'U8' in uname and 'QSAD' not in uname and 'MQSAD' not in uname: return 1, 1, 1, 1
+  dst_suf, src_suf = _suffix(name)
+  return _REGS.get(dst_suf, 1), _REGS.get(src_suf, 1), _REGS.get(src_suf, 1), _REGS.get(src_suf, 1)
+@cache
+def spec_dtype(name: str) -> tuple[str | None, str | None, str | None, str | None]:
+  uname = name.upper()
+  if uname in _SPECIAL_DTYPE: return _SPECIAL_DTYPE[uname]
+  if 'SAD' in uname and ('U8' in uname or 'U16' in uname) and 'QSAD' not in uname and 'MQSAD' not in uname: return 'U32', 'U32', 'U32', 'U32'
+  if '_CMP_' in uname or '_CMPX_' in uname:
+    dst_suf, src_suf = _suffix(name)
+    return 'EXEC' if '_CMPX_' in uname else 'VCC', src_suf, src_suf, None
+  dst_suf, src_suf = _suffix(name)
+  return dst_suf, src_suf, src_suf, src_suf
+_F16_RE = re.compile(r'_[FIUB]16(?:_|$)')
+_F64_RE = re.compile(r'_[FIUB]64(?:_|$)')
+@cache
+def spec_is_16bit(name: str) -> bool:
+  uname = name.upper()
+  if 'SAD' in uname or 'PACK' in uname or '_PK_' in uname or 'SAT_PK' in uname or 'DOT2' in uname: return False
+  if '_F32' in uname or '_I32' in uname or '_U32' in uname or '_B32' in uname: return False
+  return bool(_F16_RE.search(uname))
+@cache
+def spec_is_64bit(name: str) -> bool: return bool(_F64_RE.search(name.upper()))
+_3SRC = {'FMA', 'MAD', 'MIN3', 'MAX3', 'MED3', 'DIV_FIX', 'DIV_FMAS', 'DIV_SCALE', 'SAD', 'LERP', 'ALIGN', 'CUBE', 'BFE', 'BFI',
+         'PERM_B32', 'PERMLANE', 'CNDMASK', 'XOR3', 'OR3', 'ADD3', 'LSHL_OR', 'AND_OR', 'LSHL_ADD', 'ADD_LSHL', 'XAD', 'MAXMIN',
+         'MINMAX', 'DOT2', 'DOT4', 'DOT8', 'WMMA', 'CVT_PK_U8', 'MULLIT', 'CO_CI'}
+_2SRC = {'FMAC'}  # FMAC uses dst as implicit accumulator, so only 2 explicit sources
+def spec_num_srcs(name: str) -> int:
+  name = name.upper()
+  if any(k in name for k in _2SRC): return 2
+  return 3 if any(k in name for k in _3SRC) else 2
+def is_dtype_16(dt: str | None) -> bool: return dt is not None and '16' in dt
+def is_dtype_64(dt: str | None) -> bool: return dt is not None and '64' in dt

-  def __init__(self, offset: int = 0, sz: int = 512, *, neg: bool = False, abs_: bool = False, hi: bool = False):
-    self.offset, self.sz = offset, sz
-    self.neg, self.abs_, self.hi = neg, abs_, hi
-
-  def __hash__(self): return hash((self.offset, self.sz, self.neg, self.abs_, self.hi))
-  def __getitem__(self, key):
-    if isinstance(key, slice):
-      start, stop = key.start or 0, key.stop or (self.sz - 1)
-      if start < 0 or stop >= self.sz: raise RuntimeError(f"slice [{start}:{stop}] out of bounds for size {self.sz}")
-      return Reg(self.offset + start, stop - start + 1)
-    if key < 0 or key >= self.sz: raise RuntimeError(f"index {key} out of bounds for size {self.sz}")
-    return Reg(self.offset + key, 1)
-  def __eq__(self, other):
-    if isinstance(other, Reg):
-      return (self.offset == other.offset and self.sz == other.sz and
-              self.neg == other.neg and self.abs_ == other.abs_ and self.hi == other.hi)
-    return NotImplemented
-  def __add__(self, other):
-    if isinstance(other, int): return Reg(self.offset + other, self.sz)
-    return NotImplemented
-  def __neg__(self) -> 'Reg': return Reg(self.offset, self.sz, neg=not self.neg, abs_=self.abs_, hi=self.hi)
-  def __abs__(self) -> 'Reg': return Reg(self.offset, self.sz, neg=self.neg, abs_=True, hi=self.hi)
+# Bit field DSL
+class BitField:
+  def __init__(self, hi: int, lo: int, name: str | None = None): self.hi, self.lo, self.name, self._marker = hi, lo, name, None
+  def __set_name__(self, owner, name):
+    import typing
+    self.name, self._owner = name, owner
+    # Cache marker at class definition time
+    hints = typing.get_type_hints(owner, include_extras=True)
+    if name in hints:
+      hint = hints[name]
+      if typing.get_origin(hint) is Annotated:
+        args = typing.get_args(hint)
+        self._marker = args[1] if len(args) > 1 else None
+  def __eq__(self, val: int) -> tuple[BitField, int]: return (self, val)  # type: ignore
+  def mask(self) -> int: return (1 << (self.hi - self.lo + 1)) - 1
  @property
-  def h(self) -> 'Reg': return Reg(self.offset, self.sz, neg=self.neg, abs_=self.abs_, hi=True)
-  @property
-  def l(self) -> 'Reg': return Reg(self.offset, self.sz, neg=self.neg, abs_=self.abs_, hi=False)
-  def fmt(self, sz=None, parens=False, upper=False) -> str:
-    o, sz = self.offset, sz or self.sz
-    l, r = ("[", "]") if parens or sz > 1 else ("", "")  # brackets for multi-reg or when parens=True
-    if 256 <= o < 512: idx = o - 256; base = f"v{l}{idx}{r}" if sz == 1 else f"v[{idx}:{idx + sz - 1}]"
-    elif o < 106: base = f"s{l}{o}{r}" if sz == 1 else f"s[{o}:{o + sz - 1}]"
-    elif sz == 2 and o in self._PAIRS: base = self._PAIRS[o] if upper else self._PAIRS[o].lower()
-    elif o in self._NAMES: base = self._NAMES[o] if upper else self._NAMES[o].lower()  # special regs (any sz)
-    elif 108 <= o < 124: idx = o - 108; base = f"ttmp{l}{idx}{r}" if sz == 1 else f"ttmp[{idx}:{idx + sz - 1}]"
-    elif 128 <= o <= 192: base = str(o - 128)  # inline int constants (0-64)
-    elif 193 <= o <= 208: base = str(-(o - 192))  # inline negative int constants (-1 to -16)
-    else: raise RuntimeError(f"unknown register: offset={o}, sz={sz}")
-    if self.hi: base += ".h"
-    if self.abs_: base = f"abs({base})" if upper else f"|{base}|"
-    if self.neg: base = f"-{base}"
-    return base
-  def __repr__(self): return self.fmt(parens=True, upper=True)
-
-# Full src encoding space
-src = Reg(0, 512)
-
-# Slices for each region (inclusive end)
-s = src[0:105]           # SGPR0-105
-VCC_LO = src[106]
-VCC_HI = src[107]
-VCC = src[106:107]
-ttmp = src[108:123]      # TTMP0-15
-NULL = OFF = src[124]
-M0 = src[125]
-EXEC_LO = src[126]
-EXEC_HI = src[127]
-EXEC = src[126:127]
-# 128: 0, 129-192: integers 1-64, 193-208: integers -1 to -16
-# 240-248: float constants (0.5, -0.5, 1.0, -1.0, 2.0, -2.0, 4.0, -4.0, 1/(2*PI))
-INV_2PI = src[248]
-SDWA = src[249]
-DPP = DPP16 = src[250]
-VCCZ = src[251]
-EXECZ = src[252]
-SCC = src[253]
-SRC_LDS_DIRECT = src[254]
-LIT = src[255]           # literal constant marker
-v = src[256:511]         # VGPR0-255
-
-# ══════════════════════════════════════════════════════════════
-# BitField
-# ══════════════════════════════════════════════════════════════
+  def marker(self) -> type | None: return self._marker
+  @overload
+  def __get__(self, obj: None, objtype: type) -> BitField: ...
+  @overload
+  def __get__(self, obj: object, objtype: type | None = None) -> int: ...
+  def __get__(self, obj, objtype=None):
+    if obj is None: return self
+    val = unwrap(obj._values.get(self.name, 0))
+    # Convert to IntEnum if marker is an IntEnum subclass
+    if self.marker and isinstance(self.marker, type) and issubclass(self.marker, IntEnum):
+      # VOP3 with VOPC opcodes (0-255) -> VOPCOp, VOP3SD opcodes -> VOP3SDOp
+      if self.marker is VOP3Op:
+        if val < 256: return VOPCOp(val)
+        if val in Inst._VOP3SD_OPS: return VOP3SDOp(val)
+      try: return self.marker(val)
+      except ValueError: pass
+    return val

 class _Bits:
-  """Helper for defining bit fields with slice syntax: bits[hi:lo] or bits[n]."""
-  def __getitem__(self, key) -> 'BitField': return BitField(key.start, key.stop) if isinstance(key, slice) else BitField(key, key)
+  def __getitem__(self, key) -> BitField: return BitField(key.start, key.stop) if isinstance(key, slice) else BitField(key, key)
 bits = _Bits()

-class BitField:
-  name: str | None
-  def __init__(self, hi: int, lo: int, default: int = 0):
-    self.hi, self.lo, self.default, self.name, self.mask = hi, lo, default, None, (1 << (hi - lo + 1)) - 1
-  def __set_name__(self, owner, name: str): self.name = name
-  def __eq__(self, other) -> 'FixedBitField':  # type: ignore[override]
-    if isinstance(other, int): return FixedBitField(self.hi, self.lo, other)
-    raise TypeError(f"BitField.__eq__ expects int, got {type(other).__name__}")
-  def enum(self, enum_cls) -> 'EnumBitField': return EnumBitField(self.hi, self.lo, enum_cls)
-  def encode(self, val) -> int:
-    assert isinstance(val, int), f"BitField.encode expects int, got {type(val).__name__}"
-    return val
-  def decode(self, val): return val
-  def set(self, raw: int, val) -> int:
-    if val is None: val = self.default
-    encoded = self.encode(val)
-    # Handle signed values: convert negative to 2's complement
-    if encoded < 0: encoded = encoded & self.mask
-    if encoded < 0 or encoded > self.mask: raise RuntimeError(f"field '{self.name}': value {encoded} doesn't fit in {self.hi - self.lo + 1} bits")
-    return (raw & ~(self.mask << self.lo)) | (encoded << self.lo)
-  def __get__(self, obj, objtype=None):
-    if obj is None: return self
-    return self.decode((obj._raw >> self.lo) & self.mask)
-  def __set__(self, obj, val): obj._raw = self.set(obj._raw, val)
+# Source operand with modifiers - base class for anything that can be a src with neg/abs
+class SrcMod:
+  __slots__ = ('val', 'neg', 'abs_')
+  def __init__(self, val: int, neg: bool = False, abs_: bool = False): self.val, self.neg, self.abs_ = val, neg, abs_
+  def __repr__(self): return f"{'-' if self.neg else ''}{'|' if self.abs_ else ''}{self.val}{'|' if self.abs_ else ''}"
+  def __neg__(self): return SrcMod(self.val, not self.neg, self.abs_)
+  def __abs__(self): return SrcMod(self.val, self.neg, True)

-class FixedBitField(BitField):
-  def set(self, raw: int, val=None) -> int:
-    assert val is None, f"FixedBitField does not accept values, got {val}"
-    return super().set(raw, self.default)
+# Register types
+class Reg(SrcMod):
+  __slots__ = ('idx', 'count', 'hi')
+  def __init__(self, idx: int, count: int = 1, hi: bool = False, neg: bool = False, abs_: bool = False):
+    self.idx, self.count, self.hi = idx, count, hi
+    super().__init__(idx, neg, abs_)
+  def __repr__(self): return f"{self.__class__.__name__.lower()[0]}[{self.idx}]" if self.count == 1 else f"{self.__class__.__name__.lower()[0]}[{self.idx}:{self.idx + self.count}]"
+  def __neg__(self): return self.__class__(self.idx, self.count, self.hi, not self.neg, self.abs_)
+  def __abs__(self): return self.__class__(self.idx, self.count, self.hi, self.neg, True)
+  @property
+  def l(self): return self.__class__(self.idx, self.count, False, self.neg, self.abs_)
+  @property
+  def h(self): return self.__class__(self.idx, self.count, True, self.neg, self.abs_)

-class EnumBitField(BitField):
-  def __init__(self, hi: int, lo: int, enum_cls, allowed: set | None = None):
-    super().__init__(hi, lo)
-    self._enum = enum_cls
-    self.allowed = allowed  # if set, only these enum values are valid for this encoding
-  def encode(self, val) -> int:
-    if not isinstance(val, self._enum): raise RuntimeError(f"expected {self._enum.__name__}, got {type(val).__name__}")
-    if self.allowed is not None and val not in self.allowed:
-      raise RuntimeError(f"opcode {val.name} not allowed in this encoding")
-    return val.value
-  def decode(self, raw): return self._enum(raw)
+T = TypeVar('T', bound=Reg)
+class _RegFactory(Generic[T]):
+  def __init__(self, cls: type[T], name: str): self._cls, self._name = cls, name
+  @overload
+  def __getitem__(self, key: int) -> Reg: ...
+  @overload
+  def __getitem__(self, key: slice) -> Reg: ...
+  def __getitem__(self, key: int | slice) -> Reg:
+    return self._cls(key.start, key.stop - key.start + 1) if isinstance(key, slice) else self._cls(key)
+  def __repr__(self): return f"<{self._name} factory>"

-# ══════════════════════════════════════════════════════════════
-# Typed fields
-# ══════════════════════════════════════════════════════════════
+class SGPR(Reg): pass
+class VGPR(Reg): pass
+class TTMP(Reg): pass
+s: _RegFactory[SGPR] = _RegFactory(SGPR, "SGPR")
+v: _RegFactory[VGPR] = _RegFactory(VGPR, "VGPR")
+ttmp: _RegFactory[TTMP] = _RegFactory(TTMP, "TTMP")

-import struct
-def _f32(f: float) -> int: return struct.unpack('I', struct.pack('f', f))[0]
+# Special registers as SrcMod objects (support -VCC_LO, abs(EXEC_LO), etc.)
+VCC_LO, VCC_HI, VCC = SrcMod(106), SrcMod(107), SrcMod(106)
+EXEC_LO, EXEC_HI, EXEC = SrcMod(126), SrcMod(127), SrcMod(126)
+SCC, M0, NULL, OFF = SrcMod(253), SrcMod(125), SrcMod(124), SrcMod(124)

-class SrcField(BitField):
-  _valid_range = (0, 511)  # inclusive
-  _FLOAT_ENC = {0.5: 240, -0.5: 241, 1.0: 242, -1.0: 243, 2.0: 244, -2.0: 245, 4.0: 246, -4.0: 247}
+# Field type markers (runtime classes for validation)
+class _SSrc: pass
+class _Src: pass
+class _Imm: pass
+class _SImm: pass
+class _VDSTYEnc: pass  # VOPD vdsty: encoded = actual >> 1, actual = (encoded << 1) | ((vdstx & 1) ^ 1)
+class _SGPRField: pass
+class _VGPRField: pass

-  def __init__(self, hi: int, lo: int, default=s[0]):
-    super().__init__(hi, lo, default)
-    expected_size = self._valid_range[1] - self._valid_range[0] + 1
-    actual_size = 1 << (hi - lo + 1)
-    if actual_size != expected_size:
-      raise RuntimeError(f"{self.__class__.__name__}: field size {hi - lo + 1} bits ({actual_size}) doesn't match range {self._valid_range} ({expected_size})")
+# Type aliases for annotations - tells mypy it's a BitField while preserving marker info
+SSrc = Annotated[BitField, _SSrc]
+Src = Annotated[BitField, _Src]
+Imm = Annotated[BitField, _Imm]
+SImm = Annotated[BitField, _SImm]
+VDSTYEnc = Annotated[BitField, _VDSTYEnc]
+SGPRField = Annotated[BitField, _SGPRField]
+VGPRField = Annotated[BitField, _VGPRField]
+class RawImm:
+  def __init__(self, val: int): self.val = val
+  def __repr__(self): return f"RawImm({self.val})"
+  def __eq__(self, other): return isinstance(other, RawImm) and self.val == other.val

-  def encode(self, val) -> int:
-    """Encode value. Returns 255 (literal marker) for out-of-range values."""
-    if isinstance(val, Reg): offset = val.offset
-    elif isinstance(val, float): offset = self._FLOAT_ENC.get(val, 255)
-    elif isinstance(val, int) and 0 <= val <= 64: offset = 128 + val
-    elif isinstance(val, int) and -16 <= val < 0: offset = 192 - val
-    elif isinstance(val, int): offset = 255  # literal
-    else: raise TypeError(f"invalid src value {val}")
-    if not (self._valid_range[0] <= offset <= self._valid_range[1]):
-      raise TypeError(f"{self.__class__.__name__}: {val} (offset {offset}) out of range {self._valid_range}")
-    return offset - self._valid_range[0]
+def unwrap(val) -> int:
+  if isinstance(val, RawImm): return val.val
+  if isinstance(val, SrcMod) and not isinstance(val, Reg): return val.val  # Special registers like VCC_LO, NULL
+  if hasattr(val, 'value'): return val.value  # IntEnum
+  if hasattr(val, 'idx'): return val.idx  # Reg
+  return val

-  def decode(self, raw): return src[raw + self._valid_range[0]]
+# Encoding/decoding constants
+FLOAT_ENC = {0.5: 240, -0.5: 241, 1.0: 242, -1.0: 243, 2.0: 244, -2.0: 245, 4.0: 246, -4.0: 247}
+FLOAT_DEC = {v: str(k) for k, v in FLOAT_ENC.items()}
+SPECIAL_GPRS = {106: "vcc_lo", 107: "vcc_hi", 124: "null", 125: "m0", 126: "exec_lo", 127: "exec_hi", 253: "scc"}
+SPECIAL_PAIRS = {106: "vcc", 126: "exec"}
+SRC_FIELDS = {'src0', 'src1', 'src2', 'ssrc0', 'ssrc1', 'soffset', 'srcx0', 'srcy0'}
+RAW_FIELDS = {'vdata', 'vdst', 'vaddr', 'addr', 'data', 'data0', 'data1', 'sdst', 'sdata', 'vsrc1'}

-  def __get__(self, obj, objtype=None):
-    if obj is None: return self
-    reg = self.decode((obj._raw >> self.lo) & self.mask)
-    # Resize register based on operand info (skip non-resizable special registers)
-    # VCC/EXEC pairs (106, 126), NULL (124), M0 (125), float constants (240-255)
-    if reg.offset not in (124, 125) and not 240 <= reg.offset <= 255:
-      # Map variant field names (vsrc0->src0, vsrc1->src1, etc.) for DPP/SDWA classes
-      assert self.name is not None
-      name = self.name[1:] if self.name.startswith('v') and self.name[1:] in obj.op_regs else self.name
-      if sz := obj.op_regs.get(name, 1): reg = Reg(reg.offset, sz, neg=reg.neg, abs_=reg.abs_, hi=reg.hi)
-    return reg
+def _encode_reg(val: Reg) -> int: return (108 if isinstance(val, TTMP) else 0) + val.idx

-class VGPRField(SrcField):
-  _valid_range = (256, 511)
-  def __init__(self, hi: int, lo: int, default=v[0]): super().__init__(hi, lo, default)
-  def encode(self, val) -> int:
-    if not isinstance(val, Reg): raise TypeError(f"VGPRField requires Reg, got {type(val).__name__}")
-    # For 8-bit vdst fields in VOP1/VOP2 16-bit ops, bit 7 is opsel for dest half
-    encoded = super().encode(val)
-    if val.hi and (self.hi - self.lo + 1) == 8:
-      if encoded >= 128:
-        raise ValueError(f"VGPRField: v[{encoded}].h not encodable in 8-bit field (v[0:127] only for .h)")
-      encoded |= 0x80
-    return encoded
-class SGPRField(SrcField): _valid_range = (0, 127)
-class SSrcField(SrcField): _valid_range = (0, 255)
+def _is_inline_const(v: int) -> bool: return 0 <= v <= 127 or 128 <= v <= 208 or 240 <= v <= 255

-class AlignedSGPRField(BitField):
-  """SGPR field with alignment requirement. Encoded as sgpr_index // alignment."""
-  _align: int = 2
-  def encode(self, val):
-    if isinstance(val, int) and val == 0: return 0  # default: encode as s[0]
-    if not isinstance(val, Reg): raise TypeError(f"{self.__class__.__name__} requires Reg, got {type(val).__name__}")
-    if not (0 <= val.offset < 128): raise ValueError(f"{self.__class__.__name__} requires SGPR, got offset {val.offset}")
-    if val.offset & (self._align - 1): raise ValueError(f"{self.__class__.__name__} requires {self._align}-aligned SGPR, got s[{val.offset}]")
-    return val.offset >> (self._align.bit_length() - 1)
-  def decode(self, raw): return src[raw << (self._align.bit_length() - 1)]
-  def __get__(self, obj, objtype=None):
-    if obj is None: return self
-    reg = self.decode((obj._raw >> self.lo) & self.mask)
-    if sz := obj.op_regs.get(self.name, 1): reg = Reg(reg.offset, sz, neg=reg.neg, abs_=reg.abs_, hi=reg.hi)
-    return reg
+def encode_src(val) -> int:
+  if isinstance(val, VGPR): return 256 + _encode_reg(val)
+  if isinstance(val, Reg): return _encode_reg(val)
+  if isinstance(val, SrcMod) and not isinstance(val, Reg): return val.val if _is_inline_const(val.val) else 255
+  if hasattr(val, 'value'): return val.value  # IntEnum
+  if isinstance(val, float): return 128 if val == 0.0 else FLOAT_ENC.get(val, 255)
+  if isinstance(val, int): return 128 + val if 0 <= val <= 64 else 192 - val if -16 <= val <= -1 else 255
+  return 255

-class SBaseField(AlignedSGPRField): _align = 2
-class SRsrcField(AlignedSGPRField): _align = 4
-
-class VDSTYField(BitField):
-  """VOPD vdsty: encoded = vgpr_idx >> 1. Actual vgpr = (encoded << 1) | ((vdstx & 1) ^ 1)."""
-  def encode(self, val):
-    if not isinstance(val, Reg): raise TypeError(f"VDSTYField requires Reg, got {type(val).__name__}")
-    if not (256 <= val.offset < 512): raise ValueError(f"VDSTYField requires VGPR, got offset {val.offset}")
-    return (val.offset - 256) >> 1
-  def __get__(self, obj, objtype=None):
-    if obj is None: return self
-    raw = (obj._raw >> self.lo) & self.mask
-    vdstx_bit0 = (obj.vdstx.offset - 256) & 1
-    vgpr_idx = (raw << 1) | (vdstx_bit0 ^ 1)
-    return Reg(256 + vgpr_idx, 1)
-
-# ══════════════════════════════════════════════════════════════
-# Operand info from XML
-# ══════════════════════════════════════════════════════════════
-
-import functools
-from extra.assembly.amd.autogen.rdna3.operands import OPERANDS as OPERANDS_RDNA3
-from extra.assembly.amd.autogen.rdna4.operands import OPERANDS as OPERANDS_RDNA4
-from extra.assembly.amd.autogen.cdna.operands import OPERANDS as OPERANDS_CDNA
-OPERANDS = {**OPERANDS_CDNA, **OPERANDS_RDNA3, **OPERANDS_RDNA4}
-
-# ══════════════════════════════════════════════════════════════
-# Inst base class
-# ══════════════════════════════════════════════════════════════
-
-def _needs_literal(val) -> bool:
-  """Check if a value needs a literal constant (can't be encoded inline)."""
-  if val is None or isinstance(val, Reg): return False
-  if isinstance(val, float): return val not in SrcField._FLOAT_ENC
-  if isinstance(val, int): return not (0 <= val <= 64 or -16 <= val < 0)
-  return False
-
-def _get_variant(cls, suffix: str):
-  """Get a variant class by suffix (e.g., '_LIT') via module lookup."""
-  import sys
-  module = sys.modules.get(cls.__module__)
-  return getattr(module, f"{cls.__name__}{suffix}", None) if module else None
-
-def _canonical_name(name: str) -> str | None:
-  """Map operand name to canonical name."""
-  if name in ('src0', 'vsrc0', 'ssrc0'): return 's0'
-  if name in ('src1', 'vsrc1', 'ssrc1'): return 's1'
-  if name == 'src2': return 's2'
-  if name in ('vdst', 'sdst', 'sdata'): return 'd'
-  if name in ('data', 'vdata', 'data0', 'vsrc'): return 'data'
-  return None
+def decode_src(val: int) -> str:
+  if val <= 105: return f"s{val}"
+  if val in SPECIAL_GPRS: return SPECIAL_GPRS[val]
+  if val in FLOAT_DEC: return FLOAT_DEC[val]
+  if 108 <= val <= 123: return f"ttmp{val - 108}"
+  if 128 <= val <= 192: return str(val - 128)
+  if 193 <= val <= 208: return str(-(val - 192))
+  if 256 <= val <= 511: return f"v{val - 256}"
+  return "lit" if val == 255 else f"?{val}"

+# Instruction base class
 class Inst:
-  _fields: list[tuple[str, BitField]]
-  _base_size: int
+  _fields: dict[str, BitField]
+  _encoding: tuple[BitField, int] | None = None
+  _defaults: dict[str, int] = {}
+  _values: dict[str, int | RawImm]
+  _words: int  # size in 32-bit words, set by decode_program
+  _literal: int | None

-  def __init_subclass__(cls):
-    # Collect fields from all parent classes, then override with this class's fields
-    inherited = {}
-    for base in reversed(cls.__mro__[1:]):
-      if hasattr(base, '_fields'):
-        inherited.update({name: field for name, field in base._fields})
-    inherited.update({name: val for name, val in cls.__dict__.items() if isinstance(val, BitField)})
-    cls._fields = list(inherited.items())
-    cls._base_size = (max(f.hi for _, f in cls._fields) + 8) // 8
+  def __init_subclass__(cls, **kwargs):
+    super().__init_subclass__(**kwargs)
+    cls._fields = {n: v[0] if isinstance(v, tuple) else v for n, v in cls.__dict__.items() if isinstance(v, BitField) or (isinstance(v, tuple) and len(v) == 2 and isinstance(v[0], BitField))}
+    if 'encoding' in cls._fields and isinstance(cls.__dict__.get('encoding'), tuple): cls._encoding = cls.__dict__['encoding']

-  def __new__(cls, *args, **kwargs):
-    # Auto-upgrade to variant if needed (only for base classes, not variants)
-    if not any(cls.__name__.endswith(sfx) for sfx in ('_LIT', '_DPP16', '_DPP8', '_SDWA', '_SDWA_SDST', '_MFMA')):
-      args_iter = iter(args)
-      for name, field in cls._fields:
-        if isinstance(field, FixedBitField): continue
-        val = kwargs.get(name) if name in kwargs else next(args_iter, None)
-        if not isinstance(field, SrcField): continue
-        if isinstance(val, Reg) and val.offset == 255 and (lit_cls := _get_variant(cls, '_LIT')): return lit_cls(*args, **kwargs)
-        if isinstance(val, Reg) and val.offset == 249:
-          if (sdwa_cls := _get_variant(cls, '_SDWA') or _get_variant(cls, '_SDWA_SDST')): return sdwa_cls(*args, **kwargs)
-        if isinstance(val, Reg) and val.offset == 250 and (dpp_cls := _get_variant(cls, '_DPP16')): return dpp_cls(*args, **kwargs)
-        if _needs_literal(val) and (lit_cls := _get_variant(cls, '_LIT')): return lit_cls(*args, **kwargs)
-    return object.__new__(cls)
+  def _or_field(self, name: str, bit: int):
+    cur = self._values.get(name, 0)
+    self._values[name] = (cur.val if isinstance(cur, RawImm) else cur) | bit

-  def __init__(self, *args, **kwargs):
-    self._raw = 0
-    # Map positional args to field names (skip FixedBitFields)
-    args_iter = iter(args)
-    vals: dict[str, Any] = {}
-    for name, field in self._fields:
-      if isinstance(field, FixedBitField): vals[name] = None
-      elif name in kwargs: vals[name] = kwargs[name]
-      else: vals[name] = next(args_iter, None)
-    assert not (remaining := list(args_iter)), f"too many positional args: {remaining}"
-    # Extract modifiers from Reg objects and merge into neg/abs/opsel
-    neg_bits, abs_bits, opsel_bits = 0, 0, 0
-    for name, bit in [('src0', 0), ('src1', 1), ('src2', 2)]:
-      if name in vals and isinstance(vals[name], Reg):
-        reg = vals[name]
-        if reg.neg: neg_bits |= (1 << bit)
-        if reg.abs_: abs_bits |= (1 << bit)
-        if reg.hi: opsel_bits |= (1 << bit)
-    if 'vdst' in vals and isinstance(vals['vdst'], Reg) and vals['vdst'].hi:
-      opsel_bits |= (1 << 3)
-    if neg_bits: vals['neg'] = (vals.get('neg') or 0) | neg_bits
-    if abs_bits: vals['abs'] = (vals.get('abs') or 0) | abs_bits
-    if opsel_bits: vals['opsel'] = (vals.get('opsel') or 0) | opsel_bits
-    # For _LIT classes, capture literal value from SrcFields that encode to 255
-    literal_val = None
-    for name, field in self._fields:
-      val = vals[name]
-      if isinstance(field, SrcField) and val is not None and _needs_literal(val):
-        literal_val = _f32(val) if isinstance(val, float) else val & 0xFFFFFFFF
-    if literal_val is not None and 'literal' in vals:
-      vals['literal'] = literal_val
-    # Set all field values
-    for name, field in self._fields:
-      self._raw = field.set(self._raw, vals[name])
-    # Validate register sizes against operand info (skip special registers like NULL, VCC, EXEC, SDWA/DPP markers)
-    for name, expected in self.op_regs.items():
-      if (val := vals.get(name)) is None: continue
-      if isinstance(val, Reg) and val.sz != expected and not (106 <= val.offset <= 127 or 249 <= val.offset <= 255):
-        raise TypeError(f"{name} expects {expected} register(s), got {val.sz}")
+  def _encode_src(self, name: str, val):
+    """Encode a source field, handling modifiers and literals."""
+    encoded = encode_src(val)
+    has_opsel = 'opsel' in self._fields
+    if isinstance(val, Reg) and val.hi and not has_opsel: encoded |= 0x80  # hi bit in src for VOP1/2/C
+    self._values[name] = RawImm(encoded)
+    # Handle neg/abs/opsel modifiers
+    if isinstance(val, SrcMod):
+      mod_bit = {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0)
+      if val.neg and 'neg' in self._fields: self._or_field('neg', mod_bit)
+      if val.abs_ and 'abs' in self._fields: self._or_field('abs', mod_bit)
+    if isinstance(val, Reg) and val.hi and has_opsel:
+      self._or_field('opsel', {'src0': 1, 'src1': 2, 'src2': 4}.get(name, 0))
+    # Track literal value if needed
+    if encoded == 255 and self._literal is None:
+      import struct
+      # Check if THIS source uses 64-bit encoding (not just src0)
+      src_idx = {'src0': 0, 'src1': 1, 'src2': 2, 'ssrc0': 0, 'ssrc1': 1}.get(name, 0)
+      src_regs = self.src_regs(src_idx)
+      is_64 = src_regs == 2
+      if isinstance(val, SrcMod) and not isinstance(val, Reg): lit32 = val.val & MASK32
+      elif isinstance(val, int) and not isinstance(val, IntEnum): lit32 = val & MASK32
+      elif isinstance(val, float): lit32 = (_i64(val) >> 32) if is_64 else _i32(val)  # f64: high 32 bits of f64 repr
+      else: return
+      self._literal = (lit32 << 32) if is_64 else lit32

-  @property
-  def op_name(self) -> str: return getattr(self, 'op').name
-  @property
-  def operands(self) -> dict: return OPERANDS.get(getattr(self, 'op'), {}) if hasattr(self, 'op') else {}
-  def _is_cdna(self) -> bool: return 'cdna' in type(self).__module__
+  def _encode_raw(self, name: str, val):
+    """Encode a raw register field (vdst, vdata, etc.)."""
+    if isinstance(val, Reg):
+      encoded = _encode_reg(val)
+      if val.hi and 'opsel' not in self._fields: encoded |= 0x80
+      self._values[name] = encoded
+      if name == 'vdst' and val.hi and 'opsel' in self._fields: self._or_field('opsel', 8)
+    elif hasattr(val, 'value'): self._values[name] = val.value

-  @functools.cached_property
-  def op_bits(self) -> dict[str, int]:
-    """Get bit widths for each operand field, with WAVE32 and addr/saddr adjustments."""
-    if not hasattr(self, 'op'): return {k: v[1] for k, v in self.operands.items()}
-    bits = {k: v[1] for k, v in self.operands.items()}
-    # RDNA (WAVE32): condition masks, carry flags, and compare results are 32-bit
-    if not self._is_cdna():
-      name = self.op_name.lower()
-      if 'cndmask' in name and 'src2' in bits: bits['src2'] = 32
-      if '_co_ci_' in name and 'src2' in bits: bits['src2'] = 32  # carry-in source
-      # VOP3SD: sdst is always wavefront-size dependent (carry-out or condition mask)
-      if 'VOP3SD' in type(self).__name__ and 'sdst' in bits: bits['sdst'] = 32
-      if 'cmp' in name and 'vdst' in bits: bits['vdst'] = 32
-    # GLOBAL/FLAT: addr is 32-bit if saddr is valid SGPR, 64-bit if saddr is NULL
-    # SCRATCH: addr is always 32-bit (offset from scratch base, not absolute address)
-    if 'addr' in bits and (saddr_field := getattr(type(self), 'saddr', None)) and type(self).__name__ not in ('SCRATCH', 'VSCRATCH'):
-      saddr_val = (self._raw >> saddr_field.lo) & saddr_field.mask  # access _raw directly to avoid recursion
-      bits['addr'] = 64 if saddr_val in (124, 125) else 32  # 124=NULL, 125=M0
-    # MUBUF/MTBUF: vaddr size depends on offen/idxen (1 or 2 regs)
-    if 'vaddr' in bits and hasattr(self, 'offen') and hasattr(self, 'idxen'):
-      bits['vaddr'] = max(1, self.offen + self.idxen) * 32
-    # F8F6F4 MFMA: CBSZ selects matrix A format, BLGP selects matrix B format
-    # VGPRs: FP8/BF8(0,1)=8, FP6/BF6(2,3)=6, FP4(4)=4
-    if 'f8f6f4' in getattr(self, 'op_name', '').lower():
-      # Use explicit fields if available (VOP3PX2), else extract from VOP3P-MAI bit positions
-      cbsz = getattr(self, 'cbsz') if hasattr(type(self), 'cbsz') else (self._raw >> 8) & 0x7
-      blgp = getattr(self, 'blgp') if hasattr(type(self), 'blgp') else (self._raw >> 61) & 0x7
-      vgprs = {0: 8, 1: 8, 2: 6, 3: 6, 4: 4}
-      bits['src0'], bits['src1'] = vgprs.get(cbsz, 8) * 32, vgprs.get(blgp, 8) * 32
-    return bits
-  @property
-  def op_regs(self) -> dict[str, int]:
-    """Get register counts for each operand field."""
-    return {k: max(1, v // 32) for k, v in self.op_bits.items()}
+  def _validate(self, orig_args: dict):
+    """Format-specific validation. Override in subclass or check by class name."""
+    cls_name, op = self.__class__.__name__, orig_args.get('op')
+    if hasattr(op, 'value'): op = op.value
+    # SMEM: register count must match opcode
+    if cls_name == 'SMEM' and op is not None:
+      expected = {0:1, 1:2, 2:4, 3:8, 4:16, 8:1, 9:2, 10:4, 11:8, 12:16}.get(op)
+      sdata = orig_args.get('sdata')
+      if expected and isinstance(sdata, Reg) and sdata.count != expected:
+        raise ValueError(f"SMEM op {op} expects {expected} registers, got {sdata.count}")
+    # SOP1: b32=1 reg, b64=2 regs
+    if cls_name == 'SOP1' and hasattr(orig_args.get('op'), 'name'):
+      expected = 2 if orig_args['op'].name.endswith('_B64') else 1
+      for fld in ('sdst', 'ssrc0'):
+        if isinstance(orig_args.get(fld), Reg) and orig_args[fld].count != expected:
+          raise ValueError(f"SOP1 {orig_args['op'].name} expects {expected} register(s) for {fld}, got {orig_args[fld].count}")

-  @functools.cached_property
-  def canonical_op_bits(self) -> dict[str, int]:
-    """Get bit widths with canonical names: {'s0', 's1', 's2', 'd', 'data'}."""
-    bits = {'d': 32, 's0': 32, 's1': 32, 's2': 32, 'data': 32}
-    for name, val in self.op_bits.items():
-      if (cn := _canonical_name(name)): bits[cn] = val
-    return bits
+  def __init__(self, *args, literal: int | None = None, **kwargs):
+    self._values, self._literal = dict(self._defaults), None
+    field_names = [n for n in self._fields if n != 'encoding']
+    orig_args = dict(zip(field_names, args)) | kwargs
+    self._values.update(orig_args)
+    self._validate(orig_args)
+    # Pre-shift literal for 64-bit sources (literal param is always raw 32-bit value from user)
+    if literal is not None:
+      # Find which source uses the literal (255) and check its register count
+      for n, idx in [('src0', 0), ('src1', 1), ('src2', 2), ('ssrc0', 0), ('ssrc1', 1)]:
+        v = orig_args.get(n)
+        if (isinstance(v, RawImm) and v.val == 255) or (isinstance(v, int) and v == 255):
+          self._literal = (literal << 32) if self.src_regs(idx) == 2 else literal
+          break
+      else:
+        self._literal = literal  # fallback if no literal source found
+    cls_name = self.__class__.__name__

-  @functools.cached_property
-  def canonical_operands(self) -> dict:
-    """Get operands with canonical names: {'s0', 's1', 's2', 'd', 'data'}."""
-    result = {}
-    for name, val in self.operands.items():
-      if (cn := _canonical_name(name)): result[cn] = val
-    return result
+    # Format-specific setup
+    if cls_name == 'FLAT' and 'sve' in self._fields:
+      seg = self._values.get('seg', 0)
+      if (seg.val if isinstance(seg, RawImm) else seg) == 1 and isinstance(orig_args.get('addr'), VGPR): self._values['sve'] = 1
+    if cls_name == 'VOP3P':
+      op = orig_args.get('op')
+      if hasattr(op, 'value'): op = op.value
+      if op in (32, 33, 34) and 'opsel_hi' not in orig_args: self._values['opsel_hi'] = self._values['opsel_hi2'] = 0

-  @property
-  def canonical_op_regs(self) -> dict[str, int]:
-    """Get register counts with canonical names: {'s0', 's1', 's2', 'd', 'data'}."""
-    return {k: max(1, v // 32) for k, v in self.canonical_op_bits.items()}
+    # Encode all fields
+    for name, val in list(self._values.items()):
+      if name == 'encoding': continue
+      if isinstance(val, RawImm):
+        if name in RAW_FIELDS: self._values[name] = val.val
+        continue
+      field = self._fields.get(name)
+      marker = field.marker if field else None
+      # Type validation
+      if marker is _SGPRField and isinstance(val, VGPR): raise TypeError(f"field '{name}' requires SGPR, got VGPR")
+      if marker is _VGPRField and not isinstance(val, VGPR): raise TypeError(f"field '{name}' requires VGPR, got {type(val).__name__}")
+      if marker is _SSrc and isinstance(val, VGPR): raise TypeError(f"field '{name}' requires scalar source, got VGPR")
+      # Encode by field type
+      if name in SRC_FIELDS: self._encode_src(name, val)
+      elif name in RAW_FIELDS: self._encode_raw(name, val)
+      elif name == 'sbase': self._values[name] = (val.idx if isinstance(val, Reg) else val.val if isinstance(val, SrcMod) else val * 2) // 2
+      elif name in {'srsrc', 'ssamp'} and isinstance(val, Reg): self._values[name] = val.idx // 4
+      elif marker is _VDSTYEnc and isinstance(val, VGPR): self._values[name] = val.idx >> 1

-  def num_srcs(self) -> int:
-    """Get number of source operands from operand info."""
-    ops = self.operands
-    if 'src2' in ops: return 3
-    if 'src1' in ops or 'vsrc1' in ops or 'ssrc1' in ops: return 2
-    if 'src0' in ops or 'vsrc0' in ops or 'ssrc0' in ops: return 1
-    return 0
-  @classmethod
-  def _size(cls) -> int: return cls._base_size
-  def size(self) -> int: return self._base_size
-  def disasm(self) -> str:
-    from extra.assembly.amd.disasm import disasm
-    return disasm(self)
+  def _encode_field(self, name: str, val) -> int:
+    if isinstance(val, RawImm): return val.val
+    if isinstance(val, SrcMod) and not isinstance(val, Reg): return val.val  # Special regs like VCC_LO
+    if name in {'srsrc', 'ssamp'}: return val.idx // 4 if isinstance(val, Reg) else val
+    if name == 'sbase': return val.idx // 2 if isinstance(val, Reg) else val.val // 2 if isinstance(val, SrcMod) else val
+    if name in RAW_FIELDS: return _encode_reg(val) if isinstance(val, Reg) else val
+    if isinstance(val, Reg) or name in SRC_FIELDS: return encode_src(val)
+    return val.value if hasattr(val, 'value') else val

-  def to_bytes(self) -> bytes: return self._raw.to_bytes(self._base_size, 'little')
+  def to_int(self) -> int:
+    word = (self._encoding[1] & self._encoding[0].mask()) << self._encoding[0].lo if self._encoding else 0
+    for n, bf in self._fields.items():
+      if n != 'encoding' and n in self._values: word |= (self._encode_field(n, self._values[n]) & bf.mask()) << bf.lo
+    return word

-  @property
-  def _literal(self) -> int | None:
-    """Get the literal value if this instruction has one."""
-    return getattr(self, 'literal', None)
-
-  def _variant_suffix(self) -> str | None:
-    """Check if instruction needs a variant class (_LIT, _DPP8, _DPP16, _SDWA). Returns suffix or None."""
-    cls_name = type(self).__name__
-    # Don't check for variants if we're already a variant class
-    if any(s in cls_name for s in ('_LIT', '_DPP8', '_DPP16', '_SDWA')): return None
-    # VOPD: FMAMK/FMAAK opcodes always require literal (check by name since enum may differ across archs)
-    for name in ('opx', 'opy'):
-      if hasattr(self, name) and any(x in getattr(self, name).name for x in ('FMAMK', 'FMAAK')): return '_LIT'
-    for name, field in self._fields:
-      if isinstance(field, SrcField):
-        off = getattr(self, name).offset
-        if off == 255: return '_LIT'
-        if off == 249: return '_SDWA' if self._is_cdna() else '_DPP8'
-        if off == 250: return '_DPP16'
+  def _get_literal(self) -> int | None:
+    for n in SRC_FIELDS:
+      if n in self._values and not isinstance(v := self._values[n], RawImm) and isinstance(v, int) and not isinstance(v, IntEnum) and not (0 <= v <= 64 or -16 <= v <= -1): return v
    return None

+  def _is_64bit_op(self) -> bool:
+    """Check if this instruction uses 64-bit operands (and thus 64-bit literals)."""
+    op = self._values.get('op')
+    if op is None: return False
+    op_name = op.name if hasattr(op, 'name') else None
+    # Look up op name from int if needed (happens in from_bytes path)
+    if op_name is None and self.__class__.__name__ == 'VOP3':
+      try: op_name = VOP3Op(op).name
+      except ValueError: pass
+    if op_name is None and self.__class__.__name__ == 'VOPC':
+      try: op_name = VOPCOp(op).name
+      except ValueError: pass
+    if op_name is None: return False
+    # V_LDEXP_F64 has 32-bit integer src1, so literal is 32-bit
+    return op_name != 'V_LDEXP_F64' and op_name.endswith(('_F64', '_B64', '_I64', '_U64'))
+
+  def to_bytes(self) -> bytes:
+    result = self.to_int().to_bytes(self._size(), 'little')
+    lit = self._get_literal() or getattr(self, '_literal', None)
+    if lit is None: return result
+    # For 64-bit sources, literal is stored in high 32 bits internally, but encoded as 4 bytes
+    # Find which source uses the literal (255) and check its register count
+    lit_src_is_64 = False
+    for n, idx in [('src0', 0), ('src1', 1), ('src2', 2), ('ssrc0', 0), ('ssrc1', 1)]:
+      if n not in self._values: continue
+      v = self._values[n]
+      if (isinstance(v, RawImm) and v.val == 255) or (isinstance(v, int) and v == 255):
+        lit_src_is_64 = self.is_src_64(idx)
+        break
+    lit32 = (lit >> 32) if lit_src_is_64 else lit
+    return result + (lit32 & MASK32).to_bytes(4, 'little')
+
+  @classmethod
+  def _size(cls) -> int: return 4 if issubclass(cls, Inst32) else 8
+  def size(self) -> int:
+    # Literal is always 4 bytes in the binary (for 64-bit ops, it's in high 32 bits)
+    return self._size() + (4 if self._literal is not None else 0)
+
+  @classmethod
+  def from_int(cls, word: int):
+    inst = object.__new__(cls)
+    inst._values = {n: RawImm(v) if n in SRC_FIELDS else v for n, bf in cls._fields.items() if n != 'encoding' for v in [(word >> bf.lo) & bf.mask()]}
+    inst._literal = None
+    return inst
+
  @classmethod
  def from_bytes(cls, data: bytes):
-    inst = object.__new__(cls)
-    inst._raw = int.from_bytes(data[:cls._base_size], 'little')
-    # Upgrade to variant class if needed (_LIT, _DPP8, _DPP16, _SDWA)
-    if (suffix := inst._variant_suffix()) and (var_cls := _get_variant(cls, suffix)) is not None:
-      return var_cls.from_bytes(data)
+    inst = cls.from_int(int.from_bytes(data[:cls._size()], 'little'))
+    op_val = inst._values.get('op', 0)
+    has_literal = cls.__name__ == 'VOP2' and op_val in (44, 45, 55, 56)
+    has_literal = has_literal or (cls.__name__ == 'SOP2' and op_val in (69, 70))
+    # VOPD fmaak/fmamk always have a literal (opx/opy value 1 or 2)
+    opx, opy = inst._values.get('opx', 0), inst._values.get('opy', 0)
+    has_literal = has_literal or (cls.__name__ == 'VOPD' and (opx in (1, 2) or opy in (1, 2)))
+    for n in SRC_FIELDS:
+      if n in inst._values and isinstance(inst._values[n], RawImm) and inst._values[n].val == 255: has_literal = True
+    if has_literal:
+      # For 64-bit ops, the literal is 32 bits placed in the HIGH 32 bits of the 64-bit value
+      # (low 32 bits are zero). This is how AMD hardware interprets 32-bit literals for 64-bit ops.
+      # Check which source uses the literal and whether THAT source is 64-bit
+      if len(data) >= cls._size() + 4:
+        lit32 = int.from_bytes(data[cls._size():cls._size()+4], 'little')
+        # Find which source has literal (255) and check its register count
+        lit_src_is_64 = False
+        for n, idx in [('src0', 0), ('src1', 1), ('src2', 2)]:
+          if n in inst._values and isinstance(inst._values[n], RawImm) and inst._values[n].val == 255:
+            lit_src_is_64 = inst.src_regs(idx) == 2
+            break
+        inst._literal = (lit32 << 32) if lit_src_is_64 else lit32
    return inst

-  def __eq__(self, other): return type(self) is type(other) and self._raw == other._raw
-  def __hash__(self): return hash((type(self), self._raw))
-
  def __repr__(self):
-    # collect (repr, is_default) pairs, strip trailing defaults so repr roundtrips with eval
-    name = self.op.name.lower() if hasattr(self, 'op') else type(self).__name__
-    parts = [(repr(v := getattr(self, n)), v == f.default) for n, f in self._fields if n != 'op' and not isinstance(f, FixedBitField)]
-    while parts and parts[-1][1]: parts.pop()
-    return f"{name}({', '.join(p[0] for p in parts)})"
+    # Use _fields order and exclude fields that are 0/default (for consistent repr after roundtrip)
+    def is_zero(v): return (isinstance(v, int) and v == 0) or (isinstance(v, VGPR) and v.idx == 0 and v.count == 1)
+    items = [(k, self._values[k]) for k in self._fields if k in self._values and k != 'encoding'
+             and not (is_zero(self._values[k]) and k not in {'op'})]
+    lit = f", literal={hex(self._literal)}" if self._literal is not None else ""
+    return f"{self.__class__.__name__}({', '.join(f'{k}={v}' for k, v in items)}{lit})"
+
+  def __getattr__(self, name: str):
+    if name.startswith('_'): raise AttributeError(name)
+    return unwrap(self._values.get(name, 0))
+
+  def lit(self, v: int, neg: bool = False) -> str:
+    s = f"0x{self._literal:x}" if v == 255 and self._literal else decode_src(v)
+    return f"-{s}" if neg else s
+
+  def __eq__(self, other):
+    if not isinstance(other, Inst): return NotImplemented
+    return self.__class__ == other.__class__ and self._values == other._values and self._literal == other._literal
+
+  def __hash__(self): return hash((self.__class__.__name__, tuple(sorted((k, repr(v)) for k, v in self._values.items())), self._literal))
+
+  def disasm(self) -> str:
+    from extra.assembly.amd.asm import disasm
+    return disasm(self)
+
+  _enum_map = {'VOP1': VOP1Op, 'VOP2': VOP2Op, 'VOP3': VOP3Op, 'VOP3SD': VOP3SDOp, 'VOP3P': VOP3POp, 'VOPC': VOPCOp,
+               'SOP1': SOP1Op, 'SOP2': SOP2Op, 'SOPC': SOPCOp, 'SOPK': SOPKOp, 'SOPP': SOPPOp,
+               'SMEM': SMEMOp, 'DS': DSOp, 'FLAT': FLATOp, 'MUBUF': MUBUFOp, 'MTBUF': MTBUFOp, 'MIMG': MIMGOp,
+               'VOPD': VOPDOp, 'VINTERP': VINTERPOp}
+  _VOP3SD_OPS = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770}
+
+  @property
+  def op(self):
+    """Return the op as an enum (e.g., VOP1Op.V_MOV_B32). VOP3 returns VOPCOp/VOP3SDOp for those op ranges."""
+    val = self._values.get('op')
+    if val is None: return None
+    if hasattr(val, 'name'): return val  # already an enum
+    cls_name = self.__class__.__name__
+    assert cls_name in self._enum_map, f"no enum map for {cls_name}"
+    return self._enum_map[cls_name](val)
+
+  @cached_property
+  def op_name(self) -> str:
+    op = self.op
+    return op.name if hasattr(op, 'name') else ''
+
+  @cached_property
+  def _spec_regs(self) -> tuple[int, int, int, int]: return spec_regs(self.op_name)
+  @cached_property
+  def _spec_dtype(self) -> tuple[str | None, str | None, str | None, str | None]: return spec_dtype(self.op_name)
+  def dst_regs(self) -> int: return self._spec_regs[0]
+  def src_regs(self, n: int) -> int: return self._spec_regs[n + 1]
+  def num_srcs(self) -> int: return spec_num_srcs(self.op_name)
+  def dst_dtype(self) -> str | None: return self._spec_dtype[0]
+  def src_dtype(self, n: int) -> str | None: return self._spec_dtype[n + 1]
+  def is_src_16(self, n: int) -> bool: return self._spec_regs[n + 1] == 1 and is_dtype_16(self._spec_dtype[n + 1])
+  def is_src_64(self, n: int) -> bool: return self._spec_regs[n + 1] == 2
+  def is_16bit(self) -> bool: return spec_is_16bit(self.op_name)
+  def is_64bit(self) -> bool: return spec_is_64bit(self.op_name)
+  def is_dst_16(self) -> bool: return self._spec_regs[0] == 1 and is_dtype_16(self._spec_dtype[0])
+
+class Inst32(Inst): pass
+class Inst64(Inst): pass
@@ -1,480 +0,0 @@
-# AMD ISA code generator - generates enum.py, ins.py, operands.py, str_pcode.py
-# Sources: XML from https://gpuopen.com/download/machine-readable-isa/latest/
-#          PDF manuals from AMD documentation
-import re, zlib, xml.etree.ElementTree as ET, zipfile
-from tinygrad.helpers import fetch
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# Configuration
-# ═══════════════════════════════════════════════════════════════════════════════
-
-ARCHS = {
-  "rdna3": {"xml": "amdgpu_isa_rdna3_5.xml", "pdf": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content"},
-  "rdna4": {"xml": "amdgpu_isa_rdna4.xml", "pdf": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content"},
-  "cdna": {"xml": "amdgpu_isa_cdna4.xml", "pdf": "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"},
-}
-XML_URL = "https://gpuopen.com/download/machine-readable-isa/latest/"
-# Map XML encoding names to codebase names
-NAME_MAP = {"VOP3_SDST_ENC": "VOP3SD", "VOP3_SDST_ENC_LIT": "VOP3SD_LIT", "VOP3_SDST_ENC_DPP16": "VOP3SD_DPP16",
-            "VOP3_SDST_ENC_DPP8": "VOP3SD_DPP8", "VOPDXY": "VOPD", "VOPDXY_LIT": "VOPD_LIT", "VDS": "DS"}
-# Instructions missing from XML but present in PDF
-FIXES = {"rdna3": {"SOPK": {22: "S_SUBVECTOR_LOOP_BEGIN", 23: "S_SUBVECTOR_LOOP_END"}, "FLAT": {55: "FLAT_ATOMIC_CSUB_U32"}},
-         "rdna4": {"SOP1": {80: "S_GET_BARRIER_STATE", 81: "S_BARRIER_INIT", 82: "S_BARRIER_JOIN"}, "SOPP": {9: "S_WAITCNT", 21: "S_BARRIER_LEAVE"}},
-         "cdna": {"DS": {152: "DS_GWS_SEMA_RELEASE_ALL", 154: "DS_GWS_SEMA_V", 156: "DS_GWS_SEMA_P"},
-                  "VOP3P": {44: "V_MFMA_LD_SCALE_B32", 62: "V_MFMA_F32_16X16X8_XF32", 63: "V_MFMA_F32_32X32X4_XF32"}}}
-# Fields missing from XML but present in hardware (format: {arch: {encoding: [(name, hi, lo), ...]}})
-FIELD_FIXES = {"cdna": {"VOP3P": [("opsel_hi2", 14, 14)]}}
-# Encoding suffixes to strip (variants we don't generate separate classes for)
-_ENC_SUFFIXES = ("_NSA1",)
-# Encoding suffix to class suffix mapping (for variants we DO generate)
-_ENC_SUFFIX_MAP = {"_INST_LITERAL": "_LIT", "_VOP_DPP16": "_DPP16", "_VOP_DPP": "_DPP16", "_VOP_DPP8": "_DPP8",
-                   "_VOP_SDWA": "_SDWA", "_VOP_SDWA_SDST_ENC": "_SDWA_SDST", "_MFMA": "_MFMA"}
-# Field name normalization
-_FIELD_RENAMES = {"opsel_hi_2": "opsel_hi2", "op_sel_hi_2": "opsel_hi2", "op_sel": "opsel", "bound_ctrl": "bc",
-                  "tgt": "target", "row_en": "row", "unorm": "unrm", "clamp": "clmp", "wait_exp": "waitexp",
-                  "simm32": "literal", "dpp_ctrl": "dpp", "acc_cd": "acc_cd", "acc": "acc",
-                  "dst_sel": "dst_sel", "dst_unused": "dst_unused", "src0_sel": "src0_sel", "src1_sel": "src1_sel"}
-# Encoding variants to skip entirely (NSA is for MIMG graphics instructions)
-_SKIP_ENCODINGS = ("NSA",)
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# XML parsing helpers
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def _strip_enc(name: str) -> str:
-  """Strip ENC_ prefix and normalize encoding suffixes."""
-  name = name.removeprefix("ENC_")
-  for sfx in _ENC_SUFFIXES: name = name.replace(sfx, "")
-  # Process longer suffixes first to avoid partial matches (e.g., _VOP_DPP8 before _VOP_DPP)
-  for old, new in sorted(_ENC_SUFFIX_MAP.items(), key=lambda x: -len(x[0])): name = name.replace(old, new)
-  return name
-
-def _norm_field(name: str) -> str:
-  """Normalize field name to match expected names."""
-  for old, new in _FIELD_RENAMES.items(): name = name.replace(old, new)
-  return name
-
-def _map_flat(enc_name: str, instr_name: str) -> str:
-  """Map FLAT/GLOBAL/SCRATCH encoding to correct enum based on instruction prefix."""
-  if enc_name in ("FLAT_GLBL", "FLAT_GLOBAL"): return "GLOBAL"
-  if enc_name == "FLAT_SCRATCH": return "SCRATCH"
-  if enc_name in ("FLAT", "VFLAT", "VGLOBAL", "VSCRATCH"):
-    v = "V" if enc_name.startswith("V") else ""
-    if instr_name.startswith("GLOBAL_"): return f"{v}GLOBAL"
-    if instr_name.startswith("SCRATCH_"): return f"{v}SCRATCH"
-    return f"{v}FLAT"
-  return enc_name
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# XML parsing
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def parse_xml(filename: str):
-  root = ET.fromstring(zipfile.ZipFile(fetch(XML_URL)).read(filename))
-  encodings, enums, types, fmts, op_types_set = {}, {}, {}, {}, set()
-  # Extract HWREG and MSG enums from OperandTypes
-  op_enum_map = {("OPR_HWREG", "ID"): "HWREG", ("OPR_SENDMSG_RTN", "MSG"): "MSG"}
-  for ot in root.findall(".//OperandTypes/OperandType"):
-    ot_name = ot.findtext("OperandTypeName")
-    for field in ot.findall(".//Field"):
-      if (enum_name := op_enum_map.get((ot_name, field.findtext("FieldName")))):
-        enums[enum_name] = {int(pv.findtext("Value")): pv.findtext("Name").upper() for pv in field.findall(".//PredefinedValue")}
-  # Extract DataFormats with BitCount
-  for df in root.findall("ISA/DataFormats/DataFormat"):
-    name, bits = df.findtext("DataFormatName"), df.findtext("BitCount")
-    if name and bits: fmts[name] = int(bits)
-  # Extract encoding definitions
-  for enc in root.findall("ISA/Encodings/Encoding"):
-    name = enc.findtext("EncodingName")
-    is_base = name.startswith("ENC_") or name in ("VOP3_SDST_ENC", "VOPDXY")
-    is_variant = any(sfx in name for sfx in _ENC_SUFFIX_MAP)
-    if not is_base and not is_variant: continue
-    if any(s in name for s in _SKIP_ENCODINGS): continue
-    fields = [(_norm_field(f.findtext("FieldName").lower()), int(f.find("BitLayout/Range").findtext("BitOffset") or 0) + int(f.find("BitLayout/Range").findtext("BitCount") or 0) - 1,
-               int(f.find("BitLayout/Range").findtext("BitOffset") or 0))
-              for f in enc.findall(".//MicrocodeFormat/BitMap/Field") if f.find("BitLayout/Range") is not None]
-    ident = (enc.findall("EncodingIdentifiers/EncodingIdentifier") or [None])[0]
-    enc_field = next((f for f in fields if f[0] == "encoding"), None)
-    # For multi-dword formats, encoding field may be in higher dword but identifier pattern is always in dword0; use % 32
-    enc_bits = "".join(ident.text[len(ident.text)-1-b] for b in range(enc_field[1] % 32, (enc_field[2] % 32)-1, -1)) if ident is not None and enc_field else None
-    base_name = _strip_enc(name)
-    encodings[NAME_MAP.get(base_name, base_name)] = (fields, enc_bits)
-  # Extract instruction opcodes and operand info
-  # Track which encodings each opcode appears in (for detecting LIT-only ops)
-  opcode_encs: dict[str, dict[int, set[str]]] = {}  # {base_fmt: {opcode: {enc_names}}}
-  for instr in root.findall("ISA/Instructions/Instruction"):
-    name = instr.findtext("InstructionName")
-    for enc in instr.findall("InstructionEncodings/InstructionEncoding"):
-      if enc.findtext("EncodingCondition") != "default": continue
-      base, opcode = _map_flat(_strip_enc(enc.findtext("EncodingName")), name), int(enc.findtext("Opcode") or 0)
-      enc_name = NAME_MAP.get(base, base)
-      # Encoding variants use the same Op enum as the base format
-      base_enum = enc_name
-      for sfx in ("_SDWA_SDST", "_DPP16", "_DPP8", "_SDWA", "_LIT", "_MFMA"):
-        base_enum = base_enum.replace(sfx, "")
-      # Track which encodings this opcode appears in
-      opcode_encs.setdefault(base_enum, {}).setdefault(opcode, set()).add(enc_name)
-      # ADDTID instructions go in both FLAT and GLOBAL enums (pcode uses FLATOp for these)
-      if "ADDTID" in name:
-        if base == "GLOBAL": enums.setdefault("FLAT", {})[opcode] = name
-        elif base == "VGLOBAL": enums.setdefault("VFLAT", {})[opcode] = name
-      enums.setdefault(base_enum, {})[opcode] = name
-      # Extract operand info
-      op_info = {op.findtext("FieldName").lower(): (op.findtext("DataFormatName"), int(op.findtext("OperandSize") or 0), op.findtext("OperandType"))
-                 for op in enc.findall("Operands/Operand") if op.findtext("FieldName")}
-      for fmt, _, otype in op_info.values():
-        if fmt and fmt not in fmts: fmts[fmt] = 0
-        if otype: op_types_set.add(otype)
-      if op_info: types[(name, base_enum)] = op_info
-  # Find opcodes that only exist in a specific variant encoding (no base format version)
-  suffix_only_ops: dict[str, dict[str, set[int]]] = {}  # {suffix: {base_fmt: {opcodes}}}
-  for base_fmt, opcodes in opcode_encs.items():
-    for opcode, encs in opcodes.items():
-      suffix = next((s for s in _ENC_SUFFIX_MAP.values() if all(s in e for e in encs)), None)
-      if suffix is not None: suffix_only_ops.setdefault(suffix, {}).setdefault(base_fmt, set()).add(opcode)
-  return encodings, enums, types, fmts, op_types_set, suffix_only_ops
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# PDF parsing
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def extract_pdf_text(url: str) -> list[list[tuple[float, float, str, str]]]:
-  """Extract positioned text from PDF. Returns list of text elements (x, y, text, font) per page."""
-  data = fetch(url).read_bytes()
-  # Parse xref table to locate objects
-  xref: dict[int, int] = {}
-  pos = int(re.search(rb'startxref\s+(\d+)', data).group(1)) + 4
-  while data[pos:pos+7] != b'trailer':
-    while data[pos:pos+1] in b' \r\n': pos += 1
-    line_end = data.find(b'\n', pos)
-    start_obj, count = map(int, data[pos:line_end].split()[:2])
-    pos = line_end + 1
-    for i in range(count):
-      if data[pos+17:pos+18] == b'n' and (off := int(data[pos:pos+10])) > 0: xref[start_obj + i] = off
-      pos += 20
-
-  def get_stream(n: int) -> bytes:
-    obj = data[xref[n]:data.find(b'endobj', xref[n])]
-    raw = obj[obj.find(b'stream\n') + 7:obj.find(b'\nendstream')]
-    return zlib.decompress(raw) if b'/FlateDecode' in obj else raw
-
-  pages = []
-  for n in sorted(xref):
-    if b'/Type /Page' not in data[xref[n]:xref[n]+500]: continue
-    if not (m := re.search(rb'/Contents (\d+) 0 R', data[xref[n]:xref[n]+500])): continue
-    stream = get_stream(int(m.group(1))).decode('latin-1')
-    elements, font = [], ''
-    for bt in re.finditer(r'BT(.*?)ET', stream, re.S):
-      x, y = 0.0, 0.0
-      for m in re.finditer(r'(/F[\d.]+) [\d.]+ Tf|([\d.+-]+) ([\d.+-]+) Td|[\d.+-]+ [\d.+-]+ [\d.+-]+ [\d.+-]+ ([\d.+-]+) ([\d.+-]+) Tm|<([0-9A-Fa-f]+)>.*?Tj|\[([^\]]+)\] TJ', bt.group(1)):
-        if m.group(1): font = m.group(1)
-        elif m.group(2): x, y = x + float(m.group(2)), y + float(m.group(3))
-        elif m.group(4): x, y = float(m.group(4)), float(m.group(5))
-        elif m.group(6) and (t := bytes.fromhex(m.group(6)).decode('latin-1')).strip(): elements.append((x, y, t, font))
-        elif m.group(7) and (t := ''.join(bytes.fromhex(h).decode('latin-1') for h in re.findall(r'<([0-9A-Fa-f]+)>', m.group(7)))).strip(): elements.append((x, y, t, font))
-    pages.append(sorted(elements, key=lambda e: (-e[1], e[0])))
-  return pages
-
-def extract_pcode(pages: list[list[tuple[float, float, str, str]]], name_to_op: dict[str, int]) -> dict[tuple[str, int], str]:
-  """Extract pseudocode for instructions. Returns {(name, opcode): pseudocode}."""
-  # First pass: find all instruction headers across all pages
-  all_instructions: list[tuple[int, float, str, int]] = []  # (page_idx, y, name, opcode)
-  for page_idx, page in enumerate(pages):
-    by_y: dict[int, list[tuple[float, str]]] = {}
-    for x, y, t, _ in page:
-      by_y.setdefault(round(y), []).append((x, t))
-    for y, items in sorted(by_y.items(), reverse=True):
-      left = [(x, t) for x, t in items if 55 < x < 65]
-      right = [(x, t) for x, t in items if 535 < x < 550]
-      if left and right and left[0][1] in name_to_op and right[0][1].isdigit():
-        all_instructions.append((page_idx, y, left[0][1], int(right[0][1])))
-
-  # Second pass: extract pseudocode between consecutive instructions
-  pcode: dict[tuple[str, int], str] = {}
-  for i, (page_idx, y, name, opcode) in enumerate(all_instructions):
-    if i + 1 < len(all_instructions):
-      next_page, next_y = all_instructions[i + 1][0], all_instructions[i + 1][1]
-    else:
-      next_page, next_y = page_idx, 0
-    # Collect F6 text from current position to next instruction (pseudocode is at x ≈ 69)
-    lines = []
-    for p in range(page_idx, next_page + 1):
-      start_y = y if p == page_idx else 800
-      end_y = next_y if p == next_page else 0
-      lines.extend((p, y2, t) for x, y2, t, f in pages[p] if f in ('/F6.0', '/F7.0') and end_y < y2 < start_y and 60 < x < 80)
-    if lines:
-      sorted_lines = sorted(lines, key=lambda x: (x[0], -x[1]))
-      # Stop at large Y gaps (>30) - indicates section break
-      filtered = [sorted_lines[0]]
-      for j in range(1, len(sorted_lines)):
-        prev_page, prev_y, _ = sorted_lines[j-1]
-        curr_page, curr_y, _ = sorted_lines[j]
-        if curr_page == prev_page and prev_y - curr_y > 30: break
-        if curr_page != prev_page and prev_y > 60 and curr_y < 730: break
-        filtered.append(sorted_lines[j])
-      pcode_lines = [t.replace('Ê', '').strip() for _, _, t in filtered]
-      if pcode_lines: pcode[(name, opcode)] = '\n'.join(pcode_lines)
-  return pcode
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# Code generation
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def write_common(all_fmts, all_op_types, path):
-  lines = ["# autogenerated from AMD ISA XML - do not edit", "from enum import Enum, auto", ""]
-  lines.append("class ReprEnum(Enum):")
-  lines.append('  """Enum with clean repr that roundtrips with eval()."""')
-  lines.append('  def __repr__(self): return f"{type(self).__name__}.{self.name}"')
-  lines.append("")
-  lines.append("class Fmt(Enum):")
-  for fmt in sorted(all_fmts.keys()): lines.append(f"  {fmt} = auto()")
-  lines.append("")
-  lines.append("FMT_BITS = {")
-  for fmt, bits in sorted(all_fmts.items()): lines.append(f"  Fmt.{fmt}: {bits},")
-  lines.append("}")
-  lines.append("")
-  lines.append("class OpType(Enum):")
-  for ot in sorted(all_op_types): lines.append(f"  {ot} = auto()")
-  with open(path, "w") as f: f.write("\n".join(lines))
-
-def write_enum(enums, path):
-  lines = ["# autogenerated from AMD ISA XML - do not edit", "from extra.assembly.amd.autogen.common import ReprEnum, Fmt, FMT_BITS, OpType  # noqa: F401", ""]
-  for name, ops in sorted(enums.items()):
-    if not ops: continue
-    suffix = "_E32" if name in ("VOP1", "VOP2", "VOPC") else "_E64" if name == "VOP3" else ""
-    lines.append(f"class {name}(ReprEnum):" if name in ("HWREG", "MSG") else f"class {name}Op(ReprEnum):")
-    aliases = []
-    for op, mem in sorted(ops.items()):
-      msuf = suffix if name != "VOP3" or op < 512 else ""
-      lines.append(f"  {mem}{msuf} = {op}")
-      if msuf: aliases.append((mem, msuf))
-    for mem, msuf in aliases: lines.append(f"  {mem} = {mem}{msuf}")
-    lines.append("")
-  with open(path, "w") as f: f.write("\n".join(lines))
-
-def write_ins(encodings, enums, suffix_only_ops, types, arch, path):
-  _VGPR_FIELDS = {"vdst", "vdstx", "vsrc0", "vsrc1", "vsrc2", "vsrc3", "vsrcx1", "vsrcy1", "vaddr", "vdata", "data", "data0", "data1", "addr", "vsrc"}
-  _VARIANT_SUFFIXES = ("_LIT", "_DPP16", "_DPP8", "_SDWA_SDST", "_SDWA", "_MFMA")
-  def get_base_fmt(fmt):
-    for sfx in _VARIANT_SUFFIXES: fmt = fmt.replace(sfx, "")
-    return fmt
-  def field_def(name, hi, lo, fmt, enc_bits=None):
-    bits = hi - lo + 1
-    base_fmt = get_base_fmt(fmt)
-    if name == "encoding" and enc_bits: return f"FixedBitField({hi}, {lo}, 0b{enc_bits})"
-    if name == "op" and fmt not in ("DPP", "SDWA"): return f"EnumBitField({hi}, {lo}, {base_fmt}Op)"
-    if name in ("opx", "opy"): return f"EnumBitField({hi}, {lo}, VOPDOp)"
-    if name == "vdsty": return f"VDSTYField({hi}, {lo})"
-    if name in _VGPR_FIELDS and bits == 8: return f"VGPRField({hi}, {lo})"
-    if name == "sbase" and bits == 6: return f"SBaseField({hi}, {lo})"
-    if name in ("srsrc", "ssamp") and bits == 5: return f"SRsrcField({hi}, {lo})"
-    if name in ("sdst", "sdata") and bits == 7: return f"SGPRField({hi}, {lo})"
-    if name in ("soffset", "saddr") and bits == 7: return f"SGPRField({hi}, {lo}, default=NULL)"
-    if name.startswith("ssrc") and bits == 8: return f"SSrcField({hi}, {lo})"
-    if name in ("saddr", "soffset") and bits == 8: return f"SSrcField({hi}, {lo}, default=NULL)"
-    if name.startswith("src") and bits == 9: return f"SrcField({hi}, {lo})"
-    # GLOBAL/SCRATCH: offset is 13-bit signed [12:0], FLAT: 12-bit unsigned (XML has 12-bit for all)
-    if name == "offset" and base_fmt in ("GLOBAL", "SCRATCH"): return f"BitField(12, {lo})"
-    if base_fmt == "VOP3P" and name == "opsel_hi": return f"BitField({hi}, {lo}, default=3)"
-    if base_fmt == "VOP3P" and name == "opsel_hi2": return f"BitField({hi}, {lo}, default=1)"
-    return f"BitField({hi}, {lo})"
-  ORDER = ['encoding', 'op', 'opx', 'opy', 'vdst', 'vdstx', 'vdsty', 'sdst', 'vdata', 'sdata', 'addr', 'vaddr', 'data', 'data0', 'data1',
-           'src0', 'srcx0', 'srcy0', 'vsrc0', 'ssrc0', 'src1', 'vsrc1', 'vsrcx1', 'vsrcy1', 'ssrc1', 'src2', 'vsrc2', 'src3', 'vsrc3',
-           'saddr', 'sbase', 'srsrc', 'ssamp', 'soffset', 'offset', 'simm16', 'literal', 'en', 'target', 'attr', 'attr_chan',
-           'omod', 'neg', 'neg_hi', 'abs', 'clmp', 'opsel', 'opsel_hi', 'waitexp', 'wait_va',
-           'dmask', 'dim', 'seg', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe', 'unrm', 'done', 'row',
-           'dpp', 'fi', 'bc', 'row_mask', 'bank_mask', 'src0_neg', 'src0_abs', 'src1_neg', 'src1_abs',
-           'cbsz', 'abid', 'acc_cd', 'acc', 'blgp', 'lane_sel_0', 'lane_sel_1', 'lane_sel_2', 'lane_sel_3',
-           'lane_sel_4', 'lane_sel_5', 'lane_sel_6', 'lane_sel_7', 'dst_sel', 'dst_unused', 'src0_sel', 'src1_sel']
-  sort_fields = lambda fields: sorted(fields, key=lambda f: (ORDER.index(f[0]) if f[0] in ORDER else 999, f[2]))
-
-  # Separate base encodings from variants
-  base_encodings, variant_encodings = {}, {}
-  for enc_name, data in encodings.items():
-    base = get_base_fmt(enc_name)
-    if base == enc_name: base_encodings[enc_name] = data
-    else: variant_encodings[enc_name] = data
-
-  # Build sets of ops by their vdst type from operand metadata
-  sdst_opcodes = {}  # ops where vdst is OPR_SREG (writes to SGPR)
-  for fmt, ops in enums.items():
-    for op, name in ops.items():
-      op_types = types.get((name, fmt), {})
-      vdst_type = op_types.get("vdst", (None, None, None))[2]
-      if vdst_type == "OPR_SREG": sdst_opcodes.setdefault(fmt, set()).add(op)
-
-  lines = ["# autogenerated from AMD ISA XML - do not edit", "# ruff: noqa: F401,F403",
-           "from extra.assembly.amd.dsl import *", f"from extra.assembly.amd.autogen.{arch}.enum import *", "import functools", ""]
-
-  def fmt_allowed(op_enum: str, ops: set[int]) -> str:
-    """Format allowed ops as {EnumName.MEMBER, ...}."""
-    names = [f"{op_enum}.{enums[op_enum.removesuffix('Op')][op]}" for op in sorted(ops)]
-    return "{" + ", ".join(names) + "}"
-
-  # Generate base classes first
-  for enc_name, (fields, enc_bits) in sorted(base_encodings.items()):
-    all_ops = set(enums.get(enc_name, {}).keys())
-    # Get suffix-only ops for this format (these can't be used in base class)
-    base_suffix_ops = set().union(*(d.get(enc_name, set()) for d in suffix_only_ops.values()))
-    # Exclude SDST ops from base class (they need VOP1_SDST/VOP3_SDST/VOP3B)
-    base_allowed = all_ops - base_suffix_ops - sdst_opcodes.get(enc_name, set())
-    # RDNA3 FLAT/GLOBAL/SCRATCH share encoding bits, differentiated by seg field
-    # RDNA4 VFLAT/VGLOBAL/VSCRATCH have distinct encoding bits, no seg field needed
-    has_seg_field = any(fn == "seg" for fn, _, _ in fields)
-    if enc_name in ("FLAT", "VFLAT") and has_seg_field:
-      prefix = "V" if enc_name == "VFLAT" else ""
-      for cls, seg, op_enum in [(f"{prefix}FLAT", 0, f"{prefix}FLATOp"), (f"{prefix}GLOBAL", 2, f"{prefix}GLOBALOp"), (f"{prefix}SCRATCH", 1, f"{prefix}SCRATCHOp")]:
-        cls_ops = set(enums.get(cls, {}).keys())
-        lines.append(f"class {cls}(Inst):")
-        for fn, hi, lo in sort_fields(fields):
-          if fn == "seg": lines.append(f"  seg = FixedBitField({hi}, {lo}, {seg})")
-          elif fn == "op": lines.append(f"  op = EnumBitField({hi}, {lo}, {op_enum}, {fmt_allowed(op_enum, cls_ops)})")
-          else: lines.append(f"  {fn} = {field_def(fn, hi, lo, cls, enc_bits)}")
-        lines.append("")
-    elif enc_name not in ("FLAT_GLOBAL", "FLAT_SCRATCH", "FLAT_GLBL", "DPP", "SDWA"):
-      lines.append(f"class {enc_name}(Inst):")
-      for fn, hi, lo in sort_fields(fields):
-        if fn == "op":
-          base_fmt = get_base_fmt(enc_name)
-          lines.append(f"  op = EnumBitField({hi}, {lo}, {base_fmt}Op, {fmt_allowed(f'{base_fmt}Op', base_allowed)})")
-        else:
-          lines.append(f"  {fn} = {field_def(fn, hi, lo, enc_name, enc_bits if fn == 'encoding' else None)}")
-      lines.append("")
-
-  # Generate variant classes that inherit from base (only add extra fields)
-  for enc_name, (fields, enc_bits) in sorted(variant_encodings.items()):
-    base = get_base_fmt(enc_name)
-    if base not in base_encodings: continue  # skip if no base class
-    base_fields = {f[0] for f in base_encodings[base][0]}
-    extra_fields = [(fn, hi, lo) for fn, hi, lo in fields if fn not in base_fields]
-    # Check if this is a suffix-only variant
-    variant_suffix = next((sfx for sfx in _VARIANT_SUFFIXES if enc_name.endswith(sfx)), None)
-    is_suffix_variant = variant_suffix in suffix_only_ops
-    all_ops = set(enums.get(base, {}).keys())
-    if extra_fields or is_suffix_variant:
-      lines.append(f"class {enc_name}({base}):")
-      op_field = next((f for f in base_encodings[base][0] if f[0] == "op"), None)
-      # _LIT classes: override op to allow all opcodes (base excludes lit-only ops)
-      # other classes override op to only suffix-only opcodes
-      if op_field and is_suffix_variant:
-        _, hi, lo = op_field
-        allowed_ops = all_ops if variant_suffix == "_LIT" else suffix_only_ops[variant_suffix][base]
-        lines.append(f"  op = EnumBitField({hi}, {lo}, {base}Op, {fmt_allowed(f'{base}Op', allowed_ops)})")
-      for fn, hi, lo in sort_fields(extra_fields):
-        lines.append(f"  {fn} = {field_def(fn, hi, lo, enc_name)}")
-      lines.append("")
-
-  # SDST variants (special case - redefine vdst field type, restrict to SDST ops)
-  for base, field_hi, field_lo in [("VOP1", 24, 17), ("VOP3", 7, 0)]:
-    if base not in base_encodings: continue
-    sdst_ops = sdst_opcodes.get(base, set())
-    if not sdst_ops: continue
-    # For VOP3, all ops < 256 (compare/cmpx ops) use SDST encoding
-    all_base_ops = set(enums.get(base, {}).keys())
-    if base == "VOP3": sdst_ops = sdst_ops | {op for op in all_base_ops if op < 256}
-    op_field = next((f for f in base_encodings[base][0] if f[0] == "op"), None)
-    lines.append(f"class {base}_SDST({base}):")
-    if op_field:
-      _, hi, lo = op_field
-      lines.append(f"  op = EnumBitField({hi}, {lo}, {base}Op, {fmt_allowed(f'{base}Op', sdst_ops)})")
-    lines.append(f"  vdst = SSrcField({field_hi}, {field_lo})")
-    lines.append("")
-    # SDST_LIT class (for literals with SDST destination) - same ops, just adds literal field
-    lit_enc = variant_encodings.get(f"{base}_LIT")
-    if lit_enc:
-      lit_field = next((f for f in lit_enc[0] if f[0] == "literal"), None)
-      if lit_field:
-        lines.append(f"class {base}_SDST_LIT({base}_SDST):")
-        lines.append(f"  literal = BitField({lit_field[1]}, {lit_field[2]})")
-        lines.append("")
-
-  # Instruction helpers
-  lines.append("# instruction helpers")
-  for fmt, ops in sorted(enums.items()):
-    if fmt not in base_encodings and fmt not in ("GLOBAL", "SCRATCH", "VGLOBAL", "VSCRATCH"): continue
-    suffix = "_E32" if fmt in ("VOP1", "VOP2", "VOPC") else "_E64" if fmt == "VOP3" else ""
-    op_to_suffix = {op:suffix for suffix,ops in suffix_only_ops.items() for op in ops.get(fmt, set())}
-    fmt_sdst_ops = sdst_opcodes.get(fmt, set())
-    for op, name in sorted(ops.items()):
-      msuf = suffix if fmt != "VOP3" or op < 512 else ""
-      # Determine class: SDST variants, suffix-specific variants (e.g., _MFMA, _LIT), or base
-      if fmt == "VOP1" and op in fmt_sdst_ops: cls = "VOP1_SDST"
-      elif fmt == "VOP3" and (op in fmt_sdst_ops or op < 256): cls = "VOP3_SDST"
-      elif op_to_suffix.get(op): cls = f"{fmt}{op_to_suffix[op]}"
-      else: cls = fmt
-      lines.append(f"{name.lower()}{msuf.lower()} = functools.partial({cls}, {fmt}Op.{name}{msuf})")
-  with open(path, "w") as f: f.write("\n".join(lines))
-
-def write_operands(types, enums, arch, path):
-  valid = {(name, fmt) for fmt, ops in enums.items() for name in ops.values()}
-  lines = ["# autogenerated from AMD ISA XML - do not edit",
-           "from extra.assembly.amd.autogen.common import Fmt, OpType",
-           f"from extra.assembly.amd.autogen.{arch}.enum import *", ""]
-  lines.append("# instruction operand info: {Op: {field: (Fmt, size_bits, OpType)}}")
-  lines.append("OPERANDS = {")
-  def fmt_val(v):
-    fmt, size, otype = v
-    return f"({f'Fmt.{fmt}' if fmt else 'None'}, {size}, {f'OpType.{otype}' if otype else 'None'})"
-  for (name, enc_base), fields in sorted(types.items()):
-    if (name, enc_base) not in valid: continue
-    fstr = ", ".join(f'"{k}": {fmt_val(v)}' for k, v in sorted(fields.items()))
-    lines.append(f'  {enc_base}Op.{name}: {{{fstr}}},')
-  lines.append("}")
-  with open(path, "w") as f: f.write("\n".join(lines))
-
-def write_pcode(pcode: dict[tuple[str, int], str], enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write str_pcode.py file from extracted pseudocode."""
-  entries: list[tuple[str, str, int, str]] = []
-  for fmt_name, ops in enums.items():
-    member_suffix = "_E32" if fmt_name in ("VOP1", "VOP2", "VOPC") else "_E64" if fmt_name == "VOP3" else ""
-    for opcode, name in ops.items():
-      if (name, opcode) in pcode:
-        msuf = member_suffix if fmt_name != "VOP3" or opcode < 512 else ""
-        entries.append((f"{fmt_name}Op", f"{name}{msuf}", opcode, pcode[(name, opcode)]))
-  enum_names = sorted(set(e[0] for e in entries))
-  lines = ["# autogenerated from AMD ISA PDF - do not edit", "# ruff: noqa: E501",
-           f"from extra.assembly.amd.autogen.{arch}.enum import {', '.join(enum_names)}", "", "PCODE = {"]
-  for enum_name, name, opcode, code in sorted(entries, key=lambda x: (x[0], x[2])):
-    lines.append(f"  {enum_name}.{name}: {code!r},")
-  lines.append("}")
-  with open(path, "w") as f: f.write("\n".join(lines))
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# Main
-# ═══════════════════════════════════════════════════════════════════════════════
-
-if __name__ == "__main__":
-  import pathlib
-  all_fmts, all_op_types, arch_data = {}, set(), {}
-  # First pass: parse XML for all architectures
-  for arch, cfg in ARCHS.items():
-    print(f"Parsing XML: {cfg['xml']} -> {arch}")
-    encodings, enums, types, fmts, op_types_set, suffix_only_ops = parse_xml(cfg["xml"])
-    for fmt, ops in FIXES.get(arch, {}).items(): enums.setdefault(fmt, {}).update(ops)
-    for fmt, fields in FIELD_FIXES.get(arch, {}).items():
-      if fmt in encodings: encodings[fmt] = (encodings[fmt][0] + fields, encodings[fmt][1])
-    arch_data[arch] = {"encodings": encodings, "enums": enums, "types": types, "suffix_only_ops": suffix_only_ops}
-    for fmt, bits in fmts.items():
-      assert fmt not in all_fmts or all_fmts[fmt] == bits, f"FMT_BITS mismatch for {fmt}: {all_fmts[fmt]} vs {bits}"
-      all_fmts[fmt] = bits
-    all_op_types.update(op_types_set)
-  # Write common.py
-  common_path = pathlib.Path(__file__).parent / "autogen" / "common.py"
-  write_common(all_fmts, all_op_types, common_path)
-  print(f"Wrote common.py: {len(all_fmts)} formats, {len(all_op_types)} op types")
-  # Write per-arch files from XML
-  for arch, data in arch_data.items():
-    base = pathlib.Path(__file__).parent / "autogen" / arch
-    write_enum(data["enums"], base / "enum.py")
-    write_ins(data["encodings"], data["enums"], data["suffix_only_ops"], data["types"], arch, base / "ins.py")
-    write_operands(data["types"], data["enums"], arch, base / "operands.py")
-    print(f"  {arch}: {len(data['encodings'])} encodings, {sum(len(v) for v in data['enums'].values())} instructions")
-  # Second pass: parse PDFs and write pcode
-  for arch, cfg in ARCHS.items():
-    print(f"Parsing PDF: {arch}...")
-    pages = extract_pdf_text(cfg["pdf"])
-    name_to_op = {name: op for ops in arch_data[arch]["enums"].values() for op, name in ops.items()}
-    pcode = extract_pcode(pages, name_to_op)
-    base = pathlib.Path(__file__).parent / "autogen" / arch
-    write_pcode(pcode, arch_data[arch]["enums"], arch, base / "str_pcode.py")
-    print(f"  {arch}: {len(pcode)} pcode entries")
@@ -0,0 +1,670 @@
+# Generate AMD ISA autogen files from PDF documentation
+# Combines format/enum generation (previously in dsl.py) and pseudocode compilation (previously in pcode.py)
+# Usage: python -m extra.assembly.amd.pdf [--arch rdna3|rdna4|cdna|all]
+import re, functools
+from pathlib import Path
+from concurrent.futures import ProcessPoolExecutor
+
+PDF_URLS = {
+  "rdna3": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content",
+  "rdna4": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content",
+  "cdna": ["https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-mi300-cdna3-instruction-set-architecture.pdf",
+           "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"],
+}
+
+# Field type mappings and ordering
+FIELD_TYPES = {'SSRC0': 'SSrc', 'SSRC1': 'SSrc', 'SOFFSET': 'SSrc', 'SADDR': 'SSrc', 'SRC0': 'Src', 'SRC1': 'Src', 'SRC2': 'Src',
+  'SDST': 'SGPRField', 'SBASE': 'SGPRField', 'SDATA': 'SGPRField', 'SRSRC': 'SGPRField', 'VDST': 'VGPRField', 'VSRC1': 'VGPRField',
+  'VDATA': 'VGPRField', 'VADDR': 'VGPRField', 'ADDR': 'VGPRField', 'DATA': 'VGPRField', 'DATA0': 'VGPRField', 'DATA1': 'VGPRField',
+  'SIMM16': 'SImm', 'OFFSET': 'Imm', 'OPX': 'VOPDOp', 'OPY': 'VOPDOp', 'SRCX0': 'Src', 'SRCY0': 'Src',
+  'VSRCX1': 'VGPRField', 'VSRCY1': 'VGPRField', 'VDSTX': 'VGPRField', 'VDSTY': 'VDSTYEnc'}
+FIELD_ORDER = {
+  'SOP2': ['op', 'sdst', 'ssrc0', 'ssrc1'], 'SOP1': ['op', 'sdst', 'ssrc0'], 'SOPC': ['op', 'ssrc0', 'ssrc1'],
+  'SOPK': ['op', 'sdst', 'simm16'], 'SOPP': ['op', 'simm16'], 'VOP1': ['op', 'vdst', 'src0'], 'VOPC': ['op', 'src0', 'vsrc1'],
+  'VOP2': ['op', 'vdst', 'src0', 'vsrc1'], 'VOP3SD': ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2', 'clmp'],
+  'SMEM': ['op', 'sdata', 'sbase', 'soffset', 'offset', 'glc', 'dlc'], 'DS': ['op', 'vdst', 'addr', 'data0', 'data1'],
+  'VOP3': ['op', 'vdst', 'src0', 'src1', 'src2', 'omod', 'neg', 'abs', 'clmp', 'opsel'],
+  'VOP3P': ['op', 'vdst', 'src0', 'src1', 'src2', 'neg', 'neg_hi', 'opsel', 'opsel_hi', 'clmp'],
+  'FLAT': ['op', 'vdst', 'addr', 'data', 'saddr', 'offset', 'seg', 'dlc', 'glc', 'slc'],
+  'MUBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
+  'MTBUF': ['op', 'vdata', 'vaddr', 'srsrc', 'soffset', 'offset', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe'],
+  'MIMG': ['op', 'vdata', 'vaddr', 'srsrc', 'ssamp', 'dmask', 'dim', 'unrm', 'dlc', 'glc', 'slc'],
+  'EXP': ['en', 'target', 'vsrc0', 'vsrc1', 'vsrc2', 'vsrc3', 'done', 'row'],
+  'VINTERP': ['op', 'vdst', 'src0', 'src1', 'src2', 'waitexp', 'clmp', 'opsel', 'neg'],
+  'VOPD': ['opx', 'opy', 'vdstx', 'vdsty', 'srcx0', 'vsrcx1', 'srcy0', 'vsrcy1'],
+  'LDSDIR': ['op', 'vdst', 'attr', 'attr_chan', 'wait_va']}
+SRC_EXTRAS = {233: 'DPP8', 234: 'DPP8FI', 250: 'DPP16', 251: 'VCCZ', 252: 'EXECZ', 254: 'LDS_DIRECT'}
+FLOAT_MAP = {'0.5': 'POS_HALF', '-0.5': 'NEG_HALF', '1.0': 'POS_ONE', '-1.0': 'NEG_ONE', '2.0': 'POS_TWO', '-2.0': 'NEG_TWO',
+  '4.0': 'POS_FOUR', '-4.0': 'NEG_FOUR', '1/(2*PI)': 'INV_2PI', '0': 'ZERO'}
+INST_PATTERN = re.compile(r'^([SVD]S?_[A-Z0-9_]+)\s+(\d+)\s*$', re.M)
+
+# Patterns that can't be handled by the DSL (require special handling in emu.py)
+UNSUPPORTED = ['SGPR[', 'V_SWAP', 'eval ', 'FATAL_HALT', 'HW_REGISTERS',
+               'vscnt', 'vmcnt', 'expcnt', 'lgkmcnt',
+               'CVT_OFF_TABLE', 'ThreadMask',
+               'S1[i', 'C.i32',
+               'if n.', 'DST.u32', 'addrd = DST', 'addr = DST',
+               'BARRIER_STATE', 'ReallocVgprs',
+               'GPR_IDX', 'VSKIP', 'specified in', 'TTBL',
+               'fp6', 'bf6']  # Malformed pseudocode from PDF
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# COMPILER: pseudocode -> Python (minimal transforms)
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def compile_pseudocode(pseudocode: str) -> str:
+  """Compile pseudocode to Python. Transforms are minimal - most syntax just works."""
+  pseudocode = re.sub(r'\bpass\b', 'pass_', pseudocode)  # 'pass' is Python keyword
+  raw_lines = pseudocode.strip().split('\n')
+  joined_lines: list[str] = []
+  for line in raw_lines:
+    line = line.strip()
+    if joined_lines and (joined_lines[-1].rstrip().endswith(('||', '&&', '(', ',')) or
+                         (joined_lines[-1].count('(') > joined_lines[-1].count(')'))):
+      joined_lines[-1] = joined_lines[-1].rstrip() + ' ' + line
+    else:
+      joined_lines.append(line)
+
+  lines = []
+  indent, need_pass, in_first_match_loop = 0, False, False
+  declared_arrays: dict[str, int] = {}  # Track declared arrays: name -> size
+  for line in joined_lines:
+    line = line.strip()
+    if not line or line.startswith('//'): continue
+    if line.startswith('if '):
+      lines.append('  ' * indent + f"if {_expr(line[3:].rstrip(' then'), declared_arrays)}:")
+      indent += 1
+      need_pass = True
+    elif line.startswith('elsif '):
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      lines.append('  ' * indent + f"elif {_expr(line[6:].rstrip(' then'), declared_arrays)}:")
+      indent += 1
+      need_pass = True
+    elif line == 'else':
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      lines.append('  ' * indent + "else:")
+      indent += 1
+      need_pass = True
+    elif line.startswith('endif'):
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      need_pass = False
+    elif line.startswith('endfor'):
+      if need_pass: lines.append('  ' * indent + "pass")
+      indent -= 1
+      need_pass, in_first_match_loop = False, False
+    elif m := re.match(r'declare\s+(\w+)\s*:\s*\d+\'[FBU]\[(\d+)\]', line):
+      # Handle array declarations: declare in : 32'F[3] or declare S : 32'B[3]
+      arr_name, arr_size = m[1], int(m[2])
+      declared_arrays[arr_name] = arr_size
+      py_name = f"{arr_name}_" if arr_name == 'in' else arr_name  # 'in' is Python keyword
+      if arr_name == 'S':
+        lines.append('  ' * indent + f"{py_name} = [S0, S1, S2]")  # Map to source registers
+      else:
+        lines.append('  ' * indent + f"{py_name} = [Reg(0) for _ in range({arr_size})]")
+    elif line.startswith('declare '):
+      pass  # Ignore other declare statements
+    elif m := re.match(r'for (\w+) in (.+?)\s*:\s*(.+?) do', line):
+      start, end = _expr(m[2].strip(), declared_arrays), _expr(m[3].strip(), declared_arrays)
+      lines.append('  ' * indent + f"for {m[1]} in range({start}, int({end})+1):")
+      indent += 1
+      need_pass, in_first_match_loop = True, True
+    elif '=' in line and not line.startswith('=='):
+      need_pass = False
+      line = line.rstrip(';')
+      if m := re.match(r'\{\s*D1\.[ui]1\s*,\s*D0\.[ui]64\s*\}\s*=\s*(.+)', line):
+        rhs = _expr(m[1], declared_arrays)
+        lines.append('  ' * indent + f"_full = {rhs}")
+        lines.append('  ' * indent + f"D0.u64 = int(_full) & 0xffffffffffffffff")
+        lines.append('  ' * indent + f"D1 = Reg((int(_full) >> 64) & 1)")
+      elif any(op in line for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^=')):
+        for op in ('+=', '-=', '*=', '/=', '|=', '&=', '^='):
+          if op in line:
+            lhs, rhs = line.split(op, 1)
+            lhs_s = _expr(lhs.strip(), declared_arrays)  # Transform LHS too for array access
+            lines.append('  ' * indent + f"{lhs_s} {op} {_expr(rhs.strip(), declared_arrays)}")
+            break
+      else:
+        lhs, rhs = line.split('=', 1)
+        lhs_s, rhs_s = lhs.strip(), rhs.strip()
+        lhs_t = _expr(lhs_s, declared_arrays)  # Transform LHS for array access
+        stmt = _assign(lhs_t, _expr(rhs_s, declared_arrays), declared_arrays)
+        if in_first_match_loop and rhs_s == 'i' and (lhs_s == 'tmp' or lhs_s == 'D0.i32'):
+          stmt += "; break"
+        lines.append('  ' * indent + stmt)
+  if need_pass: lines.append('  ' * indent + "pass")
+  return '\n'.join(lines)
+
+def _assign(lhs: str, rhs: str, declared_arrays: dict[str, int] | None = None) -> str:
+  # Check for array element assignment: in_[i] should not wrap in Reg()
+  if declared_arrays and re.match(r'\w+_?\[\w+\]', lhs):
+    return f"{lhs} = {rhs}"
+  if lhs in ('tmp', 'SCC', 'VCC', 'EXEC', 'D0', 'D1', 'saveexec', 'PC'):
+    return f"{lhs} = Reg({rhs})"
+  return f"{lhs} = {rhs}"
+
+def _expr(e: str, declared_arrays: dict[str, int] | None = None) -> str:
+  e = e.strip()
+  # Handle OPSEL_HI.u3[i] and OPSEL.u3[i] - bit extraction from opsel fields
+  e = re.sub(r'(OPSEL(?:_HI)?)\.u\d+\[(\w+)\]', r'((\1 >> \2) & 1)', e)
+  # Rename 'in' to 'in_' to avoid Python keyword conflict
+  e = re.sub(r'\bin\[', 'in_[', e)
+  e = e.replace('&&', ' and ').replace('||', ' or ').replace('<>', ' != ')
+  e = re.sub(r'!([^=])', r' not \1', e)
+  e = re.sub(r'\{\s*(\w+\.u32)\s*,\s*(\w+\.u32)\s*\}', r'_pack32(\1, \2)', e)
+  def pack(m):
+    hi, lo = _expr(m[1].strip(), declared_arrays), _expr(m[2].strip(), declared_arrays)
+    return f'_pack({hi}, {lo})'
+  e = re.sub(r'\{\s*([^,{}]+)\s*,\s*([^,{}]+)\s*\}', pack, e)
+  e = re.sub(r"1201'B\(2\.0\s*/\s*PI\)", "TWO_OVER_PI_1201", e)
+  e = re.sub(r"\d+'([0-9a-fA-Fx]+)[UuFf]*", r'\1', e)
+  e = re.sub(r"\d+'[FIBU]\(", "(", e)
+  e = re.sub(r'\bB\(', '(', e)
+  e = re.sub(r'([0-9a-fA-Fx])ULL\b', r'\1', e)
+  e = re.sub(r'([0-9a-fA-Fx])LL\b', r'\1', e)
+  e = re.sub(r'([0-9a-fA-Fx])U\b', r'\1', e)
+  e = re.sub(r'(\d\.?\d*)F\b', r'\1', e)
+  e = re.sub(r'(\[laneId\])\.[uib]\d+', r'\1', e)
+  e = e.replace('+INF', 'INF').replace('-INF', '(-INF)')
+  e = re.sub(r'NAN\.f\d+', 'float("nan")', e)
+  def convert_verilog_slice(m):
+    start, width = m.group(1).strip(), m.group(2).strip()
+    return f'[({start}) + ({width}) - 1 : ({start})]'
+  e = re.sub(r'\[([^:\[\]]+)\s*\+:\s*([^:\[\]]+)\]', convert_verilog_slice, e)
+  def process_brackets(s):
+    result, i = [], 0
+    while i < len(s):
+      if s[i] == '[':
+        depth, start = 1, i + 1
+        j = start
+        while j < len(s) and depth > 0:
+          if s[j] == '[': depth += 1
+          elif s[j] == ']': depth -= 1
+          j += 1
+        inner = _expr(s[start:j-1], declared_arrays)
+        result.append('[' + inner + ']')
+        i = j
+      else:
+        result.append(s[i])
+        i += 1
+    return ''.join(result)
+  e = process_brackets(e)
+  while '?' in e:
+    depth, bracket, q = 0, 0, -1
+    for i, c in enumerate(e):
+      if c == '(': depth += 1
+      elif c == ')': depth -= 1
+      elif c == '[': bracket += 1
+      elif c == ']': bracket -= 1
+      elif c == '?' and depth == 0 and bracket == 0: q = i; break
+    if q < 0: break
+    depth, bracket, col = 0, 0, -1
+    for i in range(q + 1, len(e)):
+      if e[i] == '(': depth += 1
+      elif e[i] == ')': depth -= 1
+      elif e[i] == '[': bracket += 1
+      elif e[i] == ']': bracket -= 1
+      elif e[i] == ':' and depth == 0 and bracket == 0: col = i; break
+    if col < 0: break
+    cond, t, f = e[:q].strip(), e[q+1:col].strip(), e[col+1:].strip()
+    e = f'(({t}) if ({cond}) else ({f}))'
+  return e
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# PDF PARSING WITH PAGE CACHING
+# ═══════════════════════════════════════════════════════════════════════════════
+
+class CachedPDF:
+  """PDF wrapper with page text/table caching for faster repeated access."""
+  def __init__(self, pdf):
+    self._pdf, self._text_cache, self._table_cache = pdf, {}, {}
+  def __len__(self): return len(self._pdf.pages)
+  def text(self, i):
+    if i not in self._text_cache: self._text_cache[i] = self._pdf.pages[i].extract_text() or ''
+    return self._text_cache[i]
+  def tables(self, i):
+    if i not in self._table_cache: self._table_cache[i] = [t.extract() for t in self._pdf.pages[i].find_tables()]
+    return self._table_cache[i]
+
+def _parse_bits(s: str) -> tuple[int, int] | None:
+  return (int(m.group(1)), int(m.group(2) or m.group(1))) if (m := re.match(r'\[(\d+)(?::(\d+))?\]', s)) else None
+
+def _parse_fields_table(table: list, fmt: str, enums: set[str]) -> list[tuple]:
+  fields = []
+  for row in table[1:]:
+    if not row or not row[0]: continue
+    name, bits_str = row[0].split('\n')[0].strip(), (row[1] or '').split('\n')[0].strip()
+    if not (bits := _parse_bits(bits_str)): continue
+    enc_val, hi, lo = None, bits[0], bits[1]
+    if name == 'ENCODING' and row[2]:
+      if m := re.search(r"(?:'b|Must be:\s*)([01_]+)", row[2]):
+        enc_bits = m.group(1).replace('_', '')
+        enc_val, declared_width, actual_width = int(enc_bits, 2), hi - lo + 1, len(enc_bits)
+        if actual_width > declared_width: lo = hi - actual_width + 1
+    ftype = f"{fmt}Op" if name == 'OP' and f"{fmt}Op" in enums else FIELD_TYPES.get(name.upper())
+    fields.append((name, hi, lo, enc_val, ftype))
+  return fields
+
+def _parse_single_pdf(url: str):
+  """Parse a single PDF and return (formats, enums, src_enum, doc_name, instructions)."""
+  import pdfplumber
+  from tinygrad.helpers import fetch
+
+  pdf = CachedPDF(pdfplumber.open(fetch(url)))
+  total_pages = len(pdf)
+
+  # Auto-detect document type
+  first_page = pdf.text(0)
+  is_cdna4, is_cdna3 = 'CDNA4' in first_page or 'CDNA 4' in first_page, 'CDNA3' in first_page or 'MI300' in first_page
+  is_cdna, is_rdna4 = is_cdna3 or is_cdna4, 'RDNA4' in first_page or 'RDNA 4' in first_page
+  is_rdna35, is_rdna3 = 'RDNA3.5' in first_page or 'RDNA 3.5' in first_page, 'RDNA3' in first_page and 'RDNA3.5' not in first_page
+  doc_name = "CDNA4" if is_cdna4 else "CDNA3" if is_cdna3 else "RDNA4" if is_rdna4 else "RDNA3.5" if is_rdna35 else "RDNA3" if is_rdna3 else "Unknown"
+
+  # Find Microcode Formats section (for formats/enums)
+  microcode_start = next((i for i in range(int(total_pages * 0.2), total_pages)
+                          if re.search(r'\d+\.\d+\.\d+\.\s+SOP2\b|Chapter \d+\.\s+Microcode Formats', pdf.text(i))), int(total_pages * 0.9))
+  # Find Instructions section (for pseudocode)
+  instr_start = next((i for i in range(int(total_pages * 0.1), int(total_pages * 0.5))
+                      if re.search(r'Chapter \d+\.\s+Instructions\b', pdf.text(i))), total_pages // 3)
+  instr_end = next((i for start in [int(total_pages * 0.6), int(total_pages * 0.5), instr_start]
+                    for i in range(start, min(start + 100, total_pages))
+                    if re.search(r'Chapter \d+\.\s+Microcode Formats', pdf.text(i))), total_pages)
+
+  # Parse src enum from SSRC encoding table
+  src_enum = dict(SRC_EXTRAS)
+  for i in range(microcode_start, min(microcode_start + 10, total_pages)):
+    text = pdf.text(i)
+    if 'SSRC0' in text and 'VCC_LO' in text:
+      for m in re.finditer(r'^(\d+)\s+(\S+)', text, re.M):
+        val, name = int(m.group(1)), m.group(2).rstrip('.:')
+        if name in FLOAT_MAP: src_enum[val] = FLOAT_MAP[name]
+        elif re.match(r'^[A-Z][A-Z0-9_]*$', name): src_enum[val] = name
+      break
+
+  # Parse opcode tables
+  full_text = '\n'.join(pdf.text(i) for i in range(microcode_start, min(microcode_start + 50, total_pages)))
+  enums: dict[str, dict[int, str]] = {}
+  for m in re.finditer(r'Table \d+\. (\w+) Opcodes(.*?)(?=Table \d+\.|\n\d+\.\d+\.\d+\.\s+\w+\s*\nDescription|$)', full_text, re.S):
+    if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+([A-Z][A-Z0-9_]+)', m.group(2))}:
+      enums[m.group(1) + "Op"] = ops
+  if vopd_m := re.search(r'Table \d+\. VOPD Y-Opcodes\n(.*?)(?=Table \d+\.|15\.\d)', full_text, re.S):
+    if ops := {int(x.group(1)): x.group(2) for x in re.finditer(r'(\d+)\s+(V_DUAL_\w+)', vopd_m.group(1))}:
+      enums["VOPDOp"] = ops
+  enum_names = set(enums.keys())
+
+  # Parse instruction formats
+  def is_fields_table(t): return t and len(t) > 1 and t[0] and 'Field' in str(t[0][0] or '')
+  def has_encoding(fields): return any(f[0] == 'ENCODING' for f in fields)
+  def has_header_before_fields(text): return (pos := text.find('Field Name')) != -1 and bool(re.search(r'\d+\.\d+\.\d+\.\s+\w+\s*\n', text[:pos]))
+
+  format_headers = []
+  for i in range(50):
+    if microcode_start + i >= total_pages: break
+    text = pdf.text(microcode_start + i)
+    for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n?Description', text): format_headers.append((m.group(1), i, m.start()))
+    for m in re.finditer(r'\d+\.\d+\.\d+\.\s+(\w+)\s*\n', text):
+      fmt_name = m.group(1)
+      if is_cdna and fmt_name.isupper() and len(fmt_name) >= 2: format_headers.append((fmt_name, i, m.start()))
+      elif m.start() > len(text) - 200 and 'Description' not in text[m.end():] and i + 1 < 50:
+        next_text = pdf.text(microcode_start + i + 1).lstrip()
+        if next_text.startswith('Description') or (next_text.startswith('"RDNA') and 'Description' in next_text[:200]):
+          format_headers.append((fmt_name, i, m.start()))
+
+  formats: dict[str, list] = {}
+  for fmt_name, rel_idx, header_pos in format_headers:
+    if fmt_name in formats: continue
+    page_idx = microcode_start + rel_idx
+    text = pdf.text(page_idx)
+    field_pos = text.find('Field Name', header_pos)
+    fields = None
+    for offset in range(3):
+      if page_idx + offset >= total_pages: break
+      if offset > 0 and has_header_before_fields(pdf.text(page_idx + offset)): break
+      for t in pdf.tables(page_idx + offset) if offset > 0 or field_pos > header_pos else []:
+        if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)) and has_encoding(f): fields = f; break
+      if fields: break
+    if not fields and field_pos > header_pos:
+      for t in pdf.tables(page_idx):
+        if is_fields_table(t) and (f := _parse_fields_table(t, fmt_name, enum_names)): fields = f; break
+    if not fields: continue
+    field_names = {f[0] for f in fields}
+    for pg_offset in range(1, 3):
+      if page_idx + pg_offset >= total_pages or has_header_before_fields(pdf.text(page_idx + pg_offset)): break
+      for t in pdf.tables(page_idx + pg_offset):
+        if is_fields_table(t) and (extra := _parse_fields_table(t, fmt_name, enum_names)) and not has_encoding(extra):
+          for ef in extra:
+            if ef[0] not in field_names: fields.append(ef); field_names.add(ef[0])
+          break
+    formats[fmt_name] = fields
+
+  # Fix known PDF errors
+  if 'SMEM' in formats:
+    formats['SMEM'] = [(n, 13 if n == 'DLC' else 14 if n == 'GLC' else h, 13 if n == 'DLC' else 14 if n == 'GLC' else l, e, t)
+                       for n, h, l, e, t in formats['SMEM']]
+  if doc_name in ('RDNA3', 'RDNA3.5'):
+    if 'SOPPOp' in enums: assert 8 not in enums['SOPPOp']; enums['SOPPOp'][8] = 'S_WAITCNT_DEPCTR'
+    if 'DSOp' in enums:
+      for k, v in {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'}.items():
+        assert k not in enums['DSOp']; enums['DSOp'][k] = v
+    if 'FLATOp' in enums:
+      for k, v in {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'}.items():
+        assert k not in enums['FLATOp']; enums['FLATOp'][k] = v
+
+  # Extract pseudocode for instructions
+  all_text = '\n'.join(pdf.text(i) for i in range(instr_start, instr_end))
+  matches = list(INST_PATTERN.finditer(all_text))
+  raw_pseudocode: dict[tuple[str, int], str] = {}
+  for i, match in enumerate(matches):
+    name, opcode = match.group(1), int(match.group(2))
+    start, end = match.end(), matches[i + 1].start() if i + 1 < len(matches) else match.end() + 2000
+    snippet = all_text[start:end].strip()
+    if pseudocode := _extract_pseudocode(snippet): raw_pseudocode[(name, opcode)] = pseudocode
+
+  return {"formats": formats, "enums": enums, "src_enum": src_enum, "doc_name": doc_name, "pseudocode": raw_pseudocode, "is_cdna": is_cdna}
+
+def _extract_pseudocode(text: str) -> str | None:
+  """Extract pseudocode from an instruction description snippet."""
+  lines, result, depth, in_lambda = text.split('\n'), [], 0, 0
+  for line in lines:
+    s = line.strip()
+    if not s or re.match(r'^\d+ of \d+$', s) or re.match(r'^\d+\.\d+\..*Instructions', s): continue
+    if s.startswith(('Notes', 'Functional examples')): break
+    if s.startswith(('"RDNA', 'AMD ', 'CDNA')): continue
+    if '= lambda(' in s: in_lambda += 1; continue
+    if in_lambda > 0:
+      if s.endswith(');'): in_lambda -= 1
+      continue
+    if s.startswith('if '): depth += 1
+    elif s.startswith('endif'): depth = max(0, depth - 1)
+    if s.endswith('.') and not any(p in s for p in ['D0', 'D1', 'S0', 'S1', 'S2', 'SCC', 'VCC', 'tmp', '=']): continue
+    if re.match(r'^[a-z].*\.$', s) and '=' not in s: continue
+    is_code = (any(p in s for p in ['D0.', 'D1.', 'S0.', 'S1.', 'S2.', 'SCC =', 'SCC ?', 'VCC', 'EXEC', 'tmp =', 'tmp[', 'lane =', 'PC =',
+                                    'D0[', 'D1[', 'S0[', 'S1[', 'S2[', 'MEM[', 'RETURN_DATA', 'DATA.', 'DATA0', 'DATA1', 'ADDR']) or
+               s.startswith(('if ', 'else', 'elsif', 'endif', 'declare ', 'for ', 'endfor', '//')) or
+               re.match(r'^[a-z_]+\s*=', s) or re.match(r'^[a-z_]+\[', s) or (depth > 0 and '=' in s))
+    if is_code: result.append(s)
+  return '\n'.join(result) if result else None
+
+def _merge_results(results: list[dict]) -> dict:
+  """Merge multiple PDF parse results into a superset."""
+  merged = {"formats": {}, "enums": {}, "src_enum": dict(SRC_EXTRAS), "doc_names": [], "pseudocode": {}, "is_cdna": False}
+  for r in results:
+    merged["doc_names"].append(r["doc_name"])
+    merged["is_cdna"] = merged["is_cdna"] or r["is_cdna"]
+    for val, name in r["src_enum"].items():
+      if val in merged["src_enum"]: assert merged["src_enum"][val] == name
+      else: merged["src_enum"][val] = name
+    for enum_name, ops in r["enums"].items():
+      if enum_name not in merged["enums"]: merged["enums"][enum_name] = {}
+      for val, name in ops.items():
+        if val in merged["enums"][enum_name]: assert merged["enums"][enum_name][val] == name
+        else: merged["enums"][enum_name][val] = name
+    for fmt_name, fields in r["formats"].items():
+      if fmt_name not in merged["formats"]: merged["formats"][fmt_name] = list(fields)
+      else:
+        existing = {f[0]: (f[1], f[2]) for f in merged["formats"][fmt_name]}
+        for f in fields:
+          if f[0] in existing: assert existing[f[0]] == (f[1], f[2])
+          else: merged["formats"][fmt_name].append(f)
+    for key, pc in r["pseudocode"].items():
+      if key not in merged["pseudocode"]: merged["pseudocode"][key] = pc
+  return merged
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# CODE GENERATION
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _generate_enum_py(enums, src_enum, doc_name) -> str:
+  """Generate enum.py content (just enums, no dsl.py dependency)."""
+  def enum_lines(name, items): return [f"class {name}(IntEnum):"] + [f"  {n} = {v}" for v, n in sorted(items.items())] + [""]
+  lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit", "from enum import IntEnum", ""]
+  lines += enum_lines("SrcEnum", src_enum) + sum([enum_lines(n, ops) for n, ops in sorted(enums.items())], [])
+  return '\n'.join(lines)
+
+def _generate_ins_py(formats, enums, src_enum, doc_name) -> str:
+  """Generate ins.py content (instruction formats and helpers, imports dsl.py and enum.py)."""
+  def field_key(f, order): return order.index(f[0].lower()) if f[0].lower() in order else 1000
+  lines = [f"# autogenerated from AMD {doc_name} ISA PDF by pdf.py - do not edit",
+           "# ruff: noqa: F401,F403", "from typing import Annotated",
+           "from extra.assembly.amd.dsl import bits, BitField, Inst32, Inst64, SGPR, VGPR, TTMP as TTMP, s as s, v as v, ttmp as ttmp, SSrc, Src, SImm, Imm, VDSTYEnc, SGPRField, VGPRField",
+           "from extra.assembly.amd.autogen.{arch}.enum import *",
+           "import functools", ""]
+  format_defaults = {'VOP3P': {'opsel_hi': 3, 'opsel_hi2': 1}}
+  lines.append("# instruction formats")
+  for fmt_name, fields in sorted(formats.items()):
+    base = "Inst64" if max(f[1] for f in fields) > 31 or fmt_name == 'VOP3SD' else "Inst32"
+    order = FIELD_ORDER.get(fmt_name, [])
+    lines.append(f"class {fmt_name}({base}):")
+    if enc := next((f for f in fields if f[0] == 'ENCODING'), None):
+      lines.append(f"  encoding = bits[{enc[1]}:{enc[2]}] == 0b{enc[3]:b}" if enc[1] != enc[2] else f"  encoding = bits[{enc[1]}] == {enc[3]}")
+    if defaults := format_defaults.get(fmt_name): lines.append(f"  _defaults = {defaults}")
+    for name, hi, lo, _, ftype in sorted([f for f in fields if f[0] != 'ENCODING'], key=lambda f: field_key(f, order)):
+      ann = f":Annotated[BitField, {ftype}]" if ftype and ftype.endswith('Op') else f":{ftype}" if ftype else ""
+      lines.append(f"  {name.lower()}{ann} = bits[{hi}]" if hi == lo else f"  {name.lower()}{ann} = bits[{hi}:{lo}]")
+    lines.append("")
+  lines.append("# instruction helpers")
+  for cls_name, ops in sorted(enums.items()):
+    fmt = cls_name[:-2]
+    for op_val, name in sorted(ops.items()):
+      seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt, "")
+      tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt, f"{fmt}, {cls_name}")
+      if fmt in formats or fmt in ("GLOBAL", "SCRATCH"):
+        suffix = "_e32" if fmt in ("VOP1", "VOP2", "VOPC") else "_e64" if fmt == "VOP3" and op_val < 512 else ""
+        if name in ('V_FMAMK_F32', 'V_FMAMK_F16'):
+          lines.append(f"def {name.lower()}{suffix}(vdst, src0, K, vsrc1): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
+        elif name in ('V_FMAAK_F32', 'V_FMAAK_F16'):
+          lines.append(f"def {name.lower()}{suffix}(vdst, src0, vsrc1, K): return {fmt}({cls_name}.{name}, vdst, src0, vsrc1, literal=K)")
+        else: lines.append(f"{name.lower()}{suffix} = functools.partial({tgt}.{name}{seg})")
+  src_names = {name for _, name in src_enum.items()}
+  lines += [""] + [f"{name} = SrcEnum.{name}" for _, name in sorted(src_enum.items()) if name not in {'DPP8', 'DPP16'}]
+  if "NULL" in src_names: lines.append("OFF = NULL\n")
+  return '\n'.join(lines)
+
+def _generate_gen_pcode_py(enums, pseudocode, arch) -> str:
+  """Generate gen_pcode.py content (compiled pseudocode functions)."""
+  # Get op enums for this arch (import from .ins which re-exports from .enum)
+  import importlib
+  autogen = importlib.import_module(f"extra.assembly.amd.autogen.{arch}.ins")
+  OP_ENUMS = [getattr(autogen, name) for name in ['SOP1Op', 'SOP2Op', 'SOPCOp', 'SOPKOp', 'SOPPOp', 'VOP1Op', 'VOP2Op', 'VOP3Op', 'VOP3SDOp', 'VOP3POp', 'VOPCOp', 'VOP3AOp', 'VOP3BOp', 'DSOp'] if hasattr(autogen, name)]
+
+  # Build defined ops mapping
+  defined_ops: dict[tuple, list] = {}
+  for enum_cls in OP_ENUMS:
+    for op in enum_cls:
+      if op.name.startswith(('S_', 'V_', 'DS_')): defined_ops.setdefault((op.name, op.value), []).append((enum_cls, op))
+
+  enum_names = [e.__name__ for e in OP_ENUMS]
+  lines = [f'''# autogenerated by pdf.py - do not edit
+# to regenerate: python -m extra.assembly.amd.pdf --arch {arch}
+# ruff: noqa: E501,F405,F403
+# mypy: ignore-errors
+from extra.assembly.amd.autogen.{arch}.enum import {", ".join(enum_names)}
+from extra.assembly.amd.pcode import *
+''']
+
+  instructions: dict = {cls: {} for cls in OP_ENUMS}
+  for key, pc in pseudocode.items():
+    if key in defined_ops:
+      for enum_cls, enum_val in defined_ops[key]: instructions[enum_cls][enum_val] = pc
+
+  for enum_cls in OP_ENUMS:
+    cls_name = enum_cls.__name__
+    if not instructions.get(enum_cls): continue
+    fn_entries = []
+    for op, pc in instructions[enum_cls].items():
+      if any(p in pc for p in UNSUPPORTED): continue
+      try:
+        code = compile_pseudocode(pc)
+        code = _apply_pseudocode_fixes(op, code)
+        fn_name, fn_code = _generate_function(cls_name, op, pc, code)
+        lines.append(fn_code)
+        fn_entries.append((op, fn_name))
+      except Exception as e: print(f"  Warning: Failed to compile {op.name}: {e}")
+    if fn_entries:
+      lines.append(f'{cls_name}_FUNCTIONS = {{')
+      for op, fn_name in fn_entries: lines.append(f"  {cls_name}.{op.name}: {fn_name},")
+      lines.append('}\n')
+
+  # Add V_WRITELANE_B32 if VOP3Op exists
+  if 'VOP3Op' in enum_names:
+    lines.append('''
+# V_WRITELANE_B32: Write scalar to specific lane's VGPR (not in PDF pseudocode)
+def _VOP3Op_V_WRITELANE_B32(s0, s1, s2, d0, scc, vcc, lane, exec_mask, literal, VGPR, _vars, src0_idx=0, vdst_idx=0):
+  wr_lane = s1 & 0x1f
+  return {'d0': d0, 'scc': scc, 'vgpr_write': (wr_lane, vdst_idx, s0 & 0xffffffff)}
+VOP3Op_FUNCTIONS[VOP3Op.V_WRITELANE_B32] = _VOP3Op_V_WRITELANE_B32
+''')
+
+  lines.append('COMPILED_FUNCTIONS = {')
+  for enum_cls in OP_ENUMS:
+    if instructions.get(enum_cls): lines.append(f'  {enum_cls.__name__}: {enum_cls.__name__}_FUNCTIONS,')
+  lines.append('}\n\ndef get_compiled_functions(): return COMPILED_FUNCTIONS')
+  return '\n'.join(lines)
+
+def _apply_pseudocode_fixes(op, code: str) -> str:
+  """Apply known fixes for PDF pseudocode bugs."""
+  if op.name == 'V_DIV_FMAS_F32':
+    code = code.replace('D0.f32 = 2.0 ** 32 * fma(S0.f32, S1.f32, S2.f32)',
+                        'D0.f32 = (2.0 ** 64 if exponent(S2.f32) > 127 else 2.0 ** -64) * fma(S0.f32, S1.f32, S2.f32)')
+  if op.name == 'V_DIV_FMAS_F64':
+    code = code.replace('D0.f64 = 2.0 ** 64 * fma(S0.f64, S1.f64, S2.f64)',
+                        'D0.f64 = (2.0 ** 128 if exponent(S2.f64) > 1023 else 2.0 ** -128) * fma(S0.f64, S1.f64, S2.f64)')
+  if op.name == 'V_DIV_SCALE_F32':
+    code = code.replace('D0.f32 = float("nan")', 'VCC = Reg(0x1); D0.f32 = float("nan")')
+    code = code.replace('elif S1.f32 == DENORM.f32:\n  D0.f32 = ldexp(S0.f32, 64)', 'elif False:\n  pass')
+    code += '\nif S1.f32 == DENORM.f32:\n  D0.f32 = float("nan")'
+    code = code.replace('elif exponent(S2.f32) <= 23:\n  D0.f32 = ldexp(S0.f32, 64)', 'elif exponent(S2.f32) <= 23:\n  VCC = Reg(0x1); D0.f32 = ldexp(S0.f32, 64)')
+    code = code.replace('elif S2.f32 / S1.f32 == DENORM.f32:\n  VCC = Reg(0x1)\n  if S0.f32 == S2.f32:\n    D0.f32 = ldexp(S0.f32, 64)', 'elif S2.f32 / S1.f32 == DENORM.f32:\n  VCC = Reg(0x1)')
+  if op.name == 'V_DIV_SCALE_F64':
+    code = code.replace('D0.f64 = float("nan")', 'VCC = Reg(0x1); D0.f64 = float("nan")')
+    code = code.replace('elif S1.f64 == DENORM.f64:\n  D0.f64 = ldexp(S0.f64, 128)', 'elif False:\n  pass')
+    code += '\nif S1.f64 == DENORM.f64:\n  D0.f64 = float("nan")'
+    code = code.replace('elif exponent(S2.f64) <= 52:\n  D0.f64 = ldexp(S0.f64, 128)', 'elif exponent(S2.f64) <= 52:\n  VCC = Reg(0x1); D0.f64 = ldexp(S0.f64, 128)')
+    code = code.replace('elif S2.f64 / S1.f64 == DENORM.f64:\n  VCC = Reg(0x1)\n  if S0.f64 == S2.f64:\n    D0.f64 = ldexp(S0.f64, 128)', 'elif S2.f64 / S1.f64 == DENORM.f64:\n  VCC = Reg(0x1)')
+  if op.name == 'V_DIV_FIXUP_F32':
+    code = code.replace('D0.f32 = ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))',
+                        'D0.f32 = ((-OVERFLOW_F32) if (sign_out) else (OVERFLOW_F32)) if isNAN(S0.f32) else ((-abs(S0.f32)) if (sign_out) else (abs(S0.f32)))')
+  if op.name == 'V_DIV_FIXUP_F64':
+    code = code.replace('D0.f64 = ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))',
+                        'D0.f64 = ((-OVERFLOW_F64) if (sign_out) else (OVERFLOW_F64)) if isNAN(S0.f64) else ((-abs(S0.f64)) if (sign_out) else (abs(S0.f64)))')
+  if op.name == 'V_TRIG_PREOP_F64':
+    code = code.replace('result = F((TWO_OVER_PI_1201[1200 : 0] << shift.u32) & 0x1fffffffffffff)',
+                        'result = float(((TWO_OVER_PI_1201[1200 : 0] << int(shift)) >> (1201 - 53)) & 0x1fffffffffffff)')
+  return code
+
+def _generate_function(cls_name: str, op, pc: str, code: str) -> tuple[str, str]:
+  """Generate a single compiled pseudocode function."""
+  has_d1 = '{ D1' in pc
+  is_cmpx = (cls_name in ('VOPCOp', 'VOP3Op')) and 'EXEC.u64[laneId]' in pc
+  is_div_scale = 'DIV_SCALE' in op.name
+  has_sdst = cls_name == 'VOP3SDOp' and ('VCC.u64[laneId]' in pc or is_div_scale)
+  has_opsel = 'OPSEL' in pc  # FMA_MIX and similar instructions need OPSEL/OPSEL_HI
+  combined = code + pc
+
+  fn_name = f"_{cls_name}_{op.name}"
+  # Function accepts Reg objects directly (uppercase names), laneId is passed directly as int
+  params = "S0, S1, S2, D0, SCC, VCC, laneId, EXEC, literal, VGPR, src0_idx=0, vdst_idx=0, PC=None"
+  if has_opsel: params += ", OPSEL=0, OPSEL_HI=0"
+  lines = [f"def {fn_name}({params}):"]
+
+  # Registers that need special handling (not passed directly)
+  # Only init if used but not first assigned as `name = Reg(...)` in the compiled code
+  def needs_init(name): return name in combined and not re.search(rf'^\s*{name}\s*=\s*Reg\(', code, re.MULTILINE)
+  special_regs = [('D1', 'Reg(0)'), ('SIMM16', 'Reg(literal)'), ('SIMM32', 'Reg(literal)'),
+                  ('SRC0', 'Reg(src0_idx)'), ('VDST', 'Reg(vdst_idx)')]
+  if needs_init('tmp'): special_regs.insert(0, ('tmp', 'Reg(0)'))
+  if needs_init('saveexec'): special_regs.insert(0, ('saveexec', 'Reg(EXEC._val)'))
+  used = {name for name, _ in special_regs if name in combined}
+
+  # Detect which registers are modified (not just read) - look for assignments
+  modifies_d0 = is_div_scale or bool(re.search(r'\bD0\b[.\[]', combined))
+  modifies_exec = is_cmpx or bool(re.search(r'EXEC\.(u32|u64|b32|b64)\s*=', combined))
+  modifies_vcc = has_sdst or bool(re.search(r'VCC\.(u32|u64|b32|b64)\s*=|VCC\.u64\[laneId\]\s*=', combined))
+  modifies_scc = bool(re.search(r'\bSCC\s*=', combined))
+  modifies_pc = bool(re.search(r'\bPC\s*=', combined))
+
+  # Build init code for special registers
+  init_lines = []
+  if is_div_scale: init_lines.append("  D0 = Reg(S0._val)")
+  for name, init in special_regs:
+    if name in used: init_lines.append(f"  {name} = {init}")
+  if 'EXEC_LO' in code: init_lines.append("  EXEC_LO = SliceProxy(EXEC, 31, 0)")
+  if 'EXEC_HI' in code: init_lines.append("  EXEC_HI = SliceProxy(EXEC, 63, 32)")
+  if 'VCCZ' in code and not re.search(r'^\s*VCCZ\s*=', code, re.MULTILINE): init_lines.append("  VCCZ = Reg(1 if VCC._val == 0 else 0)")
+  if 'EXECZ' in code and not re.search(r'^\s*EXECZ\s*=', code, re.MULTILINE): init_lines.append("  EXECZ = Reg(1 if EXEC._val == 0 else 0)")
+  code_lines = [line for line in code.split('\n') if line.strip()]
+  if init_lines:
+    lines.extend(init_lines)
+    if code_lines: lines.append("  # --- compiled pseudocode ---")
+  for line in code_lines:
+    lines.append(f"  {line}")
+
+  # Build result dict - only include registers that are modified
+  result_items = []
+  if modifies_d0: result_items.append("'D0': D0")
+  if modifies_scc: result_items.append("'SCC': SCC")
+  if modifies_vcc: result_items.append("'VCC': VCC")
+  if modifies_exec: result_items.append("'EXEC': EXEC")
+  if has_d1: result_items.append("'D1': D1")
+  if modifies_pc: result_items.append("'PC': PC")
+  lines.append(f"  return {{{', '.join(result_items)}}}\n")
+  return fn_name, '\n'.join(lines)
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# MAIN GENERATION
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def generate_arch(arch: str) -> dict:
+  """Generate enum.py, ins.py and gen_pcode.py for a single architecture."""
+  urls = PDF_URLS[arch]
+  if isinstance(urls, str): urls = [urls]
+
+  print(f"\n{'='*60}\nGenerating {arch}...")
+  print(f"Parsing {len(urls)} PDF(s)...")
+  results = [_parse_single_pdf(url) for url in urls]
+  merged = _merge_results(results) if len(results) > 1 else results[0]
+  doc_name = "+".join(merged["doc_names"]) if len(results) > 1 else merged["doc_name"]
+
+  base_path = Path(f"extra/assembly/amd/autogen/{arch}")
+  base_path.mkdir(parents=True, exist_ok=True)
+  (base_path / "__init__.py").touch()
+
+  # Write enum.py (enums only, no dsl.py dependency)
+  enum_path = base_path / "enum.py"
+  enum_content = _generate_enum_py(merged["enums"], merged["src_enum"], doc_name)
+  enum_path.write_text(enum_content)
+  print(f"Generated {enum_path}: SrcEnum ({len(merged['src_enum'])}) + {len(merged['enums'])} enums")
+
+  # Write ins.py (instruction formats and helpers, imports dsl.py and enum.py)
+  ins_path = base_path / "ins.py"
+  ins_content = _generate_ins_py(merged["formats"], merged["enums"], merged["src_enum"], doc_name).replace("{arch}", arch)
+  ins_path.write_text(ins_content)
+  print(f"Generated {ins_path}: {len(merged['formats'])} formats")
+
+  # Write gen_pcode.py (needs enum.py to exist first for imports)
+  pcode_path = base_path / "gen_pcode.py"
+  pcode_content = _generate_gen_pcode_py(merged["enums"], merged["pseudocode"], arch)
+  pcode_path.write_text(pcode_content)
+  print(f"Generated {pcode_path}: {len(merged['pseudocode'])} instructions")
+
+  return merged
+
+def _generate_arch_wrapper(arch: str):
+  """Wrapper for multiprocessing - returns arch name for ordering."""
+  generate_arch(arch)
+  return arch
+
+def generate_all():
+  """Generate all architectures in parallel."""
+  with ProcessPoolExecutor() as executor:
+    list(executor.map(_generate_arch_wrapper, PDF_URLS.keys()))
+
+if __name__ == "__main__":
+  import argparse
+  parser = argparse.ArgumentParser(description="Generate AMD ISA autogen files from PDF documentation")
+  parser.add_argument("--arch", choices=list(PDF_URLS.keys()) + ["all"], default="rdna3")
+  args = parser.parse_args()
+  if args.arch == "all": generate_all()
+  else: generate_arch(args.arch)
@@ -1,458 +0,0 @@
-"""SQTT (SQ Thread Trace) packet encoder and decoder for AMD GPUs.
-
-This module provides encoding and decoding of raw SQTT byte streams.
-The format is nibble-based with variable-width packets determined by a state machine.
-Uses BitField infrastructure from dsl.py, similar to GPU instruction encoding.
-"""
-from __future__ import annotations
-from typing import Iterator
-from enum import Enum
-from extra.assembly.amd.dsl import BitField, FixedBitField, bits
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# FIELD ENUMS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class MemSrc(Enum):
-  LDS = 0
-  LDS_ALT = 1
-  VMEM = 2
-  VMEM_ALT = 3
-
-class AluSrc(Enum):
-  NONE = 0
-  SALU = 1
-  VALU = 2
-  VALU_SALU = 3
-
-class InstOp(Enum):
-  """SQTT instruction operation types for RDNA3 (gfx1100).
-
-  Memory ops appear in two ranges depending on which SIMD executes them:
-  - 0x1x-0x2x range: ops on traced SIMD
-  - 0x5x range: ops on other SIMD (OTHER_ prefix)
-
-  GLOBAL memory ops encoding depends on addressing mode AND size:
-  - Loads: 0x21 (saddr=SGPR) or 0x22 (saddr=NULL), all sizes same
-  - Stores: base + size_offset, where VADDR is shifted +1 from SADDR
-    SADDR: 0x24(32) 0x25(64) 0x26(96) 0x27(128)
-    VADDR: 0x25(32) 0x26(64) 0x27(96) 0x28(128)
-
-  OTHER_ range follows same pattern but values overlap differently.
-  """
-  SALU = 0x0
-  SMEM = 0x1
-  JUMP = 0x3              # branch taken
-  JUMP_NO = 0x4           # branch not taken
-  MESSAGE = 0x9
-  VALU_TRANS = 0xb        # transcendental: exp, log, rcp, sqrt, sin, cos
-  VALU_64_SHIFT = 0xd     # 64-bit shifts: lshl, lshr, ashr
-  VALU_MAD64 = 0xe        # 64-bit multiply-add
-  VALU_64 = 0xf           # 64-bit: add, mul, fma, rcp, sqrt, rounding, frexp, div helpers
-  VINTERP = 0x12          # interpolation: v_interp_p10_f32, v_interp_p2_f32
-  BARRIER = 0x13
-
-  # FLAT memory ops on traced SIMD (0x1x range)
-  FLAT_LOAD = 0x1c
-  FLAT_STORE = 0x1d
-  FLAT_STORE_64 = 0x1e
-  FLAT_STORE_96 = 0x1f
-  FLAT_STORE_128 = 0x20
-
-  # GLOBAL memory ops on traced SIMD (0x2x range)
-  GLOBAL_LOAD = 0x21             # saddr=SGPR, all sizes
-  GLOBAL_LOAD_VADDR = 0x22       # saddr=NULL, all sizes
-  GLOBAL_STORE = 0x24            # saddr=SGPR, 32-bit
-  GLOBAL_STORE_64 = 0x25         # saddr=SGPR 64 or saddr=NULL 32
-  GLOBAL_STORE_96 = 0x26         # saddr=SGPR 96 or saddr=NULL 64
-  GLOBAL_STORE_128 = 0x27        # saddr=SGPR 128 or saddr=NULL 96
-  GLOBAL_STORE_VADDR_128 = 0x28  # saddr=NULL, 128-bit
-
-  # LDS ops on traced SIMD
-  LDS_LOAD = 0x29
-  LDS_STORE = 0x2b
-  LDS_STORE_64 = 0x2c
-  LDS_STORE_128 = 0x2e
-
-  # Memory ops on other SIMD (0x5x range)
-  OTHER_LDS_LOAD = 0x50
-  OTHER_LDS_STORE = 0x51
-  OTHER_LDS_STORE_64 = 0x52
-  OTHER_LDS_STORE_128 = 0x54
-  OTHER_FLAT_LOAD = 0x55
-  OTHER_FLAT_STORE = 0x56
-  OTHER_FLAT_STORE_64 = 0x57
-  OTHER_FLAT_STORE_96 = 0x58
-  OTHER_FLAT_STORE_128 = 0x59
-  OTHER_GLOBAL_LOAD = 0x5a             # saddr=SGPR, all sizes
-  OTHER_GLOBAL_LOAD_VADDR = 0x5b       # saddr=NULL or saddr=SGPR store 32
-  OTHER_GLOBAL_STORE_64 = 0x5c         # saddr=SGPR 64 or saddr=NULL 32
-  OTHER_GLOBAL_STORE_96 = 0x5d         # saddr=SGPR 96 or saddr=NULL 64
-  OTHER_GLOBAL_STORE_128 = 0x5e        # saddr=SGPR 128 or saddr=NULL 96
-  OTHER_GLOBAL_STORE_VADDR_128 = 0x5f  # saddr=NULL, 128-bit
-
-  # EXEC-modifying ops (0x7x range)
-  SALU_SAVEEXEC = 0x72    # s_*_saveexec_b32/b64
-  VALU_CMPX = 0x73        # v_cmpx_*
-
-class InstOpL4(Enum):
-  """SQTT instruction operation types for RDNA4 (gfx1200). Different encoding from RDNA3."""
-  # TODO: we need to do discovery of all of these from instructions
-  SALU = 0x0
-  SMEM = 0x1
-  UNK_02 = 0x2
-  JUMP_NO = 0x4
-  UNK_06 = 0x6
-  VMEM = 0x10
-  UNK_11 = 0x11
-  VINTERP = 0x12
-  UNK_14 = 0x14
-  OTHER_VMEM = 0x5e
-  UNK_60 = 0x60
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# PACKET TYPE BASE CLASS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class PacketType:
-  """Base class for SQTT packet types."""
-  encoding: FixedBitField
-  _raw: int
-  _time: int
-
-  def __init_subclass__(cls, **kwargs):
-    super().__init_subclass__(**kwargs)
-    cls._fields = {k: v for k, v in cls.__dict__.items() if isinstance(v, BitField)}
-    cls._size_nibbles = ((max((f.hi for f in cls._fields.values()), default=0) + 4) // 4)
-
-  @classmethod
-  def from_raw(cls, raw: int, time: int = 0):
-    inst = object.__new__(cls)
-    inst._raw, inst._time = raw, time
-    return inst
-
-  def __repr__(self) -> str:
-    fields_str = ", ".join(f"{k}={getattr(self, k)}" for k in self._fields if not k.startswith('_') and k != 'encoding')
-    return f"{self.__class__.__name__}({fields_str})"
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# TS PACKET TYPE DEFINITIONS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class TS_DELTA_S8_W3(PacketType):
-  encoding = bits[6:0] == 0b0100001
-  delta = bits[10:8]
-  _padding = bits[63:11]
-
-class TS_DELTA_S8_W3_L4(PacketType):  # Layout 4: 64->72 bits
-  encoding = bits[6:0] == 0b0100001
-  delta = bits[10:8]
-  _padding = bits[71:11]
-
-class TS_DELTA_S5_W3(PacketType):
-  encoding = bits[4:0] == 0b00110
-  delta = bits[7:5]
-  _padding = bits[51:8]
-
-class TS_DELTA_S5_W3_L4(PacketType):  # Layout 4: 52->56 bits
-  encoding = bits[4:0] == 0b00110
-  delta = bits[9:7]
-  _padding = bits[55:10]
-
-class TS_DELTA_SHORT(PacketType):
-  encoding = bits[3:0] == 0b1000
-  delta = bits[7:4]
-
-class TS_DELTA_OR_MARK(PacketType):
-  encoding = bits[6:0] == 0b0000001
-  delta = bits[47:12]
-  bit8 = bits[8:8]
-  bit9 = bits[9:9]
-  @property
-  def is_marker(self) -> bool: return bool(self.bit9 and not self.bit8)
-
-class TS_DELTA_OR_MARK_L4(PacketType):  # Layout 4: 48->64 bits
-  encoding = bits[6:0] == 0b0000001
-  delta = bits[63:12]
-  bit7 = bits[7:7]
-  bit8 = bits[8:8]
-  bit9 = bits[9:9]
-  @property
-  def is_marker(self) -> bool: return bool((self.bit9 and not self.bit8) or self.bit7)
-
-class TS_DELTA_S5_W2(PacketType):
-  encoding = bits[4:0] == 0b11100
-  delta = bits[6:5]
-  _padding = bits[47:7]
-
-class TS_DELTA_S5_W2_L4(PacketType):  # Layout 4: 48->40 bits
-  encoding = bits[4:0] == 0b11100
-  delta = bits[6:5]
-  _padding = bits[39:7]
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# PACKET TYPE DEFINITIONS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class VALUINST(PacketType):  # exclude: 1 << 2
-  encoding = bits[2:0] == 0b011
-  delta = bits[5:3]
-  flag = bits[6:6]
-  wave = bits[11:7]
-
-class VMEMEXEC(PacketType):  # exclude: 1 << 0
-  encoding = bits[3:0] == 0b1111
-  delta = bits[5:4]
-  src = bits[7:6].enum(MemSrc)
-
-class ALUEXEC(PacketType):  # exclude: 1 << 1
-  encoding = bits[3:0] == 0b1110
-  delta = bits[5:4]
-  src = bits[7:6].enum(AluSrc)
-
-class IMMEDIATE(PacketType):  # exclude: 1 << 5
-  encoding = bits[3:0] == 0b1101
-  delta = bits[6:4]
-  wave = bits[11:7]
-
-class IMMEDIATE_MASK(PacketType):  # exclude: 1 << 5
-  encoding = bits[4:0] == 0b00100
-  delta = bits[7:5]
-  mask = bits[23:8]
-
-class WAVERDY(PacketType):  # exclude: 1 << 3
-  encoding = bits[4:0] == 0b10100
-  delta = bits[7:5]
-  mask = bits[23:8]
-
-class WAVEEND(PacketType):  # exclude: 1 << 4
-  encoding = bits[4:0] == 0b10101
-  delta = bits[7:5]
-  flag7 = bits[8:8]
-  simd = bits[10:9]
-  cu_lo = bits[13:11]
-  wave = bits[19:15]
-  @property
-  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)
-
-class WAVESTART(PacketType):  # exclude: 1 << 4
-  encoding = bits[4:0] == 0b01100
-  delta = bits[6:5]
-  flag7 = bits[7:7]
-  simd = bits[9:8]
-  cu_lo = bits[12:10]
-  wave = bits[17:13]
-  id7 = bits[31:18]
-  @property
-  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)
-
-class WAVESTART_L4(PacketType):  # Layout 4 has wave field at different position
-  encoding = bits[4:0] == 0b01100
-  delta = bits[6:5]
-  flag7 = bits[7:7]
-  simd = bits[9:8]
-  cu_lo = bits[12:10]
-  wave = bits[19:15]
-  id7 = bits[31:20]
-  @property
-  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)
-
-class WAVEALLOC(PacketType):  # exclude: 1 << 10
-  encoding = bits[4:0] == 0b00101
-  delta = bits[7:5]
-  _padding = bits[19:8]
-
-class WAVEALLOC_L4(PacketType):  # Layout 4: 20->24 bits
-  encoding = bits[4:0] == 0b00101
-  delta = bits[7:5]
-  _padding = bits[23:8]
-
-class PERF(PacketType):  # exclude: 1 << 11
-  encoding = bits[4:0] == 0b10110
-  delta = bits[7:5]
-  arg = bits[27:8]
-
-class PERF_L4(PacketType):  # Layout 4: 28->32 bits
-  encoding = bits[4:0] == 0b10110
-  delta = bits[9:7]
-  arg = bits[31:10]
-
-class NOP(PacketType):
-  encoding = bits[3:0] == 0b0000
-  delta = None  # type: ignore
-  _padding = bits[3:0]
-
-class TS_WAVE_STATE(PacketType):
-  encoding = bits[6:0] == 0b1010001
-  delta = bits[15:7]
-  coarse = bits[23:16]
-  @property
-  def wave_interest(self) -> bool: return bool(self.coarse & 1)
-  @property
-  def terminate_all(self) -> bool: return bool(self.coarse & 8)
-
-class EVENT(PacketType):  # exclude: 1 << 7
-  encoding = bits[7:0] == 0b01100001
-  delta = bits[10:8]
-  event = bits[23:11]
-
-class EVENT_BIG(PacketType):
-  encoding = bits[7:0] == 0b11100001
-  delta = bits[10:8]
-  event = bits[31:11]
-
-class REG(PacketType):
-  encoding = bits[3:0] == 0b1001
-  delta = bits[6:4]
-  slot = bits[9:7]
-  hi_byte = bits[15:8]
-  subop = bits[31:16]
-  val32 = bits[63:32]
-  @property
-  def is_config(self) -> bool: return bool(self.hi_byte & 0x80)
-
-class SNAPSHOT(PacketType):
-  encoding = bits[6:0] == 0b1110001
-  delta = bits[9:7]
-  snap = bits[63:10]
-
-class LAYOUT_HEADER(PacketType):
-  encoding = bits[6:0] == 0b0010001
-  delta = None  # type: ignore
-  layout = bits[12:7]
-  simd = bits[14:13]
-  group = bits[17:15]
-  sel_a = bits[31:28]
-  sel_b = bits[36:33]
-  flag4 = bits[59:59]
-  _padding = bits[63:60]
-
-class INST(PacketType):
-  encoding = bits[2:0] == 0b010
-  delta = bits[6:4]
-  flag1 = bits[3:3]
-  flag2 = bits[7:7]
-  wave = bits[12:8]
-  op = bits[19:13].enum(InstOp)
-
-class INST_L4(PacketType):  # Layout 4: different delta position and InstOp encoding
-  encoding = bits[2:0] == 0b010
-  delta = bits[5:3]
-  flag1 = bits[6:6]
-  flag2 = bits[7:7]
-  wave = bits[12:8]
-  op = bits[19:13].enum(InstOpL4)
-
-class UTILCTR(PacketType):
-  encoding = bits[6:0] == 0b0110001
-  delta = bits[8:7]
-  ctr = bits[47:9]
-
-# Packet types with rocprof type IDs as keys
-PACKET_TYPES_L3: dict[int, type[PacketType]] = {
-  1: VALUINST, 2: VMEMEXEC, 3: ALUEXEC, 4: IMMEDIATE, 5: IMMEDIATE_MASK, 6: WAVERDY, 7: TS_DELTA_S8_W3, 8: WAVEEND,
-  9: WAVESTART, 10: TS_DELTA_S5_W2, 11: WAVEALLOC, 12: TS_DELTA_S5_W3, 13: PERF, 14: UTILCTR, 15: TS_DELTA_SHORT,
-  16: NOP, 17: TS_WAVE_STATE, 18: EVENT, 19: EVENT_BIG, 20: REG, 21: SNAPSHOT, 22: TS_DELTA_OR_MARK, 23: LAYOUT_HEADER, 24: INST,
-}
-PACKET_TYPES_L4: dict[int, type[PacketType]] = {
-  **PACKET_TYPES_L3,
-  7: TS_DELTA_S8_W3_L4, 9: WAVESTART_L4, 10: TS_DELTA_S5_W2_L4, 11: WAVEALLOC_L4,
-  12: TS_DELTA_S5_W3_L4, 13: PERF_L4, 22: TS_DELTA_OR_MARK_L4, 24: INST_L4,
-}
-def _build_decode_tables(packet_types: dict[int, type[PacketType]]) -> tuple[dict[int, tuple], bytes]:
-  # Build state table: byte -> opcode. Sort by mask specificity (more bits first), NOP last
-  sorted_types = sorted(packet_types.items(), key=lambda x: (-bin(x[1].encoding.mask).count('1'), x[0] == 16))
-  state_table = bytes(next((op for op, cls in sorted_types if (b & cls.encoding.mask) == cls.encoding.default), 16) for b in range(256))
-  # Build decode info: opcode -> (pkt_cls, nib_count, delta_lo, delta_mask, special_case)
-  # special_case: 0=none, 1=TS_DELTA_OR_MARK (check is_marker), 2=TS_DELTA_SHORT (add 8)
-  decode_info = {}
-  for opcode, pkt_cls in packet_types.items():
-    delta_field = getattr(pkt_cls, 'delta', None)
-    special = {22: 1, 15: 2}.get(opcode, 0)  # TS_DELTA_OR_MARK=22, TS_DELTA_SHORT=15
-    decode_info[opcode] = (pkt_cls, pkt_cls._size_nibbles, delta_field.lo if delta_field else 0, delta_field.mask if delta_field else 0, special)
-  return decode_info, state_table
-
-_DECODE_INFO_L3, _STATE_TABLE_L3 = _build_decode_tables(PACKET_TYPES_L3)
-_DECODE_INFO_L4, _STATE_TABLE_L4 = _build_decode_tables(PACKET_TYPES_L4)
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# DECODER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def decode(data: bytes) -> Iterator[PacketType]:
-  """Decode raw SQTT blob, yielding packet instances. Auto-detects layout from LAYOUT_HEADER."""
-  n, reg, pos, nib_off, nib_count, time = len(data), 0, 0, 0, 16, 0
-  decode_info, state_table = _DECODE_INFO_L3, _STATE_TABLE_L3  # default to layout 3, will update after seeing LAYOUT_HEADER
-
-  while pos + ((nib_count + nib_off + 1) >> 1) <= n:
-    need = nib_count - nib_off
-    # 1. if unaligned, read high nibble to align
-    if nib_off: reg, pos = (reg >> 4) | ((data[pos] >> 4) << 60), pos + 1
-    # 2. read all full bytes at once
-    if (byte_count := need >> 1):
-      chunk = int.from_bytes(data[pos:pos + byte_count], 'little')
-      reg, pos = (reg >> (byte_count * 8)) | (chunk << (64 - byte_count * 8)), pos + byte_count
-    # 3. if odd, read low nibble
-    if (nib_off := need & 1): reg = (reg >> 4) | ((data[pos] & 0xF) << 60)
-
-    opcode = state_table[reg & 0xFF]
-    pkt_cls, nib_count, delta_lo, delta_mask, special = decode_info[opcode]
-    delta = (reg >> delta_lo) & delta_mask
-    if special == 1:  # TS_DELTA_OR_MARK
-      pkt = pkt_cls.from_raw(reg, 0)  # create packet to check is_marker
-      if pkt.is_marker: delta = 0
-    elif special == 2: delta += 8  # TS_DELTA_SHORT
-    time += delta
-    pkt = pkt_cls.from_raw(reg, time)
-    # detect layout from first LAYOUT_HEADER and switch decode tables if needed
-    # NOTE: CDNA uses a completely different 16-bit header format, not nibbles - not supported here
-    if pkt_cls is LAYOUT_HEADER and pkt.layout == 4:
-      decode_info, state_table = _DECODE_INFO_L4, _STATE_TABLE_L4
-    yield pkt
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# PRINTER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-PACKET_COLORS = {
-  "INST": "WHITE", "VALUINST": "BLACK", "VMEMEXEC": "yellow", "ALUEXEC": "yellow",
-  "IMMEDIATE": "YELLOW", "IMMEDIATE_MASK": "YELLOW", "WAVERDY": "cyan", "WAVEALLOC": "cyan",
-  "WAVEEND": "blue", "WAVESTART": "blue", "PERF": "magenta", "EVENT": "red", "EVENT_BIG": "red",
-  "REG": "green", "LAYOUT_HEADER": "white", "SNAPSHOT": "white", "UTILCTR": "green",
-}
-
-def format_packet(p) -> str:
-  from tinygrad.helpers import colored
-  name = type(p).__name__
-  if isinstance(p, (INST, INST_L4)):
-    op_name = p.op.name if isinstance(p.op, (InstOp, InstOpL4)) else f"0x{p.op:02x}"
-    fields = f"wave={p.wave} op={op_name}" + (" flag1" if p.flag1 else "") + (" flag2" if p.flag2 else "")
-  elif isinstance(p, VALUINST): fields = f"wave={p.wave}" + (" flag" if p.flag else "")
-  elif isinstance(p, ALUEXEC): fields = f"src={p.src.name if isinstance(p.src, AluSrc) else p.src}"
-  elif isinstance(p, VMEMEXEC): fields = f"src={p.src.name if isinstance(p.src, MemSrc) else p.src}"
-  elif isinstance(p, (WAVESTART, WAVESTART_L4, WAVEEND)): fields = f"wave={p.wave} simd={p.simd} cu={p.cu}"
-  elif hasattr(p, '_fields'):
-    filt = {'delta', 'encoding'} if not isinstance(p, (TS_DELTA_OR_MARK, TS_DELTA_OR_MARK_L4)) else {'encoding'}
-    fields = " ".join(f"{k}=0x{getattr(p, k):x}" if k in {'snap', 'val32'} else f"{k}={getattr(p, k)}"
-                      for k in p._fields if not k.startswith('_') and k not in filt)
-  else: fields = ""
-  return f"{p._time:8}: {colored(f'{name:18}', PACKET_COLORS.get(name.replace('_L4', ''), 'white'))} {fields}"
-
-def print_packets(packets) -> None:
-  from tinygrad.helpers import getenv
-  skip = {"NOP", "TS_DELTA_SHORT", "TS_WAVE_STATE", "TS_DELTA_OR_MARK",
-          "TS_DELTA_S5_W2", "TS_DELTA_S5_W3", "TS_DELTA_S8_W3", "REG", "EVENT"} if not getenv("NOSKIP") else {"NOP"}
-  for p in packets:
-    if type(p).__name__.replace("_L4", "") not in skip: print(format_packet(p))
-
-if __name__ == "__main__":
-  import sys, pickle
-  if len(sys.argv) < 2:
-    print("Usage: python sqtt.py <pkl_file>")
-    sys.exit(1)
-  with open(sys.argv[1], "rb") as f:
-    data = pickle.load(f)
-  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
-  for i, event in enumerate(sqtt_events):
-    print(f"\n=== event {i} ===")
-    print_packets(decode(event.blob))
@@ -1,161 +0,0 @@
-"""SQTT (SQ Thread Trace) packet decoder for CDNA/MI300 GPUs.
-
-CDNA uses a completely different 16-bit header format from RDNA's nibble-based encoding.
-"""
-from __future__ import annotations
-from typing import Iterator
-from extra.assembly.amd.dsl import bits
-from extra.assembly.amd.sqtt import PacketType
-
-# CDNA pkt_fmt -> size in bytes (extracted from rocprof hash table)
-CDNA_PKT_SIZES = {0: 2, 1: 8, 2: 8, 3: 4, 4: 2, 5: 6, 6: 2, 7: 2, 8: 2, 9: 2, 10: 2, 11: 8, 12: 6, 13: 4, 14: 8, 15: 6}
-
-class CDNA_DELTA(PacketType):
-  """pkt_fmt=0: 16-bit timestamp delta packet"""
-  encoding = bits[3:0] == 0
-  delta = bits[11:4]      # (data >> 4) & 0xff
-  unk_0 = bits[12:12]     # (data >> 0xc) & 1
-  unk_1 = bits[15:13]     # (data >> 0xd)
-
-class CDNA_TIMESTAMP(PacketType):
-  """pkt_fmt=1: 64-bit timestamp packet (case 0x0)"""
-  encoding = bits[3:0] == 1
-  unk_0 = bits[15:4]
-  timestamp = bits[63:16]   # stored as (data_word >> 0x10) in low 46 bits of local_58
-
-class CDNA_PKT_2(PacketType):
-  """pkt_fmt=2: 64-bit packet (case 0x4)"""
-  encoding = bits[3:0] == 2
-  unk_0 = bits[6:5]       # (data >> 5) & 3
-  unk_1 = bits[7:7]       # (data >> 7) + 1 & 1
-  unk_padding = bits[63:8]
-
-class CDNA_WAVESTART(PacketType):
-  """pkt_fmt=3: 32-bit WAVESTART packet (case 0x8)"""
-  encoding = bits[3:0] == 3
-  unk_0 = bits[5:5]       # (data >> 5) & 1
-  unk_1 = bits[9:6]       # (data >> 6) & 0xf
-  wave = bits[13:10]      # (data >> 10) & 0xf
-  simd = bits[15:14]      # (data >> 0xe) & 3
-  cu = bits[17:16]        # (data >> 0x10) & 3
-  unk_5 = bits[19:18]     # (data >> 0x12) & 3
-  unk_6 = bits[28:22]     # (data >> 0x16) & 0x7f
-  unk_padding = bits[31:29]
-
-class CDNA_PKT_4(PacketType):
-  """pkt_fmt=4: 16-bit packet (case 0xc, same as 0x8/0x14)"""
-  encoding = bits[3:0] == 4
-  unk_0 = bits[5:5]       # (data_word >> 5) & 1
-  unk_1 = bits[9:6]       # (data_word >> 6) & 0xf
-  unk_2 = bits[13:10]     # (data_word >> 10) & 0xf
-  unk_3 = bits[15:14]     # (data_word >> 0xe)
-
-class CDNA_PKT_5(PacketType):
-  """pkt_fmt=5: 48-bit packet (case 0x10)"""
-  encoding = bits[3:0] == 5
-  unk_0 = bits[6:5]       # (data >> 5) & 3
-  unk_1 = bits[7:7]       # (data >> 7) + 1 & 1
-  unk_2 = bits[15:9]      # (data >> 9) & 0x7f
-  unk_padding = bits[47:16]
-
-class CDNA_WAVEEND(PacketType):
-  """pkt_fmt=6: 16-bit WAVEEND packet (case 0x14, same as 0x8/0xc)"""
-  encoding = bits[3:0] == 6
-  unk_0 = bits[5:5]       # (data_word >> 5) & 1
-  unk_1 = bits[9:6]       # (data_word >> 6) & 0xf
-  wave = bits[13:10]      # (data_word >> 10) & 0xf
-  simd = bits[15:14]      # (data_word >> 0xe)
-
-class CDNA_EXEC(PacketType):
-  """pkt_fmt=10: 16-bit EXEC packet (case 0x24)"""
-  encoding = bits[3:0] == 10
-  unk_0 = bits[8:5]       # (data_word >> 5) & 0xf
-  unk_1 = bits[10:9]      # (data_word >> 9) & 3
-  unk_2 = bits[15:11]     # (data_word >> 0xb)
-
-class CDNA_PKT_11(PacketType):
-  """pkt_fmt=11: 64-bit packet (case 0x28)"""
-  encoding = bits[3:0] == 11
-  unk_0 = bits[8:5]       # (data_word >> 5) & 0xf
-  unk_1 = bits[10:9]      # (data_word >> 9) & 3
-  unk_2 = bits[15:15]     # (data_word >> 0xf) & 1
-  unk_padding = bits[63:16]
-
-class CDNA_INST(PacketType):
-  """pkt_fmt=13: 32-bit INST packet (case 0x30)"""
-  encoding = bits[3:0] == 13
-  unk_0 = bits[6:5]       # (data >> 5) & 3
-  unk_1 = bits[9:8]       # (data >> 8) & 3
-  unk_2 = bits[11:10]     # (data >> 10) & 3
-  unk_3 = bits[13:12]     # (data >> 0xc) & 3
-  unk_4 = bits[15:14]     # (data >> 0xe) & 3
-  unk_5 = bits[19:18]     # (data >> 0x12) & 3
-  unk_6 = bits[21:20]     # (data >> 0x14) & 3
-  unk_7 = bits[23:22]     # (data >> 0x16) & 3
-  unk_8 = bits[25:24]     # (data >> 0x18) & 3
-  unk_9 = bits[27:26]     # (data >> 0x1a) & 3
-  unk_padding = bits[31:28]
-
-class CDNA_PKT_14(PacketType):
-  """pkt_fmt=14: 64-bit packet (case 0x34)"""
-  encoding = bits[3:0] == 14
-  unk_0 = bits[5:5]       # (data >> 5) & 1
-  unk_1 = bits[9:6]       # (data >> 6) & 0xf
-  unk_2 = bits[11:10]     # (data >> 10) & 3
-  unk_3 = bits[24:12]     # (data >> 0xc) & 0x1fff
-  unk_4 = bits[37:25]     # (data >> 0x19) & 0x1fff
-  unk_5 = bits[50:38]     # (data >> 0x26) & 0x1fff
-  unk_6 = bits[51:51]     # (data >> 0x33) & 1
-  unk_padding = bits[63:52]
-
-class CDNA_PKT_15(PacketType):
-  """pkt_fmt=15: 48-bit packet (case 0x38, same as 0x10)"""
-  encoding = bits[3:0] == 15
-  unk_0 = bits[6:5]       # (data >> 5) & 3
-  unk_1 = bits[7:7]       # (data >> 7) + 1 & 1
-  unk_2 = bits[15:9]      # (data >> 9) & 0x7f
-  unk_padding = bits[47:16]
-
-CDNA_PKT_TYPES: dict[int, type[PacketType]] = {
-  0: CDNA_DELTA, 1: CDNA_TIMESTAMP, 2: CDNA_PKT_2, 3: CDNA_WAVESTART, 4: CDNA_PKT_4,
-  5: CDNA_PKT_5, 6: CDNA_WAVEEND, 10: CDNA_EXEC, 11: CDNA_PKT_11, 13: CDNA_INST, 14: CDNA_PKT_14, 15: CDNA_PKT_15,
-}
-
-# Validate CDNA packet definitions
-for pkt_fmt, pkt_cls in CDNA_PKT_TYPES.items():
-  assert pkt_cls.encoding.default == pkt_fmt, f"{pkt_cls.__name__} encoding {pkt_cls.encoding.default} != pkt_fmt {pkt_fmt}"
-  assert CDNA_PKT_SIZES[pkt_fmt] * 2 == pkt_cls._size_nibbles, f"{pkt_cls.__name__} size {pkt_cls._size_nibbles//2} != {CDNA_PKT_SIZES[pkt_fmt]}"
-
-def decode(data: bytes) -> Iterator[PacketType]:
-  """Decode CDNA SQTT blob using 16-bit header format."""
-  pos, time, ts_offset = 0, 0, None
-  while pos + 2 <= len(data):
-    header = int.from_bytes(data[pos:pos+2], 'little')
-    pkt_fmt = header & 0xf
-    pkt_size = CDNA_PKT_SIZES[pkt_fmt]
-    if pos + pkt_size > len(data): break
-
-    raw = int.from_bytes(data[pos:pos+pkt_size], 'little')
-    # pkt_fmt=0 has delta in bits[11:4], accumulate it
-    if pkt_fmt == 0: time += ((raw >> 4) & 0xff) * 4
-    # pkt_fmt=1 with unk_0=0 is absolute timestamp - use it to anchor time
-    if pkt_fmt == 1 and ((raw >> 4) & 0xfff) == 0:
-      abs_ts = raw >> 16
-      if ts_offset is None: ts_offset = abs_ts - time  # first timestamp: save offset
-      else: time = ((abs_ts - ts_offset) & ~3) - 4     # subsequent: compute time, align to 4, subtract 4
-    pkt_cls = CDNA_PKT_TYPES[pkt_fmt]
-    yield pkt_cls.from_raw(raw, time)
-    pos += pkt_size
-
-if __name__ == "__main__":
-  import sys, pickle
-  if len(sys.argv) < 2:
-    print("Usage: python sqtt_cdna.py <pkl_file>")
-    sys.exit(1)
-  with open(sys.argv[1], "rb") as f:
-    data = pickle.load(f)
-  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
-  for i, event in enumerate(sqtt_events):
-    print(f"\n=== event {i} ===")
-    for pkt in decode(event.blob):
-      print(f"{pkt._time:8}: {pkt}")
@@ -1,122 +0,0 @@
-# maps SQTT trace packets to instructions.
-from dataclasses import dataclass
-from typing import Iterator
-
-from extra.assembly.amd.sqtt import decode, print_packets, INST, VALUINST, IMMEDIATE, WAVESTART, WAVEEND, InstOp, PacketType, IMMEDIATE_MASK
-from extra.assembly.amd.dsl import Inst
-from extra.assembly.amd.autogen.rdna3.ins import SOPP, s_endpgm
-from extra.assembly.amd.autogen.rdna3.enum import SOPPOp
-
-@dataclass(frozen=True)
-class InstructionInfo:
-  pc: int
-  wave: int
-  inst: Inst
-
-def map_insts(data:bytes, lib:bytes, target:int) -> Iterator[tuple[PacketType, InstructionInfo|None]]:
-  """maps SQTT packets to instructions, yields (packet, instruction_info or None)"""
-  # map pcs to insts
-  from tinygrad.viz.serve import amd_decode
-  pc_map = amd_decode(lib, target)
-
-  wave_pc:dict[int, int] = {}
-  # only processing packets on one [CU, SIMD] unit
-  def simd_select(p) -> bool: return getattr(p, "cu", 0) == 0 and getattr(p, "simd", 0) == 0
-  for p in decode(data):
-    if not simd_select(p): continue
-    if isinstance(p, WAVESTART):
-      assert p.wave not in wave_pc, "only one inflight wave per unit"
-      wave_pc[p.wave] = next(iter(pc_map))
-      continue
-    if isinstance(p, WAVEEND):
-      pc = wave_pc.pop(p.wave)
-      yield (p, InstructionInfo(pc, p.wave, s_endpgm()))
-      continue
-    # skip OTHER_ instructions, they don't belong to this unit
-    if isinstance(p, INST) and p.op.name.startswith("OTHER_"): continue
-    if isinstance(p, IMMEDIATE_MASK):
-      # immediate mask may yield multiple times per packet
-      for wave in range(16):
-        if p.mask & (1 << wave):
-          inst = pc_map[pc:=wave_pc[wave]]
-          # can this assert be more strict?
-          assert isinstance(inst, SOPP), f"IMMEDIATE_MASK packet must map to SOPP, got {inst}"
-          wave_pc[wave] += inst.size()
-          yield (p, InstructionInfo(pc, wave, inst))
-      continue
-    if isinstance(p, (VALUINST, INST, IMMEDIATE)):
-      inst = pc_map[pc:=wave_pc[p.wave]]
-      # s_delay_alu doesn't get a packet?
-      if isinstance(inst, SOPP) and inst.op in {SOPPOp.S_DELAY_ALU}:
-        wave_pc[p.wave] += inst.size()
-        inst = pc_map[pc:=wave_pc[p.wave]]
-      # identify a branch instruction, only used for asserts
-      is_branch = isinstance(inst, SOPP) and "BRANCH" in inst.op_name
-      if is_branch: assert isinstance(p, INST) and p.op in {InstOp.JUMP_NO, InstOp.JUMP}, f"branch can only be folowed by jump packets, got {p}"
-      # JUMP handling
-      if isinstance(p, INST) and p.op is InstOp.JUMP:
-        assert is_branch, f"JUMP packet must map to a branch instruction, got {inst}"
-        x = inst.simm16 & 0xffff
-        wave_pc[p.wave] += inst.size() + (x - 0x10000 if x & 0x8000 else x)*4
-      else:
-        if is_branch: assert inst.op != SOPPOp.S_BRANCH, f"S_BRANCH must have a JUMP packet, got {p}"
-        wave_pc[p.wave] += inst.size()
-      yield (p, InstructionInfo(pc, p.wave, inst))
-      continue
-    # for all other packets (VMEMEXEC, ALUEXEC, etc.), yield with None
-    yield (p, None)
-
-# test to compare every packet with the rocprof decoder
-
-def test_rocprof_inst_traces_match(sqtt, prg, target):
-  from tinygrad.viz.serve import amd_decode
-  from extra.sqtt.roc import decode as roc_decode, InstExec
-  addr_table = amd_decode(prg.lib, target)
-  disasm = {addr+prg.base:(inst.disasm(), inst.size()) for addr,inst in addr_table.items()}
-  rctx = roc_decode([sqtt], {prg.tag:disasm})
-  rwaves = rctx.inst_execs.get((sqtt.kern, sqtt.exec_tag), [])
-  rwaves_iter:dict[int, list[Iterator[InstExec]]] = {} # wave unit (0-15) -> list of inst trace iterators for all executions on that unit
-  for w in rwaves: rwaves_iter.setdefault(w.wave_id, []).append(w.unpack_insts())
-
-  passed_insts = 0
-  for pkt, info in map_insts(sqtt.blob, prg.lib, target):
-    if DEBUG >= 2: print_packets([pkt])
-    if info is None: continue
-    if DEBUG >= 2: print(f"{' '*29}{info.inst.disasm()}")
-    rocprof_inst = next(rwaves_iter[info.wave][0])
-    ref_pc = rocprof_inst.pc-prg.base
-    # always check pc matches
-    assert ref_pc == info.pc, f"pc mismatch {ref_pc}:{disasm[rocprof_inst.pc][0]} != {info.pc}:{info.inst.disasm()}"
-    # special handling for s_endpgm, it marks the wave completion.
-    if info.inst == s_endpgm():
-      completed_wave = list(rwaves_iter[info.wave].pop(0))
-      assert len(completed_wave) == 0, f"incomplete instructions in wave {info.wave}"
-    # otherwise the packet timestamp is time + "stall"
-    else:
-      assert pkt._time == rocprof_inst.time+rocprof_inst.stall
-    passed_insts += 1
-
-  for k,v in rwaves_iter.items():
-    assert len(v) == 0, f"incomplete wave {k}"
-
-  if len(rwaves):
-    print(f"passed for {passed_insts} instructions across {len(rwaves)} waves scheduled on {len(rwaves_iter)} wave units")
-
-if __name__ == "__main__":
-  import argparse, pickle, pathlib
-  from tinygrad.helpers import temp, DEBUG
-  parser = argparse.ArgumentParser()
-  parser.add_argument('--profile', type=pathlib.Path, metavar="PATH", help='Path to profile (optional file, default: latest profile)',
-                      default=pathlib.Path(temp("profile.pkl", append_user=True)))
-  parser.add_argument('--kernel', type=str, default=None, metavar="NAME", help='Kernel to focus on (optional name, default: all kernels)')
-  args = parser.parse_args()
-  with open(args.profile, "rb") as f:
-    data = pickle.load(f)
-  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
-  kern_events = {e.tag:e for e in data if type(e).__name__ == "ProfileProgramEvent"}
-  target = next((e for e in data if type(e).__name__ == "ProfileDeviceEvent" and e.device.startswith("AMD"))).props["gfx_target_version"]
-  for e in sqtt_events:
-    if args.kernel is not None and args.kernel != e.kern: continue
-    if not e.itrace: continue
-    print(f"==== {e.kern}")
-    test_rocprof_inst_traces_match(e, kern_events[e.kern], target)
@@ -1,14 +1,13 @@
 #!/usr/bin/env python3
-"""Benchmark comparing Python vs Rust RDNA3 emulators on real tinygrad kernels."""
-import ctypes, time, os
+"""Benchmark comparing Python vs Rust RDNA3 emulators on synthetic and real tinygrad kernels."""
+import ctypes, time, os, struct, cProfile, pstats, io
 from pathlib import Path
+from typing import Callable

 # Set AMD=1 before importing tinygrad
 os.environ["AMD"] = "1"

-from extra.assembly.amd.emu import run_asm as python_run_asm, decode_program
-from extra.assembly.amd import decode_inst
-from extra.assembly.amd.autogen.rdna3.ins import SOPP, SOPPOp
+from extra.assembly.amd.emu import run_asm as python_run_asm, set_valid_mem_ranges, decode_program, step_wave, WaveState, WAVE_SIZE

 REMU_PATH = Path(__file__).parents[3] / "remu/target/release/libremu.so"
 if not REMU_PATH.exists():
@@ -43,7 +42,7 @@ def setup_buffers(buf_sizes: list[int], init_data: dict[int, bytes] | None = Non
  ranges.add((args_ptr, ctypes.sizeof(args)))
  return buffers, args, args_ptr, ranges

-def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size, args_ptr, rsrc2: int, iterations: int = 5):
+def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size, args_ptr, iterations: int = 5):
  """Benchmark an emulator and return average time."""
  gx, gy, gz = global_size
  lx, ly, lz = local_size
@@ -51,13 +50,13 @@ def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size
  lib_ptr = ctypes.addressof(kernel_buf)

  # Warmup
-  run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr, rsrc2)
+  run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr)

  # Timed runs
  times = []
  for _ in range(iterations):
    start = time.perf_counter()
-    result = run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr, rsrc2)
+    result = run_fn(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr)
    end = time.perf_counter()
    if result != 0:
      print(f"  {name} returned error: {result}")
@@ -66,61 +65,27 @@ def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size

  return sum(times) / len(times)

-def profile_instructions(kernel: bytes):
-  """Profile individual instruction compile times."""
-  from extra.assembly.amd.emu import _get_runner, _canonical_runner_cache
-  from tinygrad.helpers import Context
-  _get_runner.cache_clear()
-  _canonical_runner_cache.clear()
+def create_synthetic_kernel(n_ops: int) -> bytes:
+  """Create a synthetic kernel with n_ops vector operations."""
+  instructions = []
+  # VOP2 instructions: v_add_f32, v_mul_f32, v_max_f32, v_min_f32
+  ops = [
+    (0b0000011 << 25) | (1 << 17) | (0 << 9) | 256,  # v_add_f32 v0, v0, v1
+    (0b0001000 << 25) | (1 << 17) | (0 << 9) | 256,  # v_mul_f32 v0, v0, v1
+    (0b0010000 << 25) | (1 << 17) | (0 << 9) | 256,  # v_max_f32 v0, v0, v1
+    (0b0001111 << 25) | (1 << 17) | (0 << 9) | 256,  # v_min_f32 v0, v0, v1
+  ]
+  for i in range(n_ops):
+    instructions.append(ops[i % len(ops)])
+  # S_ENDPGM
+  instructions.append((0b101111111 << 23) | (48 << 16) | 0)
+  return b''.join(struct.pack('<I', inst) for inst in instructions)

-  results = []
-  i = 0
-  while i < len(kernel):
-    inst = decode_inst(kernel[i:])
-    if isinstance(inst, SOPP) and inst.op == SOPPOp.S_CODE_END: break
-    inst_bytes = bytes(kernel[i:i + inst.size() + 4])
-    try: inst_str = repr(inst)
-    except Exception: inst_str = f"<{type(inst).__name__}>"
-
-    # Time the full compile (sink + render + compile)
-    start = time.perf_counter()
-    with Context(CCACHE=0):
-      runner, is_new = _get_runner(inst_bytes)
-    compile_time = time.perf_counter() - start
-
-    results.append({
-      'inst_str': inst_str + ('' if is_new else ' [CACHED]'),
-      'compile_ms': compile_time * 1000 if is_new else 0,
-    })
-    i += inst.size()
-
-  return sorted(results, key=lambda x: x['compile_ms'], reverse=True)
-
-def benchmark_python_split(kernel: bytes, global_size, local_size, args_ptr, rsrc2: int, iterations: int = 5):
-  """Benchmark Python emulator with compile and execution times."""
-  from extra.assembly.amd.emu import _get_runner, _canonical_runner_cache
-  from tinygrad.helpers import Context
-  _get_runner.cache_clear()
-  _canonical_runner_cache.clear()
-  decode_program.cache_clear()
-
-  # Measure compile time (decode_program builds sinks, renders, and compiles)
-  compile_start = time.perf_counter()
-  with Context(CCACHE=0):
-    program = decode_program(kernel)
-  compile_time = time.perf_counter() - compile_start
-  n_compiled = len(_canonical_runner_cache)
-
-  # Execution time
-  exec_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, rsrc2, iterations)
-  return compile_time, exec_time, len(program), n_compiled
-
-def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], dict[int, bytes], int] | None:
-  """Get a real tinygrad kernel by operation name. Returns (code, global_size, local_size, buf_sizes, buf_data, rsrc2)."""
+def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], dict[int, bytes]] | None:
+  """Get a real tinygrad kernel by operation name. Returns (code, global_size, local_size, buf_sizes, buf_data)."""
  try:
    from tinygrad import Tensor
    from tinygrad.runtime.support.elf import elf_loader
-    from tinygrad.runtime.autogen import hsa
    import numpy as np
    np.random.seed(42)

@@ -147,9 +112,7 @@ def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], d
      lowered = ei.lower()
      if ei.ast.op.name == 'SINK' and lowered.prg and lowered.prg.p.lib:
        lib = bytes(lowered.prg.p.lib)
-        image = memoryview(bytearray(lib))
        _, sections, _ = elf_loader(lib)
-        rodata_entry = next((sh.header.sh_addr for sh in sections if sh.name == ".rodata"), -1)
        for sec in sections:
          if sec.name == '.text':
            buf_sizes = [b.nbytes for b in lowered.bufs]
@@ -159,47 +122,70 @@ def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], d
              if hasattr(buf, 'base') and buf.base is not None and hasattr(buf.base, '_buf'):
                try: buf_data[i] = bytes(buf.base._buf)
                except: pass
-            # Extract rsrc2 from ELF (same as ops_amd.py)
-            group_segment_size = image[rodata_entry:rodata_entry+4].cast("I")[0]
-            lds_size = ((group_segment_size + 511) // 512) & 0x1FF
-            code = hsa.amd_kernel_code_t.from_buffer_copy(bytes(image[rodata_entry:rodata_entry+256]) + b'\x00'*256)
-            rsrc2 = code.compute_pgm_rsrc2 | (lds_size << 15)
-            return (bytes(sec.content), tuple(lowered.prg.p.global_size), tuple(lowered.prg.p.local_size), buf_sizes, buf_data, rsrc2)
+            return (bytes(sec.content), tuple(lowered.prg.p.global_size), tuple(lowered.prg.p.local_size), buf_sizes, buf_data)
    return None
  except Exception as e:
    print(f"  Error getting kernel: {e}")
    return None

-TINYGRAD_TESTS = ["add", "mul", "reduce_sum", "softmax", "exp", "sin", "gelu", "matmul_small"]
+def profile_python_emu(kernel: bytes, global_size, local_size, args_ptr, n_runs: int = 1):
+  """Profile the Python emulator to find bottlenecks."""
+  gx, gy, gz = global_size
+  lx, ly, lz = local_size
+  kernel_buf = (ctypes.c_char * len(kernel)).from_buffer_copy(kernel)
+  lib_ptr = ctypes.addressof(kernel_buf)
+
+  pr = cProfile.Profile()
+  pr.enable()
+  for _ in range(n_runs):
+    python_run_asm(lib_ptr, len(kernel), gx, gy, gz, lx, ly, lz, args_ptr)
+  pr.disable()
+
+  s = io.StringIO()
+  ps = pstats.Stats(pr, stream=s).sort_stats('cumulative')
+  ps.print_stats(20)
+  return s.getvalue()
+
+def measure_step_rate(kernel: bytes, n_steps: int = 10000) -> float:
+  """Measure raw step_wave() performance (steps per second)."""
+  program = decode_program(kernel)
+  if not program: return 0.0
+
+  st = WaveState()
+  st.exec_mask = 0xffffffff
+  lds = bytearray(65536)
+  n_lanes = 32
+
+  # Reset PC for each measurement
+  start = time.perf_counter()
+  for _ in range(n_steps):
+    st.pc = 0
+    while st.pc in program:
+      result = step_wave(program, st, lds, n_lanes)
+      if result == -1: break
+  elapsed = time.perf_counter() - start
+  return n_steps / elapsed if elapsed > 0 else 0
+
+# Test configurations
+SYNTHETIC_TESTS = [
+  ("synthetic_10ops", 10, (1, 1, 1), (32, 1, 1)),
+  ("synthetic_100ops", 100, (1, 1, 1), (32, 1, 1)),
+  ("synthetic_500ops", 500, (1, 1, 1), (32, 1, 1)),
+  ("synthetic_100ops_4wg", 100, (4, 1, 1), (32, 1, 1)),
+  ("synthetic_100ops_16wg", 100, (16, 1, 1), (32, 1, 1)),
+]
+
+TINYGRAD_TESTS = ["add", "mul", "reduce_sum", "softmax", "exp", "gelu", "matmul_small"]

 def main():
  import argparse
  parser = argparse.ArgumentParser(description="Benchmark RDNA3 emulators")
+  parser.add_argument("--profile", action="store_true", help="Profile Python emulator")
+  parser.add_argument("--synthetic-only", action="store_true", help="Only run synthetic tests")
+  parser.add_argument("--tinygrad-only", action="store_true", help="Only run tinygrad tests")
  parser.add_argument("--iterations", type=int, default=3, help="Number of iterations per benchmark")
-  parser.add_argument("--profile", type=str, default=None, help="Profile instructions for a specific kernel (e.g. 'sin')")
-  parser.add_argument("--top", type=int, default=20, help="Number of top instructions to show in profile")
  args = parser.parse_args()

-  # Profile mode: show individual instruction timing
-  if args.profile:
-    kernel_info = get_tinygrad_kernel(args.profile)
-    if kernel_info is None:
-      print(f"Failed to get kernel for '{args.profile}'")
-      return
-    kernel = kernel_info[0]
-    print(f"Profiling instructions for '{args.profile}' kernel...")
-    print("=" * 110)
-    results = profile_instructions(kernel)
-    print(f"{'Instruction':<90} {'Compile(ms)':>12}")
-    print("-" * 110)
-    for r in results[:args.top]:
-      inst = r['inst_str'][:87] + "..." if len(r['inst_str']) > 90 else r['inst_str']
-      print(f"{inst:<90} {r['compile_ms']:>12.3f}")
-    print("-" * 110)
-    total = sum(r['compile_ms'] for r in results)
-    print(f"{'TOTAL':<90} {total:>12.3f}")
-    return
-
  rust_remu = get_rust_remu()
  if rust_remu is None:
    print("Rust libremu not found. Build with: cargo build --release --manifest-path extra/remu/Cargo.toml")
@@ -211,56 +197,98 @@ def main():

  results = []

-  print("\n[TINYGRAD KERNELS]")
-  print("-" * 90)
+  # Synthetic workloads
+  if not args.tinygrad_only:
+    print("\n[SYNTHETIC WORKLOADS]")
+    print("-" * 90)

-  for op_name in TINYGRAD_TESTS:
-    print(f"\n{op_name}:", end=" ", flush=True)
-    kernel_info = get_tinygrad_kernel(op_name)
-    if kernel_info is None:
-      print("failed to compile")
-      continue
+    for name, n_ops, global_size, local_size in SYNTHETIC_TESTS:
+      kernel = create_synthetic_kernel(n_ops)
+      n_insts = count_instructions(kernel)
+      n_workgroups = global_size[0] * global_size[1] * global_size[2]
+      n_threads = local_size[0] * local_size[1] * local_size[2]
+      total_work = n_insts * n_workgroups * n_threads

-    kernel, global_size, local_size, buf_sizes, buf_data, rsrc2 = kernel_info
-    buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes, buf_data)
+      print(f"\n{name}: {n_insts} insts × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")

-    # Benchmark Python emulator (must be first to measure compile time before cache is populated)
-    py_compile, py_exec, n_insts, n_compiled = benchmark_python_split(kernel, global_size, local_size, args_ptr, rsrc2, args.iterations)
+      buf_sizes = [4096]
+      buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes)
+      set_valid_mem_ranges(ranges)

-    n_workgroups = global_size[0] * global_size[1] * global_size[2]
-    n_threads = local_size[0] * local_size[1] * local_size[2]
-    total_work = n_insts * n_workgroups * n_threads
+      # Benchmark
+      py_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, args.iterations)
+      rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, args.iterations) if rust_remu else None

-    print(f"{n_insts} insts ({n_compiled} unique) × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")
-    rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, rsrc2, args.iterations) if rust_remu else None
+      if py_time:
+        py_rate = total_work / py_time / 1e6
+        print(f"  Python: {py_time*1000:8.3f} ms  ({py_rate:7.2f} M ops/s)")
+      if rust_time:
+        rust_rate = total_work / rust_time / 1e6
+        speedup = py_time / rust_time if py_time else 0
+        print(f"  Rust:   {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")

-    if py_compile is not None:
-      py_exec_rate = total_work / py_exec / 1e6
-      print(f"  Compile:        {py_compile*1000:8.3f} ms  ({n_compiled} unique)")
-      print(f"  Exec:           {py_exec*1000:8.3f} ms  ({py_exec_rate:7.2f} M ops/s)")
-    if rust_time:
-      rust_rate = total_work / rust_time / 1e6
-      speedup = py_exec / rust_time if py_exec else 0
-      print(f"  Rust:           {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")
+      results.append(("synthetic", name, n_insts, n_workgroups, py_time, rust_time))

-    results.append((op_name, n_insts, n_compiled, n_workgroups, py_compile, py_exec, rust_time))
+  # Tinygrad kernels
+  if not args.synthetic_only:
+    print("\n[TINYGRAD KERNELS]")
+    print("-" * 90)
+
+    for op_name in TINYGRAD_TESTS:
+      print(f"\n{op_name}:", end=" ", flush=True)
+      kernel_info = get_tinygrad_kernel(op_name)
+      if kernel_info is None:
+        print("failed to compile")
+        continue
+
+      kernel, global_size, local_size, buf_sizes, buf_data = kernel_info
+      n_insts = count_instructions(kernel)
+      n_workgroups = global_size[0] * global_size[1] * global_size[2]
+      n_threads = local_size[0] * local_size[1] * local_size[2]
+      total_work = n_insts * n_workgroups * n_threads
+
+      print(f"{n_insts} insts × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")
+
+      buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes, buf_data)
+      set_valid_mem_ranges(ranges)
+
+      py_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, args.iterations)
+      rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, args.iterations) if rust_remu else None
+
+      if py_time:
+        py_rate = total_work / py_time / 1e6
+        print(f"  Python: {py_time*1000:8.3f} ms  ({py_rate:7.2f} M ops/s)")
+      if rust_time:
+        rust_rate = total_work / rust_time / 1e6
+        speedup = py_time / rust_time if py_time else 0
+        print(f"  Rust:   {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")
+
+      results.append(("tinygrad", op_name, n_insts, n_workgroups, py_time, rust_time))
+
+      # Optional profiling
+      if args.profile and py_time:
+        print("\n  [PROFILE - Top 10 functions]")
+        profile_output = profile_python_emu(kernel, global_size, local_size, args_ptr)
+        for line in profile_output.split('\n')[5:15]:
+          if line.strip(): print(f"    {line}")

  # Summary table
-  print("\n" + "=" * 110)
+  print("\n" + "=" * 90)
  print("SUMMARY")
-  print("=" * 110)
-  print(f"{'Name':<16} {'Insts':<6} {'Unique':<6} {'WGs':<5} {'Compile (ms)':<14} {'Exec (ms)':<12} {'Rust (ms)':<12} {'Speedup':<10}")
-  print("-" * 110)
+  print("=" * 90)
+  print(f"{'Type':<10} {'Name':<25} {'Insts':<8} {'WGs':<6} {'Python (ms)':<14} {'Rust (ms)':<14} {'Speedup':<10}")
+  print("-" * 90)

-  for name, n_insts, n_compiled, n_wgs, py_compile, py_exec, rust_time in results:
-    compile_ms = f"{py_compile*1000:.3f}" if py_compile else "error"
-    exec_ms = f"{py_exec*1000:.3f}" if py_exec else "error"
+  for test_type, name, n_insts, n_wgs, py_time, rust_time in results:
+    py_ms = f"{py_time*1000:.3f}" if py_time else "error"
    if rust_time:
      rust_ms = f"{rust_time*1000:.3f}"
-      speedup = f"{py_exec/rust_time:.1f}x" if py_exec else "N/A"
+      speedup = f"{py_time/rust_time:.1f}x" if py_time else "N/A"
    else:
      rust_ms, speedup = "N/A", "N/A"
-    print(f"{name:<16} {n_insts:<6} {n_compiled:<6} {n_wgs:<5} {compile_ms:<14} {exec_ms:<12} {rust_ms:<12} {speedup:<10}")
+    print(f"{test_type:<10} {name:<25} {n_insts:<8} {n_wgs:<6} {py_ms:<14} {rust_ms:<14} {speedup:<10}")
+
+

 if __name__ == "__main__":
  main()
@@ -0,0 +1,196 @@
+# Usability tests for the RDNA3 ASM DSL
+# These tests demonstrate how the DSL *should* work for a good user experience
+# Currently many of these tests fail - they document desired behavior
+
+import unittest
+from extra.assembly.amd.autogen.rdna3.ins import *
+from extra.assembly.amd.dsl import Inst, RawImm, SGPR, VGPR
+
+class TestRegisterSliceSyntax(unittest.TestCase):
+  """
+  Issue: Register slice syntax should use AMD assembly convention (inclusive end).
+
+  In AMD assembly, s[4:7] means registers s4, s5, s6, s7 (4 registers, inclusive).
+  The DSL should match this convention so that:
+  - s[4:7] gives 4 registers
+  - Disassembler output can be copied directly back into DSL code
+
+  Fix: Change _RegFactory.__getitem__ to use inclusive end:
+    key.stop - key.start + 1  (instead of key.stop - key.start)
+  """
+  def test_register_slice_count(self):
+    # s[4:7] should give 4 registers: s4, s5, s6, s7 (AMD convention, inclusive)
+    reg = s[4:7]
+    self.assertEqual(reg.count, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")
+
+  def test_register_slice_roundtrip(self):
+    # Round-trip: DSL -> disasm -> DSL should preserve register count
+    reg = s[4:7]  # 4 registers in AMD convention
+    inst = s_load_b128(reg, s[0:1], NULL, 0)
+    disasm = inst.disasm()
+    # Disasm shows s[4:7] - user should be able to copy this back
+    self.assertIn("s[4:7]", disasm)
+    # And s[4:7] in DSL should give the same 4 registers
+    reg_from_disasm = s[4:7]
+    self.assertEqual(reg_from_disasm.count, 4, "s[4:7] from disasm should give 4 registers")
+
+
+class TestReprReadability(unittest.TestCase):
+  """
+  Issue: repr() leaks internal RawImm type and omits zero-valued fields.
+
+  When you create v_mov_b32_e32(v[0], v[1]), the repr shows:
+    VOP1(op=1, src0=RawImm(257))
+
+  Problems:
+  1. vdst=v[0] is omitted because 0 is treated as "default"
+  2. src0 shows RawImm(257) instead of v[1]
+  3. User sees encoded values (257 = 256 + 1) instead of register names
+
+  Expected repr: VOP1(op=1, vdst=v[0], src0=v[1])
+  """
+  def test_repr_shows_registers_not_raw_imm(self):
+    inst = v_mov_b32_e32(v[0], v[1])
+    # Should show v[1], not RawImm(257)
+    self.assertNotIn("RawImm", repr(inst), "repr should not expose RawImm internal type")
+    self.assertIn("v[1]", repr(inst), "repr should show register name")
+
+  def test_repr_includes_zero_dst(self):
+    inst = v_mov_b32_e32(v[0], v[1])
+    # v[0] is a valid destination register, should be shown
+    self.assertIn("vdst", repr(inst), "repr should include vdst even when 0")
+
+  def test_repr_roundtrip(self):
+    # repr should produce something that can be eval'd back
+    inst = v_mov_b32_e32(v[0], v[1])
+    # This would require repr to output valid Python, e.g.:
+    # "VOP1(op=VOP1Op.V_MOV_B32, vdst=v[0], src0=v[1])"
+    r = repr(inst)
+    # At minimum, it should be human-readable
+    self.assertIn("v[", r, "repr should show register syntax")
+
+
+class TestInstructionEquality(unittest.TestCase):
+  """
+  Issue: No __eq__ method - instruction comparison requires repr() workaround.
+
+  Two identical instructions should compare equal with ==, but currently:
+    inst1 == inst2 returns False
+
+  The test_handwritten.py works around this with:
+    self.assertEqual(repr(self.inst), repr(reasm))
+  """
+  def test_identical_instructions_equal(self):
+    inst1 = v_mov_b32_e32(v[0], v[1])
+    inst2 = v_mov_b32_e32(v[0], v[1])
+    self.assertEqual(inst1, inst2, "identical instructions should be equal")
+
+  def test_different_instructions_not_equal(self):
+    inst1 = v_mov_b32_e32(v[0], v[1])
+    inst2 = v_mov_b32_e32(v[0], v[2])
+    self.assertNotEqual(inst1, inst2, "different instructions should not be equal")
+
+
+class TestVOPDHelperSignature(unittest.TestCase):
+  """
+  Issue: VOPD helper functions have confusing semantics.
+
+  v_dual_mul_f32 is defined as:
+    v_dual_mul_f32 = functools.partial(VOPD, VOPDOp.V_DUAL_MUL_F32)
+
+  This binds VOPDOp.V_DUAL_MUL_F32 to the FIRST positional arg of VOPD.__init__,
+  which is 'opx'. So v_dual_mul_f32 sets the X operation.
+
+  But then test_dual_mul in test_handwritten.py does:
+    v_dual_mul_f32(VOPDOp.V_DUAL_MUL_F32, vdstx=v[0], ...)
+
+  This passes V_DUAL_MUL_F32 as the SECOND positional arg (opy), making both
+  X and Y operations the same. This is confusing because:
+  1. The function name suggests it handles the X operation
+  2. But you still pass an opcode as the first arg (which becomes opy)
+
+  Expected: Either make the helper fully specify both ops, or make the
+  signature clearer about what the positional arg means.
+  """
+  def test_vopd_helper_opy_should_be_required(self):
+    # Using only keyword args "works" but opy silently defaults to 0
+    inst = v_dual_mul_f32(vdstx=v[0], vdsty=v[1], srcx0=v[2], vsrcx1=v[3], srcy0=v[4], vsrcy1=v[5])
+    self.assertEqual(inst.opx, VOPDOp.V_DUAL_MUL_F32)
+    # Bug: opy defaults to 0 (V_DUAL_FMAC_F32) silently - should require explicit opy
+    # This test documents the bug - it should fail once fixed
+    self.assertNotEqual(inst.opy, VOPDOp.V_DUAL_FMAC_F32, "opy should not silently default to FMAC")
+
+  def test_vopd_helper_positional_arg_is_opy(self):
+    # The first positional arg after the partial becomes opy, not a second opx
+    inst = v_dual_mul_f32(VOPDOp.V_DUAL_MOV_B32, vdstx=v[0], vdsty=v[1], srcx0=v[2], vsrcx1=v[3], srcy0=v[4], vsrcy1=v[5])
+    self.assertEqual(inst.opx, VOPDOp.V_DUAL_MUL_F32)  # From partial
+    self.assertEqual(inst.opy, VOPDOp.V_DUAL_MOV_B32)  # From first positional arg
+
+
+class TestFieldAccessPreservesType(unittest.TestCase):
+  """
+  Issue: Field access loses type information.
+
+  After creating an instruction, accessing fields returns encoded int values:
+    inst = v_mov_b32_e32(v[0], v[1])
+    inst.vdst  # returns 0, not VGPR(0)
+
+  This makes it impossible to round-trip register types through field access.
+  """
+  def test_vdst_returns_register(self):
+    inst = v_mov_b32_e32(v[5], v[1])
+    vdst = inst.vdst
+    # Should return a VGPR, not an int
+    self.assertIsInstance(vdst, (VGPR, int), "vdst should return VGPR or at least be usable")
+    # Ideally: self.assertIsInstance(vdst, VGPR)
+
+  def test_src_returns_register_for_vgpr_source(self):
+    inst = v_mov_b32_e32(v[0], v[1])
+    # src0 is encoded as 257 (256 + 1 for v1)
+    # Ideally it should decode back to v[1]
+    src0_raw = inst._values.get('src0')
+    # Currently returns RawImm(257), should return VGPR(1) or similar
+    self.assertNotIsInstance(src0_raw, RawImm, "source should not be RawImm internally")
+
+
+class TestArgumentDiscoverability(unittest.TestCase):
+  """
+  Issue: No clear signature for positional arguments.
+
+  inspect.signature(s_load_b128) shows: (*args, literal=None, **kwargs)
+
+  Users have no way to know the argument order without reading source code.
+  The order is implicitly defined by the class field definition order.
+
+  Possible fixes:
+  1. Add explicit parameter names to functools.partial
+  2. Generate type stubs with proper signatures
+  3. Add docstrings listing the expected arguments
+  """
+  def test_signature_has_named_params(self):
+    import inspect
+    sig = inspect.signature(s_load_b128)
+    params = list(sig.parameters.keys())
+    # Currently: ['args', 'literal', 'kwargs'] (from *args, literal=None, **kwargs)
+    # Expected: something like ['sdata', 'sbase', 'soffset', 'offset', 'literal']
+    self.assertIn('sdata', params, "signature should show field names")
+
+
+class TestSpecialConstants(unittest.TestCase):
+  """
+  Issue: NULL and other constants are IntEnum values that might be confusing.
+
+  NULL = SrcEnum.NULL = 124, but users might expect NULL to be a special object
+  that clearly represents "no register" rather than a magic number.
+  """
+  def test_null_has_clear_repr(self):
+    # NULL should have a clear string representation
+    self.assertIn("NULL", str(NULL) or repr(NULL), "NULL should be clearly identifiable")
+
+  def test_null_is_distinguishable_from_int(self):
+    # NULL should be distinguishable from the raw integer 124
+    self.assertNotEqual(type(NULL), int, "NULL should not be plain int")
+
+
+if __name__ == "__main__":
+  unittest.main()
@@ -5,7 +5,6 @@ from dataclasses import dataclass
@dataclass
 class KernelInfo:
  code: bytes
-  src: str
  global_size: tuple[int, int, int]
  local_size: tuple[int, int, int]
  buf_idxs: list[int]  # indices into shared buffer pool
@@ -24,15 +23,44 @@ def get_llvm_objdump():
    if shutil.which(p): return p
  raise FileNotFoundError("llvm-objdump not found")

-ARCH_TO_TARGET:dict[str, list[str]] = {
-  "rdna3":["gfx1100"],
-  "rdna4":["gfx1200"],
-  "cdna":["gfx950", "gfx942"],
-}
+# ═══════════════════════════════════════════════════════════════════════════════
+# EXECUTION CONTEXT (for testing compiled pseudocode)
+# ═══════════════════════════════════════════════════════════════════════════════

-TARGET_TO_ARCH:dict[str, str] = {t:arch for arch,targets in ARCH_TO_TARGET.items() for t in targets}
+class ExecContext:
+  """Context for running compiled pseudocode in tests."""
+  def __init__(self, s0=0, s1=0, s2=0, d0=0, scc=0, vcc=0, lane=0, exec_mask=0xffffffff, literal=0, vgprs=None, src0_idx=0, vdst_idx=0):
+    from extra.assembly.amd.pcode import Reg, MASK32, MASK64, SliceProxy
+    self._Reg, self._MASK64, self._SliceProxy = Reg, MASK64, SliceProxy
+    self.S0, self.S1, self.S2 = Reg(s0), Reg(s1), Reg(s2)
+    self.D0, self.D1 = Reg(d0), Reg(0)
+    self.SCC, self.VCC, self.EXEC = Reg(scc), Reg(vcc), Reg(exec_mask)
+    self.tmp, self.saveexec = Reg(0), Reg(exec_mask)
+    self.lane, self.laneId, self.literal = lane, lane, literal
+    self.SIMM16, self.SIMM32 = Reg(literal), Reg(literal)
+    self.VGPR = vgprs if vgprs is not None else {}
+    self.SRC0, self.VDST = Reg(src0_idx), Reg(vdst_idx)

-def get_target(arch:str) -> str: return ARCH_TO_TARGET[arch][0]
+  def run(self, code: str):
+    """Execute compiled code."""
+    import extra.assembly.amd.pcode as pcode
+    ns = {k: getattr(pcode, k) for k in dir(pcode) if not k.startswith('_')}
+    # Also include underscore-prefixed helpers that compiled pseudocode uses
+    for k in ['_pack', '_pack32']:
+      if hasattr(pcode, k): ns[k] = getattr(pcode, k)
+    ns.update({
+      'S0': self.S0, 'S1': self.S1, 'S2': self.S2, 'D0': self.D0, 'D1': self.D1,
+      'SCC': self.SCC, 'VCC': self.VCC, 'EXEC': self.EXEC,
+      'EXEC_LO': self._SliceProxy(self.EXEC, 31, 0), 'EXEC_HI': self._SliceProxy(self.EXEC, 63, 32),
+      'tmp': self.tmp, 'saveexec': self.saveexec,
+      'lane': self.lane, 'laneId': self.laneId, 'literal': self.literal,
+      'SIMM16': self.SIMM16, 'SIMM32': self.SIMM32, 'VGPR': self.VGPR, 'SRC0': self.SRC0, 'VDST': self.VDST,
+    })
+    exec(code, ns)
+    def _sync(ctx_reg, ns_val):
+      if isinstance(ns_val, self._Reg): ctx_reg._val = ns_val._val
+      else: ctx_reg._val = int(ns_val) & self._MASK64
+    for name in ('SCC', 'VCC', 'EXEC', 'D0', 'D1', 'tmp', 'saveexec'):
+      if ns.get(name) is not getattr(self, name): _sync(getattr(self, name), ns[name])

-def get_mattr(arch:str) -> str:
-  return {"rdna3":"+real-true16,+wavefrontsize32", "rdna4":"+real-true16,+wavefrontsize32", "cdna":"+wavefrontsize64"}[arch]
+  def result(self) -> dict: return {"d0": self.D0._val, "scc": self.SCC._val & 1}
@@ -1 +0,0 @@
-"""Hardware-validated emulator tests for RDNA3 instructions."""
@@ -1,281 +0,0 @@
-"""Test infrastructure for hardware-validated RDNA3 emulator tests.
-
-Uses run_asm() with memory output, so tests can run on both emulator and real hardware.
-Set USE_HW=1 to run on both emulator and hardware, comparing results.
-"""
-import ctypes, math, os, struct
-from extra.assembly.amd.autogen.rdna3.ins import *
-
-from extra.assembly.amd.emu import run_asm
-from extra.assembly.amd.dsl import NULL, SCC, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, M0
-
-def _i32(f: float) -> int: return struct.unpack('<I', struct.pack('<f', f))[0]
-def _f32(i: int) -> float: return struct.unpack('<f', struct.pack('<I', i & 0xFFFFFFFF))[0]
-
-# f16 conversion helpers
-def f16(i: int) -> float: return struct.unpack('<e', struct.pack('<H', i & 0xFFFF))[0]
-def f32_to_f16(f: float) -> int:
-  f = float(f)
-  if math.isnan(f): return 0x7e00
-  if math.isinf(f): return 0x7c00 if f > 0 else 0xfc00
-  try: return struct.unpack('<H', struct.pack('<e', f))[0]
-  except OverflowError: return 0x7c00 if f > 0 else 0xfc00
-
-# For backwards compatibility with tests using SrcEnum.NULL etc.
-class SrcEnum:
-  NULL = NULL
-  VCC_LO = VCC_LO
-  VCC_HI = VCC_HI
-  EXEC_LO = EXEC_LO
-  EXEC_HI = EXEC_HI
-  SCC = SCC
-  M0 = M0
-  POS_HALF = 0.5
-  NEG_HALF = -0.5
-  POS_ONE = 1.0
-  NEG_ONE = -1.0
-  POS_TWO = 2.0
-  NEG_TWO = -2.0
-  POS_FOUR = 4.0
-  NEG_FOUR = -4.0
-
-VCC = VCC_LO  # For VOP3SD sdst field (VCC_LO is exported from dsl)
-USE_HW = os.environ.get("USE_HW", "0") == "1"
-FLOAT_TOLERANCE = 1e-5
-
-def get_gpu_target() -> tuple[int, int, int]:
-  """Get the GPU target as (major, minor, stepping) tuple."""
-  if not USE_HW: return (0, 0, 0)
-  from tinygrad.device import Device
-  return Device["AMD"].target
-
-def skip_unless_gfx(min_major: int, min_minor: int = 0, reason: str = ""):
-  """Skip test if GPU target is below the minimum required version."""
-  import unittest
-  def decorator(test_func):
-    if not USE_HW: return test_func
-    target = get_gpu_target()
-    if target[0] < min_major or (target[0] == min_major and target[1] < min_minor):
-      return unittest.skip(reason or f"requires gfx{min_major}{min_minor}0+")(test_func)
-    return test_func
-  return decorator
-
-# Output buffer layout: vgpr[16][32], sgpr[16], vcc, scc, exec
-N_VGPRS, N_SGPRS, WAVE_SIZE = 16, 16, 32
-VGPR_BYTES = N_VGPRS * WAVE_SIZE * 4  # 16 regs * 32 lanes * 4 bytes = 2048
-SGPR_BYTES = N_SGPRS * 4  # 16 regs * 4 bytes = 64
-OUT_BYTES = VGPR_BYTES + SGPR_BYTES + 12  # + vcc + scc + exec
-
-# Float conversion helpers
-def f2i(f: float) -> int: return _i32(f)
-def i2f(i: int) -> float: return _f32(i)
-def f2i64(f: float) -> int: return struct.unpack('<Q', struct.pack('<d', f))[0]
-def i642f(i: int) -> float: return struct.unpack('<d', struct.pack('<Q', i))[0]
-
-def assemble(instructions: list) -> bytes:
-  return b''.join(inst.to_bytes() for inst in instructions)
-
-# Simple WaveState class for test output parsing (mirrors emu.py interface for tests)
-class WaveState:
-  def __init__(self):
-    self.vgpr = [[0] * 256 for _ in range(32)]  # vgpr[lane][reg]
-    self.sgpr = [0] * 128
-    self.vcc = 0
-    self.scc = 0
-
-def get_prologue_epilogue(n_lanes: int) -> tuple[list, list]:
-  """Generate prologue and epilogue instructions for state capture."""
-  prologue = [
-    s_mov_b32(s[80], s[0]),
-    s_mov_b32(s[81], s[1]),
-    v_mov_b32_e32(v[255], v[0]),
-  ]
-  for i in range(N_VGPRS):
-    prologue.append(v_mov_b32_e32(v[i], 0))
-  for i in range(N_SGPRS):
-    prologue.append(s_mov_b32(s[i], 0))
-  prologue.append(s_mov_b32(VCC_LO, 0))
-
-  epilogue = [
-    s_mov_b32(s[90], VCC_LO),
-    s_cselect_b32(s[91], 1, 0),
-    # Save EXEC early (before we modify it for VGPR stores)
-    s_mov_b32(s[95], EXEC_LO),
-    # Restore EXEC to all active lanes for VGPR stores (test may have modified EXEC)
-    s_mov_b32(EXEC_LO, (1 << n_lanes) - 1),
-    s_load_b64(s[92:93], s[80:81], 0, soffset=NULL),
-    s_waitcnt(0),  # simm16=0 waits for all
-    v_lshlrev_b32_e32(v[240], 2, v[255]),
-  ]
-  for i in range(N_VGPRS):
-    epilogue.append(global_store_b32(addr=v[240], data=v[i], saddr=s[92:93], offset=i * WAVE_SIZE * 4))
-  epilogue.append(v_mov_b32_e32(v[241], 0))
-  epilogue.append(v_cmp_eq_u32_e32(v[255], v[241]))
-  epilogue.append(s_and_saveexec_b32(s[94], VCC_LO))
-  epilogue.append(v_mov_b32_e32(v[240], 0))
-  for i in range(N_SGPRS):
-    epilogue.append(v_mov_b32_e32(v[243], s[i]))
-    epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + i * 4))
-  epilogue.append(v_mov_b32_e32(v[243], s[90]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + SGPR_BYTES))
-  epilogue.append(v_mov_b32_e32(v[243], s[91]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + SGPR_BYTES + 4))
-  # Store EXEC (saved earlier in s[95])
-  epilogue.append(v_mov_b32_e32(v[243], s[95]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + SGPR_BYTES + 8))
-  epilogue.append(s_mov_b32(EXEC_LO, s[94]))
-  epilogue.append(s_endpgm())
-  return prologue, epilogue
-
-def parse_output(out_buf: bytes, n_lanes: int) -> WaveState:
-  """Parse output buffer into WaveState."""
-  st = WaveState()
-  for i in range(N_VGPRS):
-    for lane in range(n_lanes):
-      off = i * WAVE_SIZE * 4 + lane * 4
-      st.vgpr[lane][i] = struct.unpack_from('<I', out_buf, off)[0]
-  for i in range(N_SGPRS):
-    st.sgpr[i] = struct.unpack_from('<I', out_buf, VGPR_BYTES + i * 4)[0]
-  st.vcc = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES)[0]
-  st.scc = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES + 4)[0]
-  # Store EXEC in its proper location (index 126)
-  st.sgpr[EXEC_LO.offset] = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES + 8)[0]
-  return st
-
-def run_program_emu(instructions: list, n_lanes: int = 1) -> WaveState:
-  """Run instructions via emulator run_asm, dump state to memory, return WaveState."""
-  out_buf = (ctypes.c_uint8 * OUT_BYTES)(*([0] * OUT_BYTES))
-  out_addr = ctypes.addressof(out_buf)
-
-  prologue, epilogue = get_prologue_epilogue(n_lanes)
-  code = assemble(prologue + instructions + epilogue)
-
-  args = (ctypes.c_uint64 * 1)(out_addr)
-  args_ptr = ctypes.addressof(args)
-  kernel_buf = (ctypes.c_char * len(code)).from_buffer_copy(code)
-  lib_ptr = ctypes.addressof(kernel_buf)
-
-  # rsrc2: USER_SGPR_COUNT=2, ENABLE_SGPR_WORKGROUP_ID_X/Y/Z=1, LDS_SIZE=128 (64KB)
-  rsrc2 = 0x19c | (128 << 15)
-  scratch_size = 0x10000  # 64KB per lane, matches .amdhsa_private_segment_fixed_size in run_program_hw
-  result = run_asm(lib_ptr, len(code), 1, 1, 1, n_lanes, 1, 1, args_ptr, rsrc2, scratch_size)
-  assert result == 0, f"run_asm failed with {result}"
-
-  return parse_output(bytes(out_buf), n_lanes)
-
-def run_program_hw(instructions: list, n_lanes: int = 1) -> WaveState:
-  """Run instructions on real AMD hardware via HIPCompiler and AMDProgram."""
-  from tinygrad.device import Device
-  from tinygrad.runtime.ops_amd import AMDProgram
-  from tinygrad.runtime.support.compiler_amd import HIPCompiler
-  from tinygrad.helpers import flat_mv
-
-  dev = Device["AMD"]
-  compiler = HIPCompiler(dev.arch)
-
-  prologue, epilogue = get_prologue_epilogue(n_lanes)
-  code = assemble(prologue + instructions + epilogue)
-
-  byte_str = ', '.join(f'0x{b:02x}' for b in code)
-  asm_src = f""".text
-.globl test
-.p2align 8
-.type test,@function
-test:
-.byte {byte_str}
-
-.rodata
-.p2align 6
-.amdhsa_kernel test
-  .amdhsa_next_free_vgpr 256
-  .amdhsa_next_free_sgpr 96
-  .amdhsa_wavefront_size32 1
-  .amdhsa_user_sgpr_kernarg_segment_ptr 1
-  .amdhsa_kernarg_size 8
-  .amdhsa_group_segment_fixed_size 65536
-  .amdhsa_private_segment_fixed_size 65536
-  .amdhsa_enable_private_segment 1
-.end_amdhsa_kernel
-
-.amdgpu_metadata
---
-amdhsa.version:
-  - 1
-  - 0
-amdhsa.kernels:
-  - .name: test
-    .symbol: test.kd
-    .kernarg_segment_size: 8
-    .group_segment_fixed_size: 65536
-    .private_segment_fixed_size: 65536
-    .kernarg_segment_align: 8
-    .wavefront_size: 32
-    .sgpr_count: 96
-    .vgpr_count: 256
-    .max_flat_workgroup_size: 1024
-...
-.end_amdgpu_metadata
-"""
-
-  lib = compiler.compile(asm_src)
-  prg = AMDProgram(dev, "test", lib)
-
-  out_gpu = dev.allocator.alloc(OUT_BYTES)
-  assert out_gpu.va_addr % 16 == 0, f"buffer not 16-byte aligned: 0x{out_gpu.va_addr:x}"
-  prg(out_gpu, global_size=(1, 1, 1), local_size=(n_lanes, 1, 1), wait=True)
-
-  out_buf = bytearray(OUT_BYTES)
-  dev.allocator._copyout(flat_mv(memoryview(out_buf)), out_gpu)
-
-  return parse_output(bytes(out_buf), n_lanes)
-
-def compare_wave_states(emu_st: WaveState, hw_st: WaveState, n_lanes: int, n_vgprs: int = N_VGPRS, ulp_tolerance: int = 0) -> list[str]:
-  """Compare two WaveStates and return list of differences.
-
-  Args:
-    ulp_tolerance: Allow up to this many ULPs difference for float comparisons (0 = exact match required)
-  """
-  import math
-  diffs = []
-  for i in range(n_vgprs):
-    for lane in range(n_lanes):
-      emu_val = emu_st.vgpr[lane][i]
-      hw_val = hw_st.vgpr[lane][i]
-      if emu_val != hw_val:
-        emu_f, hw_f = _f32(emu_val), _f32(hw_val)
-        if math.isnan(emu_f) and math.isnan(hw_f):
-          continue
-        # Check ULP difference for floats (only for same-sign values)
-        if ulp_tolerance > 0 and (emu_val < 0x80000000) == (hw_val < 0x80000000):
-          ulp_diff = abs(int(emu_val) - int(hw_val))
-          if ulp_diff <= ulp_tolerance:
-            continue
-        diffs.append(f"v[{i}] lane {lane}: emu=0x{emu_val:08x} ({emu_f:.6g}) hw=0x{hw_val:08x} ({hw_f:.6g})")
-  for i in range(N_SGPRS):
-    emu_val = emu_st.sgpr[i]
-    hw_val = hw_st.sgpr[i]
-    if emu_val != hw_val:
-      diffs.append(f"s[{i}]: emu=0x{emu_val:08x} hw=0x{hw_val:08x}")
-  if emu_st.vcc != hw_st.vcc:
-    diffs.append(f"vcc: emu=0x{emu_st.vcc:08x} hw=0x{hw_st.vcc:08x}")
-  if emu_st.scc != hw_st.scc:
-    diffs.append(f"scc: emu={emu_st.scc} hw={hw_st.scc}")
-  return diffs
-
-def run_program(instructions: list, n_lanes: int = 1, ulp_tolerance: int = 0) -> WaveState:
-  """Run instructions and return WaveState.
-
-  If USE_HW=1, runs on both emulator and hardware, compares results, and raises if they differ.
-  Otherwise, runs only on emulator.
-
-  Args:
-    ulp_tolerance: Allow up to this many ULPs difference for float comparisons (0 = exact match required)
-  """
-  emu_st = run_program_emu(instructions, n_lanes)
-  if USE_HW:
-    hw_st = run_program_hw(instructions, n_lanes)
-    diffs = compare_wave_states(emu_st, hw_st, n_lanes, ulp_tolerance=ulp_tolerance)
-    if diffs:
-      raise AssertionError(f"Emulator vs Hardware mismatch:\n" + "\n".join(diffs))
-    return hw_st
-  return emu_st
@@ -1,765 +0,0 @@
-"""Tests for DS instructions - data share (LDS) operations.
-
-Includes: ds_store_b32, ds_load_b32, ds_store_2addr_*, ds_load_2addr_*,
-          ds_add_*, ds_max_*, ds_min_*, ds_and_*, ds_or_*, ds_xor_*,
-          ds_inc_*, ds_dec_*, ds_cmpstore_*, ds_storexchg_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestDS2Addr(unittest.TestCase):
-  """Tests for DS_*_2ADDR instructions."""
-
-  def test_ds_store_load_2addr_b32(self):
-    """DS_STORE_2ADDR_B32 and DS_LOAD_2ADDR_B32 with offset * 4."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2:3], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB)
-
-  def test_ds_store_load_2addr_b64(self):
-    """DS_STORE_2ADDR_B64 and DS_LOAD_2ADDR_B64."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B64, addr=v[10], data0=v[0:1], data1=v[2:3], vdst=v[0], offset0=0, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4:7], offset0=0, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][6], 0x12345678)
-    self.assertEqual(st.vgpr[0][7], 0x9ABCDEF0)
-
-
-class TestDS2AddrMore(unittest.TestCase):
-  """Additional DS_*_2ADDR tests."""
-
-  def test_ds_store_load_2addr_b32_nonzero_offsets(self):
-    """DS_STORE_2ADDR_B32 with non-zero offsets (offset*4 scaling)."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0x11111111),
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x22222222),
-      v_mov_b32_e32(v[1], s[2]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=2, offset1=5),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2:3], offset0=2, offset1=5),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x11111111, "v2 should have value from offset 8 (2*4)")
-    self.assertEqual(st.vgpr[0][3], 0x22222222, "v3 should have value from offset 20 (5*4)")
-
-  def test_ds_2addr_b64_no_overlap(self):
-    """DS_LOAD_2ADDR_B64 with adjacent offsets should not overlap."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0x11111111),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_mov_b32(s[2], 0x22222222),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=4),
-      s_mov_b32(s[2], 0x33333333),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=8),
-      s_mov_b32(s[2], 0x44444444),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=12),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4:7], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should be 0x11111111")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should be 0x22222222")
-    self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should be 0x33333333")
-    self.assertEqual(st.vgpr[0][7], 0x44444444, "v7 should be 0x44444444")
-
-  def test_ds_load_2addr_b32_no_overwrite(self):
-    """DS_LOAD_2ADDR_B32 should only write 2 VGPRs."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[2]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[4], s[2]),  # Sentinel
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2:3], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF, "v4 should be untouched")
-
-  def test_ds_load_b64_no_overwrite(self):
-    """DS_LOAD_B64 should only write 2 VGPRs."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_store_b64(addr=v[10], data0=v[0:1], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0x12345678),
-      v_mov_b32_e32(v[4], s[2]),  # Sentinel
-      ds_load_b64(addr=v[10], vdst=v[2:3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][3], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][4], 0x12345678, "v4 should be untouched")
-
-
-class TestDSB96(unittest.TestCase):
-  """Tests for DS_STORE_B96 and DS_LOAD_B96 (96-bit / 3 dwords)."""
-
-  def test_ds_store_load_b96(self):
-    """DS_STORE_B96 stores 3 VGPRs, DS_LOAD_B96 loads them back."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x33333333),
-      v_mov_b32_e32(v[2], s[0]),
-      ds_store_b96(addr=v[10], data0=v[0:2]),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b96(addr=v[10], vdst=v[4:6]),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have first dword")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have second dword")
-    self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should have third dword")
-
-  def test_ds_store_b96_with_offset(self):
-    """DS_STORE_B96 with non-zero offset."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0xCCCCCCCC),
-      v_mov_b32_e32(v[2], s[0]),
-      DS(DSOp.DS_STORE_B96, addr=v[10], data0=v[0:2], offset0=12),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B96, addr=v[10], vdst=v[4:6], offset0=12),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][5], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][6], 0xCCCCCCCC)
-
-
-class TestDSB128(unittest.TestCase):
-  """Tests for DS_STORE_B128 and DS_LOAD_B128 (128-bit / 4 dwords)."""
-
-  def test_ds_store_load_b128(self):
-    """DS_STORE_B128 stores 4 VGPRs, DS_LOAD_B128 loads them back."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x33333333),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x44444444),
-      v_mov_b32_e32(v[3], s[0]),
-      ds_store_b128(addr=v[10], data0=v[0:3]),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b128(addr=v[10], vdst=v[4:7]),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have first dword")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have second dword")
-    self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should have third dword")
-    self.assertEqual(st.vgpr[0][7], 0x44444444, "v7 should have fourth dword")
-
-  def test_ds_store_b128_with_offset(self):
-    """DS_STORE_B128 with non-zero offset."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0xCCCCCCCC),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xDDDDDDDD),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_B128, addr=v[10], data0=v[0:3], offset0=16),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B128, addr=v[10], vdst=v[4:7], offset0=16),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][5], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][6], 0xCCCCCCCC)
-    self.assertEqual(st.vgpr[0][7], 0xDDDDDDDD)
-
-
-class TestDSAtomic(unittest.TestCase):
-  """Tests for DS atomic operations."""
-
-  def test_ds_max_rtn_u32(self):
-    """DS_MAX_RTN_U32: atomically store max and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_max_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100, "v2 should have old value (100)")
-    self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200")
-
-  def test_ds_min_rtn_u32(self):
-    """DS_MIN_RTN_U32: atomically store min and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_min_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 200)
-    self.assertEqual(st.vgpr[0][3], 100)
-
-  def test_ds_and_rtn_b32(self):
-    """DS_AND_RTN_B32: atomically AND and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xFF00FF00),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0xFFFF0000),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_and_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xFF00FF00)
-    self.assertEqual(st.vgpr[0][3], 0xFF000000)
-
-  def test_ds_or_rtn_b32(self):
-    """DS_OR_RTN_B32: atomically OR and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0x00FF0000),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0x000000FF),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_or_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x00FF0000)
-    self.assertEqual(st.vgpr[0][3], 0x00FF00FF)
-
-  def test_ds_xor_rtn_b32(self):
-    """DS_XOR_RTN_B32: atomically XOR and return old value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0xFFFFFFFF),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_xor_rtn_b32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0x55555555)
-
-  def test_ds_inc_rtn_u32(self):
-    """DS_INC_RTN_U32: increment with wrap."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 5),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 10),  # limit
-      v_mov_b32_e32(v[1], s[2]),
-      ds_inc_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 5)
-    self.assertEqual(st.vgpr[0][3], 6)
-
-  def test_ds_dec_rtn_u32(self):
-    """DS_DEC_RTN_U32: decrement with wrap."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 5),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 10),  # limit
-      v_mov_b32_e32(v[1], s[2]),
-      ds_dec_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 5)
-    self.assertEqual(st.vgpr[0][3], 4)
-
-  def test_ds_cmpstore_b32_match(self):
-    """DS_CMPSTORE_B32: conditional store when compare matches."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),  # new value
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[2], s[2]),  # compare = 100 (matches)
-      ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 200)
-
-  def test_ds_cmpstore_b32_no_match(self):
-    """DS_CMPSTORE_B32: no store when compare doesn't match."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),  # new value
-      s_mov_b32(s[2], 50),
-      v_mov_b32_e32(v[2], s[2]),  # compare = 50 (doesn't match)
-      ds_cmpstore_b32(addr=v[10], data0=v[1], data1=v[2], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 100)
-
-  def test_ds_max_u32_no_rtn(self):
-    """DS_MAX_U32 (no RTN): atomically store max, no return value."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 200),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_max_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][3], 200, "v3 should have max(100, 200) = 200")
-
-  def test_ds_add_u32_no_rtn_preserves_vdst(self):
-    """DS_ADD_U32 (no RTN) should NOT write to vdst."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[2]),  # sentinel
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 50),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_add_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xDEADBEEF, "v2 should preserve sentinel")
-    self.assertEqual(st.vgpr[0][3], 150, "v3 should have 100 + 50 = 150")
-
-  def test_ds_add_rtn_u32_writes_vdst(self):
-    """DS_ADD_RTN_U32 should write old value to vdst."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[2]),  # sentinel
-      s_mov_b32(s[2], 100),
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 50),
-      v_mov_b32_e32(v[1], s[2]),
-      ds_add_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100, "v2 should have old value (100)")
-    self.assertEqual(st.vgpr[0][3], 150, "v3 should have 100 + 50 = 150")
-
-  def test_ds_dec_rtn_u32_wrap(self):
-    """DS_DEC_RTN_U32: decrement wraps when value is 0 or > limit."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[2], 0),  # Start at 0
-      v_mov_b32_e32(v[0], s[2]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 10),  # limit
-      v_mov_b32_e32(v[1], s[2]),
-      ds_dec_rtn_u32(addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0, "v2 should have old value (0)")
-    # When mem == 0 or mem > limit, result = limit
-    self.assertEqual(st.vgpr[0][3], 10, "v3 should wrap to limit (10)")
-
-
-class TestDSStorexchg(unittest.TestCase):
-  """Tests for DS_STOREXCHG instructions."""
-
-  def test_ds_storexchg_rtn_b32(self):
-    """DS_STOREXCHG_RTN_B32: exchange value and return old."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      ds_store_b32(addr=v[10], data0=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STOREXCHG_RTN_B32, addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[10], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB)
-
-
-class TestDSRegisterWidth(unittest.TestCase):
-  """Regression tests: DS loads should only write correct number of VGPRs."""
-
-  def test_ds_load_b32_no_overwrite(self):
-    """DS_LOAD_B32 should only write 1 VGPR."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),  # sentinel
-      ds_store_b32(addr=v[0], data0=v[1], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      ds_load_b32(addr=v[0], vdst=v[1], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][2], 0x11111111, "v2 should be untouched")
-
-
-class TestDS2AddrStride64(unittest.TestCase):
-  """Tests for DS_*_2ADDR_STRIDE64 (offset * 256 for B32, offset * 512 for B64)."""
-
-  def test_ds_store_load_2addr_stride64_b32(self):
-    """DS_STORE_2ADDR_STRIDE64_B32: stores at ADDR + offset*256."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[2:3], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xAAAAAAAA, "v2 from addr 256")
-    self.assertEqual(st.vgpr[0][3], 0xBBBBBBBB, "v3 from addr 512")
-
-  def test_ds_store_load_2addr_stride64_b64(self):
-    """DS_STORE_2ADDR_STRIDE64_B64: stores at ADDR + offset*512."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[0]),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0:1], data1=v[2:3], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[4:7], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][6], 0x12345678)
-    self.assertEqual(st.vgpr[0][7], 0x9ABCDEF0)
-
-  def test_ds_storexchg_2addr_rtn_b32(self):
-    """DS_STOREXCHG_2ADDR_RTN_B32: exchange at two addresses."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4:5], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[6:7], offset0=0, offset1=1),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "old val 0")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "old val 1")
-    self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "new val 0")
-    self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "new val 1")
-
-
-  def test_ds_storexchg_rtn_b64(self):
-    """DS_STOREXCHG_RTN_B64: exchange 64-bit value and return old."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[0], s[0]),   # initial low
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[1], s[0]),   # initial high
-      DS(DSOp.DS_STORE_B64, addr=v[10], data0=v[0:1], vdst=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[2], s[0]),   # new low
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[3], s[0]),   # new high
-      DS(DSOp.DS_STOREXCHG_RTN_B64, addr=v[10], data0=v[2:3], vdst=v[4:5], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B64, addr=v[10], vdst=v[6:7], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF, "v4 should have old low dword")
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE, "v5 should have old high dword")
-    self.assertEqual(st.vgpr[0][6], 0x12345678, "v6 should have new low dword")
-    self.assertEqual(st.vgpr[0][7], 0x9ABCDEF0, "v7 should have new high dword")
-
-  def test_ds_store_load_2addr_stride64_b64_roundtrip(self):
-    """DS_STORE_2ADDR_STRIDE64_B64 followed by DS_LOAD_2ADDR_STRIDE64_B64 works correctly."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0:1], data1=v[0:1], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[2:5], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x11111111, "v2 should have val1 low")
-    self.assertEqual(st.vgpr[0][3], 0x22222222, "v3 should have val1 high")
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have val2 low")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have val2 high")
-
-  def test_ds_storexchg_2addr_stride64_rtn_b32(self):
-    """DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32: exchange at two addresses (offset*256)."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4:5], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[6:7], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have old value")
-    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have old value")
-    self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "v6 should have new value")
-    self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "v7 should have new value")
-
-  def test_ds_storexchg_2addr_stride64_rtn_b64_returns_old(self):
-    """DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64: returns old values correctly."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0:1], data1=v[0:1], vdst=v[0], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[6], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[7], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64, addr=v[10], data0=v[6:7], data1=v[6:7], vdst=v[8:11], offset0=1, offset1=2),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][8], 0x11111111, "v8 should have old val1 low")
-    self.assertEqual(st.vgpr[0][9], 0x22222222, "v9 should have old val1 high")
-    self.assertEqual(st.vgpr[0][10], 0x11111111, "v10 should have old val2 low")
-    self.assertEqual(st.vgpr[0][11], 0x22222222, "v11 should have old val2 high")
-
-
-class TestAtomicOrdering(unittest.TestCase):
-  """Tests for atomic operation return values and ordering."""
-
-  def test_ds_add_rtn_sequence(self):
-    """DS_ADD_RTN returns correct old values in sequence."""
-    instructions = [
-      v_mov_b32_e32(v[10], 0),
-      v_mov_b32_e32(v[0], 100),
-      DS(DSOp.DS_STORE_B32, addr=v[10], data0=v[0], vdst=v[0], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[1], 25),
-      DS(DSOp.DS_ADD_RTN_U32, addr=v[10], data0=v[1], vdst=v[2], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_ADD_RTN_U32, addr=v[10], data0=v[1], vdst=v[3], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B32, addr=v[10], vdst=v[4], offset0=0),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100, "First add should return 100")
-    self.assertEqual(st.vgpr[0][3], 125, "Second add should return 125")
-    self.assertEqual(st.vgpr[0][4], 150, "Final value should be 150")
-
-
-class TestDsPermute(unittest.TestCase):
-  """Tests for DS_PERMUTE_B32 and DS_BPERMUTE_B32 instructions."""
-
-  def test_ds_permute_b32_identity(self):
-    """DS_PERMUTE_B32 with identity permutation (lane 0 sends to lane 0)."""
-    # For simplicity, test with single lane
-    instructions = [
-      v_mov_b32_e32(v[0], 0),  # addr = 0 (lane 0)
-      v_mov_b32_e32(v[1], 0xDEADBEEF),  # data
-      ds_permute_b32(v[2], v[0], v[1]),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Lane 0 sends to lane 0, so lane 0 gets 0xDEADBEEF
-    self.assertEqual(st.vgpr[0][2], 0xDEADBEEF)
-
-  def test_ds_bpermute_b32_identity(self):
-    """DS_BPERMUTE_B32 with identity permutation (each lane reads from itself)."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),  # addr = 0 (read from lane 0)
-      v_mov_b32_e32(v[1], 0xCAFEBABE),  # data in lane 0
-      ds_bpermute_b32(v[2], v[0], v[1]),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Lane 0 reads from lane 0's v[1]
-    self.assertEqual(st.vgpr[0][2], 0xCAFEBABE)
-
-  def test_ds_permute_b32_broadcast(self):
-    """DS_PERMUTE_B32 broadcast - all lanes send to lane 0."""
-    # With 4 lanes, all sending to lane 0, highest lane wins
-    instructions = [
-      v_mov_b32_e32(v[0], 0),  # All lanes send to addr 0 (lane 0)
-      v_mov_b32_e32(v[1], 0x11111111),  # All lanes send same data
-      ds_permute_b32(v[2], v[0], v[1]),
-      s_waitcnt(lgkmcnt=0),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    # Lane 0 receives data (highest numbered active lane wins)
-    self.assertEqual(st.vgpr[0][2], 0x11111111)
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,363 +0,0 @@
-"""Tests for FLAT instructions - flat memory operations.
-
-Includes: flat_load_*, flat_store_*, flat_atomic_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestFlatAtomic(unittest.TestCase):
-  """Tests for FLAT atomic instructions."""
-
-  def _make_test(self, setup_instrs, atomic_instr, check_fn, test_offset=2000):
-    """Helper to create atomic test instructions."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ] + setup_instrs + [atomic_instr, s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    check_fn(st)
-
-  def test_flat_atomic_add_u32(self):
-    """FLAT_ATOMIC_ADD_U32 adds to memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_swap_b32(self):
-    """FLAT_ATOMIC_SWAP_B32 swaps memory value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_and_b32(self):
-    """FLAT_ATOMIC_AND_B32 ANDs with memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xFF00FF00),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xFFFF0000),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_AND_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0xFF00FF00)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_or_b32(self):
-    """FLAT_ATOMIC_OR_B32 ORs with memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0x00FF0000),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0x0000FF00),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_OR_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0x00FF0000)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_inc_u32(self):
-    """FLAT_ATOMIC_INC_U32 increments and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 10),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 100),  # threshold
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 10)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_dec_u32(self):
-    """FLAT_ATOMIC_DEC_U32 decrements and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 10),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_DEC_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 10)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_sub_u32(self):
-    """FLAT_ATOMIC_SUB_U32 subtracts from memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 30),
-      v_mov_b32_e32(v[3], s[0]),  # sub 30
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SUB_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100, "v4 should have old value (100)")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_xor_b32(self):
-    """FLAT_ATOMIC_XOR_B32 XORs with memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      v_mov_b32_e32(v[3], s[0]),  # XOR mask
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_XOR_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA, "v4 should have old value")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_min_u32(self):
-    """FLAT_ATOMIC_MIN_U32 stores min and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[3], s[0]),  # compare value (smaller)
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_MIN_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100, "v4 should have old value (100)")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_max_u32(self):
-    """FLAT_ATOMIC_MAX_U32 stores max and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[3], s[0]),  # compare value (larger)
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_MAX_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 50, "v4 should have old value (50)")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_inc_u64_returns_old_value(self):
-    """FLAT_ATOMIC_INC_U64 should return full 64-bit old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      # Store initial 64-bit value: 0xCAFEBABE_DEADBEEF
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Threshold: 0xFFFFFFFF_FFFFFFFF
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      v_mov_b32_e32(v[4], s[0]),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0xDEADBEEF, "v6 should have old value low dword")
-      self.assertEqual(st.vgpr[0][7], 0xCAFEBABE, "v7 should have old value high dword")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_add_u64(self):
-    """FLAT_ATOMIC_ADD_U64 adds 64-bit value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0x00000001),  # add 1
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x00000000),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0x11111111, "v6 should have old value low")
-      self.assertEqual(st.vgpr[0][7], 0x22222222, "v7 should have old value high")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_flat_atomic_swap_b64(self):
-    """FLAT_ATOMIC_SWAP_B64 swaps 64-bit value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0xCCCCCCCC),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0xDDDDDDDD),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "v6 should have old value low")
-      self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "v7 should have old value high")
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-
-class TestFlatLoad(unittest.TestCase):
-  """Tests for FLAT load instructions."""
-
-  def test_flat_load_b32(self):
-    """FLAT_LOAD_B32 loads 32-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B32, addr=v[0:1], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-
-  def test_flat_load_b64(self):
-    """FLAT_LOAD_B64 loads 64-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B64, addr=v[0:1], vdst=v[4:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][4], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][5], 0xCAFEBABE)
-
-  def test_flat_load_b96(self):
-    """FLAT_LOAD_B96 loads 96-bit (3 dword) value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0x33333333),
-      v_mov_b32_e32(v[4], s[0]),
-      global_store_b96(addr=v[0:1], data=v[2:4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B96, addr=v[0:1], vdst=v[5:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][5], 0x11111111)
-    self.assertEqual(st.vgpr[0][6], 0x22222222)
-    self.assertEqual(st.vgpr[0][7], 0x33333333)
-
-  def test_flat_load_b128(self):
-    """FLAT_LOAD_B128 loads 128-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0x33333333),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x44444444),
-      v_mov_b32_e32(v[5], s[0]),
-      global_store_b128(addr=v[0:1], data=v[2:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B128, addr=v[0:1], vdst=v[6:9], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][6], 0x11111111)
-    self.assertEqual(st.vgpr[0][7], 0x22222222)
-    self.assertEqual(st.vgpr[0][8], 0x33333333)
-    self.assertEqual(st.vgpr[0][9], 0x44444444)
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,679 +0,0 @@
-"""Tests for GLOBAL instructions - global memory operations.
-
-Includes: global_load_*, global_store_*, global_atomic_*, global_load_d16_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestGlobalAtomic(unittest.TestCase):
-  """Tests for GLOBAL atomic instructions."""
-
-  def _make_test(self, setup_instrs, atomic_instr, check_fn, test_offset=2000):
-    """Helper to create atomic test instructions."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ] + setup_instrs + [atomic_instr, s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    check_fn(st)
-
-  def test_global_atomic_add_u32(self):
-    """GLOBAL_ATOMIC_ADD_U32 adds to memory and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 100),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 50),
-      v_mov_b32_e32(v[3], s[0]),
-    ]
-    atomic = GLOBAL(GLOBALOp.GLOBAL_ATOMIC_ADD_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][4], 100)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-  def test_global_atomic_add_u64(self):
-    """GLOBAL_ATOMIC_ADD_U64 adds 64-bit value and returns old value."""
-    TEST_OFFSET = 2000
-    setup = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0x00000000),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[0], 0x00000001),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x00000000),
-      v_mov_b32_e32(v[5], s[0]),
-    ]
-    atomic = GLOBAL(GLOBALOp.GLOBAL_ATOMIC_ADD_U64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
-    def check(st):
-      self.assertEqual(st.vgpr[0][6], 0xFFFFFFFF)
-      self.assertEqual(st.vgpr[0][7], 0x00000000)
-    self._make_test(setup, atomic, check, TEST_OFFSET)
-
-
-class TestGlobalLoad(unittest.TestCase):
-  """Tests for GLOBAL load instructions."""
-
-  def test_global_load_b96(self):
-    """GLOBAL_LOAD_B96 loads 96-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0xCCCCCCCC),
-      v_mov_b32_e32(v[4], s[0]),
-      global_store_b96(addr=v[0:1], data=v[2:4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B96, addr=v[0:1], vdst=v[5:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][5], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][6], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][7], 0xCCCCCCCC)
-
-  def test_global_load_b128(self):
-    """GLOBAL_LOAD_B128 loads 128-bit value correctly."""
-    TEST_OFFSET = 2000
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[0], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[0]),
-      s_mov_b32(s[0], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[0]),
-      s_mov_b32(s[0], 0x12345678),
-      v_mov_b32_e32(v[4], s[0]),
-      s_mov_b32(s[0], 0x9ABCDEF0),
-      v_mov_b32_e32(v[5], s[0]),
-      global_store_b128(addr=v[0:1], data=v[2:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B128, addr=v[0:1], vdst=v[6:9], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][6], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][7], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][8], 0x12345678)
-    self.assertEqual(st.vgpr[0][9], 0x9ABCDEF0)
-
-
-class TestGlobalStore(unittest.TestCase):
-  """Tests for GLOBAL store instructions."""
-
-  def test_global_store_b8_basic(self):
-    """GLOBAL_STORE_B8 stores a single byte from VDATA[7:0]."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      # First store 0xDEADBEEF to memory
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Now store single byte 0x42 to same address (should only change byte 0)
-      v_mov_b32_e32(v[2], 0x42),
-      global_store_b8(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Read back and check
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Only byte 0 should change from 0xEF to 0x42
-    self.assertEqual(st.vgpr[0][0], 0xDEADBE42, "Only byte 0 should be modified")
-
-  def test_global_store_b8_byte1(self):
-    """GLOBAL_STORE_B8 at offset+1 stores to byte 1."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[2], 0x42),
-      global_store_b8(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+1),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEAD42EF, "Only byte 1 should be modified")
-
-  def test_global_store_b16_basic(self):
-    """GLOBAL_STORE_B16 stores a 16-bit value from VDATA[15:0]."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADCAFE, "Only lower 16 bits should be modified")
-
-  def test_global_store_b16_high_half(self):
-    """GLOBAL_STORE_B16 at offset+2 stores to high 16 bits."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+2),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xCAFEBEEF, "Only upper 16 bits should be modified")
-
-  def test_global_store_b16_byte_offset_1(self):
-    """GLOBAL_STORE_B16 at byte offset 1 stores bytes 1-2 within the same word."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDDCCBBAA),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Store 0xBEEF at byte offset 1 (bytes 1-2)
-      s_mov_b32(s[4], 0xBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+1),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Bytes 1-2 should be 0xBEEF (0xEF at byte 1, 0xBE at byte 2)
-    # Original: 0xDDCCBBAA -> bytes [AA, BB, CC, DD]
-    # After:    0xDDBEEFAA -> bytes [AA, EF, BE, DD]
-    self.assertEqual(st.vgpr[0][0], 0xDDBEEFAA, "Bytes 1-2 should be 0xBEEF")
-
-  def test_global_store_b16_cross_word_boundary(self):
-    """GLOBAL_STORE_B16 at byte offset 3 crosses word boundary (byte 3 of word N, byte 0 of word N+1)."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Initialize two consecutive words
-      s_mov_b32(s[4], 0xDDCCBBAA),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_mov_b32(s[4], 0x44332211),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      # Store 0xBEEF at byte offset 3 (crosses word boundary)
-      # Low byte (0xEF) goes to byte 3 of first word
-      # High byte (0xBE) goes to byte 0 of second word
-      s_mov_b32(s[4], 0xBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+3),
-      s_waitcnt(vmcnt=0),
-      # Load back both words
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[4], data=v[4], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      v_mov_b32_e32(v[1], v[4]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # First word: 0xDDCCBBAA -> 0xEFCCBBAA (byte 3 becomes 0xEF)
-    # Second word: 0x44332211 -> 0x443322BE (byte 0 becomes 0xBE)
-    self.assertEqual(st.vgpr[0][0], 0xEFCCBBAA, "Byte 3 of first word should be 0xEF")
-    self.assertEqual(st.vgpr[0][1], 0x443322BE, "Byte 0 of second word should be 0xBE")
-
-  def test_global_store_b64_basic(self):
-    """GLOBAL_STORE_B64 stores 8 bytes from v[n:n+1] to memory."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      s_mov_b32(s[5], 0xCAFEBABE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], s[5]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b64(addr=v[0], data=v[2:3], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B64, addr=v[0], vdst=v[4:5], data=v[4:5], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[4]),
-      v_mov_b32_e32(v[1], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][1], 0xCAFEBABE)
-
-
-class TestD16HiLoads(unittest.TestCase):
-  """Tests for D16_HI load instructions that load into high 16 bits."""
-
-  def test_global_load_d16_hi_b16_preserves_low_bits(self):
-    """GLOBAL_LOAD_D16_HI_B16 must preserve low 16 bits of destination."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000BEEF),
-      v_mov_b32_e32(v[3], s[4]),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[0:1], vdst=v[3], data=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      v_mov_b32_e32(v[1], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0xCAFEBEEF, f"Expected 0xCAFEBEEF, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_b16_data_differs_from_vdst(self):
-    """GLOBAL_LOAD_D16_HI_B16 where data field differs from vdst."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b16(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000DEAD),
-      v_mov_b32_e32(v[0], s[4]),  # data field - should NOT affect result
-      v_mov_b32_e32(v[1], 0),     # vdst - low bits should be preserved
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[1]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0xCAFE0000, f"Expected 0xCAFE0000, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_u8_data_differs_from_vdst(self):
-    """GLOBAL_LOAD_D16_HI_U8 where data field differs from vdst."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xAB),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b8(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000DEAD),
-      v_mov_b32_e32(v[4], s[4]),  # data field
-      s_mov_b32(s[4], 0x0000BEEF),
-      v_mov_b32_e32(v[5], s[4]),  # vdst
-      v_mov_b32_e32(v[3], 0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_U8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0x00ABBEEF, f"Expected 0x00ABBEEF, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_b16_same_addr_and_dst_zero_addr(self):
-    """GLOBAL_LOAD_D16_HI_B16 with same register for addr and vdst, addr value=0."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b16(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[1], 0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[1]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    self.assertEqual(result, 0xCAFE0000, f"Expected 0xCAFE0000, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_b16_tril_exact_pattern(self):
-    """Exact pattern from tril() failure: data=v0 differs from vdst=v1."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0x01010101),
-      v_mov_b32_e32(v[10], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b32(addr=v[3], data=v[10], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b32(addr=v[3], data=v[10], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      # Set v[0] to 0x0101 (simulating prior u16 load result)
-      s_mov_b32(s[4], 0x0101),
-      v_mov_b32_e32(v[0], s[4]),
-      # Set v[1] to 0
-      v_mov_b32_e32(v[1], 0),
-      # Load using v[1] as addr AND vdst, but v[0] as data
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2:3], offset=TEST_OFFSET+6),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[1]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    # Expected: hi=0x0101 (loaded), lo=0x0000 (from v1) -> 0x01010000
-    self.assertEqual(result, 0x01010000, f"Expected 0x01010000, got 0x{result:08x}")
-
-  def test_global_load_d16_hi_i8_data_differs_from_vdst(self):
-    """GLOBAL_LOAD_D16_HI_I8 where data field differs from vdst."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0x80),  # negative signed byte = -128
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], 0),
-      global_store_b8(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0x0000DEAD),
-      v_mov_b32_e32(v[4], s[4]),  # data field
-      s_mov_b32(s[4], 0x0000BEEF),
-      v_mov_b32_e32(v[5], s[4]),  # vdst
-      v_mov_b32_e32(v[3], 0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_I8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][0]
-    # 0x80 sign-extended = 0xFF80, lo=0xBEEF -> 0xFF80BEEF
-    self.assertEqual(result, 0xFF80BEEF, f"Expected 0xFF80BEEF, got 0x{result:08x}")
-
-  def test_global_store_b64_tril_pattern(self):
-    """Test the exact pattern from tril() kernel that was failing."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0x01010101),
-      v_mov_b32_e32(v[10], s[4]),
-      v_mov_b32_e32(v[11], s[4]),
-      s_mov_b32(s[4], 0x01),
-      v_mov_b32_e32(v[12], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b64(addr=v[0], data=v[10:11], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b8(addr=v[0], data=v[12], saddr=s[2:3], offset=TEST_OFFSET+8),
-      s_waitcnt(vmcnt=0),
-
-      v_mov_b32_e32(v[2], 0),
-      v_mov_b32_e32(v[1], 0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_U16, addr=v[2], vdst=v[0], data=v[0], saddr=s[2:3], offset=TEST_OFFSET+3),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2:3], offset=TEST_OFFSET+6),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[4], data=v[4], saddr=s[2:3], offset=TEST_OFFSET+8),
-      s_waitcnt(vmcnt=0),
-
-      v_and_b32_e32(v[5], 0xffff, v[0]),
-      v_lshlrev_b32_e32(v[0], 24, v[0]),
-      v_lshrrev_b32_e32(v[5], 8, v[5]),
-      v_or_b32_e32(v[0], v[3], v[0]),
-      v_or_b32_e32(v[1], v[5], v[1]),
-
-      global_store_b64(addr=v[2], data=v[0:1], saddr=s[2:3], offset=TEST_OFFSET+16),
-      s_waitcnt(vmcnt=0),
-
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B64, addr=v[2], vdst=v[6:7], data=v[6:7], saddr=s[2:3], offset=TEST_OFFSET+16),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[6]),
-      v_mov_b32_e32(v[1], v[7]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-
-    v0 = st.vgpr[0][0]
-    v1 = st.vgpr[0][1]
-    self.assertEqual(v0, 0x01000001, f"v0: expected 0x01000001, got 0x{v0:08x}")
-    self.assertEqual(v1, 0x01010001, f"v1: expected 0x01010001, got 0x{v1:08x}")
-
-    byte5 = (v1 >> 8) & 0xff
-    self.assertEqual(byte5, 0x00, f"byte5: expected 0x00, got 0x{byte5:02x}")
-
-
-class TestGlobalOffset(unittest.TestCase):
-  """Tests for GLOBAL instructions with different offsets.
-
-  These tests verify that instruction deduplication correctly handles different offset values.
-  If offset is made dynamic incorrectly, instructions with different offsets may load/store wrong data.
-  """
-
-  def test_global_load_different_offsets(self):
-    """Load from two different offsets and verify correct values."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      # Store 0xAAAAAAAA at offset 100
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=100),
-      # Store 0xBBBBBBBB at offset 200
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=200),
-      s_waitcnt(vmcnt=0),
-      # Load from offset 100 -> should get 0xAAAAAAAA
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[3], saddr=SrcEnum.NULL, offset=100),
-      # Load from offset 200 -> should get 0xBBBBBBBB
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[4], saddr=SrcEnum.NULL, offset=200),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      v_mov_b32_e32(v[1], v[4]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, f"offset 100: expected 0xAAAAAAAA, got 0x{st.vgpr[0][0]:08x}")
-    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB, f"offset 200: expected 0xBBBBBBBB, got 0x{st.vgpr[0][1]:08x}")
-
-  def test_global_store_different_offsets(self):
-    """Store to two different offsets and verify correct values."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      # Store 0x11111111 at offset 300
-      s_mov_b32(s[0], 0x11111111),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=300),
-      # Store 0x22222222 at offset 400
-      s_mov_b32(s[0], 0x22222222),
-      v_mov_b32_e32(v[3], s[0]),
-      global_store_b32(addr=v[0:1], data=v[3], saddr=SrcEnum.NULL, offset=400),
-      s_waitcnt(vmcnt=0),
-      # Load back to verify
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[4], saddr=SrcEnum.NULL, offset=300),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[5], saddr=SrcEnum.NULL, offset=400),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[4]),
-      v_mov_b32_e32(v[1], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x11111111, f"offset 300: expected 0x11111111, got 0x{st.vgpr[0][0]:08x}")
-    self.assertEqual(st.vgpr[0][1], 0x22222222, f"offset 400: expected 0x22222222, got 0x{st.vgpr[0][1]:08x}")
-
-  def test_global_negative_offset_no_saddr(self):
-    """Test negative offset without saddr (VGPR pair for address).
-    Store 0xAAAA at offset 100, 0xBBBB at offset 200.
-    Load with offset -100 from vaddr pointing to base+200 -> should get 0xAAAA (at 100).
-    Load with offset -100 from vaddr pointing to base+300 -> should get 0xBBBB (at 200)."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-      # Store 0xAAAAAAAA at offset 100, 0xBBBBBBBB at offset 200
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=100),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=200),
-      s_waitcnt(vmcnt=0),
-      # vaddr = base+200, load with offset -100 -> should get value at 100
-      s_add_u32(s[4], s[2], 200),
-      s_addc_u32(s[5], s[3], 0),
-      v_mov_b32_e32(v[4], s[4]),
-      v_mov_b32_e32(v[5], s[5]),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[4:5], vdst=v[6], saddr=SrcEnum.NULL, offset=-100),
-      # vaddr = base+300, load with offset -100 -> should get value at 200
-      s_add_u32(s[4], s[2], 300),
-      s_addc_u32(s[5], s[3], 0),
-      v_mov_b32_e32(v[4], s[4]),
-      v_mov_b32_e32(v[5], s[5]),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[4:5], vdst=v[7], saddr=SrcEnum.NULL, offset=-100),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[6]),
-      v_mov_b32_e32(v[1], v[7]),
-      v_mov_b32_e32(v[4], 0),
-      v_mov_b32_e32(v[5], 0),
-      v_mov_b32_e32(v[6], 0),
-      v_mov_b32_e32(v[7], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-      s_mov_b32(s[4], 0),
-      s_mov_b32(s[5], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, f"offset 200-100=100: expected 0xAAAAAAAA, got 0x{st.vgpr[0][0]:08x}")
-    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB, f"offset 300-100=200: expected 0xBBBBBBBB, got 0x{st.vgpr[0][1]:08x}")
-
-  def test_global_negative_offset_with_saddr(self):
-    """Test negative offset with saddr (SGPR pair for base address).
-    Store 0xAAAA at offset 100, 0xBBBB at offset 200.
-    Load with offset -100 from saddr pointing to base+200 -> should get 0xAAAA (at 100).
-    Load with offset -100 from saddr pointing to base+300 -> should get 0xBBBB (at 200)."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      # Store 0xAAAAAAAA at offset 100, 0xBBBBBBBB at offset 200
-      s_mov_b32(s[0], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=100),
-      s_mov_b32(s[0], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=200),
-      s_waitcnt(vmcnt=0),
-      # saddr = base+200, load with offset -100 -> should get value at 100
-      s_add_u32(s[4], s[2], 200),
-      s_addc_u32(s[5], s[3], 0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[6], saddr=s[4:5], offset=-100),
-      # saddr = base+300, load with offset -100 -> should get value at 200
-      s_add_u32(s[4], s[2], 300),
-      s_addc_u32(s[5], s[3], 0),
-      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[7], saddr=s[4:5], offset=-100),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[6]),
-      v_mov_b32_e32(v[1], v[7]),
-      v_mov_b32_e32(v[6], 0),
-      v_mov_b32_e32(v[7], 0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-      s_mov_b32(s[4], 0),
-      s_mov_b32(s[5], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, f"offset 200-100=100: expected 0xAAAAAAAA, got 0x{st.vgpr[0][0]:08x}")
-    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB, f"offset 300-100=200: expected 0xBBBBBBBB, got 0x{st.vgpr[0][1]:08x}")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,355 +0,0 @@
-"""Tests for SCRATCH instructions - scratch (private) memory operations.
-
-Includes: scratch_load_*, scratch_store_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestScratchStore(unittest.TestCase):
-  """Tests for SCRATCH store instructions."""
-
-  def test_scratch_store_b32_basic(self):
-    """SCRATCH_STORE_B32 stores 32-bit value to scratch memory."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      # Store via scratch
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Load back via scratch
-      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
-
-  def test_scratch_store_b64_basic(self):
-    """SCRATCH_STORE_B64 stores 64-bit value to scratch memory."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      s_mov_b32(s[5], 0xCAFEBABE),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], s[5]),
-      v_mov_b32_e32(v[0], 0),
-      scratch_store_b64(addr=v[0], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_b64(addr=v[0], vdst=v[4:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[4]),
-      v_mov_b32_e32(v[1], v[5]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][1], 0xCAFEBABE)
-
-  def test_scratch_store_b8_basic(self):
-    """SCRATCH_STORE_B8 stores single byte to scratch memory."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      # First store full word
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Store single byte
-      v_mov_b32_e32(v[2], 0x42),
-      scratch_store_b8(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Load back
-      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Only byte 0 should change from 0xEF to 0x42
-    self.assertEqual(st.vgpr[0][0], 0xDEADBE42)
-
-  def test_scratch_store_b16_basic(self):
-    """SCRATCH_STORE_B16 stores 16-bit value to scratch memory."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[0], 0),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      s_mov_b32(s[4], 0xCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b16(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADCAFE)
-
-
-class TestScratchLoad(unittest.TestCase):
-  """Tests for SCRATCH load instructions."""
-
-  def test_scratch_load_b96(self):
-    """SCRATCH_LOAD_B96 loads 96-bit value correctly."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[4]),
-      s_mov_b32(s[4], 0xBBBBBBBB),
-      v_mov_b32_e32(v[3], s[4]),
-      s_mov_b32(s[4], 0xCCCCCCCC),
-      v_mov_b32_e32(v[4], s[4]),
-      scratch_store_b96(addr=v[0], data=v[2:4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_b96(addr=v[0], vdst=v[5:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[5]),
-      v_mov_b32_e32(v[1], v[6]),
-      v_mov_b32_e32(v[2], v[7]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA)
-    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB)
-    self.assertEqual(st.vgpr[0][2], 0xCCCCCCCC)
-
-  def test_scratch_load_b128(self):
-    """SCRATCH_LOAD_B128 loads 128-bit value correctly."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[4]),
-      s_mov_b32(s[4], 0xCAFEBABE),
-      v_mov_b32_e32(v[3], s[4]),
-      s_mov_b32(s[4], 0x12345678),
-      v_mov_b32_e32(v[4], s[4]),
-      s_mov_b32(s[4], 0x9ABCDEF0),
-      v_mov_b32_e32(v[5], s[4]),
-      scratch_store_b128(addr=v[0], data=v[2:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_b128(addr=v[0], vdst=v[6:9], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[6]),
-      v_mov_b32_e32(v[1], v[7]),
-      v_mov_b32_e32(v[2], v[8]),
-      v_mov_b32_e32(v[3], v[9]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
-    self.assertEqual(st.vgpr[0][1], 0xCAFEBABE)
-    self.assertEqual(st.vgpr[0][2], 0x12345678)
-    self.assertEqual(st.vgpr[0][3], 0x9ABCDEF0)
-
-  def test_scratch_load_u8(self):
-    """SCRATCH_LOAD_U8 loads unsigned byte with zero extension."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0xDEADBEAB),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_u8(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xAB)
-
-  def test_scratch_load_i8(self):
-    """SCRATCH_LOAD_I8 loads signed byte with sign extension."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0x80),  # -128 as signed byte
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b8(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_i8(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFF80)
-
-  def test_scratch_load_u16(self):
-    """SCRATCH_LOAD_U16 loads unsigned 16-bit with zero extension."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0xDEADCAFE),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_u16(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xCAFE)
-
-  def test_scratch_load_i16(self):
-    """SCRATCH_LOAD_I16 loads signed 16-bit with sign extension."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0x8000),  # -32768 as signed 16-bit
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b16(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      scratch_load_i16(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFF8000)
-
-
-class TestScratchSVE(unittest.TestCase):
-  """Tests for SCRATCH SVE (Scratch VGPR Enable) bit behavior."""
-
-  def test_scratch_sve_zero_ignores_vaddr(self):
-    """With SVE=0, VADDR should be ignored in address calculation."""
-    TEST_OFFSET = 256
-    # Store a marker value at offset 256 (where SVE=0 should go)
-    # Then set v[0] to a non-zero value (100) and store via scratch with SVE=0
-    # If SVE=0 is handled correctly, the VADDR (100) should be IGNORED,
-    # and the store should go to offset 256, not 256+100=356
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      # First, store 0xAAAAAAAA at offset 256 with v[0]=0
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=0),
-      s_waitcnt(vmcnt=0),
-      # Now set v[0] to 100 (non-zero) and store 0xBBBBBBBB with SVE=0
-      # With SVE=0, v[0] should be IGNORED, so this should overwrite offset 256
-      v_mov_b32_e32(v[0], 100),
-      s_mov_b32(s[4], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=0),
-      s_waitcnt(vmcnt=0),
-      # Load back from offset 256 (with v[0]=0) - should get 0xBBBBBBBB
-      v_mov_b32_e32(v[0], 0),
-      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=0),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # If SVE=0 works correctly, v[0] should be 0xBBBBBBBB (the second store overwrote the first)
-    # If SVE=0 is wrong (VADDR used), v[0] would be 0xAAAAAAAA (stores went to different locations)
-    self.assertEqual(st.vgpr[0][0], 0xBBBBBBBB, "SVE=0 should ignore VADDR, both stores should go to same location")
-
-  def test_scratch_sve_one_uses_vaddr(self):
-    """With SVE=1, VADDR should be used as offset in address calculation."""
-    TEST_OFFSET = 256
-    # Store at offset 256 with v[0]=0, then store at offset 256 with v[0]=100 and SVE=1
-    # With SVE=1, the second store should go to 256+100=356, not 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      # First, store 0xAAAAAAAA at offset 256 with v[0]=0
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[4], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=1),
-      s_waitcnt(vmcnt=0),
-      # Now set v[0] to 100 and store 0xBBBBBBBB with SVE=1
-      # With SVE=1, v[0] IS used, so this should go to offset 256+100=356
-      v_mov_b32_e32(v[0], 100),
-      s_mov_b32(s[4], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[4]),
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=1),
-      s_waitcnt(vmcnt=0),
-      # Load back from offset 256 (with v[0]=0) - should still be 0xAAAAAAAA
-      v_mov_b32_e32(v[0], 0),
-      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=1),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # If SVE=1 works correctly, v[0] should be 0xAAAAAAAA (stores went to different locations)
-    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, "SVE=1 should use VADDR, stores should go to different locations")
-
-
-class TestScratchMultiLane(unittest.TestCase):
-  """Tests for SCRATCH operations with multiple lanes."""
-
-  def test_scratch_store_load_multi_lane(self):
-    """SCRATCH store/load works correctly with multiple lanes (private per-lane memory)."""
-    TEST_OFFSET = 256
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Each lane stores its lane ID
-      v_mov_b32_e32(v[0], 0),
-      v_mov_b32_e32(v[2], v[255]),  # v[255] has packed workitem IDs, low 10 bits = x
-      v_and_b32_e32(v[2], 0x3FF, v[2]),  # extract lane ID
-      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      # Load back
-      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      v_mov_b32_e32(v[0], v[3]),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    # Each lane should have loaded its own lane ID
-    for lane in range(4):
-      self.assertEqual(st.vgpr[lane][0], lane, f"Lane {lane} should have value {lane}")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,448 +0,0 @@
-"""Tests for SMEM instructions - scalar memory operations.
-
-Includes: s_load_b32, s_load_b64, s_load_b128, s_load_b256, s_load_b512
-Tests both immediate and register offset addressing modes.
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-# Use offset into output buffer for test data (output buffer is 2124 bytes)
-TEST_OFFSET = 2000
-
-# Cache invalidation sequence for scalar loads after vector stores
-# s_wait_idle waits for all outstanding memory operations including cache flushes
-CACHE_INV = [s_gl1_inv(), s_dcache_inv(), s_wait_idle()]
-
-class TestSLoadRegisterOffset(unittest.TestCase):
-  """Tests for s_load with register offset (soffset field).
-
-  Bug: s_load_b32(s[dst], s[base:base+1], s[off]) ignores the register offset
-  and only uses the immediate offset field. This causes incorrect memory loads
-  when the offset comes from a register.
-  """
-
-  def test_s_load_b32_register_offset_basic(self):
-    """s_load_b32 with register offset should load from base + reg_offset."""
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test values to output buffer: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
-      s_mov_b32(s[4], 0xAAAAAAAA),
-      s_mov_b32(s[5], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], s[5]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Now test s_load with register offset
-      # Put offset value in s[4]: offset = 4 bytes (1 dword)
-      s_mov_b32(s[4], 4),
-      # Load from out_ptr + TEST_OFFSET + s[4] (should load 0xBBBBBBBB)
-      s_load_b32(s[5], s[2:3], s[4], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[5], 0xBBBBBBBB,
-      f"s_load with reg offset 4 should load 0xBBBBBBBB: s[5]=0x{st.sgpr[5]:08x}")
-
-  def test_s_load_b32_register_offset_different_from_immediate(self):
-    """s_load_b32 with register offset loads different data than immediate offset 0."""
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test values: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
-      s_mov_b32(s[4], 0xAAAAAAAA),
-      s_mov_b32(s[5], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[4]),
-      v_mov_b32_e32(v[3], s[5]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load with immediate offset 0
-      s_load_b32(s[5], s[2:3], NULL, offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Load with register offset 4
-      s_mov_b32(s[4], 4),
-      s_load_b32(s[6], s[2:3], s[4], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # s[5] has dword at offset 0 (0xAAAAAAAA), s[6] has dword at offset 4 (0xBBBBBBBB)
-    self.assertEqual(st.sgpr[5], 0xAAAAAAAA)
-    self.assertEqual(st.sgpr[6], 0xBBBBBBBB)
-    self.assertNotEqual(st.sgpr[5], st.sgpr[6],
-      f"s_load with reg offset 4 should load different value than offset 0: "
-      f"s[5]=0x{st.sgpr[5]:08x}, s[6]=0x{st.sgpr[6]:08x}")
-
-  def test_s_load_b32_register_offset_same_as_dst(self):
-    """s_load_b32 where soffset register is same as destination.
-
-    This is the exact pattern that exposes the bug:
-    s_load_b32(s[8], s[2:3], s[8])
-    The offset should be read BEFORE the destination is overwritten.
-    """
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test values: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
-      s_mov_b32(s[6], 0xAAAAAAAA),
-      s_mov_b32(s[7], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[6]),
-      v_mov_b32_e32(v[3], s[7]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Set up s[4] = 4 (offset in bytes)
-      s_mov_b32(s[4], 4),
-      # Load using s[4] as both offset and destination
-      # Should load from base + 4, then store result in s[4]
-      s_load_b32(s[4], s[2:3], s[4], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Also load with immediate offset 4 for comparison
-      s_load_b32(s[5], s[2:3], NULL, offset=TEST_OFFSET+4),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # s[4] and s[5] should have the same value (both loaded from offset 4 = 0xBBBBBBBB)
-    self.assertEqual(st.sgpr[4], 0xBBBBBBBB)
-    self.assertEqual(st.sgpr[4], st.sgpr[5],
-      f"s_load with reg offset s[4]=4 should match immediate offset=4: "
-      f"s[4]=0x{st.sgpr[4]:08x}, s[5]=0x{st.sgpr[5]:08x}")
-
-  def test_s_load_b32_register_offset_zero(self):
-    """s_load_b32 with register offset = 0 should be same as immediate offset 0."""
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test value: 0xDEADBEEF at offset
-      s_mov_b32(s[7], 0xDEADBEEF),
-      v_mov_b32_e32(v[2], s[7]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load with register offset 0
-      s_mov_b32(s[4], 0),
-      s_load_b32(s[5], s[2:3], s[4], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Load with immediate offset 0
-      s_load_b32(s[6], s[2:3], NULL, offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[5], 0xDEADBEEF)
-    self.assertEqual(st.sgpr[5], st.sgpr[6],
-      f"s_load with reg offset 0 should match immediate offset 0: "
-      f"s[5]=0x{st.sgpr[5]:08x}, s[6]=0x{st.sgpr[6]:08x}")
-
-  def test_s_load_b32_register_plus_immediate_offset(self):
-    """s_load_b32 with both register and immediate offset should add them."""
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test values: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
-      s_mov_b32(s[8], 0xAAAAAAAA),
-      s_mov_b32(s[9], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[8]),
-      v_mov_b32_e32(v[3], s[9]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # reg offset = 4, imm offset = 0 -> total offset = 4
-      s_mov_b32(s[4], 4),
-      s_load_b32(s[5], s[2:3], s[4], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # reg offset = 0, imm offset = 4 -> total offset = 4
-      s_mov_b32(s[6], 0),
-      s_load_b32(s[7], s[2:3], s[6], offset=TEST_OFFSET+4),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Both should load from offset 4 (0xBBBBBBBB)
-    self.assertEqual(st.sgpr[5], 0xBBBBBBBB)
-    self.assertEqual(st.sgpr[7], 0xBBBBBBBB)
-    self.assertEqual(st.sgpr[5], st.sgpr[7],
-      f"reg_off=4 + imm_off=0 should equal reg_off=0 + imm_off=4: "
-      f"s[5]=0x{st.sgpr[5]:08x}, s[7]=0x{st.sgpr[7]:08x}")
-
-
-class TestSLoadMultiDword(unittest.TestCase):
-  """Tests for multi-dword s_load with register offset."""
-
-  def test_s_load_b64_register_offset(self):
-    """s_load_b64 with register offset should load 2 dwords from base + reg_offset."""
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test values: 0xAAAAAAAA, 0xBBBBBBBB at offset
-      s_mov_b32(s[10], 0xAAAAAAAA),
-      s_mov_b32(s[11], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[10]),
-      v_mov_b32_e32(v[3], s[11]),
-      v_mov_b32_e32(v[0], 0),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load with register offset 0
-      s_mov_b32(s[4], 0),
-      s_load_b64(s[6:7], s[2:3], s[4], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Compare with immediate offset
-      s_load_b64(s[8:9], s[2:3], NULL, offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[6], 0xAAAAAAAA)
-    self.assertEqual(st.sgpr[7], 0xBBBBBBBB)
-    self.assertEqual(st.sgpr[6], st.sgpr[8])
-    self.assertEqual(st.sgpr[7], st.sgpr[9])
-
-  def test_s_load_b128_register_offset(self):
-    """s_load_b128 with register offset should load 4 dwords from base + reg_offset."""
-    instructions = [
-      # Load output buffer pointer from args
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      # Store test values: 0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD at offset
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[14], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[14]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_mov_b32(s[14], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[14]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_mov_b32(s[14], 0xCCCCCCCC),
-      v_mov_b32_e32(v[2], s[14]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+8),
-      s_mov_b32(s[14], 0xDDDDDDDD),
-      v_mov_b32_e32(v[2], s[14]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+12),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load with register offset 0 (s_load_b128 requires 4-aligned dest: s[4], s[8], s[12], ...)
-      s_mov_b32(s[15], 0),
-      s_load_b128(s[4:7], s[2:3], s[15], offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Compare with immediate offset
-      s_load_b128(s[8:11], s[2:3], NULL, offset=TEST_OFFSET),
-      s_waitcnt(0),
-      # Zero out pointer regs (different addresses in emu vs hw)
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0xAAAAAAAA)
-    self.assertEqual(st.sgpr[5], 0xBBBBBBBB)
-    self.assertEqual(st.sgpr[6], 0xCCCCCCCC)
-    self.assertEqual(st.sgpr[7], 0xDDDDDDDD)
-    self.assertEqual(st.sgpr[4], st.sgpr[8])
-    self.assertEqual(st.sgpr[5], st.sgpr[9])
-
-
-class TestSLoadLarge(unittest.TestCase):
-  """Tests for large s_load operations (s_load_b256, s_load_b512)."""
-
-  def test_s_load_b256_basic(self):
-    """s_load_b256 loads 8 consecutive dwords."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      # Store 8 test values
-      s_mov_b32(s[20], 0x11111111),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
-      s_mov_b32(s[20], 0x22222222),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+4),
-      s_mov_b32(s[20], 0x33333333),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+8),
-      s_mov_b32(s[20], 0x44444444),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+12),
-      s_mov_b32(s[20], 0x55555555),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+16),
-      s_mov_b32(s[20], 0x66666666),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+20),
-      s_mov_b32(s[20], 0x77777777),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+24),
-      s_mov_b32(s[20], 0x88888888),
-      v_mov_b32_e32(v[2], s[20]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+28),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load all 8 dwords with s_load_b256
-      s_load_b256(s[4:11], s[2:3], NULL, offset=TEST_OFFSET),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0x11111111)
-    self.assertEqual(st.sgpr[5], 0x22222222)
-    self.assertEqual(st.sgpr[6], 0x33333333)
-    self.assertEqual(st.sgpr[7], 0x44444444)
-    self.assertEqual(st.sgpr[8], 0x55555555)
-    self.assertEqual(st.sgpr[9], 0x66666666)
-    self.assertEqual(st.sgpr[10], 0x77777777)
-    self.assertEqual(st.sgpr[11], 0x88888888)
-
-  def test_s_load_b512_basic(self):
-    """s_load_b512 loads 16 consecutive dwords."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      # Store 16 test values (use a pattern: 0x10, 0x20, ..., 0x100)
-      *[instr for i in range(16) for instr in [
-        s_mov_b32(s[20], (i + 1) * 0x11111111),
-        v_mov_b32_e32(v[2], s[20]),
-        global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET + i * 4),
-      ]],
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load all 16 dwords with s_load_b512
-      s_load_b512(s[64:79], s[2:3], NULL, offset=TEST_OFFSET),
-      s_waitcnt(lgkmcnt=0),
-      # Copy results to lower regs for verification (since st.sgpr only has 16 regs in test)
-      s_mov_b32(s[4], s[64]),
-      s_mov_b32(s[5], s[65]),
-      s_mov_b32(s[6], s[78]),
-      s_mov_b32(s[7], s[79]),
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0x11111111, "first dword")
-    self.assertEqual(st.sgpr[5], 0x22222222, "second dword")
-    self.assertEqual(st.sgpr[6], 0xFFFFFFFF & (15 * 0x11111111), "15th dword")
-    self.assertEqual(st.sgpr[7], 0xFFFFFFFF & (16 * 0x11111111), "16th dword")
-
-  def test_s_load_b256_with_register_offset(self):
-    """s_load_b256 with register offset should add reg offset to address."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      # Store pattern at TEST_OFFSET+8: skip first 2 dwords
-      *[instr for i in range(8) for instr in [
-        s_mov_b32(s[20], (i + 1) * 0x11111111),
-        v_mov_b32_e32(v[2], s[20]),
-        global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET + 8 + i * 4),
-      ]],
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load with register offset 8
-      s_mov_b32(s[20], 8),
-      s_load_b256(s[4:11], s[2:3], s[20], offset=TEST_OFFSET),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0x11111111, "first dword at offset+8")
-    self.assertEqual(st.sgpr[5], 0x22222222, "second dword at offset+8")
-    self.assertEqual(st.sgpr[11], 0x88888888, "last dword at offset+8")
-
-
-class TestSLoadOffset(unittest.TestCase):
-  """Tests for s_load with different immediate offsets.
-
-  These tests verify that instruction deduplication correctly handles different offset values.
-  If offset is made dynamic incorrectly, instructions with different offsets may load wrong data.
-  """
-
-  def test_s_load_different_offsets(self):
-    """Load from two different offsets and verify correct values."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      # Store 0xAAAAAAAA at offset 100
-      s_mov_b32(s[4], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=100),
-      # Store 0xBBBBBBBB at offset 200
-      s_mov_b32(s[4], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[4]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=200),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # Load from offset 100 -> should get 0xAAAAAAAA
-      s_load_b32(s[4], s[2:3], NULL, offset=100),
-      # Load from offset 200 -> should get 0xBBBBBBBB
-      s_load_b32(s[5], s[2:3], NULL, offset=200),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0xAAAAAAAA, f"offset 100: expected 0xAAAAAAAA, got 0x{st.sgpr[4]:08x}")
-    self.assertEqual(st.sgpr[5], 0xBBBBBBBB, f"offset 200: expected 0xBBBBBBBB, got 0x{st.sgpr[5]:08x}")
-
-  def test_s_load_negative_offset(self):
-    """Test negative offset (21-bit signed).
-    Store 0xAAAA at offset 100, 0xBBBB at offset 200.
-    Load with offset -100 from base+200 -> should get 0xAAAA.
-    Load with offset -100 from base+300 -> should get 0xBBBB."""
-    instructions = [
-      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
-      s_waitcnt(lgkmcnt=0),
-      v_mov_b32_e32(v[0], 0),
-      # Store 0xAAAAAAAA at offset 100, 0xBBBBBBBB at offset 200
-      s_mov_b32(s[8], 0xAAAAAAAA),
-      v_mov_b32_e32(v[2], s[8]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=100),
-      s_mov_b32(s[8], 0xBBBBBBBB),
-      v_mov_b32_e32(v[2], s[8]),
-      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=200),
-      s_waitcnt(vmcnt=0),
-      *CACHE_INV,
-      # base+200, load with offset -100 -> should get value at 100
-      s_add_u32(s[6], s[2], 200),
-      s_addc_u32(s[7], s[3], 0),
-      s_load_b32(s[4], s[6:7], NULL, offset=-100),
-      # base+300, load with offset -100 -> should get value at 200
-      s_add_u32(s[6], s[2], 300),
-      s_addc_u32(s[7], s[3], 0),
-      s_load_b32(s[5], s[6:7], NULL, offset=-100),
-      s_waitcnt(lgkmcnt=0),
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 0),
-      s_mov_b32(s[6], 0),
-      s_mov_b32(s[7], 0),
-      s_mov_b32(s[8], 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0xAAAAAAAA, f"offset 200-100=100: expected 0xAAAAAAAA, got 0x{st.sgpr[4]:08x}")
-    self.assertEqual(st.sgpr[5], 0xBBBBBBBB, f"offset 300-100=200: expected 0xBBBBBBBB, got 0x{st.sgpr[5]:08x}")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,892 +0,0 @@
-"""Tests for SOP instructions - scalar operations.
-
-Includes: s_add_u32, s_mov_b32, s_and_b32, s_or_b32, s_quadmask_b32, s_wqm_b32,
-          s_cbranch_vccnz, s_cbranch_vccz
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestBasicScalar(unittest.TestCase):
-  """Tests for basic scalar operations."""
-
-  def test_s_add_u32(self):
-    """S_ADD_U32 adds two scalar values."""
-    instructions = [
-      s_mov_b32(s[0], 100),
-      s_mov_b32(s[1], 200),
-      s_add_u32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 300)
-
-  def test_s_add_u32_carry(self):
-    """S_ADD_U32 sets SCC on overflow."""
-    instructions = [
-      s_mov_b32(s[0], 64),
-      s_not_b32(s[0], s[0]),  # ~64 = 0xffffffbf
-      s_mov_b32(s[1], 64),
-      s_add_u32(s[2], s[0], s[1]),  # 0xffffffbf + 64 = 0xffffffff
-      s_mov_b32(s[3], 1),
-      s_add_u32(s[4], s[2], s[3]),  # 0xffffffff + 1 = overflow
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[4], 0)
-    self.assertEqual(st.scc, 1)
-
-  def test_s_brev_b32(self):
-    """S_BREV_B32 reverses bits of a 32-bit value."""
-    # 10 = 0b00000000000000000000000000001010
-    # reversed = 0b01010000000000000000000000000000 = 0x50000000
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_brev_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0x50000000)
-
-  def test_s_brev_b32_all_ones(self):
-    """S_BREV_B32 with all ones stays all ones."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_brev_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0xFFFFFFFF)
-
-  def test_s_brev_b32_single_bit(self):
-    """S_BREV_B32 with bit 0 set becomes bit 31."""
-    instructions = [
-      s_mov_b32(s[0], 1),
-      s_brev_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0x80000000)
-
-  @skip_unless_gfx(11, 5, "SALU FP ops require gfx1150+")
-  def test_s_fmamk_f32(self):
-    """S_FMAMK_F32: D = S0 * literal + S1."""
-    # 2.0 * 3.0 + 1.0 = 7.0
-    instructions = [
-      s_mov_b32(s[0], f2i(2.0)),
-      s_mov_b32(s[1], f2i(1.0)),
-      s_fmamk_f32(s[2], s[0], s[1], literal=f2i(3.0)),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], f2i(7.0))
-
-  @skip_unless_gfx(11, 5, "SALU FP ops require gfx1150+")
-  def test_s_fmamk_f32_negative(self):
-    """S_FMAMK_F32 with negative values."""
-    # -2.0 * 4.0 + 10.0 = 2.0
-    instructions = [
-      s_mov_b32(s[0], f2i(-2.0)),
-      s_mov_b32(s[1], f2i(10.0)),
-      s_fmamk_f32(s[2], s[0], s[1], literal=f2i(4.0)),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], f2i(2.0))
-
-
-class TestQuadmaskWqm(unittest.TestCase):
-  """Tests for S_QUADMASK_B32 and S_WQM_B32."""
-
-  def test_s_quadmask_b32_all_quads_active(self):
-    """S_QUADMASK_B32 with all quads active."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # All lanes active
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Each quad (4 lanes) with any bit set -> 1 bit in result
-    # 32 lanes = 8 quads, all active -> 0xFF
-    self.assertEqual(st.sgpr[1], 0xFF)
-
-  def test_s_quadmask_b32_alternating_quads(self):
-    """S_QUADMASK_B32 with alternating quads active."""
-    instructions = [
-      s_mov_b32(s[0], 0x0F0F0F0F),  # Quads 0,2,4,6 active
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Quads 0,2,4,6 have at least one bit -> 0b01010101 = 0x55
-    self.assertEqual(st.sgpr[1], 0x55)
-
-  def test_s_quadmask_b32_no_quads_active(self):
-    """S_QUADMASK_B32 with no quads active."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0)
-
-  def test_s_quadmask_b32_single_lane_per_quad(self):
-    """S_QUADMASK_B32 with single lane active in each quad."""
-    instructions = [
-      s_mov_b32(s[0], 0x11111111),  # Bit 0 of each nibble
-      s_quadmask_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # All 8 quads have at least one lane -> 0xFF
-    self.assertEqual(st.sgpr[1], 0xFF)
-
-  def test_s_wqm_b32_all_active(self):
-    """S_WQM_B32 with all lanes active returns all 1s."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_wqm_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0xFFFFFFFF)
-
-  def test_s_wqm_b32_alternating_quads(self):
-    """S_WQM_B32 with single lane per quad expands to full quads."""
-    instructions = [
-      s_mov_b32(s[0], 0x11111111),  # One lane per quad
-      s_wqm_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Each quad with any bit expands to all 4 bits
-    self.assertEqual(st.sgpr[1], 0xFFFFFFFF)
-
-  def test_s_wqm_b32_zero(self):
-    """S_WQM_B32 with zero input returns zero."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_wqm_b32(s[1], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0)
-
-
-class TestBranch(unittest.TestCase):
-  """Tests for branch instructions."""
-
-  def test_cbranch_vccnz_ignores_vcc_hi(self):
-    """S_CBRANCH_VCCNZ should only check VCC_LO in wave32."""
-    instructions = [
-      # Set VCC_LO = 0, VCC_HI = 1
-      s_mov_b32(VCC_LO, 0),
-      s_mov_b32(VCC_HI, 1),
-      v_mov_b32_e32(v[0], 0),
-      # If VCC_HI is incorrectly used, branch will be taken
-      s_cbranch_vccnz(1),  # Skip next instruction if VCC != 0
-      v_mov_b32_e32(v[0], 42),  # This should execute
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 42, "Branch should NOT be taken (VCC_LO is 0)")
-
-  def test_cbranch_vccz_ignores_vcc_hi(self):
-    """S_CBRANCH_VCCZ should only check VCC_LO in wave32."""
-    instructions = [
-      # Set VCC_LO = 1, VCC_HI = 0
-      s_mov_b32(VCC_LO, 1),
-      s_mov_b32(VCC_HI, 0),
-      v_mov_b32_e32(v[0], 0),
-      # If VCC_HI is incorrectly used, branch will be taken
-      s_cbranch_vccz(1),  # Skip next instruction if VCC == 0
-      v_mov_b32_e32(v[0], 42),  # This should execute
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 42, "Branch should NOT be taken (VCC_LO is 1)")
-
-  def test_cbranch_vccnz_branches_on_vcc_lo(self):
-    """S_CBRANCH_VCCNZ branches when VCC_LO is non-zero."""
-    instructions = [
-      s_mov_b32(VCC_LO, 1),
-      v_mov_b32_e32(v[0], 0),
-      s_cbranch_vccnz(1),  # Skip next instruction if VCC != 0
-      v_mov_b32_e32(v[0], 42),  # This should be skipped
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0, "Branch should be taken (VCC_LO is 1)")
-
-
-class Test64BitLiterals(unittest.TestCase):
-  """Tests for 64-bit literal encoding in instructions."""
-
-  def test_64bit_literal_negative_encoding(self):
-    """64-bit literal -2^32 encodes correctly."""
-    lit = -4294967296.0  # -2^32
-    lit_bits = f2i64(lit)
-    instructions = [
-      s_mov_b32(s[0], lit_bits & 0xffffffff),
-      s_mov_b32(s[1], lit_bits >> 32),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = i642f(st.vgpr[0][0] | (st.vgpr[0][1] << 32))
-    self.assertAlmostEqual(result, -4294967296.0, places=5)
-
-class TestSCCBehavior(unittest.TestCase):
-  """Tests for SCC condition code behavior."""
-
-  def test_scc_from_s_cmp(self):
-    """SCC should be set by scalar compare."""
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_cmp_eq_u32(s[0], 10),
-      s_cselect_b32(s[1], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 1, "SCC should be true")
-    self.assertEqual(st.scc, 1)
-
-  def test_scc_clear(self):
-    """SCC should be cleared by failing compare."""
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_cmp_eq_u32(s[0], 20),
-      s_cselect_b32(s[1], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0, "SCC should be false")
-    self.assertEqual(st.scc, 0)
-
-
-class TestSignedArithmetic(unittest.TestCase):
-  """Tests for S_ADD_I32, S_SUB_I32 and their SCC overflow behavior."""
-
-  def test_s_add_i32_no_overflow(self):
-    """S_ADD_I32: 1 + 1 = 2, no overflow, SCC=0."""
-    instructions = [
-      s_mov_b32(s[0], 1),
-      s_add_i32(s[1], s[0], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 2)
-    self.assertEqual(st.scc, 0, "No overflow, SCC should be 0")
-
-  def test_s_add_i32_positive_overflow(self):
-    """S_ADD_I32: MAX_INT + 1 overflows, SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0x7FFFFFFF),  # MAX_INT
-      s_add_i32(s[1], s[0], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 0x80000000)  # Wraps to MIN_INT
-    self.assertEqual(st.scc, 1, "Overflow, SCC should be 1")
-
-  def test_s_add_i32_negative_no_overflow(self):
-    """S_ADD_I32: -10 + 20 = 10, no overflow."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFF6),  # -10 in two's complement
-      s_mov_b32(s[1], 20),
-      s_add_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 10)
-    self.assertEqual(st.scc, 0)
-
-  def test_s_add_i32_negative_overflow(self):
-    """S_ADD_I32: MIN_INT + (-1) underflows, SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),  # MIN_INT
-      s_mov_b32(s[1], 0xFFFFFFFF),  # -1
-      s_add_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0x7FFFFFFF)  # Wraps to MAX_INT
-    self.assertEqual(st.scc, 1, "Underflow, SCC should be 1")
-
-  def test_s_sub_i32_no_overflow(self):
-    """S_SUB_I32: 10 - 5 = 5, no overflow."""
-    instructions = [
-      s_mov_b32(s[0], 10),
-      s_mov_b32(s[1], 5),
-      s_sub_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 5)
-    self.assertEqual(st.scc, 0)
-
-  def test_s_sub_i32_overflow(self):
-    """S_SUB_I32: MAX_INT - (-1) overflows, SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0x7FFFFFFF),  # MAX_INT
-      s_mov_b32(s[1], 0xFFFFFFFF),  # -1
-      s_sub_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0x80000000)  # Wraps to MIN_INT
-    self.assertEqual(st.scc, 1, "Overflow, SCC should be 1")
-
-  def test_s_mul_hi_u32(self):
-    """S_MUL_HI_U32: high 32 bits of u32 * u32."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),  # 2^31
-      s_mov_b32(s[1], 4),
-      s_mul_hi_u32(s[2], s[0], s[1]),  # (2^31 * 4) >> 32 = 2
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 2)
-
-  def test_s_mul_hi_u32_max(self):
-    """S_MUL_HI_U32: 0xFFFFFFFF * 0xFFFFFFFF."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_mov_b32(s[1], 0xFFFFFFFF),
-      s_mul_hi_u32(s[2], s[0], s[1]),  # (0xFFFFFFFF * 0xFFFFFFFF) >> 32 = 0xFFFFFFFE
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0xFFFFFFFE)
-
-  def test_s_mul_hi_i32_positive(self):
-    """S_MUL_HI_I32: positive * positive."""
-    instructions = [
-      s_mov_b32(s[0], 0x40000000),  # 2^30
-      s_mov_b32(s[1], 4),
-      s_mul_hi_i32(s[2], s[0], s[1]),  # (2^30 * 4) >> 32 = 1
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 1)
-
-  def test_s_mul_hi_i32_neg_times_neg(self):
-    """S_MUL_HI_I32: (-1) * (-1) = 1, high bits = 0."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # -1
-      s_mov_b32(s[1], 0xFFFFFFFF),  # -1
-      s_mul_hi_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0)
-
-  def test_s_mul_hi_i32_neg_times_pos(self):
-    """S_MUL_HI_I32: (-1) * 2 = -2, high bits = -1 (sign extension)."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # -1
-      s_mov_b32(s[1], 2),
-      s_mul_hi_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0xFFFFFFFF)  # -1 sign extends
-
-  def test_s_mul_hi_i32_min_int(self):
-    """S_MUL_HI_I32: MIN_INT * 2 = -2^32, high = -1."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),  # -2^31 (MIN_INT)
-      s_mov_b32(s[1], 2),
-      s_mul_hi_i32(s[2], s[0], s[1]),  # (-2^31 * 2) >> 32 = -1
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0xFFFFFFFF)
-
-  def test_s_mul_i32(self):
-    """S_MUL_I32: signed multiply low 32 bits."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # -1
-      s_mov_b32(s[1], 10),
-      s_mul_i32(s[2], s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0xFFFFFFF6)  # -10
-
-  def test_division_sequence_from_llvm(self):
-    """Test the division sequence pattern from LLVM-generated code."""
-    # This sequence is from the sin kernel and computes integer division
-    # s10 = dividend, s18 = divisor, result in s6/s14
-    dividend = 0x28BE60DB  # Some value from the sin kernel
-    divisor = 3  # Simplified divisor
-    instructions = [
-      s_mov_b32(s[10], dividend),
-      s_mov_b32(s[18], divisor),
-      # Compute reciprocal approximation: s6 = ~0 / divisor (approx)
-      s_mov_b32(s[11], 0),
-      s_sub_i32(s[11], s[11], s[18]),  # s11 = -divisor
-      # For testing, just verify basic arithmetic works
-      s_mul_i32(s[6], s[10], 2),
-      s_add_i32(s[7], s[6], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[6], (dividend * 2) & 0xFFFFFFFF)
-    self.assertEqual(st.sgpr[7], ((dividend * 2) + 1) & 0xFFFFFFFF)
-
-
-class TestBitSet(unittest.TestCase):
-  """Tests for S_BITSET0_B32 and S_BITSET1_B32 instructions."""
-
-  def test_s_bitset1_b32_set_bit0(self):
-    """S_BITSET1_B32: set bit 0 in destination."""
-    instructions = [
-      s_mov_b32(s[0], 0),     # start with 0
-      s_mov_b32(s[1], 0),     # bit position = 0
-      s_bitset1_b32(s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 1, "Bit 0 should be set")
-
-  def test_s_bitset1_b32_set_bit31(self):
-    """S_BITSET1_B32: set bit 31 in destination."""
-    instructions = [
-      s_mov_b32(s[0], 0),     # start with 0
-      s_mov_b32(s[1], 31),    # bit position = 31
-      s_bitset1_b32(s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0x80000000, "Bit 31 should be set")
-
-  def test_s_bitset1_b32_preserves_other_bits(self):
-    """S_BITSET1_B32: preserves bits not being set."""
-    instructions = [
-      s_mov_b32(s[0], 0xFF00FF00),  # existing pattern
-      s_mov_b32(s[1], 0),            # bit position = 0
-      s_bitset1_b32(s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0xFF00FF01, "Should set bit 0 while preserving others")
-
-  def test_s_bitset0_b32_clear_bit0(self):
-    """S_BITSET0_B32: clear bit 0 in destination."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # start with all bits set
-      s_mov_b32(s[1], 0),            # bit position = 0
-      s_bitset0_b32(s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0xFFFFFFFE, "Bit 0 should be cleared")
-
-  def test_s_bitset0_b32_clear_bit31(self):
-    """S_BITSET0_B32: clear bit 31 in destination."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),  # start with all bits set
-      s_mov_b32(s[1], 31),           # bit position = 31
-      s_bitset0_b32(s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0x7FFFFFFF, "Bit 31 should be cleared")
-
-  def test_s_bitset1_b32_uses_low5_bits(self):
-    """S_BITSET1_B32: only uses low 5 bits of position (mod 32)."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_mov_b32(s[1], 32 + 5),   # position = 37, but mod 32 = 5
-      s_bitset1_b32(s[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0x20, "Bit 5 should be set (37 mod 32 = 5)")
-
-
-class TestBfeI64(unittest.TestCase):
-  """Tests for S_BFE_I64 - 64-bit bit field extract with sign extension.
-
-  Regression tests for sign extension bug where 32-bit masks were incorrectly
-  used for 64-bit operations, causing the high 32 bits to not be sign-extended.
-  """
-
-  def test_s_bfe_i64_positive_no_sign_extend(self):
-    """S_BFE_I64: positive value (1) in 16 bits should not sign extend."""
-    # S1 encodes: [22:16] = width, [5:0] = offset
-    # width=16, offset=0 -> S1 = (16 << 16) | 0 = 0x100000
-    instructions = [
-      s_mov_b32(s[0], 1),         # S0 lo = 1
-      s_mov_b32(s[1], 0),         # S0 hi = 0
-      s_mov_b32(s[2], 0x100000),  # width=16, offset=0
-      s_bfe_i64(s[4:5], s[0:1], s[2]),
-      v_mov_b32_e32(v[0], s[4]),
-      v_mov_b32_e32(v[1], s[5]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 1, "lo should be 1")
-    self.assertEqual(st.vgpr[0][1], 0, "hi should be 0 (no sign extend)")
-
-  def test_s_bfe_i64_negative_sign_extend(self):
-    """S_BFE_I64: 0xFFFF (-1 in 16 bits) should sign extend to 64 bits.
-
-    This is the main regression test - before the fix, hi was 0 instead of 0xFFFFFFFF.
-    """
-    instructions = [
-      s_mov_b32(s[0], 0xFFFF),    # S0 lo = -1 in 16 bits
-      s_mov_b32(s[1], 0),         # S0 hi = 0
-      s_mov_b32(s[2], 0x100000),  # width=16, offset=0
-      s_bfe_i64(s[4:5], s[0:1], s[2]),
-      v_mov_b32_e32(v[0], s[4]),
-      v_mov_b32_e32(v[1], s[5]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF, "lo should be 0xFFFFFFFF")
-    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
-
-  def test_s_bfe_i64_8bit_negative_sign_extend(self):
-    """S_BFE_I64: 0xFF (-1 in 8 bits) should sign extend to 64 bits."""
-    # width=8, offset=0 -> S1 = (8 << 16) | 0 = 0x80000
-    instructions = [
-      s_mov_b32(s[0], 0xFF),      # S0 lo = -1 in 8 bits
-      s_mov_b32(s[1], 0),         # S0 hi = 0
-      s_mov_b32(s[2], 0x80000),   # width=8, offset=0
-      s_bfe_i64(s[4:5], s[0:1], s[2]),
-      v_mov_b32_e32(v[0], s[4]),
-      v_mov_b32_e32(v[1], s[5]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF, "lo should be 0xFFFFFFFF")
-    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
-
-  def test_s_bfe_i64_8bit_positive(self):
-    """S_BFE_I64: 0x7F (127 in 8 bits) should not sign extend."""
-    # width=8, offset=0 -> S1 = (8 << 16) | 0 = 0x80000
-    instructions = [
-      s_mov_b32(s[0], 0x7F),      # S0 lo = 127 in 8 bits (MSB=0)
-      s_mov_b32(s[1], 0),         # S0 hi = 0
-      s_mov_b32(s[2], 0x80000),   # width=8, offset=0
-      s_bfe_i64(s[4:5], s[0:1], s[2]),
-      v_mov_b32_e32(v[0], s[4]),
-      v_mov_b32_e32(v[1], s[5]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x7F, "lo should be 0x7F")
-    self.assertEqual(st.vgpr[0][1], 0, "hi should be 0 (no sign extend)")
-
-  def test_s_bfe_i64_with_offset(self):
-    """S_BFE_I64: extract from non-zero bit offset with sign extension."""
-    # Extract 16 bits starting at bit 8: value 0xFF00 >> 8 = 0xFF = -1 in 8 bits? No wait...
-    # Let's put 0x8000FF00: extract 16 bits at offset 8 = 0x00FF (positive)
-    # Put 0xFF00_0000: extract 16 bits at offset 16 = 0xFF00 = -256 in signed 16-bit
-    instructions = [
-      s_mov_b32(s[0], 0xFF000000),  # bits [31:24] = 0xFF, [23:16] = 0x00
-      s_mov_b32(s[1], 0),
-      # width=16, offset=16 -> S1 = (16 << 16) | 16 = 0x100010
-      s_mov_b32(s[2], 0x100010),
-      s_bfe_i64(s[4:5], s[0:1], s[2]),
-      v_mov_b32_e32(v[0], s[4]),
-      v_mov_b32_e32(v[1], s[5]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Extract bits [31:16] = 0xFF00, sign bit is bit 15 of extracted = bit 31 of original = 1
-    # So result should be sign-extended 0xFF00 -> 0xFFFFFF00 in lo, 0xFFFFFFFF in hi
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFF00, "lo should be sign-extended 0xFF00")
-    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
-
-  def test_s_bfe_i64_32bit_negative(self):
-    """S_BFE_I64: extract 32 bits with sign extension."""
-    # width=32, offset=0 -> S1 = (32 << 16) | 0 = 0x200000
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),  # MIN_INT32 = -2^31
-      s_mov_b32(s[1], 0),
-      s_mov_b32(s[2], 0x200000),    # width=32, offset=0
-      s_bfe_i64(s[4:5], s[0:1], s[2]),
-      v_mov_b32_e32(v[0], s[4]),
-      v_mov_b32_e32(v[1], s[5]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x80000000, "lo should be 0x80000000")
-    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
-
-
-class Test64BitCompare(unittest.TestCase):
-  """Tests for 64-bit scalar compare instructions."""
-
-  def test_s_cmp_eq_u64_equal(self):
-    """S_CMP_EQ_U64: comparing equal 64-bit values sets SCC=1."""
-    val = 0x123456789ABCDEF0
-    instructions = [
-      s_mov_b32(s[0], val & 0xFFFFFFFF),
-      s_mov_b32(s[1], val >> 32),
-      s_mov_b32(s[2], val & 0xFFFFFFFF),
-      s_mov_b32(s[3], val >> 32),
-      s_cmp_eq_u64(s[0:1], s[2:3]),
-      s_cselect_b32(s[4], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.scc, 1)
-    self.assertEqual(st.sgpr[4], 1)
-
-  def test_s_cmp_eq_u64_different_upper_bits(self):
-    """S_CMP_EQ_U64: values differing only in upper 32 bits are not equal."""
-    # This is the bug case - if only lower 32 bits are compared, these would be equal
-    instructions = [
-      s_mov_b32(s[0], 0),  # lower 32 bits of value 0
-      s_mov_b32(s[1], 0),  # upper 32 bits of value 0
-      s_mov_b32(s[2], 0),  # lower 32 bits of 0x100000000
-      s_mov_b32(s[3], 1),  # upper 32 bits of 0x100000000
-      s_cmp_eq_u64(s[0:1], s[2:3]),
-      s_cselect_b32(s[4], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.scc, 0, "0 != 0x100000000, SCC should be 0")
-    self.assertEqual(st.sgpr[4], 0)
-
-  def test_s_cmp_lg_u64_different(self):
-    """S_CMP_LG_U64: different 64-bit values sets SCC=1."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_mov_b32(s[1], 0),  # s[0:1] = 0
-      s_mov_b32(s[2], 0),
-      s_mov_b32(s[3], 1),  # s[2:3] = 0x100000000
-      s_cmp_lg_u64(s[0:1], s[2:3]),
-      s_cselect_b32(s[4], 1, 0),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.scc, 1, "0 != 0x100000000, SCC should be 1")
-    self.assertEqual(st.sgpr[4], 1)
-
-
-class TestSOPPNop(unittest.TestCase):
-  """Tests for S_NOP and other SOPP instructions with expression-based for loops.
-
-  S_NOP's pcode uses 'for i in 0U : SIMM16.u16[3 : 0].u32 do' which requires
-  the parser to handle non-constant loop bounds.
-  """
-
-  def test_s_nop_basic(self):
-    """S_NOP executes without side effects."""
-    # S_NOP with immediate 0 should just do nothing
-    instructions = [
-      s_mov_b32(s[0], 42),
-      s_nop(0),  # nop with simm16=0
-      s_mov_b32(s[1], 100),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 42)
-    self.assertEqual(st.sgpr[1], 100)
-
-  def test_s_nop_with_count(self):
-    """S_NOP with count parameter executes multiple nops."""
-    # S_NOP with immediate 3 should execute 4 nops (0:3 inclusive)
-    instructions = [
-      s_mov_b32(s[0], 1),
-      s_nop(3),  # nop with simm16=3 -> 4 iterations
-      s_add_u32(s[0], s[0], 1),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 2)
-
-
-class TestNullRegister(unittest.TestCase):
-  """Tests for NULL register (124) behavior - writes should be discarded, reads return 0."""
-
-  def test_s_mov_b32_from_null(self):
-    """S_MOV_B32 from NULL should read as 0."""
-    instructions = [
-      s_mov_b32(s[0], 0xDEADBEEF),  # Set s[0] to sentinel
-      s_mov_b32(s[0], NULL),  # Read from NULL - should be 0
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0)
-
-  def test_s_add_u32_with_null_src(self):
-    """S_ADD_U32 with NULL as source should use 0."""
-    instructions = [
-      s_mov_b32(s[0], 100),
-      s_add_u32(s[1], s[0], NULL),  # 100 + 0 = 100
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[1], 100)
-
-  def test_s_mov_b32_to_null(self):
-    """S_MOV_B32 to NULL (sdst=124) should discard the write."""
-    instructions = [
-      s_mov_b32(s[0], 0xDEADBEEF),  # Set s[0] to sentinel
-      s_mov_b32(NULL, 42),  # Write to NULL - should be discarded
-      # s[0] should still be 0xDEADBEEF since NULL write doesn't affect it
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0], 0xDEADBEEF)
-
-  def test_s_add_u32_to_null(self):
-    """S_ADD_U32 with sdst=NULL should discard result but still set SCC."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_mov_b32(s[1], 1),
-      s_add_u32(NULL, s[0], s[1]),  # overflow, write to NULL
-      s_cselect_b32(s[2], 1, 0),  # capture SCC
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # SCC should still be set from overflow even though result was discarded
-    self.assertEqual(st.sgpr[2], 1)
-    self.assertEqual(st.scc, 1)
-
-  def test_s_and_b32_to_null(self):
-    """S_AND_B32 with sdst=NULL should discard result but still set SCC."""
-    instructions = [
-      s_mov_b32(s[0], 0xFF00FF00),
-      s_mov_b32(s[1], 0x0F0F0F0F),
-      s_and_b32(NULL, s[0], s[1]),  # result=0x0F000F00, non-zero so SCC=1
-      s_cselect_b32(s[2], 1, 0),  # capture SCC
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 1)  # SCC=1 because result was non-zero
-    self.assertEqual(st.scc, 1)
-
-  def test_s_or_b32_to_null_zero_result(self):
-    """S_OR_B32 with sdst=NULL and zero result should set SCC=0."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_mov_b32(s[1], 0),
-      s_or_b32(NULL, s[0], s[1]),  # result=0, so SCC=0
-      s_cselect_b32(s[2], 1, 0),  # capture SCC
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[2], 0)  # SCC=0 because result was zero
-    self.assertEqual(st.scc, 0)
-
-
-class Test64BitSOP1InlineConstants(unittest.TestCase):
-  """Tests for 64-bit SOP1 instructions with inline constants.
-
-  Regression tests for bug where rsrc_dyn didn't properly handle 64-bit
-  inline constants, incorrectly duplicating lo bits to hi instead of
-  zero/sign-extending.
-  """
-
-  def test_s_mov_b64_inline_0(self):
-    """S_MOV_B64 with inline constant 0."""
-    instructions = [
-      s_mov_b64(s[0:1], 0),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_mov_b64_inline_16(self):
-    """S_MOV_B64 with inline constant 16 should set lo=16, hi=0."""
-    instructions = [
-      s_mov_b64(s[0:1], 16),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 16)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_mov_b64_inline_64(self):
-    """S_MOV_B64 with inline constant 64 (max positive)."""
-    instructions = [
-      s_mov_b64(s[0:1], 64),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 64)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_mov_b64_inline_neg1(self):
-    """S_MOV_B64 with inline constant -1 should sign-extend."""
-    instructions = [
-      s_mov_b64(s[0:1], -1),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF)
-    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF)
-
-  def test_s_mov_b64_inline_neg16(self):
-    """S_MOV_B64 with inline constant -16 should sign-extend."""
-    instructions = [
-      s_mov_b64(s[0:1], -16),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFFF0)
-    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF)
-
-  def test_s_mov_b64_float_const_1_0(self):
-    """S_MOV_B64 with float inline constant 1.0 - casts F32 to F64."""
-    instructions = [
-      s_mov_b64(s[0:1], 1.0),  # inline constant 242 (1.0f)
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # Hardware casts F32 to F64: 1.0f64 = 0x3FF0000000000000
-    self.assertEqual(st.vgpr[0][0], 0x00000000)  # lo
-    self.assertEqual(st.vgpr[0][1], 0x3FF00000)  # hi
-
-  def test_s_or_b64_inline_constant(self):
-    """S_OR_B64 with 64-bit inline constant."""
-    instructions = [
-      s_mov_b64(s[0:1], 0),
-      s_or_b64(s[2:3], s[0:1], 16),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 16)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_and_b64_inline_constant(self):
-    """S_AND_B64 with 64-bit inline constant."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_mov_b32(s[1], 0xFFFFFFFF),
-      s_and_b64(s[2:3], s[0:1], 16),
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 16)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-
-class Test64BitSOPLiterals(unittest.TestCase):
-  """Tests for 64-bit SOP instructions with 32-bit literals.
-
-  Tests the behavior when a 64-bit SOP instruction uses a 32-bit literal
-  (offset 255 in instruction encoding). The literal is zero-extended to 64 bits.
-  """
-
-  def test_s_mov_b64_literal(self):
-    """S_MOV_B64 with 32-bit literal value - zero-extended to 64 bits."""
-    instructions = [
-      s_mov_b64(s[0:1], 0x12345678),  # literal > 64, uses literal encoding
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x12345678)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_or_b64_literal(self):
-    """S_OR_B64 with 32-bit literal value - zero-extended to 64 bits."""
-    instructions = [
-      s_mov_b64(s[0:1], 0),
-      s_or_b64(s[2:3], s[0:1], 0x12345678),  # literal
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x12345678)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_and_b64_literal(self):
-    """S_AND_B64 with 32-bit literal value - zero-extended to 64 bits."""
-    instructions = [
-      s_mov_b32(s[0], 0xFFFFFFFF),
-      s_mov_b32(s[1], 0xFFFFFFFF),
-      s_and_b64(s[2:3], s[0:1], 0x12345678),  # literal
-      v_mov_b32_e32(v[0], s[2]),
-      v_mov_b32_e32(v[1], s[3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x12345678)
-    self.assertEqual(st.vgpr[0][1], 0)
-
-  def test_s_mov_b64_literal_negative(self):
-    """S_MOV_B64 with 0xFFFFFFFF literal - zero-extended (not sign-extended)."""
-    instructions = [
-      s_mov_b64(s[0:1], 0xFFFFFFFF),  # -1 as 32-bit, but zero-extended to 64-bit
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF)
-    self.assertEqual(st.vgpr[0][1], 0)  # zero-extended, not sign-extended
-
-  def test_s_mov_b64_literal_high_bit(self):
-    """S_MOV_B64 with 0x80000000 literal - zero-extended (not sign-extended)."""
-    instructions = [
-      s_mov_b64(s[0:1], 0x80000000),  # high bit set, but zero-extended
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0x80000000)
-    self.assertEqual(st.vgpr[0][1], 0)  # zero-extended, not sign-extended
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,983 +0,0 @@
-"""Tests for VOP2 instructions - two operand vector operations.
-
-Includes: v_add_f32, v_mul_f32, v_and_b32, v_or_b32, v_xor_b32,
-          v_lshrrev_b32, v_lshlrev_b32, v_fmac_f32, v_fmaak_f32, v_fmamk_f32,
-          v_add_nc_u32, v_cndmask_b32, v_add_f16, v_mul_f16
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-class TestBasicArithmetic(unittest.TestCase):
-  """Tests for basic arithmetic VOP2 instructions."""
-
-  def test_v_add_f32(self):
-    """V_ADD_F32 adds two floats."""
-    instructions = [
-      v_mov_b32_e32(v[0], 1.0),
-      v_mov_b32_e32(v[1], 2.0),
-      v_add_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 3.0, places=5)
-
-  def test_v_mul_f32(self):
-    """V_MUL_F32 multiplies two floats."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 4.0),
-      v_mul_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 8.0, places=5)
-
-  def test_v_fmac_f32(self):
-    """V_FMAC_F32: d = d + a*b using inline constants."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 4.0),
-      v_mov_b32_e32(v[2], 1.0),
-      v_fmac_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
-
-  def test_v_fmaak_f32(self):
-    """V_FMAAK_F32: d = a * b + K using inline constants."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 4.0),
-      v_fmaak_f32_e32(v[2], v[0], v[1], literal=0x3f800000),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
-
-  def test_v_fmamk_f32_basic(self):
-    """V_FMAMK_F32: d = a * K + b."""
-    instructions = [
-      v_mov_b32_e32(v[0], 2.0),
-      v_mov_b32_e32(v[1], 1.0),
-      v_fmamk_f32_e32(v[2], v[0], v[1], literal=0x40800000),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
-
-  def test_v_fmamk_f32_small_constant(self):
-    """V_FMAMK_F32 with small constant."""
-    instructions = [
-      v_mov_b32_e32(v[0], 4.0),
-      v_mov_b32_e32(v[1], 1.0),
-      v_fmamk_f32_e32(v[2], v[0], v[1], literal=f2i(0.5)),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 3.0, places=5)
-
-
-class TestBitManipulation(unittest.TestCase):
-  """Tests for bit manipulation VOP2 instructions."""
-
-  def test_v_and_b32(self):
-    """V_AND_B32 bitwise and."""
-    instructions = [
-      s_mov_b32(s[0], 0xff),
-      s_mov_b32(s[1], 0x0f),
-      v_mov_b32_e32(v[0], s[0]),
-      v_and_b32_e32(v[1], s[1], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x0f)
-
-  def test_v_and_b32_quadrant(self):
-    """V_AND_B32 for quadrant extraction (n & 3)."""
-    instructions = [
-      s_mov_b32(s[0], 15915),
-      v_mov_b32_e32(v[0], s[0]),
-      v_and_b32_e32(v[1], 3, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 15915 & 3)
-
-  def test_v_lshrrev_b32(self):
-    """V_LSHRREV_B32 logical shift right."""
-    instructions = [
-      s_mov_b32(s[0], 0xff00),
-      v_mov_b32_e32(v[0], s[0]),
-      v_lshrrev_b32_e32(v[1], 8, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0xff)
-
-  def test_v_lshlrev_b32(self):
-    """V_LSHLREV_B32 logical shift left."""
-    instructions = [
-      s_mov_b32(s[0], 0xff),
-      v_mov_b32_e32(v[0], s[0]),
-      v_lshlrev_b32_e32(v[1], 8, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0xff00)
-
-  def test_v_xor_b32(self):
-    """V_XOR_B32 bitwise xor (used in sin for sign)."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),
-      s_mov_b32(s[1], f2i(1.0)),
-      v_mov_b32_e32(v[0], s[1]),
-      v_xor_b32_e32(v[1], s[0], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][1]), -1.0, places=5)
-
-  def test_v_xor_b32_sign_flip(self):
-    """V_XOR_B32 for sign flip pattern."""
-    instructions = [
-      s_mov_b32(s[0], 0x80000000),
-      v_mov_b32_e32(v[0], -2.0),
-      v_xor_b32_e32(v[1], s[0], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][1]), 2.0, places=5)
-
-
-class TestSpecialValues(unittest.TestCase):
-  """Tests for special float values - inf, nan, zero handling."""
-
-  def test_v_mul_f32_zero_times_inf(self):
-    """V_MUL_F32: 0 * inf = NaN."""
-    import math
-    instructions = [
-      v_mov_b32_e32(v[0], 0),
-      s_mov_b32(s[0], 0x7f800000),
-      v_mov_b32_e32(v[1], s[0]),
-      v_mul_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertTrue(math.isnan(i2f(st.vgpr[0][2])))
-
-  def test_v_add_f32_inf_minus_inf(self):
-    """V_ADD_F32: inf + (-inf) = NaN."""
-    import math
-    instructions = [
-      s_mov_b32(s[0], 0x7f800000),
-      s_mov_b32(s[1], 0xff800000),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f32_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertTrue(math.isnan(i2f(st.vgpr[0][2])))
-
-
-class TestF16Ops(unittest.TestCase):
-  """Tests for 16-bit VOP2 operations."""
-
-  def test_v_add_f16_basic(self):
-    """V_ADD_F16 adds two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4200, f"Expected 0x4200 (f16 3.0), got 0x{result:04x}")
-
-  def test_v_add_f16_negative(self):
-    """V_ADD_F16 with negative values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0xc000),  # f16 -2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0xbc00, f"Expected 0xbc00 (f16 -1.0), got 0x{result:04x}")
-
-  def test_v_mul_f16_basic(self):
-    """V_MUL_F16 multiplies two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      s_mov_b32(s[1], 0x4200),  # f16 3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mul_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4600, f"Expected 0x4600 (f16 6.0), got 0x{result:04x}")
-
-  def test_v_mul_f16_by_zero(self):
-    """V_MUL_F16 by zero."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0),
-      v_mul_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x0000, f"Expected 0x0000 (f16 0.0), got 0x{result:04x}")
-
-  def test_v_fmac_f16_basic(self):
-    """V_FMAC_F16: d = d + a*b."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      s_mov_b32(s[1], 0x4200),  # f16 3.0
-      s_mov_b32(s[2], 0x3c00),  # f16 1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      v_fmac_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(result, 0x4700, f"Expected 0x4700 (f16 7.0), got 0x{result:04x}")
-
-  def test_v_max_f16_basic(self):
-    """V_MAX_F16 returns the maximum of two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_max_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4000, f"Expected 0x4000 (f16 2.0), got 0x{result:04x}")
-
-  def test_v_min_f16_basic(self):
-    """V_MIN_F16 returns the minimum of two f16 values."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_min_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x3c00, f"Expected 0x3c00 (f16 1.0), got 0x{result:04x}")
-
-  def test_v_fmaak_f16_basic(self):
-    """V_FMAAK_F16: d = a * b + K."""
-    instructions = [
-      s_mov_b32(s[0], 0x4000),  # f16 2.0
-      s_mov_b32(s[1], 0x4200),  # f16 3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_fmaak_f16_e32(v[2], v[0], v[1], literal=0x3c00),  # + f16 1.0
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(result, 0x4700, f"Expected 0x4700 (f16 7.0), got 0x{result:04x}")
-
-
-class TestHiHalfOps(unittest.TestCase):
-  """Tests for VOP2 16-bit operations with hi-half operands."""
-
-  def test_v_add_f16_src0_hi_fold(self):
-    """V_ADD_F16 with src0 hi-half fold (same register, different halves)."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # lo=f16(1.0), hi=f16(2.0)
-      v_mov_b32_e32(v[0], s[0]),
-      VOP3(VOP3Op.V_ADD_F16, vdst=v[1], src0=v[0], src1=v[0], opsel=0b0001),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    self.assertEqual(result, 0x4200, f"Expected f16(3.0)=0x4200, got 0x{result:04x}")
-
-  def test_v_add_f16_src0_hi_different_reg(self):
-    """V_ADD_F16 with src0 hi-half from different register."""
-    instructions = [
-      s_mov_b32(s[0], 0x40000000),  # hi=f16(2.0), lo=0
-      s_mov_b32(s[1], 0x00003c00),  # hi=0, lo=f16(1.0)
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      VOP3(VOP3Op.V_ADD_F16, vdst=v[2], src0=v[0], src1=v[1], opsel=0b0001),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4200, f"Expected f16(3.0)=0x4200, got 0x{result:04x}")
-
-  def test_v_mul_f16_src0_hi(self):
-    """V_MUL_F16 with src0 from high half."""
-    instructions = [
-      s_mov_b32(s[0], 0x40000000),  # hi=f16(2.0), lo=0
-      s_mov_b32(s[1], 0x00004200),  # hi=0, lo=f16(3.0)
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      VOP3(VOP3Op.V_MUL_F16, vdst=v[2], src0=v[0], src1=v[1], opsel=0b0001),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
-
-  def test_v_mul_f16_hi_half(self):
-    """V_MUL_F16 reading from high half."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # lo=1.0, hi=2.0
-      v_mov_b32_e32(v[0], s[0]),
-      VOP3(VOP3Op.V_MUL_F16, vdst=v[1], src0=v[0], src1=v[0], opsel=0b0011),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    self.assertEqual(result, 0x4400, f"Expected f16(4.0)=0x4400, got 0x{result:04x}")
-
-  def test_v_fma_f16_hi_dest(self):
-    """V_FMA_F16 writing to high half with opsel.
-
-    Uses V_FMA_F16 (not V_FMAC_F16) because it has explicit src2 operand
-    which makes opsel handling clearer.
-    """
-    instructions = [
-      s_mov_b32(s[0], 0x3c000000),  # hi=f16(1.0), lo=0
-      s_mov_b32(s[1], 0x4000),      # f16(2.0) in lo
-      s_mov_b32(s[2], 0x4200),      # f16(3.0) in lo
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      # V_FMA_F16: dst = src0 * src1 + src2
-      # opsel=0b1100: bit2=src2 hi, bit3=dst hi
-      # So: v[0].hi = v[1].lo * v[2].lo + v[0].hi = 2.0 * 3.0 + 1.0 = 7.0
-      VOP3(VOP3Op.V_FMA_F16, vdst=v[0], src0=v[1], src1=v[2], src2=v[0], opsel=0b1100),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][0] >> 16) & 0xffff
-    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(hi, 0x4700, f"Expected f16(7.0)=0x4700 in hi, got 0x{hi:04x}")
-
-  def test_v_add_f16_multilane(self):
-    """V_ADD_F16 with multiple lanes."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_add_f16_e32(v[2], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    for lane in range(4):
-      result = st.vgpr[lane][2] & 0xffff
-      self.assertEqual(result, 0x4200, f"Lane {lane}: expected 0x4200, got 0x{result:04x}")
-
-
-class TestVop2F16HiHalf(unittest.TestCase):
-  """Regression tests for VOP2 f16 hi-half operand handling.
-
-  These test the bugs where:
-  1. VOP2 vsrc1 >= 384 (v[128]+) wasn't extracting hi 16 bits
-  2. VOP2 vdst >= 384 (v[128]+) wasn't preserving lo 16 bits
-  """
-
-  def test_v_add_f16_e32_vsrc1_hi_half(self):
-    """V_ADD_F16_E32 with vsrc1 from hi-half (v[128]+).
-
-    When vsrc1 >= 384 (representing v[128]+), the hardware reads from the hi 16 bits
-    of v[vsrc1-128]. The emulator must extract bits [31:16] from the actual VGPR.
-
-    Regression test for: VOP2 f16 vsrc1 hi-half extraction bug.
-    """
-    instructions = [
-      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
-      s_mov_b32(s[0], 0x40003c00),
-      v_mov_b32_e32(v[0], s[0]),
-      # v_add_f16_e32 v[1], v[0], v[128]  (vsrc1=v[128] reads hi of v[0])
-      # In VOP2 encoding, vsrc1=384 means v[128], which maps to v[0].hi
-      # v[1] = v[0].lo + v[0].hi = 1.0 + 2.0 = 3.0
-      VOP2(VOP2Op.V_ADD_F16, vdst=v[1], src0=v[0], vsrc1=v[128]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    # 1.0 + 2.0 = 3.0, f16 3.0 = 0x4200
-    self.assertEqual(result, 0x4200, f"Expected f16(3.0)=0x4200, got 0x{result:04x}")
-
-  def test_v_mul_f16_e32_vsrc1_hi_half(self):
-    """V_MUL_F16_E32 with vsrc1 from hi-half.
-
-    Regression test for: VOP2 f16 vsrc1 hi-half extraction bug.
-    """
-    instructions = [
-      # v[0] = 0x4200_4000: hi=f16(3.0), lo=f16(2.0)
-      s_mov_b32(s[0], 0x42004000),
-      v_mov_b32_e32(v[0], s[0]),
-      # v_mul_f16_e32 v[1], v[0], v[128]  (vsrc1=v[128] reads hi of v[0])
-      # v[1] = v[0].lo * v[0].hi = 2.0 * 3.0 = 6.0
-      VOP2(VOP2Op.V_MUL_F16, vdst=v[1], src0=v[0], vsrc1=v[128]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    # 2.0 * 3.0 = 6.0, f16 6.0 = 0x4600
-    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
-
-  def test_v_add_f16_e32_vdst_hi_half(self):
-    """V_ADD_F16_E32 writing to hi-half destination (v[128]+).
-
-    When vdst >= 384 (representing v[128]+), the hardware writes to bits [31:16]
-    of v[vdst-128] while preserving bits [15:0]. The emulator must merge the result.
-
-    Regression test for: VOP2 f16 vdst hi-half write bug.
-    """
-    instructions = [
-      # v[0] = 0x0000_BEEF: lo has marker value
-      s_mov_b32(s[0], 0x0000BEEF),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = f16(1.0), v[2] = f16(2.0)
-      s_mov_b32(s[1], 0x3c00),
-      s_mov_b32(s[2], 0x4000),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      # v_add_f16_e32 v[128], v[1], v[2]  (vdst=v[128] writes hi of v[0])
-      # v[0].hi = 1.0 + 2.0 = 3.0, v[0].lo preserved = 0xBEEF
-      VOP2(VOP2Op.V_ADD_F16, vdst=v[128], src0=v[1], vsrc1=v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][0] >> 16) & 0xffff
-    lo = st.vgpr[0][0] & 0xffff
-    # hi = 3.0 = 0x4200, lo preserved = 0xBEEF
-    self.assertEqual(hi, 0x4200, f"Expected hi=f16(3.0)=0x4200, got 0x{hi:04x}")
-    self.assertEqual(lo, 0xBEEF, f"Expected lo preserved=0xBEEF, got 0x{lo:04x}")
-
-  def test_v_mul_f16_e32_vdst_hi_half(self):
-    """V_MUL_F16_E32 writing to hi-half destination.
-
-    Regression test for: VOP2 f16 vdst hi-half write bug.
-    """
-    instructions = [
-      # v[0] = 0x0000_DEAD: lo has marker value
-      s_mov_b32(s[0], 0x0000DEAD),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = f16(2.0), v[2] = f16(4.0)
-      s_mov_b32(s[1], 0x4000),
-      s_mov_b32(s[2], 0x4400),
-      v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]),
-      # v_mul_f16_e32 v[128], v[1], v[2]  (vdst=v[128] writes hi of v[0])
-      # v[0].hi = 2.0 * 4.0 = 8.0, v[0].lo preserved = 0xDEAD
-      VOP2(VOP2Op.V_MUL_F16, vdst=v[128], src0=v[1], vsrc1=v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][0] >> 16) & 0xffff
-    lo = st.vgpr[0][0] & 0xffff
-    # hi = 8.0 = 0x4800, lo preserved = 0xDEAD
-    self.assertEqual(hi, 0x4800, f"Expected hi=f16(8.0)=0x4800, got 0x{hi:04x}")
-    self.assertEqual(lo, 0xDEAD, f"Expected lo preserved=0xDEAD, got 0x{lo:04x}")
-
-  def test_v_add_f16_e32_both_hi_half(self):
-    """V_ADD_F16_E32 with both vsrc1 and vdst as hi-half (different underlying regs).
-
-    Tests the combination of both fixes: reading vsrc1 from hi-half AND
-    writing result to hi-half destination, using different underlying VGPRs.
-
-    Regression test for: VOP2 f16 hi-half bugs (combined).
-    """
-    instructions = [
-      # v[0] = 0x4000_xxxx: hi=f16(2.0) for vsrc1
-      s_mov_b32(s[0], 0x40000000),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = 0x0000_3c00: lo=f16(1.0) for src0
-      s_mov_b32(s[1], 0x00003c00),
-      v_mov_b32_e32(v[1], s[1]),
-      # v[2] = 0x0000_CAFE: lo=marker for vdst preservation
-      s_mov_b32(s[2], 0x0000CAFE),
-      v_mov_b32_e32(v[2], s[2]),
-      # v_add_f16_e32 v[130], v[1], v[128]
-      # src0 = v[1].lo = 1.0
-      # vsrc1 = v[128] reads v[0].hi = 2.0
-      # result = 1.0 + 2.0 = 3.0
-      # vdst = v[130] writes to v[2].hi, preserving v[2].lo
-      VOP2(VOP2Op.V_ADD_F16, vdst=v[130], src0=v[1], vsrc1=v[128]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][2] >> 16) & 0xffff
-    lo = st.vgpr[0][2] & 0xffff
-    # hi = 3.0 = 0x4200, lo preserved = 0xCAFE
-    self.assertEqual(hi, 0x4200, f"Expected hi=f16(3.0)=0x4200, got 0x{hi:04x}")
-    self.assertEqual(lo, 0xCAFE, f"Expected lo preserved=0xCAFE, got 0x{lo:04x}")
-
-  def test_v_fmac_f16_e32_vsrc1_hi_half(self):
-    """V_FMAC_F16_E32 with vsrc1 from hi-half.
-
-    V_FMAC_F16: vdst = vdst + src0 * vsrc1
-
-    Regression test for: VOP2 f16 vsrc1 hi-half extraction bug.
-    """
-    instructions = [
-      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
-      s_mov_b32(s[0], 0x40003c00),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = f16(3.0) = 0x4200
-      s_mov_b32(s[1], 0x4200),
-      v_mov_b32_e32(v[1], s[1]),
-      # v_fmac_f16_e32 v[1], v[0], v[128]
-      # vdst = v[1] = 3.0 + v[0].lo * v[0].hi = 3.0 + 1.0 * 2.0 = 5.0
-      VOP2(VOP2Op.V_FMAC_F16, vdst=v[1], src0=v[0], vsrc1=v[128]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xffff
-    # 3.0 + 1.0 * 2.0 = 5.0, f16 5.0 = 0x4500
-    self.assertEqual(result, 0x4500, f"Expected f16(5.0)=0x4500, got 0x{result:04x}")
-
-  def test_v_fmac_f16_e32_vdst_hi_half(self):
-    """V_FMAC_F16_E32 writing to hi-half destination.
-
-    V_FMAC_F16: vdst.h = vdst.h + src0 * vsrc1
-
-    When vdst is v[128]+, the accumulator D0 must also read from the hi-half.
-    This tests the bug where D0 was read from lo-half instead of hi-half.
-
-    Regression test for: VOP2 FMAC hi-half D0 accumulator read bug.
-    """
-    instructions = [
-      # v[0] = 0x3800_DEAD: hi=f16(0.5), lo=marker (0xDEAD)
-      s_mov_b32(s[0], 0x3800DEAD),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = f16(2.0) = 0x4000
-      s_mov_b32(s[1], 0x4000),
-      v_mov_b32_e32(v[1], s[1]),
-      # v[2] = f16(3.0) = 0x4200
-      s_mov_b32(s[2], 0x4200),
-      v_mov_b32_e32(v[2], s[2]),
-      # v_fmac_f16_e32 v[128], v[1], v[2]
-      # vdst = v[128] means v[0].hi
-      # D0 = v[0].hi = 0.5
-      # result = D0 + src0 * vsrc1 = 0.5 + 2.0 * 3.0 = 6.5
-      # v[0].hi = 6.5, v[0].lo preserved = 0xDEAD
-      VOP2(VOP2Op.V_FMAC_F16, vdst=v[128], src0=v[1], vsrc1=v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][0] >> 16) & 0xffff
-    lo = st.vgpr[0][0] & 0xffff
-    # hi = 6.5 = 0x4680, lo preserved = 0xDEAD
-    self.assertEqual(hi, 0x4680, f"Expected hi=f16(6.5)=0x4680, got 0x{hi:04x}")
-    self.assertEqual(lo, 0xDEAD, f"Expected lo preserved=0xDEAD, got 0x{lo:04x}")
-
-  def test_v_mul_f16_e32_src0_hi_half(self):
-    """V_MUL_F16_E32 with src0 from hi-half (src0 >= v[128]).
-
-    When src0 >= 384 (representing v[128]+), the hardware reads from the hi 16 bits
-    of v[src0-128]. The emulator must extract bits [31:16] from the actual VGPR.
-
-    Regression test for: VOP2 f16 src0 hi-half extraction bug.
-    """
-    instructions = [
-      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
-      s_mov_b32(s[0], 0x40003c00),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = f16(3.0) = 0x4200
-      s_mov_b32(s[1], 0x4200),
-      v_mov_b32_e32(v[1], s[1]),
-      # v_mul_f16_e32 v[2], v[128], v[1]
-      # src0 = v[128] reads from v[0].hi = 2.0
-      # result = 2.0 * 3.0 = 6.0
-      VOP2(VOP2Op.V_MUL_F16, vdst=v[2], src0=v[128], vsrc1=v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    # 2.0 * 3.0 = 6.0, f16 6.0 = 0x4600
-    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
-
-  def test_v_add_f16_e32_src0_hi_half(self):
-    """V_ADD_F16_E32 with src0 from hi-half (src0 >= v[128]).
-
-    Regression test for: VOP2 f16 src0 hi-half extraction bug.
-    """
-    instructions = [
-      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
-      s_mov_b32(s[0], 0x40003c00),
-      v_mov_b32_e32(v[0], s[0]),
-      # v[1] = f16(5.0) = 0x4500
-      s_mov_b32(s[1], 0x4500),
-      v_mov_b32_e32(v[1], s[1]),
-      # v_add_f16_e32 v[2], v[128], v[1]
-      # src0 = v[128] reads from v[0].hi = 2.0
-      # result = 2.0 + 5.0 = 7.0
-      VOP2(VOP2Op.V_ADD_F16, vdst=v[2], src0=v[128], vsrc1=v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    # 2.0 + 5.0 = 7.0, f16 7.0 = 0x4700
-    self.assertEqual(result, 0x4700, f"Expected f16(7.0)=0x4700, got 0x{result:04x}")
-
-
-class TestF16InlineConstants(unittest.TestCase):
-  """Regression tests for VOP2 F16 inline float constants.
-
-  For 16-bit VOP2 operations (v_add_f16, v_mul_f16, etc.), inline float constants
-  like 1.0, 2.0 must use F16 encoding (0x3c00, 0x4000) not F32 encoding (0x3f800000).
-
-  The emulator's rsrc() function needs bits=16 to select F16_INLINE constants.
-
-  Regression test for: VOP2 16-bit inline constant using F32 instead of F16.
-  """
-
-  def test_v_add_f16_inline_constant_1_0(self):
-    """V_ADD_F16_E32 with inline constant 1.0 should use F16 encoding."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      v_mov_b32_e32(v[0], s[0]),
-      # v_add_f16_e32 v[1], 1.0, v[0]  -- 1.0 must be F16 0x3c00, not F32 0x3f800000
-      v_add_f16_e32(v[1], 1.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xFFFF
-    # 1.0 + 1.0 = 2.0, f16 2.0 = 0x4000
-    self.assertEqual(result, 0x4000, f"Expected f16(2.0)=0x4000, got 0x{result:04x}")
-
-  def test_v_add_f16_inline_constant_2_0(self):
-    """V_ADD_F16_E32 with inline constant 2.0."""
-    instructions = [
-      s_mov_b32(s[0], 0x4200),  # f16 3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_add_f16_e32(v[1], 2.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xFFFF
-    # 2.0 + 3.0 = 5.0, f16 5.0 = 0x4500
-    self.assertEqual(result, 0x4500, f"Expected f16(5.0)=0x4500, got 0x{result:04x}")
-
-  def test_v_mul_f16_inline_constant(self):
-    """V_MUL_F16_E32 with inline constant 2.0."""
-    instructions = [
-      s_mov_b32(s[0], 0x4200),  # f16 3.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mul_f16_e32(v[1], 2.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][1] & 0xFFFF
-    # 2.0 * 3.0 = 6.0, f16 6.0 = 0x4600
-    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
-
-
-class TestCndmask(unittest.TestCase):
-  """Tests for V_CNDMASK_B32 and V_CNDMASK_B16."""
-
-  def test_v_cndmask_b16_select_src0(self):
-    """V_CNDMASK_B16 selects src0 when VCC bit is 0."""
-    instructions = [
-      s_mov_b32(VCC_LO, 0),  # VCC = 0
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cndmask_b16(v[2], v[0], v[1], VCC),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x3c00, f"Expected src0=0x3c00, got 0x{result:04x}")
-
-  def test_v_cndmask_b16_select_src1(self):
-    """V_CNDMASK_B16 selects src1 when VCC bit is 1."""
-    instructions = [
-      s_mov_b32(VCC_LO, 1),  # VCC = 1
-      s_mov_b32(s[0], 0x3c00),  # f16 1.0
-      s_mov_b32(s[1], 0x4000),  # f16 2.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cndmask_b16(v[2], v[0], v[1], VCC),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    result = st.vgpr[0][2] & 0xffff
-    self.assertEqual(result, 0x4000, f"Expected src1=0x4000, got 0x{result:04x}")
-
-  def test_v_cndmask_b16_write_hi(self):
-    """V_CNDMASK_B16 can write to high 16 bits with opsel."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c003800),  # src0: hi=1.0, lo=0.5
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x4000c000),  # src1: hi=2.0, lo=-2.0
-      v_mov_b32_e32(v[1], s[1]),
-      s_mov_b32(s[2], 0xDEAD0000),  # v2 initial: hi=0xDEAD, lo=0
-      v_mov_b32_e32(v[2], s[2]),
-      s_mov_b32(VCC_LO, 0),  # vcc = 0, select src0
-      # opsel=0b1011: bit0=src0 hi, bit1=src1 hi, bit3=dst hi
-      VOP3(VOP3Op.V_CNDMASK_B16, vdst=v[2], src0=v[0], src1=v[1], src2=SrcEnum.VCC_LO, opsel=0b1011),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    hi = (st.vgpr[0][2] >> 16) & 0xffff
-    lo = st.vgpr[0][2] & 0xffff
-    # vcc=0 selects src0.h = 1.0 = 0x3c00, writes to hi
-    self.assertEqual(hi, 0x3c00, f"Expected hi=0x3c00 (1.0), got 0x{hi:04x}")
-    self.assertEqual(lo, 0x0000, f"Expected lo preserved as 0, got 0x{lo:04x}")
-
-
-class TestSpecialFloatValues(unittest.TestCase):
-  """Tests for special float value handling in VOP2 instructions."""
-
-  def test_neg_zero_add(self):
-    """-0.0 + 0.0 = +0.0 (IEEE 754)."""
-    neg_zero = 0x80000000
-    instructions = [
-      s_mov_b32(s[0], neg_zero),
-      v_mov_b32_e32(v[0], s[0]),
-      v_add_f32_e32(v[1], 0.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x00000000, "Should be +0.0")
-
-  def test_neg_zero_mul(self):
-    """-0.0 * -1.0 = +0.0."""
-    neg_zero = 0x80000000
-    instructions = [
-      s_mov_b32(s[0], neg_zero),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mul_f32_e32(v[1], -1.0, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x00000000, "Should be +0.0")
-
-  def test_inf_minus_inf(self):
-    """+inf - inf = NaN."""
-    import math
-    pos_inf = 0x7f800000
-    neg_inf = 0xff800000
-    instructions = [
-      s_mov_b32(s[0], pos_inf),
-      s_mov_b32(s[1], neg_inf),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_sub_f32_e32(v[2], v[0], v[1]),  # inf - (-inf) = inf
-      v_add_f32_e32(v[3], v[0], v[1]),  # inf + (-inf) = NaN
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], pos_inf, "inf - (-inf) = inf")
-    self.assertTrue(math.isnan(i2f(st.vgpr[0][3])), "inf + (-inf) = NaN")
-
-  def test_denormal_f32_mul_ftz(self):
-    """Denormal * normal - RDNA3 flushes denormals to zero (FTZ mode)."""
-    smallest_denorm = 0x00000001  # Smallest positive denormal
-    instructions = [
-      s_mov_b32(s[0], smallest_denorm),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mul_f32_e32(v[1], 2.0, v[0]),  # Denormal input gets flushed to 0
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][1], 0x00000000)
-
-
-class TestCarryOps(unittest.TestCase):
-  """Tests for VOP2 carry instructions (v_add_co_ci_u32, v_sub_co_ci_u32, v_subrev_co_ci_u32)."""
-
-  def test_v_subrev_co_ci_u32_no_borrow(self):
-    """V_SUBREV_CO_CI_U32: D0 = S1 - S0 - VCC_IN, when VCC_IN=0."""
-    instructions = [
-      s_mov_b32(VCC_LO, 0),  # VCC = 0 (no borrow in)
-      v_mov_b32_e32(v[0], 5),  # S0 = 5
-      v_mov_b32_e32(v[1], 10),  # S1 = 10
-      v_subrev_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 10 - 5 - 0 = 5
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 5)
-    self.assertEqual(st.vcc, 0)  # No borrow out
-
-  def test_v_subrev_co_ci_u32_with_borrow(self):
-    """V_SUBREV_CO_CI_U32: D0 = S1 - S0 - VCC_IN, when VCC_IN=1."""
-    instructions = [
-      s_mov_b32(VCC_LO, 1),  # VCC = 1 (borrow in)
-      v_mov_b32_e32(v[0], 5),  # S0 = 5
-      v_mov_b32_e32(v[1], 10),  # S1 = 10
-      v_subrev_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 10 - 5 - 1 = 4
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 4)
-    self.assertEqual(st.vcc, 0)  # No borrow out
-
-  def test_v_subrev_co_ci_u32_generates_borrow(self):
-    """V_SUBREV_CO_CI_U32: generates borrow when S0 + VCC_IN > S1."""
-    instructions = [
-      s_mov_b32(VCC_LO, 0),  # VCC = 0
-      v_mov_b32_e32(v[0], 10),  # S0 = 10
-      v_mov_b32_e32(v[1], 5),  # S1 = 5
-      v_subrev_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 5 - 10 - 0 = -5 (underflow)
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0xFFFFFFFB)  # -5 as unsigned
-    self.assertEqual(st.vcc, 1)  # Borrow out
-
-  def test_v_add_co_ci_u32_no_carry(self):
-    """V_ADD_CO_CI_U32: D0 = S0 + S1 + VCC_IN, when VCC_IN=0."""
-    instructions = [
-      s_mov_b32(VCC_LO, 0),  # VCC = 0 (no carry in)
-      v_mov_b32_e32(v[0], 5),  # S0 = 5
-      v_mov_b32_e32(v[1], 10),  # S1 = 10
-      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 5 + 10 + 0 = 15
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 15)
-    self.assertEqual(st.vcc, 0)  # No carry out
-
-  def test_v_add_co_ci_u32_with_carry(self):
-    """V_ADD_CO_CI_U32: D0 = S0 + S1 + VCC_IN, when VCC_IN=1."""
-    instructions = [
-      s_mov_b32(VCC_LO, 1),  # VCC = 1 (carry in)
-      v_mov_b32_e32(v[0], 5),  # S0 = 5
-      v_mov_b32_e32(v[1], 10),  # S1 = 10
-      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 5 + 10 + 1 = 16
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 16)
-    self.assertEqual(st.vcc, 0)  # No carry out
-
-  def test_v_add_co_ci_u32_generates_carry(self):
-    """V_ADD_CO_CI_U32: generates carry when overflow occurs."""
-    instructions = [
-      s_mov_b32(VCC_LO, 1),  # VCC = 1 (carry in)
-      s_mov_b32(s[0], 0xFFFFFFFF),  # max u32
-      v_mov_b32_e32(v[0], s[0]),  # S0 = 0xFFFFFFFF
-      v_mov_b32_e32(v[1], 0),  # S1 = 0
-      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 0xFFFFFFFF + 0 + 1 = 0 (overflow)
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0)  # Overflowed to 0
-    self.assertEqual(st.vcc, 1)  # Carry out
-
-  def test_v_add_co_ci_u32_clears_carry(self):
-    """V_ADD_CO_CI_U32: VCC must be updated even when no carry is generated.
-
-    This tests the case where VCC=1 going in (carry-in consumed) but the addition
-    does not overflow, so VCC must be cleared to 0.
-
-    Regression test for: VCC not being written by v_add_co_ci_u32_e32.
-    """
-    instructions = [
-      s_mov_b32(VCC_LO, 1),  # VCC = 1 (carry in)
-      v_mov_b32_e32(v[0], 1),  # S0 = 1
-      v_mov_b32_e32(v[1], 1),  # S1 = 1
-      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 1 + 1 + 1 = 3 (no overflow)
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 3)  # 1 + 1 + 1 = 3
-    self.assertEqual(st.vcc, 0)  # No carry out - VCC must be cleared
-
-  def test_v_add_co_ci_u32_multilane_clears_vcc(self):
-    """V_ADD_CO_CI_U32 with multiple lanes: VCC bits must be updated per-lane.
-
-    When VCC has multiple bits set (one per active lane), and the addition doesn't
-    overflow for any lane, all VCC bits must be cleared.
-
-    Regression test for: VCC not being written by v_add_co_ci_u32_e32 in multi-lane case.
-    """
-    instructions = [
-      s_mov_b32(VCC_LO, 0b11),  # VCC = 0b11 (lanes 0,1 have carry-in)
-      v_mov_b32_e32(v[0], 1),  # S0 = 1 for all lanes
-      v_mov_b32_e32(v[1], 1),  # S1 = 1 for all lanes
-      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 1 + 1 + 1 = 3 (no overflow)
-    ]
-    st = run_program(instructions, n_lanes=2)
-    self.assertEqual(st.vgpr[0][2], 3)  # lane 0: 1 + 1 + 1 = 3
-    self.assertEqual(st.vgpr[1][2], 3)  # lane 1: 1 + 1 + 1 = 3
-    self.assertEqual(st.vcc, 0)  # No carry out for any lane - all VCC bits must be cleared
-
-  def test_v_add_co_ci_u32_preserves_inactive_vcc_bits(self):
-    """V_ADD_CO_CI_U32: VCC carry-out overwrites entire VCC register.
-
-    VOP2 carry instructions write ALL VCC bits based on carry-out, clearing
-    bits for lanes that don't overflow regardless of EXEC mask.
-
-    Note: This differs from VOPC which only writes active lane bits.
-    """
-    instructions = [
-      s_mov_b32(VCC_LO, 0x00010000),  # VCC bit 16 set
-      v_mov_b32_e32(v[0], 1),  # S0 = 1
-      v_mov_b32_e32(v[1], 1),  # S1 = 1
-      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 1 + 1 + 0 = 2 (no carry)
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.vgpr[0][2], 2)  # lane 0: 1 + 1 + 0 = 2
-    # VCC should be completely cleared (all lanes have no carry-out)
-    self.assertEqual(st.vcc, 0)
-
-  def test_v_add_co_ci_u32_all_lanes_same_result(self):
-    """V_ADD_CO_CI_U32: all active lanes should produce the same result.
-
-    When the same constant inputs are used across all lanes, each lane should
-    compute the same result and write to its own VGPR slot.
-
-    Regression test for: VGPR writes not happening for all lanes.
-    """
-    instructions = [
-      s_mov_b32(VCC_LO, 0),  # No carry-in
-      v_mov_b32_e32(v[0], 3),  # inline constant 3
-      v_mov_b32_e32(v[1], 5),  # value 5
-      v_add_co_ci_u32_e32(v[1], 3, v[1]),  # v[1] = 3 + v[1] + 0 = 3 + 5 = 8
-    ]
-    st = run_program(instructions, n_lanes=4)
-    # All 4 lanes should have v[1] = 8
-    for lane in range(4):
-      self.assertEqual(st.vgpr[lane][1], 8, f"lane {lane} should have v[1]=8")
-
-  def test_v_sub_co_ci_u32_no_borrow(self):
-    """V_SUB_CO_CI_U32: D0 = S0 - S1 - VCC_IN, when VCC_IN=0."""
-    instructions = [
-      s_mov_b32(VCC_LO, 0),  # VCC = 0 (no borrow in)
-      v_mov_b32_e32(v[0], 10),  # S0 = 10
-      v_mov_b32_e32(v[1], 5),  # S1 = 5
-      v_sub_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 10 - 5 - 0 = 5
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 5)
-    self.assertEqual(st.vcc, 0)  # No borrow out
-
-  def test_v_sub_co_ci_u32_vop3sd_separate_carry_regs(self):
-    """VOP3SD V_SUB_CO_CI_U32: carry-in from src2, carry-out to sdst (separate registers).
-
-    This tests the VOP3SD encoding where src2 specifies the carry-in register
-    independently from sdst (carry-out). The bug was reading carry-in from sdst
-    instead of src2.
-
-    Computation: D0 = S0 - S1 - carry_in = 0 - 0 - 1 = -1 = 0xFFFFFFFF
-    """
-    instructions = [
-      s_mov_b32(s[6], 1),  # carry-in = 1 (in s[6])
-      s_mov_b32(s[10], 0),  # carry-out dest = 0 initially (in s[10])
-      # VOP3SD: v_sub_co_ci_u32(vdst, sdst, src0, src1, src2)
-      # src2 is carry-in (s[6]=1), sdst is carry-out (s[10])
-      v_sub_co_ci_u32(v[0], s[10], 0, 0, s[6]),  # D0 = 0 - 0 - 1 = -1
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF)  # -1 as unsigned
-    self.assertEqual(st.sgpr[10], 1)  # Borrow out to s[10]
-
-  def test_v_add_co_ci_u32_vop3sd_separate_carry_regs(self):
-    """VOP3SD V_ADD_CO_CI_U32: carry-in from src2, carry-out to sdst (separate registers).
-
-    This tests the VOP3SD encoding where src2 specifies the carry-in register
-    independently from sdst (carry-out).
-
-    Computation: D0 = S0 + S1 + carry_in = 5 + 10 + 1 = 16
-    """
-    instructions = [
-      s_mov_b32(s[6], 1),  # carry-in = 1 (in s[6])
-      s_mov_b32(s[10], 0),  # carry-out dest = 0 initially (in s[10])
-      # VOP3SD: v_add_co_ci_u32(vdst, sdst, src0, src1, src2)
-      v_add_co_ci_u32(v[0], s[10], 5, 10, s[6]),  # D0 = 5 + 10 + 1 = 16
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 16)
-    self.assertEqual(st.sgpr[10], 0)  # No carry out
-
-  def test_v_add_co_ci_u32_vop3sd_null_sdst(self):
-    """VOP3SD V_ADD_CO_CI_U32 with sdst=NULL: carry output is discarded.
-
-    When sdst=NULL (register 124), the carry-out should NOT be written anywhere.
-    We verify this by checking that VCC (which we set to a sentinel value) is unchanged.
-    """
-    instructions = [
-      s_mov_b32(VCC_LO, 0xDEADBEEF),  # Sentinel value in VCC
-      s_mov_b32(s[6], 0),  # carry-in = 0
-      # VOP3SD with NULL sdst: carry-out should be discarded
-      # Uses 0xFFFFFFFF + 1 + 0 = 0 with carry-out=1, but carry should not be written
-      v_add_co_ci_u32(v[0], NULL, 0xFFFFFFFF, 1, s[6]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][0], 0)  # 0xFFFFFFFF + 1 + 0 = 0 (overflow)
-    self.assertEqual(st.vcc, 0xDEADBEEF)  # VCC unchanged - carry was discarded
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,936 +0,0 @@
-"""Tests for VOPC instructions - vector compare operations.
-
-Includes: v_cmp_class_f32, v_cmp_class_f16, v_cmp_eq_*, v_cmp_lt_*, v_cmp_gt_*
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import *
-
-VCC = 106  # SGPR index for VCC_LO
-
-class TestCmpClass(unittest.TestCase):
-  """Tests for V_CMP_CLASS_F32 float classification."""
-
-  def test_cmp_class_quiet_nan(self):
-    """V_CMP_CLASS_F32 detects quiet NaN."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000010),  # bit 1 = quiet NaN
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect quiet NaN")
-
-  def test_cmp_class_signaling_nan(self):
-    """V_CMP_CLASS_F32 detects signaling NaN."""
-    signal_nan = 0x7f800001
-    instructions = [
-      s_mov_b32(s[0], signal_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000001),  # bit 0 = signaling NaN
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect signaling NaN")
-
-  def test_cmp_class_positive_inf(self):
-    """V_CMP_CLASS_F32 detects +inf."""
-    pos_inf = 0x7f800000
-    instructions = [
-      s_mov_b32(s[0], pos_inf),
-      s_mov_b32(s[1], 0b1000000000),  # bit 9 = +inf
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect +inf")
-
-  def test_cmp_class_negative_inf(self):
-    """V_CMP_CLASS_F32 detects -inf."""
-    neg_inf = 0xff800000
-    instructions = [
-      s_mov_b32(s[0], neg_inf),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000100),  # bit 2 = -inf
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect -inf")
-
-  def test_cmp_class_normal_positive(self):
-    """V_CMP_CLASS_F32 detects positive normal."""
-    instructions = [
-      v_mov_b32_e32(v[0], 1.0),
-      s_mov_b32(s[1], 0b0100000000),  # bit 8 = positive normal
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive normal")
-
-  def test_cmp_class_normal_negative(self):
-    """V_CMP_CLASS_F32 detects negative normal."""
-    instructions = [
-      v_mov_b32_e32(v[0], -1.0),
-      v_mov_b32_e32(v[1], 0b0000001000),  # bit 3 = negative normal
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative normal")
-
-  def test_cmp_class_quiet_nan_not_signaling(self):
-    """Quiet NaN does not match signaling NaN mask."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000001),  # bit 0 = signaling NaN only
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "Quiet NaN should not match signaling mask")
-
-  def test_cmp_class_signaling_nan_not_quiet(self):
-    """Signaling NaN does not match quiet NaN mask."""
-    signal_nan = 0x7f800001
-    instructions = [
-      s_mov_b32(s[0], signal_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0b0000000010),  # bit 1 = quiet NaN only
-      v_cmp_class_f32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "Signaling NaN should not match quiet mask")
-
-  def test_v_cmp_sets_vcc_bits(self):
-    """V_CMP_EQ sets VCC bits based on per-lane comparison."""
-    instructions = [
-      s_mov_b32(s[0], 5),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cmp_eq_u32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should match")
-
-
-class TestCmpClassF16(unittest.TestCase):
-  """Tests for V_CMP_CLASS_F16 float classification.
-
-  Class bit mapping:
-    bit 0 = signaling NaN
-    bit 1 = quiet NaN
-    bit 2 = -infinity
-    bit 3 = -normal
-    bit 4 = -denormal
-    bit 5 = -zero
-    bit 6 = +zero
-    bit 7 = +denormal
-    bit 8 = +normal
-    bit 9 = +infinity
-  """
-
-  def test_cmp_class_f16_positive_zero(self):
-    """V_CMP_CLASS_F16: +zero matches bit 6."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0x0000),  # f16 +0.0
-      v_mov_b32_e32(v[1], 0x40),     # bit 6 = +zero
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive zero")
-
-  def test_cmp_class_f16_negative_zero(self):
-    """V_CMP_CLASS_F16: -zero matches bit 5."""
-    instructions = [
-      s_mov_b32(s[0], 0x8000),       # f16 -0.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x20),     # bit 5 = -zero
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative zero")
-
-  def test_cmp_class_f16_positive_normal(self):
-    """V_CMP_CLASS_F16: +1.0 (normal) matches bit 8."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),       # f16 +1.0
-      s_mov_b32(s[1], 0x100),        # bit 8 = +normal
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive normal")
-
-  def test_cmp_class_f16_negative_normal(self):
-    """V_CMP_CLASS_F16: -1.0 (normal) matches bit 3."""
-    instructions = [
-      s_mov_b32(s[0], 0xbc00),       # f16 -1.0
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x08),     # bit 3 = -normal
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative normal")
-
-  def test_cmp_class_f16_positive_infinity(self):
-    """V_CMP_CLASS_F16: +inf matches bit 9."""
-    instructions = [
-      s_mov_b32(s[0], 0x7c00),       # f16 +inf
-      s_mov_b32(s[1], 0x200),        # bit 9 = +inf
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive infinity")
-
-  def test_cmp_class_f16_negative_infinity(self):
-    """V_CMP_CLASS_F16: -inf matches bit 2."""
-    instructions = [
-      s_mov_b32(s[0], 0xfc00),       # f16 -inf
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x04),     # bit 2 = -inf
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative infinity")
-
-  def test_cmp_class_f16_quiet_nan(self):
-    """V_CMP_CLASS_F16: quiet NaN matches bit 1."""
-    instructions = [
-      s_mov_b32(s[0], 0x7e00),       # f16 quiet NaN
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x02),     # bit 1 = quiet NaN
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect quiet NaN")
-
-  def test_cmp_class_f16_signaling_nan(self):
-    """V_CMP_CLASS_F16: signaling NaN matches bit 0."""
-    instructions = [
-      s_mov_b32(s[0], 0x7c01),       # f16 signaling NaN
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x01),     # bit 0 = signaling NaN
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect signaling NaN")
-
-  def test_cmp_class_f16_positive_denormal(self):
-    """V_CMP_CLASS_F16: positive denormal matches bit 7."""
-    instructions = [
-      v_mov_b32_e32(v[0], 1),        # f16 +denormal (0x0001)
-      v_mov_b32_e32(v[1], 0x80),     # bit 7 = +denormal
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect positive denormal")
-
-  def test_cmp_class_f16_negative_denormal(self):
-    """V_CMP_CLASS_F16: negative denormal matches bit 4."""
-    instructions = [
-      s_mov_b32(s[0], 0x8001),       # f16 -denormal
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], 0x10),     # bit 4 = -denormal
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Should detect negative denormal")
-
-  def test_cmp_class_f16_combined_mask_zeros(self):
-    """V_CMP_CLASS_F16: mask 0x60 covers both +zero and -zero."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),         # f16 +0.0
-      v_mov_b32_e32(v[1], 0x60),      # bits 5 and 6 (+-zero)
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with mask 0x60")
-
-  def test_cmp_class_f16_combined_mask_1f8(self):
-    """V_CMP_CLASS_F16: mask 0x1f8 covers -normal,-denorm,-zero,+zero,+denorm,+normal.
-
-    This is the exact mask used in the f16 sin kernel at PC=46.
-    """
-    instructions = [
-      v_mov_b32_e32(v[0], 0),         # f16 +0.0
-      s_mov_b32(s[0], 0x1f8),
-      v_mov_b32_e32(v[1], s[0]),      # mask 0x1f8
-      v_cmp_class_f16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with mask 0x1f8")
-
-  def test_cmp_class_f16_vop3_encoding(self):
-    """V_CMP_CLASS_F16 in VOP3 encoding (v_cmp_class_f16_e64)."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0),         # f16 +0.0
-      s_mov_b32(s[0], 0x1f8),         # class mask
-      v_cmp_class_f16_e64(VCC_LO, v[0], s[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with VOP3 encoding")
-
-  def test_cmp_class_f16_vop3_normal_positive(self):
-    """V_CMP_CLASS_F16 VOP3 encoding with +1.0 (normal)."""
-    instructions = [
-      s_mov_b32(s[0], 0x3c00),        # f16 +1.0
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x1f8),         # class mask
-      v_cmp_class_f16_e64(VCC_LO, v[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +1.0 (normal) with mask 0x1f8")
-
-  def test_cmp_class_f16_vop3_nan_fails_mask(self):
-    """V_CMP_CLASS_F16 VOP3: NaN should NOT match mask 0x1f8 (no NaN bits set)."""
-    instructions = [
-      s_mov_b32(s[0], 0x7e00),        # f16 quiet NaN
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x1f8),         # class mask
-      v_cmp_class_f16_e64(VCC_LO, v[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "VCC should be 0 for NaN with mask 0x1f8 (no NaN bits)")
-
-  def test_cmp_class_f16_vop3_inf_fails_mask(self):
-    """V_CMP_CLASS_F16 VOP3: +inf should NOT match mask 0x1f8 (no inf bits set)."""
-    instructions = [
-      s_mov_b32(s[0], 0x7c00),        # f16 +inf
-      v_mov_b32_e32(v[0], s[0]),
-      s_mov_b32(s[1], 0x1f8),         # class mask
-      v_cmp_class_f16_e64(VCC_LO, v[0], s[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "VCC should be 0 for +inf with mask 0x1f8 (no inf bits)")
-
-
-class TestCmpInt(unittest.TestCase):
-  """Tests for integer comparison operations."""
-
-  def test_v_cmp_eq_u32(self):
-    """V_CMP_EQ_U32 sets VCC bits based on per-lane comparison."""
-    instructions = [
-      s_mov_b32(s[0], 5),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cmp_eq_u32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should match")
-
-  def test_v_cmp_ne_u32_with_zero(self):
-    """V_CMP_NE_U32: compare with zero, used for int->bool cast."""
-    instructions = [
-      v_mov_b32_e32(v[1], 0),
-      v_cmp_eq_u32_e32(1, v[255]),  # vcc = (lane == 1)
-      v_cndmask_b32_e64(v[1], v[1], 1, VCC_LO),  # v1[lane1] = 1
-      v_cmp_ne_u32_e32(0, v[1]),  # vcc = (0 != v1)
-      v_cndmask_b32_e64(v[0], 0, 1, VCC_LO),  # v0 = vcc ? 1 : 0
-    ]
-    st = run_program(instructions, n_lanes=2)
-    self.assertEqual(st.vgpr[0][0], 0, "lane 0: 0 != 0 should be false")
-    self.assertEqual(st.vgpr[1][0], 1, "lane 1: 0 != 1 should be true")
-    self.assertEqual(st.vcc & 0x3, 0x2, "VCC should be 0b10")
-
-  def test_v_cmp_ne_u32_all_nonzero(self):
-    """V_CMP_NE_U32: all lanes have nonzero values."""
-    instructions = [
-      v_mov_b32_e32(v[1], 5),
-      v_cmp_ne_u32_e32(0, v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should be != 0")
-
-  def test_cmp_eq_u16_opsel_lo_lo(self):
-    """V_CMP_EQ_U16 comparing lo halves."""
-    instructions = [
-      s_mov_b32(s[0], 0x12340005),  # lo=5, hi=0x1234
-      s_mov_b32(s[1], 0xABCD0005),  # lo=5, hi=0xABCD
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[1]),
-      v_cmp_eq_u16_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Lo halves should be equal")
-
-  def test_cmp_eq_u16_opsel_hi_hi(self):
-    """V_CMP_EQ_U16 comparing hi halves with VOP3 opsel."""
-    instructions = [
-      s_mov_b32(s[2], 0x00051234),  # hi=5, lo=0x1234
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x0005ABCD),  # hi=5, lo=0xABCD
-      v_mov_b32_e32(v[1], s[2]),
-      v_cmp_eq_u16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "Hi halves should be equal: 5==5")
-
-  def test_cmp_eq_u16_opsel_hi_hi_equal(self):
-    """V_CMP_EQ_U16 VOP3 with opsel=3 compares hi halves (equal case)."""
-    instructions = [
-      s_mov_b32(s[2], 0x12340005),  # lo=5, hi=0x1234
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x12340009),  # lo=9, hi=0x1234
-      v_mov_b32_e32(v[1], s[2]),
-      v_cmp_eq_u16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "hi==hi should be true: 0x1234==0x1234")
-
-  def test_cmp_gt_u16_opsel_hi(self):
-    """V_CMP_GT_U16 VOP3 with opsel=3 compares hi halves."""
-    instructions = [
-      s_mov_b32(s[2], 0x99990005),  # lo=5, hi=0x9999
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x12340005),  # lo=5, hi=0x1234
-      v_mov_b32_e32(v[1], s[2]),
-      v_cmp_gt_u16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "hi>hi should be true: 0x9999>0x1234")
-
-
-class TestCmpFloat(unittest.TestCase):
-  """Tests for float comparison operations."""
-
-  def test_v_cmp_lt_f16_vsrc1_hi(self):
-    """V_CMP_LT_F16 with both operands from high half using VOP3 opsel."""
-    instructions = [
-      s_mov_b32(s[2], 0x3c000000),  # hi=1.0 (f16), lo=0
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x40000000),  # hi=2.0 (f16), lo=0
-      v_mov_b32_e32(v[1], s[2]),
-      v_cmp_lt_f16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "1.0 < 2.0 should be true")
-
-  def test_v_cmp_gt_f16_vsrc1_hi(self):
-    """V_CMP_GT_F16 with both operands from high half using VOP3 opsel."""
-    instructions = [
-      s_mov_b32(s[2], 0x40000000),  # hi=2.0 (f16), lo=0
-      v_mov_b32_e32(v[0], s[2]),
-      s_mov_b32(s[2], 0x3c000000),  # hi=1.0 (f16), lo=0
-      v_mov_b32_e32(v[1], s[2]),
-      v_cmp_gt_f16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.sgpr[0] & 1, 1, "2.0 > 1.0 should be true")
-
-  def test_v_cmp_eq_f16_vsrc1_hi_equal(self):
-    """v_cmp_eq_f16 with equal low and high halves."""
-    instructions = [
-      s_mov_b32(s[0], 0x42004200),  # hi=3.0 (0x4200), lo=3.0 (0x4200)
-      v_mov_b32_e32(v[0], s[0]),
-      v_cmp_eq_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Expected vcc=1 (3.0 == 3.0)")
-
-  def test_v_cmp_neq_f16_vsrc1_hi(self):
-    """v_cmp_neq_f16 with different low and high halves."""
-    instructions = [
-      s_mov_b32(s[0], 0x40003c00),  # hi=2.0 (0x4000), lo=1.0 (0x3c00)
-      v_mov_b32_e32(v[0], s[0]),
-      v_cmp_lg_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "Expected vcc=1 (1.0 != 2.0)")
-
-  def test_v_cmp_nge_f16_inf_self(self):
-    """v_cmp_nge_f16 comparing -inf with itself (unordered less than).
-
-    Regression test: -inf < -inf should be false (IEEE 754).
-    """
-    instructions = [
-      s_mov_b32(s[0], 0xFC00FC00),  # both halves = -inf (0xFC00)
-      v_mov_b32_e32(v[0], s[0]),
-      v_cmp_nge_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "Expected vcc=0 (-inf >= -inf)")
-
-  def test_v_cmp_f16_multilane(self):
-    """v_cmp_lt_f16 with vsrc1=v128 across multiple lanes."""
-    instructions = [
-      # Lane 0: v0 = 0x40003c00 (hi=2.0, lo=1.0) -> 1.0 < 2.0 = true
-      # Lane 1: v0 = 0x3c004000 (hi=1.0, lo=2.0) -> 2.0 < 1.0 = false
-      v_mov_b32_e32(v[0], 0x40003c00),  # default
-      v_cmp_eq_u32_e32(1, v[255]),  # vcc = (lane == 1)
-      v_cndmask_b32_e64(v[0], v[0], 0x3c004000, SrcEnum.VCC_LO),
-      v_cmp_lt_f16_e32(v[0], v[0].h),
-    ]
-    st = run_program(instructions, n_lanes=2)
-    self.assertEqual(st.vcc & 1, 1, "Lane 0: expected vcc=1 (1.0 < 2.0)")
-    self.assertEqual((st.vcc >> 1) & 1, 0, "Lane 1: expected vcc=0 (2.0 < 1.0)")
-
-
-class TestVOP3VOPCModifiers(unittest.TestCase):
-  """Tests for VOP3 VOPC with abs/neg modifiers."""
-
-  def test_v_cmp_ge_f32_abs_both(self):
-    """v_cmp_ge_f32 with abs on both sources: abs(0.0) >= abs(-1.0) = false.
-
-    Regression test: int16 mod operation uses v_cmp_ge_f32 with abs modifiers.
-    """
-    instructions = [
-      v_mov_b32_e32(v[0], 0.0),
-      v_mov_b32_e32(v[1], -1.0),
-      # abs=0b11 means abs(src0) and abs(src1)
-      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "abs(0.0) >= abs(-1.0) should be false")
-
-  def test_v_cmp_ge_f32_abs_negative_divisor(self):
-    """v_cmp_ge_f32 with abs: remainder check for negative divisor.
-
-    Tests the exact comparison used in int16 mod: abs(rem_f) >= abs(div_f).
-    For 1 % -1: rem_f = 0.0, div_f = -1.0, so abs(0.0) >= abs(-1.0) = false.
-    """
-    instructions = [
-      v_mov_b32_e32(v[0], 0.0),    # remainder as float
-      v_mov_b32_e32(v[1], -1.0),   # divisor as float
-      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "abs(0.0) >= abs(-1.0) should be false")
-
-  def test_v_cmp_ge_f32_abs_small_remainder(self):
-    """v_cmp_ge_f32 with abs: abs(-0.5) >= abs(-3.0) = false."""
-    instructions = [
-      v_mov_b32_e32(v[0], -0.5),
-      v_mov_b32_e32(v[1], -3.0),
-      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "abs(-0.5) >= abs(-3.0) should be false")
-
-  def test_v_cmp_ge_f32_abs_equal(self):
-    """v_cmp_ge_f32 with abs: abs(-1.0) >= abs(1.0) = true."""
-    instructions = [
-      v_mov_b32_e32(v[0], -1.0),
-      v_mov_b32_e32(v[1], 1.0),
-      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "abs(-1.0) >= abs(1.0) should be true")
-
-
-class TestVOP3VOPC64Bit(unittest.TestCase):
-  """Tests for VOP3 VOPC with 64-bit operands."""
-
-  def test_v_cmp_lt_f64_basic(self):
-    """v_cmp_lt_f64: 0.0 < 1.0 = true."""
-    zero_f64 = f2i64(0.0)
-    one_f64 = f2i64(1.0)
-    instructions = [
-      s_mov_b32(s[0], zero_f64 & 0xffffffff),
-      s_mov_b32(s[1], zero_f64 >> 32),
-      s_mov_b32(s[2], one_f64 & 0xffffffff),
-      s_mov_b32(s[3], one_f64 >> 32),
-      v_cmp_lt_f64_e64(VCC_LO, s[0:1], s[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "0.0 < 1.0 should be true")
-
-  def test_v_cmp_lt_f64_negative(self):
-    """v_cmp_lt_f64: -1.0 < 0.0 = true."""
-    neg_one_f64 = f2i64(-1.0)
-    zero_f64 = f2i64(0.0)
-    instructions = [
-      s_mov_b32(s[0], neg_one_f64 & 0xffffffff),
-      s_mov_b32(s[1], neg_one_f64 >> 32),
-      s_mov_b32(s[2], zero_f64 & 0xffffffff),
-      s_mov_b32(s[3], zero_f64 >> 32),
-      v_cmp_lt_f64_e64(VCC_LO, s[0:1], s[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "-1.0 < 0.0 should be true")
-
-  def test_v_cmp_lt_i64_signed(self):
-    """v_cmp_lt_i64: 0 < -1 (signed) = false."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_mov_b32(s[1], 0),              # s[0:1] = 0
-      s_mov_b32(s[2], 0xffffffff),
-      s_mov_b32(s[3], 0xffffffff),     # s[2:3] = -1
-      v_cmp_lt_i64_e64(VCC_LO, s[0:1], s[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "0 < -1 (signed) should be false")
-
-  def test_v_cmp_lt_u64_unsigned(self):
-    """v_cmp_lt_u64: 0 < 0xFFFFFFFFFFFFFFFF (unsigned) = true."""
-    instructions = [
-      s_mov_b32(s[0], 0),
-      s_mov_b32(s[1], 0),              # s[0:1] = 0
-      s_mov_b32(s[2], 0xffffffff),
-      s_mov_b32(s[3], 0xffffffff),     # s[2:3] = max uint64
-      v_cmp_lt_u64_e64(VCC_LO, s[0:1], s[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "0 < max_uint64 should be true")
-
-
-class TestVOPCF64(unittest.TestCase):
-  """Tests for VOPC (E32 encoding) with 64-bit float operands. Regression test for f64 compare bug."""
-
-  def test_v_cmp_lt_f64_e32_true(self):
-    """v_cmp_lt_f64_e32: 2.0 < 3.0 = true."""
-    lo0, hi0 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
-    lo1, hi1 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
-    instructions = [
-      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
-      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
-      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
-      v_cmp_lt_f64_e32(v[0:1], v[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "2.0 < 3.0 should be true")
-
-  def test_v_cmp_lt_f64_e32_false(self):
-    """v_cmp_lt_f64_e32: 3.0 < 2.0 = false."""
-    lo0, hi0 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
-    lo1, hi1 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
-    instructions = [
-      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
-      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
-      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
-      v_cmp_lt_f64_e32(v[0:1], v[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "3.0 < 2.0 should be false")
-
-  def test_v_cmp_nlt_f64_e32_true(self):
-    """v_cmp_nlt_f64_e32: !(3.0 < 2.0) = true."""
-    lo0, hi0 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
-    lo1, hi1 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
-    instructions = [
-      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
-      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
-      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
-      v_cmp_nlt_f64_e32(v[0:1], v[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "!(3.0 < 2.0) should be true")
-
-  def test_v_cmp_nlt_f64_e32_false(self):
-    """v_cmp_nlt_f64_e32: !(2.0 < 3.0) = false."""
-    lo0, hi0 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
-    lo1, hi1 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
-    instructions = [
-      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
-      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
-      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
-      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
-      v_cmp_nlt_f64_e32(v[0:1], v[2:3]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "!(2.0 < 3.0) should be false")
-
-
-class TestCmpxExec(unittest.TestCase):
-  """Tests for V_CMPX instructions that modify EXEC mask."""
-
-  def test_v_cmpx_ngt_f32_e64_all_true(self):
-    """V_CMPX_NGT_F32_E64: all lanes pass (literal <= all values)."""
-    # 131072.0 = 0x48000000
-    # All values > 131072, so !(131072 > val) = true for all
-    instructions = [
-      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
-      v_mov_b32_e32(v[0], f2i(200000.0)),  # lane 0
-      v_cmp_eq_u32_e32(1, v[255]),
-      v_cndmask_b32_e64(v[1], v[0], f2i(300000.0), VCC_LO),  # lane 1
-      v_cmp_eq_u32_e32(2, v[255]),
-      v_cndmask_b32_e64(v[1], v[1], f2i(400000.0), VCC_LO),  # lane 2
-      # Now v[1] has: lane0=200000, lane1=300000, lane2=400000
-      # Compare: !(131072.0 > v[1]) i.e., 131072.0 <= v[1]
-      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[1]),
-    ]
-    st = run_program(instructions, n_lanes=3)
-    # All values > 131072, so all lanes should remain active
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x7, "All 3 lanes should remain active")
-
-  def test_v_cmpx_ngt_f32_e64_some_false(self):
-    """V_CMPX_NGT_F32_E64: some lanes fail (literal > some values)."""
-    instructions = [
-      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
-      v_mov_b32_e32(v[0], f2i(100000.0)),  # lane 0: 131072 > 100000 = true, so !(true) = false
-      v_cmp_eq_u32_e32(1, v[255]),
-      v_cndmask_b32_e64(v[1], v[0], f2i(200000.0), VCC_LO),  # lane 1: 131072 > 200000 = false, so !(false) = true
-      v_cmp_eq_u32_e32(2, v[255]),
-      v_cndmask_b32_e64(v[1], v[1], f2i(150000.0), VCC_LO),  # lane 2: 131072 > 150000 = false, so !(false) = true
-      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[1]),
-    ]
-    st = run_program(instructions, n_lanes=3)
-    # lane 0: fail (100000 < 131072), lanes 1,2: pass
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x6, "Lanes 1,2 should be active, lane 0 inactive")
-
-  def test_v_cmpx_ngt_f32_e64_all_false(self):
-    """V_CMPX_NGT_F32_E64: all lanes fail (literal > all values)."""
-    instructions = [
-      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
-      v_mov_b32_e32(v[0], f2i(100.0)),  # all lanes have 100.0
-      # 131072 > 100 = true, so !(true) = false for all
-      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[0]),
-    ]
-    st = run_program(instructions, n_lanes=3)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x0, "All lanes should be inactive")
-
-  def test_v_cmpx_ngt_f32_e64_large_values(self):
-    """V_CMPX_NGT_F32_E64: test with values that trigger Payne-Hanek in sin().
-
-    This is a regression test for the sin(859240.0) bug.
-    Values 859240, 1000000, 100594688 should all pass !(131072 > val).
-    """
-    instructions = [
-      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
-      v_mov_b32_e32(v[0], f2i(859240.0)),   # lane 0
-      v_cmp_eq_u32_e32(1, v[255]),
-      v_cndmask_b32_e64(v[1], v[0], f2i(1000000.0), VCC_LO),   # lane 1
-      v_cmp_eq_u32_e32(2, v[255]),
-      v_cndmask_b32_e64(v[1], v[1], f2i(100594688.0), VCC_LO), # lane 2
-      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[1]),
-    ]
-    st = run_program(instructions, n_lanes=3)
-    # All values > 131072, so !(131072 > val) = true for all
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x7, "All 3 lanes should remain active")
-
-
-class TestVCCBehavior(unittest.TestCase):
-  """Tests for VCC condition code behavior."""
-
-  def test_vcc_all_lanes_true(self):
-    """VCC should have all bits set when all lanes compare true."""
-    instructions = [
-      v_mov_b32_e32(v[0], 5),
-      v_mov_b32_e32(v[1], 5),
-      v_cmp_eq_u32_e32(v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=32)
-    self.assertEqual(st.vcc, 0xFFFFFFFF, "All 32 lanes should be true")
-
-  def test_vcc_lane_dependent(self):
-    """VCC should differ per lane based on lane_id comparison."""
-    instructions = [
-      v_mov_b32_e32(v[0], 16),
-      v_cmp_lt_u32_e32(v[255], v[0]),  # lanes 0-15 are < 16
-    ]
-    st = run_program(instructions, n_lanes=32)
-    self.assertEqual(st.vcc & 0xFFFF, 0xFFFF, "Lanes 0-15 should be true")
-    self.assertEqual(st.vcc >> 16, 0x0000, "Lanes 16-31 should be false")
-
-
-class TestCmpNge(unittest.TestCase):
-  """Tests for V_CMP_NGE (not-greater-or-equal) with NaN semantics.
-
-  NGE = !(a >= b). With NaN inputs:
-  - If either input is NaN, a >= b is false, so !(false) = true
-  - This differs from a < b which returns false for NaN inputs
-  """
-
-  def test_v_cmp_nge_f32_normal_values(self):
-    """v_cmp_nge_f32: basic comparison with normal floats."""
-    instructions = [
-      v_mov_b32_e32(v[0], f2i(1.0)),
-      v_mov_b32_e32(v[1], f2i(2.0)),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(1.0 >= 2.0) = !(false) = true
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "!(1.0 >= 2.0) should be true")
-
-  def test_v_cmp_nge_f32_equal_values(self):
-    """v_cmp_nge_f32: equal values should return false."""
-    instructions = [
-      v_mov_b32_e32(v[0], f2i(1.0)),
-      v_mov_b32_e32(v[1], f2i(1.0)),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(1.0 >= 1.0) = !(true) = false
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "!(1.0 >= 1.0) should be false")
-
-  def test_v_cmp_nge_f32_greater_value(self):
-    """v_cmp_nge_f32: greater value should return false."""
-    instructions = [
-      v_mov_b32_e32(v[0], f2i(2.0)),
-      v_mov_b32_e32(v[1], f2i(1.0)),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(2.0 >= 1.0) = !(true) = false
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 0, "!(2.0 >= 1.0) should be false")
-
-  def test_v_cmp_nge_f32_neg_inf(self):
-    """v_cmp_nge_f32: -inf compared to normal value."""
-    neg_inf = 0xff800000  # -inf
-    instructions = [
-      s_mov_b32(s[0], neg_inf),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], f2i(1.0)),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(-inf >= 1.0) = !(false) = true
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "!(-inf >= 1.0) should be true")
-
-  def test_v_cmp_nge_f32_clears_inactive_vcc_bits(self):
-    """v_cmp_nge_f32 with partial EXEC clears inactive VCC bits (hardware behavior)."""
-    neg_inf = 0xff800000  # -inf
-    instructions = [
-      # Set VCC to all 1s first
-      s_mov_b32(VCC_LO, 0xFFFFFFFF),
-      # Set EXEC to only lane 0
-      s_mov_b32(EXEC_LO, 0x00000001),
-      # v0 = 1.0 for lane 0
-      v_mov_b32_e32(v[0], f2i(1.0)),
-      # Compare: !(-inf >= 1.0) = true for lane 0
-      v_cmp_nge_f32_e32(neg_inf, v[0]),
-    ]
-    st = run_program(instructions, n_lanes=16)
-    # Hardware clears inactive lane bits, only active lane results remain
-    # Lane 0 result = 1 (true), lanes 1-15 = 0 (cleared)
-    self.assertEqual(st.vcc, 0x00000001, "VCC should only have active lane results")
-
-  def test_v_cmp_nge_f32_nan_src0(self):
-    """v_cmp_nge_f32: NaN in src0 should return true (NaN >= x is false)."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], f2i(1.0)),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(NaN >= 1.0) = !(false) = true
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "!(NaN >= 1.0) should be true")
-
-  def test_v_cmp_nge_f32_nan_src1(self):
-    """v_cmp_nge_f32: NaN in src1 should return true (x >= NaN is false)."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], f2i(1.0)),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(1.0 >= NaN) = !(false) = true
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "!(1.0 >= NaN) should be true")
-
-  def test_v_cmp_nge_f32_both_nan(self):
-    """v_cmp_nge_f32: both NaN should return true."""
-    quiet_nan = 0x7fc00000
-    instructions = [
-      s_mov_b32(s[0], quiet_nan),
-      v_mov_b32_e32(v[0], s[0]),
-      v_mov_b32_e32(v[1], s[0]),
-      v_cmp_nge_f32_e32(v[0], v[1]),  # !(NaN >= NaN) = !(false) = true
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vcc & 1, 1, "!(NaN >= NaN) should be true")
-
-
-class TestCmpxPartialWavefront(unittest.TestCase):
-  """Tests for V_CMPX with partial wavefronts (fewer than 32 active lanes).
-
-  Regression tests for bug where v_cmpx incorrectly set EXEC bits for inactive
-  lanes when the wavefront had fewer than 32 lanes. This caused garbage data
-  from uninitialized lanes to corrupt memory writes.
-  """
-
-  def test_v_cmpx_eq_u32_partial_wave_3_lanes(self):
-    """V_CMPX_EQ_U32 with 3 active lanes should only affect those 3 lanes.
-
-    With n_lanes=3, initial EXEC=0x7. After v_cmpx comparing lane_id == 1,
-    only lane 1 should pass, so EXEC should become 0x2 (not have bits 3-31 set).
-    """
-    instructions = [
-      v_cmpx_eq_u32_e32(1, v[255]),  # EXEC = lanes where lane_id == 1
-    ]
-    st = run_program(instructions, n_lanes=3)
-    # Only lane 1 should be active (bit 1 set)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x2,
-                     "Only lane 1 should be active after v_cmpx_eq_u32 with 3 lanes")
-
-  def test_v_cmpx_eq_u32_partial_wave_5_lanes(self):
-    """V_CMPX_EQ_U32 with 5 active lanes."""
-    instructions = [
-      v_cmpx_eq_u32_e32(3, v[255]),  # EXEC = lanes where lane_id == 3
-    ]
-    st = run_program(instructions, n_lanes=5)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x8,
-                     "Only lane 3 should be active after v_cmpx_eq_u32 with 5 lanes")
-
-  def test_v_cmpx_lt_u32_partial_wave(self):
-    """V_CMPX_LT_U32 with partial wavefront."""
-    # VOPC: src0 < vsrc1, so we need v_cmpx_gt_u32 to get lane_id < 2
-    instructions = [
-      v_cmpx_gt_u32_e32(2, v[255]),  # EXEC = lanes where 2 > lane_id (i.e., lane_id < 2)
-    ]
-    st = run_program(instructions, n_lanes=4)
-    # Lanes 0,1 should be active (bits 0,1 set = 0x3)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x3,
-                     "Only lanes 0,1 should be active after v_cmpx_gt_u32(2, lane_id) with 4 lanes")
-
-  def test_v_cmpx_ge_u32_partial_wave(self):
-    """V_CMPX_GE_U32 with partial wavefront."""
-    # VOPC: src0 >= vsrc1, so v_cmpx_le_u32(1, lane_id) gives lane_id >= 2? No.
-    # v_cmpx_le_u32(src0, vsrc1) = src0 <= vsrc1 = 1 <= lane_id
-    instructions = [
-      v_cmpx_le_u32_e32(2, v[255]),  # EXEC = lanes where 2 <= lane_id (i.e., lane_id >= 2)
-    ]
-    st = run_program(instructions, n_lanes=4)
-    # Lanes 2,3 should be active (bits 2,3 set = 0xC)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0xC,
-                     "Only lanes 2,3 should be active after v_cmpx_le_u32(2, lane_id) with 4 lanes")
-
-  def test_v_cmpx_ne_u32_partial_wave_all_pass(self):
-    """V_CMPX_NE_U32 where all active lanes pass."""
-    instructions = [
-      v_cmpx_ne_u32_e32(99, v[255]),  # EXEC = lanes where lane_id != 99
-    ]
-    st = run_program(instructions, n_lanes=3)
-    # All 3 lanes should remain active (bits 0,1,2 set = 0x7)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x7,
-                     "All 3 lanes should remain active when all pass")
-
-  def test_v_cmpx_eq_u32_partial_wave_none_pass(self):
-    """V_CMPX_EQ_U32 where no active lanes pass."""
-    instructions = [
-      v_cmpx_eq_u32_e32(99, v[255]),  # EXEC = lanes where lane_id == 99
-    ]
-    st = run_program(instructions, n_lanes=3)
-    # No lanes should be active
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x0,
-                     "No lanes should be active when none pass")
-
-  def test_v_cmpx_f32_partial_wave(self):
-    """V_CMPX_GT_F32 with partial wavefront - float comparison."""
-    instructions = [
-      v_cvt_f32_u32_e32(v[0], v[255]),  # v[0] = float(lane_id)
-      v_mov_b32_e32(v[1], f2i(0.5)),    # v[1] = 0.5
-      v_cmpx_gt_f32_e32(v[0], v[1]),    # EXEC = lanes where v[0] > 0.5
-    ]
-    st = run_program(instructions, n_lanes=4)
-    # Lanes 1,2,3 have values > 0.5, lane 0 has 0.0
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0xE,
-                     "Lanes 1,2,3 should be active (float > 0.5)")
-
-  def test_v_cmpx_e64_partial_wave(self):
-    """V_CMPX_EQ_U32_E64 (VOP3 encoding) with partial wavefront."""
-    instructions = [
-      v_cmpx_eq_u32_e64(EXEC_LO, v[255], 2),  # EXEC = lanes where lane_id == 2
-    ]
-    st = run_program(instructions, n_lanes=4)
-    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x4,
-                     "Only lane 2 should be active after v_cmpx_eq_u32_e64")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,161 +0,0 @@
-"""Tests for VOPD instructions - dual-issue vector operations.
-
-VOPD executes two operations simultaneously. Key behavior:
- Both ops read their sources BEFORE either writes (dual-issue semantics)
- This means if X writes to a register that Y reads, Y sees the OLD value
- Op X can use ops 0-15 (FMAC, MUL, ADD, MOV, etc.)
- Op Y can use ops 0-18 (includes ADD_NC_U32, LSHLREV, AND)
-"""
-import unittest
-from extra.assembly.amd.test.hw.helpers import run_program, run_program_emu, run_program_hw, compare_wave_states, \
-  v, s, v_mov_b32_e32, s_mov_b32
-from extra.assembly.amd.autogen.rdna3.ins import VOPD, VOPD_LIT, VOPDOp
-
-class TestVOPDBasic(unittest.TestCase):
-  """Basic VOPD functionality tests."""
-
-  def test_vopd_dual_mov(self):
-    """VOPD with two MOV operations to different registers."""
-    instructions = [
-      v_mov_b32_e32(v[0], 0x12345678),
-      v_mov_b32_e32(v[1], 0xDEADBEEF),
-      # X: v[2] = v[0], Y: v[3] = v[1]
-      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[1], v[0], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 0x12345678)
-    self.assertEqual(st.vgpr[0][3], 0xDEADBEEF)
-
-  def test_vopd_mov_and_add(self):
-    """VOPD with MOV (X) and ADD_NC_U32 (Y) - ADD_NC_U32 can only be Y op."""
-    instructions = [
-      v_mov_b32_e32(v[0], 10),
-      v_mov_b32_e32(v[1], 5),
-      # X: v[2] = 100 (literal), Y: v[3] = v[0] + v[1] = 15
-      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[3], 100, v[0], v[0], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertEqual(st.vgpr[0][2], 100)
-    self.assertEqual(st.vgpr[0][3], 15)
-
-
-class TestVOPDReadBeforeWrite(unittest.TestCase):
-  """Tests for VOPD dual-issue read-before-write semantics.
-
-  In VOPD, both X and Y operations read their sources BEFORE either writes.
-  This is critical when X's destination is Y's source.
-  """
-
-  def test_vopd_x_writes_y_reads_same_reg(self):
-    """VOPD where X writes to a register that Y reads.
-
-    X: v[2] = 0 (overwrites v[2])
-    Y: v[1] = v[2] + v[0]  (srcy0=v[2], vsrcy1=v[0])
-
-    If reads happen before writes: v[1] = OLD_v[2] + v[0] = 0xFFFFFFFF + 1 = 0
-    If writes happen before reads: v[1] = 0 + v[0] = 0 + 1 = 1
-
-    Hardware does reads-before-writes, so v[1] should be 0.
-    """
-    instructions = [
-      v_mov_b32_e32(v[0], 1),          # v[0] = 1
-      v_mov_b32_e32(v[1], 0x99999999), # v[1] = placeholder (will be overwritten)
-      v_mov_b32_e32(v[2], 0xFFFFFFFF), # v[2] = 0xFFFFFFFF
-      # X: v[2] = 0 (literal), srcx0=0, vsrcx1=v[0] (unused for MOV)
-      # Y: v[1] = srcy0 + vsrcy1 = v[2] + v[0] (should read OLD v[2] = 0xFFFFFFFF)
-      # vdsty encoding: (vdsty << 1) | ((vdstx & 1) ^ 1) where vdsty field = 0, vdstx = v[2]
-      # So vdsty_reg = (0 << 1) | ((2 & 1) ^ 1) = 0 | 1 = 1 = v[1]
-      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 0, v[2], v[0], v[0]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # X should have written 0 to v[2]
-    self.assertEqual(st.vgpr[0][2], 0, "X should write 0 to v[2]")
-    # Y should have read OLD v[2] (0xFFFFFFFF) and added v[0] (1)
-    # 0xFFFFFFFF + 1 = 0 (wrap around)
-    self.assertEqual(st.vgpr[0][1], 0, "Y should read OLD v[2]=0xFFFFFFFF, compute 0xFFFFFFFF+1=0")
-
-  def test_vopd_x_writes_y_reads_same_reg_v2(self):
-    """VOPD where X writes to a register that Y reads - cleaner test case.
-
-    X: v[2] = 0 (MOV)
-    Y: v[1] = v[2] + v[2] (ADD_NC_U32 with both sources from v[2])
-
-    If reads happen before writes: v[1] = OLD_v[2] + OLD_v[2] = 100 + 100 = 200
-    If writes happen before reads: v[1] = 0 + 0 = 0
-
-    Hardware does reads-before-writes, so v[1] should be 200.
-    """
-    instructions = [
-      v_mov_b32_e32(v[0], 0x88888888), # v[0] = unused placeholder
-      v_mov_b32_e32(v[1], 0x99999999), # v[1] = placeholder (will be overwritten)
-      v_mov_b32_e32(v[2], 100),        # v[2] = 100
-      # X: v[2] = 0 (literal)
-      # Y: v[1] = srcy0 + vsrcy1 = v[2] + v[2] (should read OLD v[2] = 100)
-      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 0, v[2], v[0], v[2]),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    # X should have written 0 to v[2]
-    self.assertEqual(st.vgpr[0][2], 0, "X should write 0 to v[2]")
-    # Y should have read OLD v[2] (100) twice and added them
-    self.assertEqual(st.vgpr[0][1], 200, "Y should read OLD v[2]=100 twice, compute 100+100=200")
-
-
-class TestVOPDLiterals(unittest.TestCase):
-  """Tests for VOPD instructions that use SIMM32 literals (FMAAK, FMAMK)."""
-
-  def test_vopd_fmaak_f32(self):
-    """VOPD V_DUAL_FMAAK_F32: D = S0 * S1 + SIMM32 (literal addend).
-
-    Tests that the 32-bit literal (SIMM32) is correctly passed to the instruction.
-    fma(2.0, 3.0, 10.0) = 2*3 + 10 = 16.0
-    """
-    from extra.assembly.amd.test.hw.helpers import f2i, i2f
-    instructions = [
-      v_mov_b32_e32(v[0], f2i(2.0)),  # v[0] = 2.0
-      v_mov_b32_e32(v[1], f2i(3.0)),  # v[1] = 3.0
-      # VOPD args: opx, opy, vdstx, vdsty, srcx0, srcy0, vsrcx1, vsrcy1
-      # X: v[2] = fma(srcx0, vsrcx1, SIMM32) = v[0]*v[1]+10.0 = 2*3+10 = 16
-      # Y: v[3] = srcy0 (MOV) = v[0] = 2.0
-      VOPD_LIT(VOPDOp.V_DUAL_FMAAK_F32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[0], v[1], v[0], literal=f2i(10.0)),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 16.0, places=5, msg="fma(2.0, 3.0, 10.0) should be 16.0")
-
-  def test_vopd_fmamk_f32(self):
-    """VOPD V_DUAL_FMAMK_F32: D = S0 * SIMM32 + S1 (literal multiplier).
-
-    Tests that the 32-bit literal (SIMM32) is correctly used as the multiplier.
-    fma(2.0, 5.0, 3.0) = 2*5 + 3 = 13.0
-    """
-    from extra.assembly.amd.test.hw.helpers import f2i, i2f
-    instructions = [
-      v_mov_b32_e32(v[0], f2i(2.0)),  # v[0] = 2.0
-      v_mov_b32_e32(v[1], f2i(3.0)),  # v[1] = 3.0
-      # X: v[2] = fma(srcx0, SIMM32, vsrcx1) = v[0]*5.0+v[1] = 2*5+3 = 13
-      # Y: v[3] = srcy0 (MOV) = v[0] = 2.0
-      VOPD_LIT(VOPDOp.V_DUAL_FMAMK_F32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[0], v[1], v[0], literal=f2i(5.0)),
-    ]
-    st = run_program(instructions, n_lanes=1)
-    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 13.0, places=5, msg="fma(2.0, 5.0, 3.0) should be 13.0")
-
-
-class TestVOPDMultilane(unittest.TestCase):
-  """Tests for VOPD with multiple lanes."""
-
-  def test_vopd_multilane_mov_add(self):
-    """VOPD MOV and ADD with multiple active lanes - no register conflict."""
-    instructions = [
-      v_mov_b32_e32(v[0], 5),
-      v_mov_b32_e32(v[1], 10),
-      # X: v[2] = 100 (constant), Y: v[1] = v[0] + v[1] = 5 + 10 = 15
-      # vdsty_reg = (vdsty << 1) | ((vdstx.offset & 1) ^ 1) = (0 << 1) | ((258 & 1) ^ 1) = 0 | 1 = 1
-      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 100, v[0], v[2], v[1]),
-    ]
-    st = run_program(instructions, n_lanes=4)
-    for lane in range(4):
-      self.assertEqual(st.vgpr[lane][2], 100, f"Lane {lane}: v[2] should be 100")
-      self.assertEqual(st.vgpr[lane][1], 15, f"Lane {lane}: v[1] should be 15 (5+10)")
-
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,13 +1,18 @@
 # Test to compare Python and Rust RDNA3 emulators by running real tinygrad kernels
-import unittest, ctypes
+import unittest, ctypes, os
 from dataclasses import dataclass
+from pathlib import Path

-from extra.assembly.amd.emu import WaveState, decode_program, WAVE_SIZE, VCC_LO, EXEC_LO, SCC
-from extra.assembly.amd import decode_inst
+# Set environment before any tinygrad imports to use MOCKGPU
+# This allows generating AMD GPU kernels without requiring real hardware
+os.environ["AMD"] = "1"
+os.environ["MOCKGPU"] = "1"
+os.environ["PYTHON_REMU"] = "1"
+
+from extra.assembly.amd.emu import WaveState, decode_program, step_wave, WAVE_SIZE, set_valid_mem_ranges
 from extra.assembly.amd.test.helpers import KernelInfo
-from extra.assembly.amd.test.bench_emu import REMU_PATH

-def set_valid_mem_ranges(ranges): pass  # emu2 doesn't need this
+REMU_PATH = Path(__file__).parents[3] / "remu/target/release/libremu.so"

 def _is_f32_nan(bits: int) -> bool:
  """Check if 32-bit value is a NaN (exponent all 1s, mantissa non-zero)."""
@@ -87,61 +92,37 @@ class PythonEmulator:
  def __init__(self):
    self.state: WaveState | None = None
    self.program: dict | None = None
-    self.vmem_buf = None
-    self.lds_buf = None
-    self.kernel_buf = None  # Keep kernel bytes alive
-    self.lib_addr = 0  # Base address of kernel code
+    self.lds: bytearray | None = None
+    self.n_lanes = 0

  def create(self, kernel: bytes, n_lanes: int):
-    import ctypes
-    from tinygrad.device import Buffer, BufferSpec
-    from tinygrad.dtype import dtypes
-    # Store kernel in a ctypes buffer so generic instructions can read from vmem at actual PC address
-    self.kernel_buf = (ctypes.c_char * len(kernel)).from_buffer_copy(kernel)
-    self.lib_addr = ctypes.addressof(self.kernel_buf)
-    # Remap program dict to use actual addresses (like run_asm does)
-    program_raw = decode_program(kernel)
-    self.program = {self.lib_addr + offset: val for offset, val in program_raw.items()}
-    self.state = WaveState(n_lanes)
-    self.state.pc = self.lib_addr  # Set PC to code base address
-    self.vmem_buf = Buffer('CPU', 1 << 40, dtypes.uint32, options=BufferSpec(external_ptr=0)).ensure_allocated()
-    self.lds_buf = Buffer('CPU', 65536 // 4, dtypes.uint32).ensure_allocated()
+    self.program = decode_program(kernel)
+    self.state = WaveState()
+    self.state.exec_mask = (1 << n_lanes) - 1
+    self.lds = bytearray(65536)
+    self.n_lanes = n_lanes

  def step(self) -> int:
-    import ctypes
-    assert self.program is not None and self.state is not None
-    pc = self.state.pc
-    if pc == 0xFFFFFFFFFFFFFFFF or pc not in self.program: return -1
-    name, fxn, globals_list, _runner = self.program[pc]
-    if fxn is None: return 1  # unsupported instruction
-    buf_addrs = {0: self.state.sgpr_buf._buf.va_addr, 1: self.state.vgpr_buf._buf.va_addr,
-                 2: self.vmem_buf._buf.va_addr, 3: self.lds_buf._buf.va_addr}
-    # Direct ctypes call - bypasses HCQ overhead
-    fxn(*[ctypes.c_uint64(buf_addrs[g]) for g in globals_list], ctypes.c_int32(0))
-    return -1 if self.state.pc == 0xFFFFFFFFFFFFFFFF else 0
-
+    assert self.program is not None and self.state is not None and self.lds is not None
+    return step_wave(self.program, self.state, self.lds, self.n_lanes)
  def set_sgpr(self, idx: int, val: int):
    assert self.state is not None
-    self.state._write_sgpr(idx, val)
+    self.state.sgpr[idx] = val & 0xffffffff
  def set_vgpr(self, lane: int, idx: int, val: int):
    assert self.state is not None
-    self.state._write_vgpr(idx, lane, val)
+    self.state.vgpr[lane][idx] = val & 0xffffffff

  def get_snapshot(self) -> StateSnapshot:
    assert self.state is not None
-    sgpr = [self.state._read_sgpr(i) for i in range(128)]
-    vgpr = [[self.state._read_vgpr(reg, lane) for reg in range(256)] for lane in range(WAVE_SIZE)]
-    # Convert actual PC address to word offset for comparison with Rust emulator
-    pc_offset = (self.state.pc - self.lib_addr) // 4 if self.state.pc != 0xFFFFFFFFFFFFFFFF else 0xFFFFFFFFFFFFFFFF
-    return StateSnapshot(pc=pc_offset, scc=self.state._read_sgpr(SCC.offset), vcc=sgpr[VCC_LO.offset],
-                         exec_mask=sgpr[EXEC_LO.offset], sgpr=sgpr, vgpr=vgpr)
+    return StateSnapshot(pc=self.state.pc, scc=self.state.scc, vcc=self.state.vcc & 0xffffffff,
+                         exec_mask=self.state.exec_mask & 0xffffffff, sgpr=list(self.state.sgpr),
+                         vgpr=[list(self.state.vgpr[i]) for i in range(WAVE_SIZE)])

 def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: tuple[int, int, int],
-                      local_size: tuple[int, int, int], program, max_steps: int, debug: bool, trace_len: int,
-                      kernel_idx: int = 0, max_workgroups: int = 8) -> tuple[bool, str, int]:
+                      program, max_steps: int, debug: bool, trace_len: int, kernel_idx: int = 0,
+                      max_workgroups: int = 8) -> tuple[bool, str, int]:
  """Run a single kernel through both emulators. Returns (success, message, total_steps)."""
  gx, gy, gz = global_size
-  lx, ly, lz = local_size
  total_steps = 0
  wg_count = 0

@@ -164,52 +145,27 @@ def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: t
          emu.set_sgpr(13, gidx)
          emu.set_sgpr(14, gidy)
          emu.set_sgpr(15, gidz)
-          # Initialize v[0] with packed workitem IDs for each lane
-          for lane in range(n_lanes):
-            tid = lane
-            z, y, x = tid // (lx * ly), (tid // lx) % ly, tid % lx
-            emu.set_vgpr(lane, 0, (z << 20) | (y << 10) | x)

        step = 0
        trace: list[tuple[int, int, str, StateSnapshot, StateSnapshot]] = []
-        prev_sync_after = False  # Track if previous instruction had known Rust bugs
        try:
          while step < max_steps:
            rust_before = rust.get_snapshot()
            python_before = python.get_snapshot()

-            inst_info = python.program.get(python.lib_addr + python_before.pc * 4)  # Convert word offset to actual address
-            inst_hex_name = inst_info[0] if inst_info else f"unknown at PC={python_before.pc}"
-            # Decode the instruction to get mnemonic for sync_after checks
-            try:
-              # Format is mnemonic_hexbytes, e.g. v_exp_f32_e32_014b027e -> hex is 014b027e
-              parts = inst_hex_name.rsplit('_', 1)
-              inst_bytes_hex = parts[1] if len(parts) == 2 else ""
-              inst_bytes = bytes.fromhex(inst_bytes_hex) if inst_bytes_hex else b''
-              decoded = decode_inst(inst_bytes) if inst_bytes else None
-              inst_mnemonic = repr(decoded).split('(')[0] if decoded else ""
-            except:
-              inst_mnemonic = ""
-            # For generic instructions, use function name for sync_after check
-            if not inst_mnemonic: inst_mnemonic = inst_hex_name
-            inst_str = inst_hex_name
+            inst = program.get(python_before.pc)
+            inst_str = inst.disasm() if inst else f"unknown at PC={python_before.pc}"
            trace.append((step, python_before.pc, inst_str, rust_before, python_before))
            if len(trace) > trace_len: trace.pop(0)

            if debug: print(f"K{kernel_idx} WG({gidx},{gidy},{gidz}) Step {step}: PC={python_before.pc}, inst={inst_str}")

-            # Instructions with known Rust emulator bugs or precision differences - sync Python to Rust after execution
+            # Instructions with known Rust emulator bugs - sync Python to Rust after execution
            # v_div_scale/v_div_fixup: Rust has different VCC handling
            # v_cvt_f16_f32: Rust clears high 16 bits, but hardware (and Python) preserves them
-            # s_add_i32/s_sub_i32: Rust has incorrect SCC overflow detection
-            # v_exp_f32/v_log_f32/v_ldexp_f32: precision differences in transcendental functions
-            # s_delay_alu: Rust handles differently
-            # v_add_co_ci_u32/v_sub_co_ci_u32/v_subrev_co_ci_u32: Rust preserves inactive VCC bits, but hardware clears all bits
-            sync_after = any(x in inst_mnemonic.lower() for x in ('v_div_scale', 'v_div_fixup', 'v_cvt_f16_f32', 's_add_i32', 's_sub_i32',
-                                                                   'v_exp_f32', 'v_log_f32', 'v_ldexp_f32', 's_delay_alu',
-                                                                   'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'))
-            # Skip comparison if previous instruction had known Rust bugs (states were synced but may still differ slightly)
-            diffs = rust_before.diff(python_before, n_lanes) if not prev_sync_after else []
+            sync_after = any(x in inst_str for x in ('v_div_scale_f32', 'v_div_scale_f64', 'v_div_fixup_f32', 'v_div_fixup_f64',
+                                                      'v_cvt_f16_f32'))
+            diffs = rust_before.diff(python_before, n_lanes)
            if diffs:
              trace_lines = []
              for idx, (s, pc, d, rb, pb) in enumerate(trace):
@@ -248,12 +204,7 @@ def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: t
              for lane in range(n_lanes):
                for i in range(256): python.set_vgpr(lane, i, rust_after.vgpr[lane][i])
              assert python.state is not None
-              # Convert Rust's word-based PC to Python's actual address
-              python.state.pc = python.lib_addr + rust_after.pc * 4
-              python.state._write_sgpr(SCC.offset, rust_after.scc)
-              python.state._write_sgpr(VCC_LO.offset, rust_after.vcc)
-              python.state._write_sgpr(EXEC_LO.offset, rust_after.exec_mask)
-            prev_sync_after = sync_after
+              python.state.pc, python.state.scc, python.state.vcc, python.state.exec_mask = rust_after.pc, rust_after.scc, rust_after.vcc, rust_after.exec_mask

            if rust_result == -1:
              total_steps += step + 1
@@ -307,7 +258,7 @@ def compare_emulators_multi_kernel(kernels: list[KernelInfo], buf_pool: dict[int

    ok, msg, steps = run_single_kernel(
      kernel.code, min(n_lanes, 32), args_ptr, kernel.global_size,
-      kernel.local_size, program, max_steps, debug, trace_len, ki
+      program, max_steps, debug, trace_len, ki
    )
    total_steps += steps
    if not ok:
@@ -334,8 +285,7 @@ def compare_emulators_with_memory(kernel: bytes, n_lanes: int, buf_sizes: list,
  set_valid_mem_ranges(ranges)

  program = decode_program(kernel)
-  # Legacy wrapper assumes local_size = (n_lanes, 1, 1)
-  ok, msg, _ = run_single_kernel(kernel, n_lanes, args_ptr, global_size, (n_lanes, 1, 1), program, max_steps, debug, trace_len)
+  ok, msg, _ = run_single_kernel(kernel, n_lanes, args_ptr, global_size, program, max_steps, debug, trace_len)
  return ok, msg

 def get_kernels_from_tinygrad(op_fn) -> tuple[list[KernelInfo], dict[int, int], dict[int, bytes]]:
@@ -378,7 +328,6 @@ def get_kernels_from_tinygrad(op_fn) -> tuple[list[KernelInfo], dict[int, int],
              buf_sizes.append(b.nbytes)
            kernels.append(KernelInfo(
              code=bytes(sec.content),
-              src=lowered.prg.p.src,
              global_size=tuple(lowered.prg.p.global_size),
              local_size=tuple(lowered.prg.p.local_size),
              buf_idxs=buf_idxs,
@@ -441,7 +390,6 @@ class TestTinygradKernels(unittest.TestCase):
    from tinygrad import dtypes
    self._test_kernel(lambda T: T.empty(4, 4)[T.arange(4).cast(dtypes.int64), :])
  def test_gelu(self): self._test_kernel(lambda T: T.empty(32, 32).gelu())
-  def test_exp(self): self._test_kernel(lambda T: T.empty(1024).exp())
  def test_cross_entropy(self):
    import numpy as np
    np.random.seed(0)
@@ -449,59 +397,6 @@ class TestTinygradKernels(unittest.TestCase):
    x_np = np.random.randn(16, 10).astype(np.float32)
    self._test_kernel(lambda T: (T(x_np.tolist()).reshape(16,10) + 0).cross_entropy((T(classes).int().reshape(16) + 0)))
  def test_isinf(self): self._test_kernel(lambda T: T([float('-inf'), 0., float('inf'), 1.1]*8).isinf())
-  def test_sin_f64(self):
-    from tinygrad import dtypes
-    self._test_kernel(lambda T: T([2.0], dtype=dtypes.float64).sin())
-
-  def test_sin_large_f32(self):
-    """Test sin with large values that trigger Payne-Hanek range reduction."""
-    # Values around 859240 trigger the Payne-Hanek algorithm
-    # This tests the integer multiply-high instructions used in range reduction
-    self._test_kernel(lambda T: T([859240.0, 1000000.0, 100594688.0]).sin())
-
-  def test_clip_zero_one(self):
-    """Test clip(0, 1) - regression for binary_crossentropy failure."""
-    import numpy as np
-    np.random.seed(0)
-    x_np = np.random.uniform(-2, 2, (32, 10)).astype(np.float32).tolist()
-    self._test_kernel(lambda T: T(x_np).clip(0, 1))
-
-  def test_mod_int64(self):
-    """Test int64 modulo, especially edge cases like 1 % -1."""
-    from tinygrad import dtypes
-    self._test_kernel(lambda T: T([1, 10, -10, 7], dtype=dtypes.int64) % T([-1, 3, 3, -3], dtype=dtypes.int64))
-
-  def test_expand_flatten_sum(self):
-    """Test flatten of expanded tensor followed by sum.
-
-    Bug: flatten() of an expanded tensor produces wrong results for certain sizes.
-    Sizes that are multiples of 32 work (32, 48, 64), but sizes like 33, 49, 50 fail.
-    This breaks masked_select and nonzero operations.
-    """
-    import numpy as np
-    np.random.seed(0)
-    x_np = np.random.uniform(-2, 2, (33,)).astype(np.float32)
-    self._test_kernel(lambda T: (T(x_np.tolist()) > 0.5).unsqueeze(-1).expand(33, 3).flatten().sum())
-
-  @unittest.skip("slow and broken with AMD_LLVM=1")
-  def test_nonzero(self):
-    """Test nonzero operation - counts and gathers indices of non-zero elements."""
-    import numpy as np
-    np.random.seed(42)
-    x_np = np.random.rand(10, 5, 3).astype(np.float32)
-    self._test_kernel(lambda T: (T(x_np.tolist()) > 0.5).nonzero())
-
-  @unittest.skip("Precision differences in v_exp/v_log accumulate across kernels, causing memory divergence")
-  def test_softmax_argmax_fused(self):
-    """Test fused softmax+argmax - tracks exp2 precision issue.
-
-    The fused kernel recomputes softmax inline and Python emulator's exp2 polynomial
-    has up to 1 ULP error vs native exp2f, causing accumulated differences.
-    """
-    import torch
-    torch.manual_seed(0)
-    x_np = torch.rand(4, 10).numpy()
-    self._test_kernel(lambda T: T(x_np.tolist()).softmax(1).argmax())

 if __name__ == "__main__":
  unittest.main()
@@ -1,77 +0,0 @@
-import unittest
-import functools
-from tinygrad import Tensor, Device, dtypes
-from tinygrad.uop.ops import UOp, Ops, KernelInfo
-from tinygrad.renderer import Estimates
-from tinygrad.runtime.support.compiler_amd import HIPCompiler
-
-from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.dsl import s, v, Inst
-
-def assemble_insts(insts:list[Inst], name:str, arch:str, kernarg_size:int=8) -> tuple[UOp, UOp]:
-  kd = {"kernarg_size":kernarg_size, "user_sgpr_kernarg_segment_ptr":1, "next_free_vgpr":8, "next_free_sgpr":8, "wavefront_size32":1}
-  disasm = "\n".join([inst.disasm() for inst in insts])
-  hsasrc = f".text\n.globl {name}\n.p2align 8\n.type fn_name,@function\n{name}:\n{disasm}\ns_code_end\n"
-  hsasrc += f".rodata\n.p2align 6\n.amdhsa_kernel {name}\n"+"\n".join([f".amdhsa_{k} {v}" for k,v in kd.items()])+"\n.end_amdhsa_kernel"
-  binary = HIPCompiler(arch).compile(hsasrc)
-  return UOp(Ops.SOURCE, arg=disasm), UOp(Ops.BINARY, arg=binary)
-
-def custom_add_one(A:UOp, arch:str) -> UOp:
-  A = A.flatten()
-  assert dtypes.is_float(A.dtype.base), f"buffer dtype must be float32, got {A.dtype}"
-  threads = UOp.special(A.size, "lidx0")
-  insts = [
-    s_load_b64(s[0:1], s[0:1], soffset=NULL),
-    s_waitcnt(lgkmcnt=0),
-    v_lshlrev_b32_e32(v[0], 2, v[0]), # element offset
-    global_load_b32(v[1], v[0], saddr=s[0:1]),
-    s_waitcnt(vmcnt=0),
-    v_mov_b32_e32(v[2], 1.0),
-    v_add_f32_e32(v[1], v[1], v[2]),
-    global_store_b32(addr=v[0], data=v[1], saddr=s[0:1]),
-    s_endpgm(),
-  ]
-  sink = UOp.sink(A.base, threads, arg=KernelInfo(name:=f"custom_add_one_{A.size}", estimates=Estimates(ops=A.size, mem=A.size*4*2)))
-  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg="AMD"), UOp(Ops.LINEAR, src=(*sink.src, sink)), *assemble_insts(insts, name, arch)))
-
-def custom_add_var(A:UOp, B:UOp, arch:str) -> UOp:
-  A,B = A.flatten(), B.flatten()
-  assert A.dtype.base == dtypes.uint32, f"buffer dtype must be uint32, got {A.dtype}"
-  threads = UOp.special(A.size, "lidx0")
-  var = UOp.variable("var", 0, 10)
-  insts = [
-    s_load_b128(s[4:7], s[0:1]),
-    s_load_b32(s[8], s[0:1], offset=0x10), # all threads load the same variable
-    s_waitcnt(lgkmcnt=0),
-    v_lshlrev_b32_e32(v[0], 2, v[0]), # element offset, different per thread
-    global_load_b32(v[1], v[0], saddr=s[6:7]),
-    s_waitcnt(vmcnt=0),
-    v_add_nc_u32_e32(v[1], s[8], v[1]),
-    global_store_b32(addr=v[0], data=v[1], saddr=s[4:5]),
-    s_endpgm(),
-  ]
-  sink = UOp.sink(A.base, B.base, var, threads, arg=KernelInfo(name:=f"custom_add_one_{A.size}"))
-  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg="AMD"), UOp(Ops.LINEAR, src=(*sink.src, sink)),
-                               *assemble_insts(insts, name, arch, kernarg_size=16)))
-
-class TestCustomKernel(unittest.TestCase):
-  def test_simple(self):
-    a = Tensor.full((16, 16), 1.).contiguous().realize()
-    a = Tensor.custom_kernel(a, fxn=functools.partial(custom_add_one, arch=Device[Device.DEFAULT].renderer.arch))[0]
-    ei = a.schedule()[-1].lower()
-    self.assertEqual(ei.prg.estimates.ops, a.numel())
-    self.assertEqual(ei.prg.estimates.mem, a.nbytes()*2)
-    ei.run()
-    self.assertTrue((a.numpy() == 2.).all())
-
-  def test_variable(self):
-    b = Tensor.full((16, 16), 1, dtype=dtypes.uint32).contiguous().realize()
-    a = Tensor.zeros_like(b).contiguous().realize()
-    a = Tensor.custom_kernel(a, b, fxn=functools.partial(custom_add_var, arch=Device[Device.DEFAULT].renderer.arch))[0]
-    ei = a.schedule()[-1].lower()
-    for i in range(4):
-      ei.run({"var":i})
-      self.assertTrue((a.numpy() == 1+i).all())
-
-if __name__ == "__main__":
-  unittest.main()
@@ -1,170 +0,0 @@
-import unittest
-from extra.assembly.amd.dsl import *
-from extra.assembly.amd.dsl import VDSTYField
-from extra.assembly.amd.autogen.rdna3.enum import VOP1Op, VOP2Op
-from extra.assembly.amd.autogen.rdna3.ins import VOP1
-
-class TestRegisters(unittest.TestCase):
-  def test_vgpr_single(self):
-    self.assertEqual(repr(v[5]), "v[5]")
-    self.assertEqual(v[5].offset, 261)  # 256 + 5
-    self.assertEqual(v[5].sz, 1)
-
-  def test_sgpr_single(self):
-    self.assertEqual(repr(s[10]), "s[10]")
-    self.assertEqual(s[10].offset, 10)
-
-  def test_vgpr_range(self):
-    self.assertEqual(repr(v[0:3]), "v[0:3]")
-    self.assertEqual(v[0:3].offset, 256)
-    self.assertEqual(v[0:3].sz, 4)
-
-  def test_sgpr_range(self):
-    self.assertEqual(repr(s[4:5]), "s[4:5]")
-    self.assertEqual(s[4:5].sz, 2)
-
-  def test_ttmp_reslice(self):
-    # ttmp is src[108:123], so ttmp[0] should be src[108]
-    self.assertEqual(ttmp[0].offset, 108)
-    self.assertEqual(ttmp[1].offset, 109)
-    # ttmp[0:1] is 2 elements (inclusive slicing)
-    self.assertEqual(ttmp[0:1].offset, 108)
-    self.assertEqual(ttmp[0:1].sz, 2)
-    # ttmp[0:1][0] should be src[108]
-    self.assertEqual(ttmp[0:1][0].offset, 108)
-
-  def test_special_regs(self):
-    self.assertEqual(NULL.offset, 124)
-    self.assertEqual(M0.offset, 125)
-    self.assertEqual(EXEC_LO.offset, 126)
-    self.assertEqual(EXEC_HI.offset, 127)
-    # Check repr round-trips
-    self.assertEqual(repr(NULL), "NULL")
-    self.assertEqual(repr(M0), "M0")
-    self.assertEqual(repr(EXEC_LO), "EXEC_LO")
-    self.assertEqual(repr(EXEC), "EXEC")
-
-  def test_vcc(self):
-    self.assertEqual(VCC.offset, 106)
-    self.assertEqual(VCC.sz, 2)
-    self.assertEqual(VCC_LO.offset, 106)
-    self.assertEqual(VCC_HI.offset, 107)
-    # Check repr round-trips
-    self.assertEqual(repr(VCC_LO), "VCC_LO")
-    self.assertEqual(repr(VCC_HI), "VCC_HI")
-    self.assertEqual(repr(VCC), "VCC")
-
-  def test_float_constants(self):
-    self.assertEqual(src[240].offset, 240)
-    self.assertEqual(repr(src[240]), "0.5")
-    self.assertEqual(repr(src[242]), "1.0")
-    self.assertEqual(repr(src[243]), "-1.0")
-
-  def test_int_constants(self):
-    self.assertEqual(repr(src[128]), "0")
-    self.assertEqual(repr(src[129]), "1")
-    self.assertEqual(repr(src[192]), "64")
-    self.assertEqual(repr(src[193]), "-1")
-    self.assertEqual(repr(src[208]), "-16")
-
-class TestEnumBitField(unittest.TestCase):
-  def test_enum_name(self):
-    self.assertEqual(VOP1Op.V_MOV_B32_E32.name, "V_MOV_B32_E32")
-
-  def test_enum_value(self):
-    self.assertEqual(VOP1Op.V_MOV_B32_E32.value, 1)
-
-  def test_enum_comparison(self):
-    self.assertEqual(VOP1Op.V_MOV_B32_E32, VOP1Op.V_MOV_B32_E32)
-    self.assertNotEqual(VOP1Op.V_NOP_E32, VOP1Op.V_MOV_B32_E32)
-
-  def test_enum_different_types(self):
-    # VOP1Op and VOP2Op are different enums, even if same value
-    self.assertNotEqual(VOP1Op.V_MOV_B32_E32, VOP2Op.V_CNDMASK_B32_E32)
-
-  def test_wrong_enum_type_raises(self):
-    # Passing VOP2Op to VOP1 should raise
-    with self.assertRaises(RuntimeError):
-      VOP1(VOP2Op.V_CNDMASK_B32_E32, v[5], v[6])
-
-class TestVOP1(unittest.TestCase):
-  def test_class_setup(self):
-    self.assertEqual(VOP1._size(), 4)
-    field_names = [n for n, _ in VOP1._fields]
-    self.assertIn('encoding', field_names)
-    self.assertIn('op', field_names)
-    self.assertIn('vdst', field_names)
-    self.assertIn('src0', field_names)
-
-  def test_encoding_vgpr_vgpr(self):
-    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
-    raw = i._raw
-    # Check each field
-    self.assertEqual((raw >> 25) & 0x7f, 0b0111111)  # encoding
-    self.assertEqual((raw >> 17) & 0xff, 5)          # vdst (just VGPR index)
-    self.assertEqual((raw >> 9) & 0xff, 1)           # op
-    self.assertEqual(raw & 0x1ff, 262)               # src0 (256 + 6)
-
-  def test_encoding_vgpr_sgpr(self):
-    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], s[10])
-    raw = i._raw
-    self.assertEqual((raw >> 17) & 0xff, 5)    # vdst (just VGPR index)
-    self.assertEqual(raw & 0x1ff, 10)          # src0 (SGPR encoded)
-
-  def test_to_bytes(self):
-    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
-    b = i.to_bytes()
-    self.assertEqual(len(b), 4)
-    self.assertEqual(int.from_bytes(b, 'little'), i._raw)
-
-  def test_from_bytes(self):
-    i1 = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
-    i2 = VOP1.from_bytes(i1.to_bytes())
-    self.assertEqual(i1._raw, i2._raw)
-
-  def test_repr(self):
-    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
-    self.assertEqual(repr(i), "v_mov_b32_e32(v[5], v[6])")
-
-  def test_repr_sgpr_src(self):
-    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], s[10])
-    self.assertEqual(repr(i), "v_mov_b32_e32(v[5], s[10])")
-
-  def test_kwargs(self):
-    i1 = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
-    i2 = VOP1(op=VOP1Op.V_MOV_B32_E32, vdst=v[5], src0=v[6])
-    self.assertEqual(i1._raw, i2._raw)
-
-  def test_kwargs_partial(self):
-    i1 = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
-    i2 = VOP1(VOP1Op.V_MOV_B32_E32, src0=v[6], vdst=v[5])
-    self.assertEqual(i1._raw, i2._raw)
-
-class TestVDSTYField(unittest.TestCase):
-  def test_encode_even_vgpr(self):
-    f = VDSTYField(6, 0)  # 7-bit field
-    self.assertEqual(f.encode(v[0]), 0)
-    self.assertEqual(f.encode(v[2]), 1)
-    self.assertEqual(f.encode(v[4]), 2)
-    self.assertEqual(f.encode(v[254]), 127)
-
-  def test_encode_non_vgpr_raises(self):
-    f = VDSTYField(6, 0)
-    with self.assertRaises(ValueError) as ctx:
-      f.encode(s[0])
-    self.assertIn("VGPR", str(ctx.exception))
-
-  def test_encode_non_reg_raises(self):
-    f = VDSTYField(6, 0)
-    with self.assertRaises(TypeError) as ctx:
-      f.encode(42)
-    self.assertIn("Reg", str(ctx.exception))
-
-  def test_decode_returns_raw(self):
-    f = VDSTYField(6, 0)
-    # decode returns raw value, actual vdsty computed with vdstx context
-    self.assertEqual(f.decode(0), 0)
-    self.assertEqual(f.decode(127), 127)
-
-if __name__ == "__main__":
-  unittest.main()
@@ -1,332 +0,0 @@
-"""Tests for the pcode parser."""
-import unittest
-from collections import defaultdict
-from tinygrad.helpers import DEBUG
-from tinygrad.dtype import dtypes
-from tinygrad.uop.ops import UOp, Ops
-from extra.assembly.amd.emu import parse_pcode
-from extra.assembly.amd.pcode import parse_expr
-from extra.assembly.amd.autogen.rdna3.str_pcode import PCODE
-from extra.assembly.amd.autogen.rdna3.enum import VOP1Op, VOP2Op, VOP3Op, SOP1Op, SOP2Op, DSOp
-
-def _srcs():
-  """Create minimal source variables for pcode parsing."""
-  u32 = lambda v=0: UOp.const(dtypes.uint32, v)
-  return {'S0': u32(), 'S1': u32(), 'S2': u32(), 'SCC': u32(), 'VCC': UOp.const(dtypes.uint64, 0), 'laneId': u32()}
-
-class TestBasicParsing(unittest.TestCase):
-  """Test basic pcode parsing for common instruction patterns."""
-
-  def test_v_add_f32(self):
-    """Test parsing V_ADD_F32 pcode."""
-    _, assigns = parse_pcode(PCODE[VOP2Op.V_ADD_F32_E32], _srcs())
-    self.assertEqual(len(assigns), 1)
-    dest, _ = assigns[0]
-    self.assertTrue(dest.startswith('D0'))
-
-  def test_v_lshlrev_b32(self):
-    """Test parsing V_LSHLREV_B32 pcode."""
-    _, assigns = parse_pcode(PCODE[VOP2Op.V_LSHLREV_B32_E32], _srcs())
-    self.assertEqual(len(assigns), 1)
-
-  def test_s_cselect_b32(self):
-    """Test parsing S_CSELECT_B32 pcode with ternary."""
-    _, assigns = parse_pcode(PCODE[SOP2Op.S_CSELECT_B32], _srcs())
-    self.assertEqual(len(assigns), 1)
-
-  def test_v_add_co_ci_u32(self):
-    """Test parsing V_ADD_CO_CI_U32 with carry."""
-    _, assigns = parse_pcode(PCODE[VOP2Op.V_ADD_CO_CI_U32_E32], _srcs())
-    self.assertGreaterEqual(len(assigns), 1)
-
-class TestWithSources(unittest.TestCase):
-  """Test pcode parsing with actual source operand values."""
-
-  def test_v_add_f32_with_sources(self):
-    """Test V_ADD_F32 with actual float constants."""
-    s0 = UOp.const(dtypes.uint32, 0x3f800000)  # 1.0f
-    s1 = UOp.const(dtypes.uint32, 0x40000000)  # 2.0f
-    _, assigns = parse_pcode(PCODE[VOP2Op.V_ADD_F32_E32], {'S0': s0, 'S1': s1})
-    self.assertEqual(len(assigns), 1)
-    dest, val = assigns[0]
-    self.assertTrue(dest.startswith('D0'))
-    # Result should be an ADD operation
-    self.assertEqual(val.op, Ops.ADD)
-
-  def test_v_mul_f32_with_sources(self):
-    """Test V_MUL_F32 with actual float constants."""
-    s0 = UOp.const(dtypes.uint32, 0x40000000)  # 2.0f
-    s1 = UOp.const(dtypes.uint32, 0x40400000)  # 3.0f
-    _, assigns = parse_pcode(PCODE[VOP2Op.V_MUL_F32_E32], {'S0': s0, 'S1': s1})
-    self.assertEqual(len(assigns), 1)
-    dest, val = assigns[0]
-    self.assertEqual(val.op, Ops.MUL)
-
-class TestParseExpr(unittest.TestCase):
-  """Test the parse_expr function directly."""
-
-  def test_integer_literals(self):
-    """Test parsing integer literals."""
-    self.assertEqual(parse_expr('0', {}).arg, 0)
-    self.assertEqual(parse_expr('42', {}).arg, 42)
-    self.assertEqual(parse_expr('42U', {}).arg, 42)
-
-  def test_negative_integers(self):
-    """Test parsing negative integer literals."""
-    result = parse_expr('-1', {})
-    self.assertEqual(result.arg, -1)
-    self.assertEqual(result.dtype, dtypes.int)
-
-  def test_float_literals(self):
-    """Test parsing float literals."""
-    result = parse_expr('1.0F', {})
-    self.assertEqual(result.arg, 1.0)
-    self.assertEqual(result.dtype, dtypes.float32)
-
-  def test_hex_literals(self):
-    """Test parsing hex literals."""
-    result = parse_expr('0xFF', {})
-    self.assertEqual(result.arg, 255)
-
-  def test_variable_lookup(self):
-    """Test variable lookup in parse_expr."""
-    vars = {'x': UOp.const(dtypes.uint32, 42)}
-    result = parse_expr('x', vars)
-    self.assertEqual(result.arg, 42)
-
-  def test_binary_ops(self):
-    """Test parsing binary operations."""
-    vars = {'a': UOp.const(dtypes.uint32, 10), 'b': UOp.const(dtypes.uint32, 5)}
-
-    # Addition
-    result = parse_expr('a + b', vars)
-    self.assertEqual(result.op, Ops.ADD)
-
-    # Subtraction with constant folding
-    result = parse_expr('10 - 5', {})
-    self.assertEqual(result.op, Ops.CONST)
-    self.assertEqual(result.arg, 5)
-
-  def test_ternary(self):
-    """Test parsing ternary expressions."""
-    vars = {'cond': UOp.const(dtypes.bool, True), 'a': UOp.const(dtypes.uint32, 1), 'b': UOp.const(dtypes.uint32, 0)}
-    result = parse_expr('cond ? a : b', vars)
-    self.assertEqual(result.op, Ops.WHERE)
-
-class TestForLoopParsing(unittest.TestCase):
-  """Test for loop parsing (CLZ/CTZ patterns)."""
-
-  def test_clz_pcode_exists(self):
-    """Verify CLZ pcode is available."""
-    pcode = PCODE.get(VOP1Op.V_CLZ_I32_U32_E32)
-    self.assertIsNotNone(pcode)
-    self.assertIn('for', pcode.lower())
-
-  def test_clz_parsing(self):
-    """Test CLZ pcode parsing produces correct structure."""
-    pcode = PCODE[VOP1Op.V_CLZ_I32_U32_E32]
-    S0 = UOp.const(dtypes.uint32, 0xFFFFFFFF)  # All ones - CLZ should be 0
-    vars, assigns = parse_pcode(pcode, {'S0': S0})
-
-    self.assertEqual(len(assigns), 1)
-    dest, val = assigns[0]
-    self.assertTrue(dest.startswith('D0'))
-    # Result should be a nested WHERE structure
-    self.assertEqual(val.op, Ops.WHERE)
-
-  def test_clz_with_zero(self):
-    """Test CLZ with input 0 - should return -1."""
-    pcode = PCODE[VOP1Op.V_CLZ_I32_U32_E32]
-    S0 = UOp.const(dtypes.uint32, 0)
-    vars, assigns = parse_pcode(pcode, {'S0': S0})
-
-    # Check that the innermost value (default) is -1 (may be wrapped in CAST)
-    val = assigns[0][1]
-    # Traverse to innermost WHERE
-    while val.op == Ops.WHERE:
-      val = val.src[2]  # false branch
-    # Unwrap CAST if present
-    while val.op == Ops.CAST:
-      val = val.src[0]
-    self.assertEqual(val.arg, -1)
-
-  def test_ctz_parsing(self):
-    """Test CTZ pcode parsing."""
-    pcode = PCODE.get(VOP1Op.V_CTZ_I32_B32_E32)
-    if pcode is None:
-      self.skipTest("V_CTZ_I32_B32_E32 pcode not available")
-
-    S0 = UOp.const(dtypes.uint32, 1)  # LSB set - CTZ should be 0
-    vars, assigns = parse_pcode(pcode, {'S0': S0})
-    self.assertEqual(len(assigns), 1)
-
-class TestDSPcodePatterns(unittest.TestCase):
-  """Test DS instruction pcode patterns."""
-
-  def test_ds_load_b32_pcode(self):
-    """Test DS_LOAD_B32 pcode is parseable."""
-    pcode = PCODE.get(DSOp.DS_LOAD_B32)
-    self.assertIsNotNone(pcode)
-    self.assertIn('RETURN_DATA', pcode)
-    self.assertIn('MEM[', pcode)
-
-  def test_ds_store_b32_pcode(self):
-    """Test DS_STORE_B32 pcode is parseable."""
-    pcode = PCODE.get(DSOp.DS_STORE_B32)
-    self.assertIsNotNone(pcode)
-    self.assertIn('MEM[', pcode)
-    self.assertIn('DATA', pcode)
-
-  def test_mem_read_parsing(self):
-    """Test MEM[addr].type read expression parsing."""
-    # Create a mock LDS buffer
-    lds = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(16384), arg=3)
-    addr = UOp.const(dtypes.uint32, 0)
-    vars = {'_lds': lds, 'ADDR': addr, 'OFFSET': UOp.const(dtypes.uint32, 0)}
-
-    result = parse_expr('MEM[ADDR + OFFSET].b32', vars)
-    # Should be an INDEX operation into LDS
-    self.assertIsNotNone(result)
-
-  def test_ds_store_2addr_b32_parsing(self):
-    """Test DS_STORE_2ADDR_B32 pcode parsing produces MEM writes."""
-    pcode = PCODE.get(DSOp.DS_STORE_2ADDR_B32)
-    self.assertIsNotNone(pcode)
-    srcs = {
-      'ADDR': UOp.const(dtypes.uint32, 0),
-      'OFFSET0': UOp.const(dtypes.uint32, 0),
-      'OFFSET1': UOp.const(dtypes.uint32, 1),
-      'DATA': UOp.const(dtypes.uint32, 0xAAAAAAAA),
-      'DATA2': UOp.const(dtypes.uint32, 0xBBBBBBBB),
-    }
-    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
-    _, assigns = parse_pcode(pcode, srcs)
-    # Should have 2 MEM write assignments
-    self.assertEqual(len(assigns), 2)
-    for dest, val in assigns:
-      self.assertTrue(dest.startswith('MEM['))
-      # val should be (addr, write_val) tuple
-      self.assertIsInstance(val, tuple)
-      self.assertEqual(len(val), 2)
-
-  def test_ds_load_2addr_b32_parsing(self):
-    """Test DS_LOAD_2ADDR_B32 pcode parsing produces RETURN_DATA assignments."""
-    pcode = PCODE.get(DSOp.DS_LOAD_2ADDR_B32)
-    self.assertIsNotNone(pcode)
-    lds = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(16384), arg=3)
-    srcs = {
-      'ADDR': UOp.const(dtypes.uint32, 0),
-      'OFFSET0': UOp.const(dtypes.uint32, 0),
-      'OFFSET1': UOp.const(dtypes.uint32, 1),
-      '_lds': lds,
-    }
-    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
-    _, assigns = parse_pcode(pcode, srcs)
-    # Should have 2 RETURN_DATA assignments
-    self.assertEqual(len(assigns), 2)
-    self.assertEqual(assigns[0][0], 'RETURN_DATA[31:0]')
-    self.assertEqual(assigns[1][0], 'RETURN_DATA[63:32]')
-
-  def test_ds_store_address_calculation(self):
-    """Test DS_STORE_2ADDR_B32 calculates correct addresses (offset * 4)."""
-    pcode = PCODE.get(DSOp.DS_STORE_2ADDR_B32)
-    srcs = {
-      'ADDR': UOp.const(dtypes.uint32, 100),
-      'OFFSET0': UOp.const(dtypes.uint32, 2),
-      'OFFSET1': UOp.const(dtypes.uint32, 5),
-      'DATA': UOp.const(dtypes.uint32, 0xAAAAAAAA),
-      'DATA2': UOp.const(dtypes.uint32, 0xBBBBBBBB),
-    }
-    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
-    _, assigns = parse_pcode(pcode, srcs)
-    # Check addresses: 100 + 2*4 = 108, 100 + 5*4 = 120
-    addr0, _ = assigns[0][1]
-    addr1, _ = assigns[1][1]
-    self.assertEqual(addr0.simplify().arg, 108)
-    self.assertEqual(addr1.simplify().arg, 120)
-
-  def test_ds_store_data_values(self):
-    """Test DS_STORE_2ADDR_B32 uses correct data values."""
-    pcode = PCODE.get(DSOp.DS_STORE_2ADDR_B32)
-    srcs = {
-      'ADDR': UOp.const(dtypes.uint32, 0),
-      'OFFSET0': UOp.const(dtypes.uint32, 0),
-      'OFFSET1': UOp.const(dtypes.uint32, 1),
-      'DATA': UOp.const(dtypes.uint32, 0xAAAAAAAA),
-      'DATA2': UOp.const(dtypes.uint32, 0xBBBBBBBB),
-    }
-    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
-    _, assigns = parse_pcode(pcode, srcs)
-    _, val0 = assigns[0][1]
-    _, val1 = assigns[1][1]
-    # DATA[31:0] should preserve the value
-    self.assertEqual(val0.simplify().arg, 0xAAAAAAAA)
-    self.assertEqual(val1.simplify().arg, 0xBBBBBBBB)
-
-class TestConditionalParsing(unittest.TestCase):
-  """Test conditional (if/elsif/else) pcode parsing."""
-
-  def test_ternary_in_assignment(self):
-    """Test parsing ternary expression (which becomes WHERE)."""
-    # S_CSELECT_B32: D0.u32 = SCC ? S0.u32 : S1.u32
-    pcode = PCODE[SOP2Op.S_CSELECT_B32]
-    s0 = UOp.const(dtypes.uint32, 10)
-    s1 = UOp.const(dtypes.uint32, 20)
-    scc = UOp.const(dtypes.uint32, 1)
-    vars, assigns = parse_pcode(pcode, {'S0': s0, 'S1': s1, 'SCC': scc})
-    self.assertEqual(len(assigns), 1)
-    dest, val = assigns[0]
-    self.assertTrue(dest.startswith('D0'))
-    # Result should be a WHERE (ternary becomes WHERE)
-    self.assertEqual(val.op, Ops.WHERE)
-
-class TestAllPcode(unittest.TestCase):
-  """Test that all pcode from all architectures can be parsed."""
-
-  def _make_srcs(self):
-    """Create dummy source variables for pcode parsing."""
-    u32, u64 = lambda v=0: UOp.const(dtypes.uint32, v), lambda v=0: UOp.const(dtypes.uint64, v)
-    lds = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(16384), arg=3)
-    return {'laneId': u32(), 'laneID': u32(), 'S0': u32(), 'S1': u32(), 'S2': u32(), 'S3': u32(), 'SRC0': u32(),
-            'D0': u32(), 'D1': u32(), 'DST': u32(), 'VDST': u32(), 'SDST': u32(),
-            'VCC': u64(), 'VCCZ': u32(), 'EXEC': u64(), 'EXEC_LO': u32(), 'EXECZ': u32(), 'SCC': u32(),
-            'SIMM16': u32(), 'SIMM32': u32(), 'OFFSET': u32(), 'OFFSET0': u32(), 'OFFSET1': u32(), 'offset1': u32(),
-            'ADDR': u32(), 'ADDR_BASE': u32(), 'TADDR': u32(), 'DATA': u32(), 'DATA0': u32(), 'DATA1': u32(), 'DATA2': u32(),
-            'VDATA': u32(), 'VDATA0': u32(), 'VDATA1': u32(), 'VDATA2': u32(), 'VDATA3': u32(),
-            'OPSEL': u32(), 'OPSEL_HI': u32(), 'NEG': u32(), 'NEG_HI': u32(), 'CLAMP': u32(),
-            'M0': u32(), 'PC': u64(), 'DENORM': u32(1), 'ROUND_MODE': u32(), 'ROUND_TOWARD_ZERO': u32(), 'ROUND_NEAREST_EVEN': u32(), 'WAVE_STATUS': u32(),
-            'MAX_FLOAT_F32': u32(0x7f7fffff), 'Unsigned': u32(1), 'clampedLOD': u32(),
-            '_lds': lds, '_vmem': lds, '_active': UOp.const(dtypes.bool, True)}
-
-  def _parse_all_pcode(self, pcode_dict, arch: str, min_pct: float):
-    """Parse all pcode. RuntimeError = parser limitation (ok), other exceptions = real bugs."""
-    srcs = self._make_srcs()
-    passed, skipped, errors = 0, 0, defaultdict(list)
-    for op, pcode in pcode_dict.items():
-      try:
-        parse_pcode(pcode, srcs)
-        passed += 1
-      except RuntimeError as e: skipped += 1; errors[str(e)].append(op.name)
-      except Exception as e: self.fail(f"[{arch}] {op.name}: {e}\nPcode: {pcode[:200]}")
-    total = len(pcode_dict)
-    pct = 100 * passed / total
-    print(f"{arch}: {passed}/{total} ({pct:.1f}%) parsed, {skipped} skipped")
-    if DEBUG >= 2:
-      for err, ops in sorted(errors.items(), key=lambda x: -len(x[1])):
-        print(f"  {err}: {', '.join(ops[:5])}{'...' if len(ops) > 5 else ''} ({len(ops)})")
-    self.assertGreaterEqual(pct, min_pct, f"[{arch}] {pct:.1f}% < {min_pct}% threshold")
-
-  def test_parse_all_cdna_pcode(self):
-    from extra.assembly.amd.autogen.cdna.str_pcode import PCODE as CDNA_PCODE
-    self._parse_all_pcode(CDNA_PCODE, "CDNA", min_pct=60)
-
-  def test_parse_all_rdna3_pcode(self):
-    from extra.assembly.amd.autogen.rdna3.str_pcode import PCODE as RDNA3_PCODE
-    self._parse_all_pcode(RDNA3_PCODE, "RDNA3", min_pct=90)
-
-  def test_parse_all_rdna4_pcode(self):
-    from extra.assembly.amd.autogen.rdna4.str_pcode import PCODE as RDNA4_PCODE
-    self._parse_all_pcode(RDNA4_PCODE, "RDNA4", min_pct=65)
-
-if __name__ == "__main__":
-  unittest.main()
@@ -1,13 +1,176 @@
 #!/usr/bin/env python3
-"""Test DS and other compute-relevant instruction formats.
-
-Note: Graphics-only formats (EXP, MUBUF, MTBUF, MIMG) are not supported - use GLOBAL/FLAT for memory access in compute.
-"""
+"""Test MUBUF, MTBUF, MIMG, EXP, DS formats against LLVM."""
 import unittest
 from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.dsl import VCC_HI, EXEC_LO, NULL
-OFF = NULL  # OFF is alias for NULL
-from extra.assembly.amd import detect_format
+from extra.assembly.amd.dsl import encode_src, RawImm
+from extra.assembly.amd.asm import detect_format
+
+class TestMUBUF(unittest.TestCase):
+  """Test MUBUF (buffer) instructions."""
+
+  def test_buffer_load_b32_basic(self):
+    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]))
+
+  def test_buffer_load_b32_idxen(self):
+    # buffer_load_b32 v5, v0, s[8:11], s3 idxen offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, idxen=1)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03]))
+
+  def test_buffer_load_b32_offen(self):
+    # buffer_load_b32 v5, v0, s[8:11], s3 offen offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x42,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, offen=1)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x42,0x03]))
+
+  def test_buffer_load_b32_glc(self):
+    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 glc
+    # GFX11: encoding: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, glc=1)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]))
+
+  def test_buffer_load_b32_slc(self):
+    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 slc
+    # GFX11: encoding: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, slc=1)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]))
+
+  def test_buffer_load_b32_dlc(self):
+    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 dlc
+    # GFX11: encoding: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, dlc=1)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]))
+
+  def test_buffer_load_b32_all_flags(self):
+    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 glc slc dlc
+    # GFX11: encoding: [0xff,0x7f,0x50,0xe0,0x00,0x05,0x02,0x03]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, glc=1, slc=1, dlc=1)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x7f,0x50,0xe0,0x00,0x05,0x02,0x03]))
+
+  def test_buffer_store_b32(self):
+    # buffer_store_b32 v1, off, s[12:15], s4 offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
+    inst = buffer_store_b32(vdata=v[1], vaddr=v[0], srsrc=s[12:16], soffset=s[4], offset=4095)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]))
+
+  def test_buffer_load_b64(self):
+    # buffer_load_b64 v[5:6], off, s[8:11], s3 offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
+    inst = buffer_load_b64(vdata=v[5:7], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]))
+
+  def test_buffer_load_soffset_m0(self):
+    # buffer_load_b32 v5, off, s[8:11], m0 offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7d]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=M0, offset=4095)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7d]))
+
+  def test_buffer_load_soffset_inline_const(self):
+    # buffer_load_b32 v5, off, s[8:11], 0 offset:4095
+    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=0, offset=4095)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]))
+
+  def test_buffer_disasm_roundtrip(self):
+    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, glc=1)
+    decoded = MUBUF.from_bytes(inst.to_bytes())
+    self.assertEqual(decoded.to_bytes(), inst.to_bytes())
+
+
+class TestMTBUF(unittest.TestCase):
+  """Test MTBUF (typed buffer) instructions."""
+
+  def test_tbuffer_load_format_x(self):
+    # tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_FMT_32_FLOAT] offset:4095
+    # BUF_FMT_32_FLOAT = 22
+    # GFX11: encoding: [0xff,0x0f,0xb0,0xe8,0x00,0x05,0x02,0x03]
+    inst = tbuffer_load_format_x(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, format=22)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0xb0,0xe8,0x00,0x05,0x02,0x03]))
+
+  def test_tbuffer_store_format_x(self):
+    # tbuffer_store_format_x v5, off, s[8:11], s3 format:[BUF_FMT_32_FLOAT] offset:4095
+    # BUF_FMT_32_FLOAT = 22
+    # GFX11: encoding: [0xff,0x0f,0xb2,0xe8,0x00,0x05,0x02,0x03]
+    inst = tbuffer_store_format_x(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, format=22)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0xb2,0xe8,0x00,0x05,0x02,0x03]))
+
+  def test_tbuffer_load_format_xy(self):
+    # tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_FMT_32_32_FLOAT] offset:4095
+    # BUF_FMT_32_32_FLOAT = 50
+    # GFX11: encoding: [0xff,0x8f,0x90,0xe9,0x00,0x05,0x02,0x03]
+    inst = tbuffer_load_format_xy(vdata=v[5:7], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, format=50)
+    self.assertEqual(inst.to_bytes(), bytes([0xff,0x8f,0x90,0xe9,0x00,0x05,0x02,0x03]))
+
+
+class TestMIMG(unittest.TestCase):
+  """Test MIMG (image) instructions."""
+
+  def test_image_load_2d(self):
+    # image_load v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+    # GFX11: encoding: [0x04,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]
+    inst = image_load(vdata=v[0:4], vaddr=v[4:6], srsrc=s[0:8], dmask=0xf, dim=1)  # dim=1 is SQ_RSRC_IMG_2D
+    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]))
+
+  def test_image_store_2d(self):
+    # image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
+    # GFX11: encoding: [0x04,0x0f,0x18,0xf0,0x04,0x00,0x00,0x00]
+    inst = image_store(vdata=v[0:4], vaddr=v[4:6], srsrc=s[0:8], dmask=0xf, dim=1)
+    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x18,0xf0,0x04,0x00,0x00,0x00]))
+
+  def test_image_load_1d(self):
+    # image_load v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
+    # GFX11: encoding: [0x00,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]
+    inst = image_load(vdata=v[0:4], vaddr=v[4], srsrc=s[0:8], dmask=0xf, dim=0)  # dim=0 is SQ_RSRC_IMG_1D
+    self.assertEqual(inst.to_bytes(), bytes([0x00,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]))
+
+  def test_image_sample(self):
+    # image_sample v[0:3], v[4:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+    # GFX11: encoding: [0x04,0x0f,0x6c,0xf0,0x04,0x00,0x00,0x08]
+    inst = image_sample(vdata=v[0:4], vaddr=v[4:6], srsrc=s[0:8], ssamp=s[8:12], dmask=0xf, dim=1)
+    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x6c,0xf0,0x04,0x00,0x00,0x08]))
+
+  def test_image_load_d16(self):
+    # image_load v[0:1], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
+    # GFX11: encoding: [0x04,0x0f,0x02,0xf0,0x04,0x00,0x00,0x00]
+    inst = image_load(vdata=v[0:2], vaddr=v[4:6], srsrc=s[0:8], dmask=0xf, dim=1, d16=1)
+    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x02,0xf0,0x04,0x00,0x00,0x00]))
+
+
+class TestEXP(unittest.TestCase):
+  """Test EXP (export) instructions."""
+
+  def test_exp_mrt0(self):
+    # exp mrt0 v0, v1, v2, v3
+    # GFX11: encoding: [0x0f,0x00,0x00,0xf8,0x00,0x01,0x02,0x03]
+    inst = EXP(en=0xf, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[2], vsrc3=v[3])
+    self.assertEqual(inst.to_bytes(), bytes([0x0f,0x00,0x00,0xf8,0x00,0x01,0x02,0x03]))
+
+  def test_exp_mrtz(self):
+    # exp mrtz v4, v3, v2, v1
+    # GFX11: encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
+    inst = EXP(en=0xf, target=8, vsrc0=v[4], vsrc1=v[3], vsrc2=v[2], vsrc3=v[1])
+    self.assertEqual(inst.to_bytes(), bytes([0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]))
+
+  def test_exp_mrtz_done(self):
+    # exp mrtz v4, v3, v2, v1 done
+    # GFX11: encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
+    inst = EXP(en=0xf, target=8, vsrc0=v[4], vsrc1=v[3], vsrc2=v[2], vsrc3=v[3], done=1)
+    self.assertEqual(inst.to_bytes(), bytes([0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x03]))
+
+  def test_exp_partial_mask(self):
+    # exp mrt0 v0, v1, off, off (en=0x3, only first two components)
+    # GFX11: encoding: [0x03,0x00,0x00,0xf8,0x00,0x01,0x00,0x00]
+    inst = EXP(en=0x3, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[0], vsrc3=v[0])
+    self.assertEqual(inst.to_bytes(), bytes([0x03,0x00,0x00,0xf8,0x00,0x01,0x00,0x00]))
+
+  def test_exp_row_en(self):
+    # exp mrtz v4, v3, v2, v1 row_en
+    # GFX11: encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01]
+    inst = EXP(en=0xf, target=8, vsrc0=v[4], vsrc1=v[3], vsrc2=v[2], vsrc3=v[1], row=1)
+    self.assertEqual(inst.to_bytes(), bytes([0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01]))


 class TestDS(unittest.TestCase):
@@ -34,7 +197,7 @@ class TestDS(unittest.TestCase):
  def test_ds_load_b64(self):
    # ds_load_b64 v[0:1], v2
    # GFX11: encoding: [0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x00]
-    inst = ds_load_b64(vdst=v[0:1], addr=v[2])
+    inst = ds_load_b64(vdst=v[0:2], addr=v[2])
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x00]))

  def test_ds_add_u32(self):
@@ -78,31 +241,31 @@ class TestFLAT(unittest.TestCase):
  def test_global_load_b32(self):
    # global_load_b32 v0, v[1:2], off (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x52,0xdc,0x01,0x00,0x7c,0x00]
-    inst = global_load_b32(vdst=v[0], addr=v[1:2], saddr=OFF)
+    inst = global_load_b32(vdst=v[0], addr=v[1:3], saddr=OFF)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x52,0xdc,0x01,0x00,0x7c,0x00]))

  def test_global_store_b32(self):
    # global_store_b32 v[0:1], v2, off (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x6a,0xdc,0x00,0x02,0x7c,0x00]
-    inst = global_store_b32(addr=v[0:1], data=v[2], saddr=OFF)
+    inst = global_store_b32(addr=v[0:2], data=v[2], saddr=OFF)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x6a,0xdc,0x00,0x02,0x7c,0x00]))

  def test_global_load_b32_saddr(self):
    # global_load_b32 v0, v1, s[0:1] (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x00]
-    inst = global_load_b32(vdst=v[0], addr=v[1], saddr=s[0:1])
+    inst = global_load_b32(vdst=v[0], addr=v[1], saddr=s[0:2])
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x00]))

  def test_global_load_b32_offset(self):
    # global_load_b32 v0, v[1:2], off offset:256 (seg=2 for global)
    # GFX11: encoding: [0x00,0x01,0x52,0xdc,0x01,0x00,0x7c,0x00]
-    inst = global_load_b32(vdst=v[0], addr=v[1:2], saddr=OFF, offset=256)
+    inst = global_load_b32(vdst=v[0], addr=v[1:3], saddr=OFF, offset=256)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x01,0x52,0xdc,0x01,0x00,0x7c,0x00]))

  def test_global_load_b64(self):
    # global_load_b64 v[0:1], v[2:3], off (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x56,0xdc,0x02,0x00,0x7c,0x00]
-    inst = global_load_b64(vdst=v[0:1], addr=v[2:3], saddr=OFF)
+    inst = global_load_b64(vdst=v[0:2], addr=v[2:4], saddr=OFF)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x56,0xdc,0x02,0x00,0x7c,0x00]))


@@ -112,19 +275,19 @@ class TestSMEM(unittest.TestCase):
  def test_smem_dlc_bit_position(self):
    # s_load_b32 s5, s[2:3], s0 dlc - tests that DLC is at bit 13 (not bit 14)
    # GFX11: encoding: [0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00]
-    inst = s_load_b32(sdata=s[5], sbase=s[2:3], soffset=s[0], dlc=1)
+    inst = s_load_b32(sdata=s[5], sbase=s[2], soffset=s[0], dlc=1)
    self.assertEqual(inst.to_bytes(), bytes([0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00]))

  def test_smem_glc_bit_position(self):
    # s_load_b32 s5, s[2:3], s0 glc - tests that GLC is at bit 14 (not bit 16)
    # GFX11: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
-    inst = s_load_b32(sdata=s[5], sbase=s[2:3], soffset=s[0], glc=1)
+    inst = s_load_b32(sdata=s[5], sbase=s[2], soffset=s[0], glc=1)
    self.assertEqual(inst.to_bytes(), bytes([0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]))

  def test_smem_glc_dlc_combined(self):
    # s_load_b32 s5, s[2:3], s0 glc dlc - tests both flags together
    # GFX11: encoding: [0x41,0x61,0x00,0xf4,0x00,0x00,0x00,0x00]
-    inst = s_load_b32(sdata=s[5], sbase=s[2:3], soffset=s[0], glc=1, dlc=1)
+    inst = s_load_b32(sdata=s[5], sbase=s[2], soffset=s[0], glc=1, dlc=1)
    self.assertEqual(inst.to_bytes(), bytes([0x41,0x61,0x00,0xf4,0x00,0x00,0x00,0x00]))

  def test_smem_disasm_roundtrip_dlc(self):
@@ -146,20 +309,23 @@ class TestVOP3Literal(unittest.TestCase):
  def test_vop3_with_literal(self):
    # v_add3_u32 v5, vcc_hi, 0xaf123456, v255
    # GFX11: encoding: [0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
-    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=VCC_HI, src1=0xaf123456, src2=v[255])
+    from extra.assembly.amd.dsl import RawImm
+    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=RawImm(107), src1=0xaf123456, src2=v[255])
    expected = bytes([0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf])
    self.assertEqual(inst.to_bytes(), expected)

  def test_vop3_literal_null_operand(self):
    # v_add3_u32 v5, null, exec_lo, 0xaf123456
    # GFX11: encoding: [0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
-    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=NULL, src1=EXEC_LO, src2=0xaf123456)
+    from extra.assembly.amd.dsl import RawImm
+    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=NULL, src1=RawImm(126), src2=0xaf123456)
    expected = bytes([0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf])
    self.assertEqual(inst.to_bytes(), expected)

  def test_vop3p_with_literal(self):
    # Test VOP3P literal encoding (also uses Inst64)
-    inst = VOP3P(VOP3POp.V_PK_ADD_F16, vdst=v[5], src0=0.5, src1=0x12345678, src2=v[0])
+    from extra.assembly.amd.dsl import RawImm
+    inst = VOP3P(VOP3POp.V_PK_ADD_F16, vdst=v[5], src0=RawImm(240), src1=0x12345678, src2=v[0])
    self.assertEqual(len(inst.to_bytes()), 12)  # 8 bytes + 4 byte literal


@@ -205,16 +371,28 @@ class TestDetectFormat(unittest.TestCase):
    self.assertEqual(detect_format(VOP3P(VOP3POp.V_PK_ADD_F16, v[0], v[1], v[2], v[3]).to_bytes()), VOP3P)

  def test_detect_smem(self):
-    self.assertEqual(detect_format(s_load_b32(sdata=s[0], sbase=s[2:3], offset=0).to_bytes()), SMEM)
-    self.assertEqual(detect_format(s_load_b64(sdata=s[0:1], sbase=s[2:3], soffset=s[5]).to_bytes()), SMEM)
+    self.assertEqual(detect_format(s_load_b32(s[0], s[2:3], 0).to_bytes()), SMEM)
+    self.assertEqual(detect_format(s_load_b64(s[0:1], s[2:3], s[5]).to_bytes()), SMEM)

  def test_detect_ds(self):
    self.assertEqual(detect_format(ds_load_b32(v[0], v[1]).to_bytes()), DS)
    self.assertEqual(detect_format(ds_store_b32(v[0], v[1]).to_bytes()), DS)

  def test_detect_flat(self):
-    self.assertEqual(detect_format(global_load_b32(vdst=v[0], addr=v[1:2], saddr=NULL).to_bytes()), GLOBAL)
-    self.assertEqual(detect_format(global_store_b32(addr=v[0:1], data=v[2], saddr=NULL).to_bytes()), GLOBAL)
+    self.assertEqual(detect_format(global_load_b32(v[0], v[1:3], RawImm(124)).to_bytes()), FLAT)
+    self.assertEqual(detect_format(global_store_b32(v[0:2], v[2], RawImm(124)).to_bytes()), FLAT)
+
+  def test_detect_mubuf(self):
+    self.assertEqual(detect_format(buffer_load_b32(v[0], v[1], s[0:4], s[5]).to_bytes()), MUBUF)
+
+  def test_detect_mtbuf(self):
+    self.assertEqual(detect_format(tbuffer_load_format_x(v[0], v[1], s[0:4], s[5], format=22).to_bytes()), MTBUF)
+
+  def test_detect_mimg(self):
+    self.assertEqual(detect_format(image_load(v[0:4], v[4:6], s[0:8], dmask=0xf, dim=1).to_bytes()), MIMG)
+
+  def test_detect_exp(self):
+    self.assertEqual(detect_format(EXP(en=0xf, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[2], vsrc3=v[3]).to_bytes()), EXP)

  def test_detect_vopd(self):
    inst = VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, vdstx=v[0], vdsty=v[1], srcx0=0, srcy0=0)
@@ -4,32 +4,29 @@
 import unittest, struct
 from extra.assembly.amd.autogen.rdna3.ins import *
 from extra.assembly.amd.dsl import Inst
+from extra.assembly.amd.asm import asm
 from extra.assembly.amd.test.test_roundtrip import compile_asm

-class IntegrationTestBase(unittest.TestCase):
+class TestIntegration(unittest.TestCase):
  inst: Inst
-  arch: str
  def tearDown(self):
    if not hasattr(self, 'inst'): return
    b = self.inst.to_bytes()
    st = self.inst.disasm()
-    # Test that the instruction can be compiled by LLVM and produces the same bytes
-    desc = f"{st:25s} {self.inst} {b!r}"
-    self.assertEqual(b, compile_asm(st, arch=self.arch), desc)
+    reasm = asm(st)
+    desc = f"{st:25s} {self.inst} {b!r} {reasm}"
+    self.assertEqual(b, compile_asm(st), desc)
+    # TODO: this compare should work for valid things
+    #self.assertEqual(self.inst, reasm)
+    self.assertEqual(repr(self.inst), repr(reasm))
    print(desc)

-class TestIntegration(IntegrationTestBase):
-  arch: str = "rdna3"
-
-  def test_wmma(self):
-    self.inst = v_wmma_f32_16x16x16_f16(v[0:7], v[184:191], v[136:143], v[0:7])
-
  def test_load_b128(self):
    self.inst = s_load_b128(s[4:7], s[0:1], NULL, 0)

  def test_load_b128_wrong_size(self):
    # this should have to be 4 regs on the loaded to
-    with self.assertRaises(TypeError):
+    with self.assertRaises(Exception):
      self.inst = s_load_b128(s[4:6], s[0:1], NULL, 0)

  def test_mov_b32(self):
@@ -128,17 +125,6 @@ class TestIntegration(IntegrationTestBase):
    int_inst = s_mov_b32(s[0], struct.unpack("I", struct.pack("f", 1337.0))[0])
    self.assertEqual(self.inst, int_inst)

-class TestIntegrationCDNA(IntegrationTestBase):
-  arch = "cdna"
-
-  def test_mfma(self):
-    from extra.assembly.amd.autogen.cdna.ins import v_mfma_f32_16x16x16_f16
-    self.inst = v_mfma_f32_16x16x16_f16(v[0:3], v[0:1], v[0:1], 0)
-
-  def test_mfma_fp8(self):
-    from extra.assembly.amd.autogen.cdna.ins import v_mfma_f32_16x16x128_f8f6f4
-    self.inst = v_mfma_f32_16x16x128_f8f6f4(v[0:3], v[0:5], v[0:5], 1, cbsz=2, blgp=2)
-
 class TestRegisterSliceSyntax(unittest.TestCase):
  """
  Issue: Register slice syntax should use AMD assembly convention (inclusive end).
@@ -154,7 +140,7 @@ class TestRegisterSliceSyntax(unittest.TestCase):
  def test_register_slice_count(self):
    # s[4:7] should give 4 registers: s4, s5, s6, s7 (AMD convention, inclusive)
    reg = s[4:7]
-    self.assertEqual(reg.sz, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")
+    self.assertEqual(reg.count, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")

  def test_register_slice_roundtrip(self):
    # Round-trip: DSL -> disasm -> DSL should preserve register count
@@ -165,7 +151,7 @@ class TestRegisterSliceSyntax(unittest.TestCase):
    self.assertIn("s[4:7]", disasm)
    # And s[4:7] in DSL should give the same 4 registers
    reg_from_disasm = s[4:7]
-    self.assertEqual(reg_from_disasm.sz, 4, "s[4:7] from disasm should give 4 registers")
+    self.assertEqual(reg_from_disasm.count, 4, "s[4:7] from disasm should give 4 registers")

 class TestInstructionEquality(unittest.TestCase):
  """
@@ -1,10 +1,9 @@
 #!/usr/bin/env python3
 """Integration test: round-trip RDNA3 assembly through AMD toolchain."""
-import unittest, io, sys
+import unittest, re, io, sys, subprocess
 from extra.assembly.amd.autogen.rdna3.ins import *
-
-def waitcnt(vmcnt: int = 0x3f, expcnt: int = 0x7, lgkmcnt: int = 0x3f) -> int:
-  return (expcnt & 0x7) | ((lgkmcnt & 0x3f) << 4) | ((vmcnt & 0x3f) << 10)
+from extra.assembly.amd.asm import waitcnt, asm
+from extra.assembly.amd.test.helpers import get_llvm_mc

 def disassemble(lib: bytes, arch: str = "gfx1100") -> str:
  """Disassemble ELF binary using tinygrad's compiler, return raw output."""
@@ -41,7 +40,7 @@ def assemble_and_disassemble(instructions: list, arch: str = "gfx1100") -> list[
  return parse_disassembly(disassemble(lib, arch))

 class TestIntegration(unittest.TestCase):
-  """Test our DSL output matches LLVM disassembly."""
+  """Test our assembler output matches LLVM disassembly."""

  def test_simple_sop1(self):
    """Test SOP1 instructions round-trip."""
@@ -91,9 +90,9 @@ class TestIntegration(unittest.TestCase):
  def test_memory_ops(self):
    """Test memory instructions."""
    instructions = [
-      s_load_b32(s[0], s[0:1], NULL),
+      s_load_b32(s[0], s[0:2], NULL),
      s_waitcnt(simm16=waitcnt(lgkmcnt=0)),
-      global_store_b32(addr=v[0:1], data=v[2], saddr=OFF),
+      global_store_b32(addr=v[0:2], data=v[2], saddr=OFF),
      s_endpgm(),
    ]
    disasm = assemble_and_disassemble(instructions)
@@ -109,12 +108,12 @@ class TestIntegration(unittest.TestCase):
      v_mov_b32_e32(v[0], s[0]),  # base addr low
      v_mov_b32_e32(v[1], s[1]),  # base addr high
      # Load value
-      global_load_b32(vdst=v[2], addr=v[0:1], saddr=OFF),
+      global_load_b32(vdst=v[2], addr=v[0:2], saddr=OFF),
      s_waitcnt(simm16=waitcnt(vmcnt=0)),
      # Add 1.0
      v_add_f32_e32(v[2], 1.0, v[2]),
      # Store result
-      global_store_b32(addr=v[0:1], data=v[2], saddr=OFF),
+      global_store_b32(addr=v[0:2], data=v[2], saddr=OFF),
      s_endpgm(),
    ]
    disasm = assemble_and_disassemble(instructions)
@@ -149,6 +148,79 @@ class TestIntegration(unittest.TestCase):
        return
    self.fail("Could not find s_mov_b32 in disassembly")

+class TestAsm(unittest.TestCase):
+  """Test asm() string parsing."""
+
+  def test_asm_basic(self):
+    """Test basic instruction parsing."""
+    inst = asm('s_mov_b32 s0, s1')
+    self.assertEqual(inst.to_bytes(), s_mov_b32(s[0], s[1]).to_bytes())
+
+  def test_asm_with_immediates(self):
+    """Test parsing with immediate values."""
+    inst = asm('s_add_u32 s0, s1, 10')
+    self.assertEqual(inst.to_bytes(), s_add_u32(s[0], s[1], 10).to_bytes())
+
+  def test_asm_float_const(self):
+    """Test parsing float constants."""
+    inst = asm('v_mul_f32_e32 v0, 1.0, v1')
+    self.assertEqual(inst.to_bytes(), v_mul_f32_e32(v[0], 1.0, v[1]).to_bytes())
+
+  def test_asm_hex_immediate(self):
+    """Test parsing hex immediates."""
+    inst = asm('s_waitcnt 0xfc07')
+    self.assertEqual(inst.to_bytes(), s_waitcnt(simm16=0xfc07).to_bytes())
+
+  def test_asm_special_regs(self):
+    """Test parsing special registers."""
+    inst = asm('s_mov_b32 s0, vcc_lo')
+    self.assertEqual(inst.to_bytes(), s_mov_b32(s[0], VCC_LO).to_bytes())
+
+  def test_asm_register_range(self):
+    """Test parsing register ranges."""
+    inst = asm('s_load_b128 s[4:7], s[0:1], null')
+    self.assertEqual(inst.to_bytes(), s_load_b128(s[4:7], s[0:1], NULL).to_bytes())
+
+  def test_asm_matches_llvm(self):
+    """Test asm() output matches LLVM assembler."""
+    from tinygrad.runtime.support.compiler_amd import HIPCompiler
+    compiler = HIPCompiler('gfx1100')
+
+    def get_llvm_bytes(instr: str) -> bytes:
+      src = f'.text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n{instr}\n'
+      lib = compiler.compile(src)
+      raw = disassemble(lib)
+      for line in raw.splitlines():
+        if instr.split()[0] in line and '//' in line:
+          hex_str = line.split('//')[1].strip().split(':')[1].strip()
+          return bytes.fromhex(hex_str)[::-1]
+      return b''
+
+    tests = ['s_mov_b32 s0, s1', 's_endpgm', 'v_add_f32_e32 v0, v1, v2']
+    for t in tests:
+      self.assertEqual(asm(t).to_bytes(), get_llvm_bytes(t), f"mismatch for: {t}")
+
+  def test_asm_vop3_modifiers(self):
+    """Test asm() with VOP3 modifiers (neg, abs, clamp)."""
+    def get_llvm_encoding(instr: str) -> str:
+      result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', '-mcpu=gfx1100', '-show-encoding'],
+                              input=instr, capture_output=True, text=True)
+      if m := re.search(r'encoding:\s*\[(.*?)\]', result.stdout):
+        return m.group(1).replace('0x','').replace(',','').replace(' ','')
+      return ''
+
+    tests = [
+      'v_fma_f32 v0, -v1, v2, v3',       # neg on src0
+      'v_fma_f32 v0, v1, |v2|, v3',      # abs on src1
+      'v_fma_f32 v0, v1, v2, v3 clamp',  # clamp
+      'v_fma_f32 v0, -v1, |v2|, v3 clamp',  # all modifiers
+      'v_fma_f32 v0, -|v1|, v2, v3',     # neg+abs on same operand
+    ]
+    for t in tests:
+      our_hex = asm(t).to_bytes().hex()
+      llvm_hex = get_llvm_encoding(t)
+      self.assertEqual(our_hex, llvm_hex, f"mismatch for: {t}")
+
 class TestTinygradIntegration(unittest.TestCase):
  """Test that we can parse disassembled tinygrad kernels."""

@@ -1,183 +1,201 @@
 #!/usr/bin/env python3
-"""Test AMD assembler/disassembler against LLVM test vectors.
-
-Only compute-relevant instruction formats are tested. Graphics-only formats not supported:
-  - MUBUF/MTBUF: buffer instructions with resource descriptors (use GLOBAL/FLAT instead)
-  - MIMG: image/texture instructions
-  - EXP/VEXPORT: export instructions for pixel/vertex output
-  - VIMAGE/VSAMPLE: image sampling instructions (RDNA4)
-  - VBUFFER: buffer instructions (RDNA4)
-"""
-import unittest, re, subprocess, functools
+"""Test RDNA3 assembler/disassembler against LLVM test vectors."""
+import unittest, re, subprocess
 from tinygrad.helpers import fetch
-from extra.assembly.amd.disasm import disasm
-from extra.assembly.amd import decode_inst, detect_format
-from extra.assembly.amd.test.helpers import get_llvm_mc, get_target, get_mattr
+from extra.assembly.amd.autogen.rdna3.ins import *
+from extra.assembly.amd.asm import asm
+from extra.assembly.amd.test.helpers import get_llvm_mc

-LLVM_BASE = "https://raw.githubusercontent.com/llvm/llvm-project/llvmorg-21.1.0/llvm/test/MC/AMDGPU"
+LLVM_BASE = "https://raw.githubusercontent.com/llvm/llvm-project/main/llvm/test/MC/AMDGPU"

-# RDNA3 (gfx11) test files for compute instructions
-# Excluded: gfx11_asm_mubuf.s, gfx11_asm_mtbuf.s, gfx11_asm_mimg.s, gfx11_asm_mubuf_alias.s, gfx11_asm_mtbuf_alias.s (graphics-only)
-RDNA_FILES = ['gfx11_asm_sop1.s', 'gfx11_asm_sop2.s', 'gfx11_asm_sopp.s', 'gfx11_asm_sopk.s', 'gfx11_asm_sopc.s',
-  'gfx11_asm_vop1.s', 'gfx11_asm_vop2.s', 'gfx11_asm_vopc.s', 'gfx11_asm_vop3.s', 'gfx11_asm_vop3p.s', 'gfx11_asm_vinterp.s',
-  'gfx11_asm_vopd.s', 'gfx11_asm_vopcx.s', 'gfx11_asm_vop3_from_vop1.s', 'gfx11_asm_vop3_from_vop2.s', 'gfx11_asm_vop3_from_vopc.s',
-  'gfx11_asm_vop3_from_vopcx.s', 'gfx11_asm_ds.s', 'gfx11_asm_smem.s', 'gfx11_asm_flat.s',
-  'gfx11_asm_wmma.s', 'gfx11_asm_vop3_features.s', 'gfx11_asm_vop3p_features.s', 'gfx11_asm_vopd_features.s',
-  'gfx11_asm_vop3_alias.s', 'gfx11_asm_vop3p_alias.s', 'gfx11_asm_vopc_alias.s', 'gfx11_asm_vopcx_alias.s', 'gfx11_asm_vinterp_alias.s',
-  'gfx11_asm_smem_alias.s']
-# CDNA (gfx9/gfx90a/gfx942/gfx950) test files for compute instructions
-# Excluded: gfx9_asm_mubuf.s, gfx9_asm_mtbuf.s, gfx90a_ldst_acc.s (has MIMG mixed in)
-# Exclude gfx90a: 'gfx90a_asm_features.s', 'mai-gfx90a.s',
-# Exclude gfx950: 'gfx950_asm_features.s' (disasm error)
-CDNA_FILES = ['gfx9_asm_sop1.s', 'gfx9_asm_sop2.s', 'gfx9_asm_sopp.s', 'gfx9_asm_sopk.s', 'gfx9_asm_sopc.s',
-  'gfx9_asm_vop1.s', 'gfx9_asm_vop2.s', 'gfx9_asm_vopc.s', 'gfx9_asm_vop3.s', 'gfx9_asm_vop3p.s',
-  'gfx9_asm_ds.s', 'gfx9_asm_flat.s', 'gfx9_asm_smem.s',
-  'flat-scratch-gfx942.s', 'gfx942_asm_features.s', 'mai-gfx942.s',
-  'gfx950_asm_vop1.s', 'gfx950_asm_read_tr.s', 'mai-gfx950.s']
-# RDNA4 (gfx12) test files for compute instructions
-# Excluded: gfx12_asm_vbuffer_mubuf.s, gfx12_asm_vbuffer_mtbuf.s, gfx12_asm_exp.s (graphics-only)
-RDNA4_FILES = ['gfx12_asm_sop1.s', 'gfx12_asm_sop2.s', 'gfx12_asm_sopp.s', 'gfx12_asm_sopk.s', 'gfx12_asm_sopc.s',
-  'gfx12_asm_vop1.s', 'gfx12_asm_vop2.s', 'gfx12_asm_vopc.s', 'gfx12_asm_vopcx.s', 'gfx12_asm_vop3.s', 'gfx12_asm_vop3c.s',
-  'gfx12_asm_vop3cx.s', 'gfx12_asm_vop3p.s', 'gfx12_asm_vop3_from_vop1.s', 'gfx12_asm_vop3_from_vop2.s',
-  'gfx12_asm_vop3p_features.s', 'gfx12_asm_vopd.s', 'gfx12_asm_vopd_features.s',
-  'gfx12_asm_ds.s', 'gfx12_asm_smem.s',
-  'gfx12_asm_wmma_w32.s']
+# Format info: (filename, format_class, op_enum)
+LLVM_TEST_FILES = {
+  # Scalar ALU
+  'sop1': ('gfx11_asm_sop1.s', SOP1, SOP1Op),
+  'sop2': ('gfx11_asm_sop2.s', SOP2, SOP2Op),
+  'sopp': ('gfx11_asm_sopp.s', SOPP, SOPPOp),
+  'sopk': ('gfx11_asm_sopk.s', SOPK, SOPKOp),
+  'sopc': ('gfx11_asm_sopc.s', SOPC, SOPCOp),
+  # Vector ALU
+  'vop1': ('gfx11_asm_vop1.s', VOP1, VOP1Op),
+  'vop2': ('gfx11_asm_vop2.s', VOP2, VOP2Op),
+  'vopc': ('gfx11_asm_vopc.s', VOPC, VOPCOp),
+  'vop3': ('gfx11_asm_vop3.s', VOP3, VOP3Op),
+  'vop3p': ('gfx11_asm_vop3p.s', VOP3P, VOP3POp),
+  'vop3sd': ('gfx11_asm_vop3.s', VOP3SD, VOP3SDOp),  # VOP3SD shares file with VOP3
+  'vinterp': ('gfx11_asm_vinterp.s', VINTERP, VINTERPOp),
+  'vopd': ('gfx11_asm_vopd.s', VOPD, VOPDOp),
+  'vopcx': ('gfx11_asm_vopcx.s', VOPC, VOPCOp),  # VOPCX uses VOPC format
+  # VOP3 promotions (VOP1/VOP2/VOPC promoted to VOP3 encoding)
+  'vop3_from_vop1': ('gfx11_asm_vop3_from_vop1.s', VOP3, VOP3Op),
+  'vop3_from_vop2': ('gfx11_asm_vop3_from_vop2.s', VOP3, VOP3Op),
+  'vop3_from_vopc': ('gfx11_asm_vop3_from_vopc.s', VOP3, VOP3Op),
+  'vop3_from_vopcx': ('gfx11_asm_vop3_from_vopcx.s', VOP3, VOP3Op),
+  # Memory
+  'ds': ('gfx11_asm_ds.s', DS, DSOp),
+  'smem': ('gfx11_asm_smem.s', SMEM, SMEMOp),
+  'flat': ('gfx11_asm_flat.s', FLAT, FLATOp),
+  'mubuf': ('gfx11_asm_mubuf.s', MUBUF, MUBUFOp),
+  'mtbuf': ('gfx11_asm_mtbuf.s', MTBUF, MTBUFOp),
+  'mimg': ('gfx11_asm_mimg.s', MIMG, MIMGOp),
+  # WMMA (matrix multiply)
+  'wmma': ('gfx11_asm_wmma.s', VOP3P, VOP3POp),
+  # Additional features
+  'vop3_features': ('gfx11_asm_vop3_features.s', VOP3, VOP3Op),
+  'vop3p_features': ('gfx11_asm_vop3p_features.s', VOP3P, VOP3POp),
+  'vopd_features': ('gfx11_asm_vopd_features.s', VOPD, VOPDOp),
+  # Alias files (alternative mnemonics)
+  'vop3_alias': ('gfx11_asm_vop3_alias.s', VOP3, VOP3Op),
+  'vop3p_alias': ('gfx11_asm_vop3p_alias.s', VOP3P, VOP3POp),
+  'vopc_alias': ('gfx11_asm_vopc_alias.s', VOPC, VOPCOp),
+  'vopcx_alias': ('gfx11_asm_vopcx_alias.s', VOPC, VOPCOp),
+  'vinterp_alias': ('gfx11_asm_vinterp_alias.s', VINTERP, VINTERPOp),
+  'smem_alias': ('gfx11_asm_smem_alias.s', SMEM, SMEMOp),
+  'mubuf_alias': ('gfx11_asm_mubuf_alias.s', MUBUF, MUBUFOp),
+  'mtbuf_alias': ('gfx11_asm_mtbuf_alias.s', MTBUF, MTBUFOp),
+}

-def _parse_llvm_tests(text: str, pattern: str) -> list[tuple[str, bytes]]:
-  tests = []
-  for block in text.split('\n\n'):
-    asm_text, encoding = None, None
-    for line in block.split('\n'):
-      line = line.strip()
-      if not line or line.startswith(('.', ';')): continue
-      if not line.startswith('//'):
-        asm_text = line.split('//')[0].strip() or asm_text
-      if m := re.search(pattern + r'[^:]*:.*?(?:encoding:\s*)?\[(0x[0-9a-f,x\s]+)\]', line, re.I):
-        encoding = m.group(1).replace('0x', '').replace(',', '').replace(' ', '')
-    if asm_text and encoding:
-      try: tests.append((asm_text, bytes.fromhex(encoding)))
-      except ValueError: pass
+def parse_llvm_tests(text: str) -> list[tuple[str, bytes]]:
+  """Parse LLVM test format into (asm, expected_bytes) pairs."""
+  tests, lines = [], text.split('\n')
+  for i, line in enumerate(lines):
+    line = line.strip()
+    if not line or line.startswith(('//', '.', ';')): continue
+    asm_text = line.split('//')[0].strip()
+    if not asm_text: continue
+    for j in range(i, min(i + 3, len(lines))):
+      # Match GFX11, W32, or W64 encodings (all valid for gfx11)
+      # Format 1: "// GFX11: v_foo ... ; encoding: [0x01,0x02,...]"
+      # Format 2: "// GFX11: [0x01,0x02,...]" (used by DS, older files)
+      if m := re.search(r'(?:GFX11|W32|W64)[^:]*:.*?encoding:\s*\[(.*?)\]', lines[j]):
+        hex_bytes = m.group(1).replace('0x', '').replace(',', '').replace(' ', '')
+      elif m := re.search(r'(?:GFX11|W32|W64)[^:]*:\s*\[(0x[0-9a-fA-F,x\s]+)\]', lines[j]):
+        hex_bytes = m.group(1).replace('0x', '').replace(',', '').replace(' ', '')
+      else:
+        continue
+      if hex_bytes:
+        try: tests.append((asm_text, bytes.fromhex(hex_bytes)))
+        except ValueError: pass
+      break
  return tests

-def _get_tests_uncached(f: str, arch: str) -> list[tuple[str, bytes]]:
-  text = fetch(f"{LLVM_BASE}/{f}").read_bytes().decode('utf-8', errors='ignore')
-  if arch == "rdna3":
-    # Match GFX11 and W32 only (wavefront32 mode)
-    tests = _parse_llvm_tests(text, r'(?:GFX11|W32)')
-  elif arch == "rdna4":
-    # Match GFX12 (but not GFX1250) and W32 only (wavefront32 mode)
-    tests = _parse_llvm_tests(text, r'(?:GFX12(?!50)|W32)')
-  elif 'gfx90a' in f or 'gfx942' in f or 'gfx950' in f:
-    tests = _parse_llvm_tests(text, r'(?:GFX90A|GFX942|GFX950)')
-  else:
-    tests = _parse_llvm_tests(text, r'(?:VI9|GFX9|CHECK)')
-  # Exclude v_interp_* (graphics-only, not on CDNA)
-  if arch == "cdna": tests = [(asm, data) for asm, data in tests if not asm.startswith('v_interp_')]
-  # Filter out tests where original ASM isn't valid on target (e.g., gfx9 tests with gfx942/gfx950 constraints)
-  if arch == "cdna" and not ('gfx942' in f or 'gfx950' in f or 'gfx90a' in f): tests = _filter_valid_asm(tests, arch)
-  return tests
+def try_assemble(text: str):
+  """Try to assemble instruction text, return bytes or None on failure."""
+  try: return asm(text).to_bytes()
+  except: return None

-@functools.cache
-def _get_tests(f: str, arch: str) -> list[tuple[str, bytes]]: return _get_tests_uncached(f, arch)
-
-def _compile_asm_batch(instrs: list[str], arch: str = "rdna3", mcpu: str|None = None) -> list[bytes]:
+def compile_asm_batch(instrs: list[str]) -> list[bytes]:
+  """Compile multiple instructions with a single llvm-mc call."""
  if not instrs: return []
-  mcpu, mattr = mcpu or get_target(arch), get_mattr(arch)
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', f'-mattr={mattr}', '-show-encoding'],
-    input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True, timeout=30)
-  if result.returncode != 0: raise RuntimeError(f"llvm-mc failed: {result.stderr.strip()}")
-  return [bytes.fromhex(line.split('encoding:')[1].strip()[1:-1].replace('0x', '').replace(',', '').replace(' ', ''))
-          for line in result.stdout.split('\n') if 'encoding:' in line]
+  asm_text = ".text\n" + "\n".join(instrs) + "\n"
+  result = subprocess.run(
+    [get_llvm_mc(), '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+    input=asm_text, capture_output=True, text=True, timeout=30)
+  if result.returncode != 0: raise RuntimeError(f"llvm-mc batch failed: {result.stderr.strip()}")
+  # Parse all encodings from output
+  results = []
+  for line in result.stdout.split('\n'):
+    if 'encoding:' not in line: continue
+    enc = line.split('encoding:')[1].strip()
+    if enc.startswith('[') and enc.endswith(']'):
+      results.append(bytes.fromhex(enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')))
+  if len(results) != len(instrs): raise RuntimeError(f"expected {len(instrs)} encodings, got {len(results)}")
+  return results

-def _filter_valid_asm(tests: list[tuple[str, bytes]], arch: str) -> list[tuple[str, bytes]]:
-  """Filter out tests where the original ASM isn't valid on the target (e.g., gfx9 tests with gfx942/gfx950 constraints)."""
-  if not tests: return []
-  mcpu = get_target(arch)
-  # Batch assemble all instructions, parse stderr to find which lines failed
-  instrs = [asm for asm, _ in tests]
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', '-show-encoding'],
-    input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True, timeout=30)
-  # Parse error lines from stderr (format: "<stdin>:N:..." where N is 1-indexed, line 1 is ".text")
-  failed_lines = set()
-  for line in result.stderr.split('\n'):
-    if m := re.match(r'<stdin>:(\d+):', line): failed_lines.add(int(m.group(1)) - 1)  # -1 for .text, so line 2 -> index 1 -> tests[0]
-  # Also filter out tests where LLVM roundtrip doesn't match original (reserved bits set in original)
-  valid = [(asm, data) for i, (asm, data) in enumerate(tests) if (i + 1) not in failed_lines]
-  if not valid: return []
-  llvm_result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', '-show-encoding'],
-    input=".text\n" + "\n".join(asm for asm, _ in valid) + "\n", capture_output=True, text=True, timeout=30)
-  llvm_bytes = [bytes.fromhex(line.split('encoding:')[1].strip()[1:-1].replace('0x', '').replace(',', '').replace(' ', ''))
-                for line in llvm_result.stdout.split('\n') if 'encoding:' in line]
-  return [(asm, data) for (asm, data), lb in zip(valid, llvm_bytes) if lb == data]
+class TestLLVM(unittest.TestCase):
+  """Test assembler and disassembler against all LLVM test vectors."""
+  tests: dict[str, list[tuple[str, bytes]]] = {}

-def _make_test(f: str, arch: str, test_type: str):
+  @classmethod
+  def setUpClass(cls):
+    for name, (filename, _, _) in LLVM_TEST_FILES.items():
+      try:
+        data = fetch(f"{LLVM_BASE}/{filename}").read_bytes()
+        cls.tests[name] = parse_llvm_tests(data.decode('utf-8', errors='ignore'))
+      except Exception as e:
+        print(f"Warning: couldn't fetch {filename}: {e}")
+        cls.tests[name] = []
+
+# Generate test methods dynamically for each format
+def _make_asm_test(name):
  def test(self):
-    tests = _get_tests(f, arch)
-    name = f"{arch}_{test_type}_{f}"
-    mcpu = "gfx942" if arch == "cdna" and "gfx942" in f else get_target(arch)
-    if test_type == "roundtrip":
-      passed, skipped = 0, 0
-      for _, data in tests:
-        try:
-          decoded = detect_format(data, arch).from_bytes(data)
-          self.assertEqual(decoded.to_bytes()[:len(data)], data)
-          passed += 1
-        except ValueError: skipped += 1  # skip invalid opcodes not in enum
-      print(f"{name}: {passed} passed, {skipped} skipped")
-      self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
-    elif test_type == "repr":
-      # Test that eval(repr(inst)) reproduces the instruction
-      if arch == "rdna3": import extra.assembly.amd.autogen.rdna3.ins as ins
-      elif arch == "rdna4": import extra.assembly.amd.autogen.rdna4.ins as ins
-      elif arch == "cdna": import extra.assembly.amd.autogen.cdna.ins as ins
-      ns = {k: getattr(ins, k) for k in dir(ins) if not k.startswith('_')}
-      passed, skipped = 0, 0
-      for _, data in tests:
-        try:
-          decoded = detect_format(data, arch).from_bytes(data)
-          if decoded.to_bytes()[:len(data)] != data: skipped += 1; continue  # skip if binary roundtrip fails
-          r = repr(decoded)
-          try:
-            decoded2 = eval(r, ns)  # noqa: S307
-            if decoded == decoded2: passed += 1
-            else: skipped += 1
-          except Exception: skipped += 1
-        except ValueError: skipped += 1
-      print(f"{name}: {passed} passed, {skipped} skipped")
-      self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
-    elif test_type == "disasm":
-      to_test = []
-      for _, data in tests:
-        try:
-          decoded = decode_inst(data, arch)
-          enc = decoded.to_bytes()[:len(data)]
-          # Skip if roundtrip fails, disasm fails, or op_name is missing (disasm starts with space)
-          if enc == data and (d := disasm(decoded)) and not d.startswith(' '): to_test.append((enc, d))
-        except: pass
-      skipped = len(tests) - len(to_test)
-      print(f"{name}: {len(to_test)} passed, {skipped} skipped")
-      self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
-      # Compare disasm->reassemble with original encoding (filter reserved bit cases where LLVM can't reproduce)
-      llvm_bytes = _compile_asm_batch([t[1] for t in to_test], arch, mcpu)
-      valid = [(enc, d, llvm) for (enc, d), llvm in zip(to_test, llvm_bytes) if llvm == enc]
-      print(f"{name}: {len(valid)}/{len(to_test)} matched LLVM encoding")
-      for enc, _, llvm in valid: self.assertEqual(llvm, enc)
+    passed, failed, skipped = 0, 0, 0
+    for asm_text, expected in self.tests.get(name, []):
+      result = try_assemble(asm_text)
+      if result is None: skipped += 1
+      elif result == expected: passed += 1
+      else: failed += 1
+    print(f"{name.upper()} asm: {passed} passed, {failed} failed, {skipped} skipped")
+    self.assertEqual(failed, 0)
  return test

-class TestLLVM(unittest.TestCase): pass
+def _make_disasm_test(name):
+  def test(self):
+    _, fmt_cls, op_enum = LLVM_TEST_FILES[name]
+    # VOP3SD opcodes that share encoding with VOP3 (only for vop3sd test, not vopc promotions)
+    vop3sd_opcodes = {288, 289, 290, 764, 765, 766, 767, 768, 769, 770}
+    is_vopc_promotion = name in ('vop3_from_vopc', 'vop3_from_vopcx')
+    undocumented = {'smem': {34, 35}, 'sopk': {22, 23}, 'sopp': {8, 58, 59}}

-for f in RDNA_FILES:
-  setattr(TestLLVM, f"test_rdna3_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "roundtrip"))
-  setattr(TestLLVM, f"test_rdna3_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "disasm"))
-  setattr(TestLLVM, f"test_rdna3_repr_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "repr"))
-for f in CDNA_FILES:
-  setattr(TestLLVM, f"test_cdna_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "roundtrip"))
-  setattr(TestLLVM, f"test_cdna_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "disasm"))
-  setattr(TestLLVM, f"test_cdna_repr_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "repr"))
-for f in RDNA4_FILES:
-  setattr(TestLLVM, f"test_rdna4_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "roundtrip"))
-  setattr(TestLLVM, f"test_rdna4_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "disasm"))
-  setattr(TestLLVM, f"test_rdna4_repr_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "repr"))
+    # First pass: decode all instructions and collect disasm strings
+    to_test: list[tuple[str, bytes, str | None, str | None]] = []  # (asm_text, data, disasm_str, error)
+    skipped = 0
+    for asm_text, data in self.tests.get(name, []):
+      if len(data) > fmt_cls._size(): continue
+      temp_inst = fmt_cls.from_bytes(data)
+      temp_op = temp_inst._values.get('op', 0)
+      temp_op = temp_op.val if hasattr(temp_op, 'val') else temp_op
+      if temp_op in undocumented.get(name, set()): skipped += 1; continue
+      if name == 'sopp':
+        simm16 = temp_inst._values.get('simm16', 0)
+        simm16 = simm16.val if hasattr(simm16, 'val') else simm16
+        sopp_no_imm = {48, 54, 53, 55, 60, 61, 62}
+        if temp_op in sopp_no_imm and simm16 != 0: skipped += 1; continue
+      try:
+        if fmt_cls.__name__ in ('VOP3', 'VOP3SD'):
+          temp = VOP3.from_bytes(data)
+          op_val = temp._values.get('op', 0)
+          op_val = op_val.val if hasattr(op_val, 'val') else op_val
+          is_vop3sd = (op_val in vop3sd_opcodes) and not is_vopc_promotion
+          decoded = VOP3SD.from_bytes(data) if is_vop3sd else VOP3.from_bytes(data)
+          if is_vop3sd: VOP3SDOp(op_val)
+          else: VOP3Op(op_val)
+        else:
+          decoded = fmt_cls.from_bytes(data)
+          op_val = decoded._values.get('op', 0)
+          op_val = op_val.val if hasattr(op_val, 'val') else op_val
+          op_enum(op_val)
+        if decoded.to_bytes()[:len(data)] != data:
+          to_test.append((asm_text, data, None, "decode roundtrip failed"))
+          continue
+        to_test.append((asm_text, data, decoded.disasm(), None))
+      except Exception as e:
+        to_test.append((asm_text, data, None, f"exception: {e}"))
+
+    # Batch compile all disasm strings with single llvm-mc call
+    disasm_strs = [(i, t[2]) for i, t in enumerate(to_test) if t[2] is not None]
+    llvm_results = compile_asm_batch([s for _, s in disasm_strs]) if disasm_strs else []
+    llvm_map = {i: llvm_results[j] for j, (i, _) in enumerate(disasm_strs)}
+
+    # Match results back
+    passed, failed = 0, 0
+    failures: list[str] = []
+    for idx, (asm_text, data, disasm_str, error) in enumerate(to_test):
+      if error:
+        failed += 1; failures.append(f"{error} for {data.hex()}")
+      elif disasm_str is not None and idx in llvm_map:
+        llvm_bytes = llvm_map[idx]
+        if llvm_bytes is not None and llvm_bytes == data: passed += 1
+        elif llvm_bytes is not None: failed += 1; failures.append(f"'{disasm_str}': expected={data.hex()} got={llvm_bytes.hex()}")
+
+    print(f"{name.upper()} disasm: {passed} passed, {failed} failed" + (f", {skipped} skipped" if skipped else ""))
+    if failures[:10]: print("  " + "\n  ".join(failures[:10]))
+    self.assertEqual(failed, 0)
+  return test
+
+for name in LLVM_TEST_FILES:
+  setattr(TestLLVM, f'test_{name}_asm', _make_asm_test(name))
+  setattr(TestLLVM, f'test_{name}_disasm', _make_disasm_test(name))

 if __name__ == "__main__":
  unittest.main()
@@ -20,12 +20,11 @@ runner = get_runner(dev.device, si.ast)
 prg = runner._prg
 lib = bytearray(prg.lib)

-# Find s_endpgm (0xBFB00000) and replace with V_MOVRELD_B32 (op=66) which has no pcode
-# VOP1 encoding: bits[31:25]=0x7E, op=bits[16:9], so op=66 -> 66<<9 = 0x8400
+# Find s_endpgm (0xBFB00000) and replace with invalid SOPP op=127 (0xBFFF0000)
 found = False
 for i in range(0, len(lib) - 4, 4):
  if struct.unpack("<I", lib[i:i+4])[0] == 0xBFB00000:
-    lib[i:i+4] = struct.pack("<I", 0x7E008400)
+    lib[i:i+4] = struct.pack("<I", 0xBFFF0000)
    found = True
    break
 assert found, "s_endpgm not found"
@@ -47,7 +46,8 @@ dev.synchronize()
    elapsed = time.perf_counter() - st

    self.assertNotEqual(result.returncode, 0, "should have raised")
-    self.assertTrue("Error" in result.stderr, f"expected an error in stderr, got: {result.stderr[:500]}")
+    self.assertTrue("NotImplementedError" in result.stderr or "ValueError" in result.stderr,
+                    f"expected NotImplementedError or ValueError in stderr")
    # Should exit immediately, not wait for the full timeout
    self.assertLess(elapsed, 9.0, f"should exit immediately on emulator exception, took {elapsed:.1f}s")

@@ -0,0 +1,404 @@
+#!/usr/bin/env python3
+"""Tests for the RDNA3 pseudocode DSL."""
+import unittest
+from extra.assembly.amd.pcode import (Reg, TypedView, SliceProxy, MASK32, MASK64,
+                                       _f32, _i32, _f16, _i16, f32_to_f16, _isnan, _bf16, _ibf16, bf16_to_f32, f32_to_bf16,
+                                       BYTE_PERMUTE, v_sad_u8, v_msad_u8)
+from extra.assembly.amd.pdf import compile_pseudocode, _expr
+from extra.assembly.amd.test.helpers import ExecContext
+from extra.assembly.amd.autogen.rdna3.gen_pcode import _VOP3SDOp_V_DIV_SCALE_F32, _VOPCOp_V_CMP_CLASS_F32
+
+class TestReg(unittest.TestCase):
+  def test_u32_read(self):
+    r = Reg(0xDEADBEEF)
+    self.assertEqual(int(r.u32), 0xDEADBEEF)
+
+  def test_u32_write(self):
+    r = Reg(0)
+    r.u32 = 0x12345678
+    self.assertEqual(r._val, 0x12345678)
+
+  def test_f32_read(self):
+    r = Reg(0x40400000)  # 3.0f
+    self.assertAlmostEqual(float(r.f32), 3.0)
+
+  def test_f32_write(self):
+    r = Reg(0)
+    r.f32 = 3.0
+    self.assertEqual(r._val, 0x40400000)
+
+  def test_i32_signed(self):
+    r = Reg(0xFFFFFFFF)  # -1 as signed
+    self.assertEqual(int(r.i32), -1)
+
+  def test_u64(self):
+    r = Reg(0xDEADBEEFCAFEBABE)
+    self.assertEqual(int(r.u64), 0xDEADBEEFCAFEBABE)
+
+  def test_f64(self):
+    r = Reg(0x4008000000000000)  # 3.0 as f64
+    self.assertAlmostEqual(float(r.f64), 3.0)
+
+class TestTypedView(unittest.TestCase):
+  def test_bit_slice(self):
+    r = Reg(0xDEADBEEF)
+    # Slices return SliceProxy which supports .u32, .u16 etc (matching pseudocode like S1.u32[1:0].u32)
+    self.assertEqual(r.u32[7:0].u32, 0xEF)
+    self.assertEqual(r.u32[15:8].u32, 0xBE)
+    self.assertEqual(r.u32[23:16].u32, 0xAD)
+    self.assertEqual(r.u32[31:24].u32, 0xDE)
+    # Also works with int() for arithmetic
+    self.assertEqual(int(r.u32[7:0]), 0xEF)
+
+  def test_single_bit_read(self):
+    r = Reg(0b11010101)
+    self.assertEqual(r.u32[0], 1)
+    self.assertEqual(r.u32[1], 0)
+    self.assertEqual(r.u32[2], 1)
+    self.assertEqual(r.u32[3], 0)
+
+  def test_single_bit_write(self):
+    r = Reg(0)
+    r.u32[5] = 1
+    r.u32[3] = 1
+    self.assertEqual(r._val, 0b00101000)
+
+  def test_nested_bit_access(self):
+    # S0.u32[S1.u32[4:0]] - access bit at position from another register
+    s0 = Reg(0b11010101)
+    s1 = Reg(3)
+    bit_pos = s1.u32[4:0]  # SliceProxy, int value = 3
+    bit_val = s0.u32[int(bit_pos)]  # bit 3 of s0 = 0
+    self.assertEqual(int(bit_pos), 3)
+    self.assertEqual(bit_val, 0)
+
+  def test_arithmetic(self):
+    r1 = Reg(0x40400000)  # 3.0f
+    r2 = Reg(0x40800000)  # 4.0f
+    result = r1.f32 + r2.f32
+    self.assertAlmostEqual(result, 7.0)
+
+  def test_comparison(self):
+    r1 = Reg(5)
+    r2 = Reg(3)
+    self.assertTrue(r1.u32 > r2.u32)
+    self.assertFalse(r1.u32 < r2.u32)
+    self.assertTrue(r1.u32 != r2.u32)
+
+class TestSliceProxy(unittest.TestCase):
+  def test_slice_read(self):
+    r = Reg(0x56781234)
+    self.assertEqual(r[15:0].u16, 0x1234)
+    self.assertEqual(r[31:16].u16, 0x5678)
+
+  def test_slice_write(self):
+    r = Reg(0)
+    r[15:0].u16 = 0x1234
+    r[31:16].u16 = 0x5678
+    self.assertEqual(r._val, 0x56781234)
+
+  def test_slice_f16(self):
+    r = Reg(0)
+    r[15:0].f16 = 3.0
+    self.assertAlmostEqual(_f16(r._val & 0xffff), 3.0, places=2)
+
+class TestCompiler(unittest.TestCase):
+  def test_ternary(self):
+    result = _expr("a > b ? 1 : 0")
+    self.assertIn("if", result)
+    self.assertIn("else", result)
+
+  def test_type_prefix_strip(self):
+    self.assertEqual(_expr("1'0U"), "0")
+    self.assertEqual(_expr("32'1"), "1")
+    self.assertEqual(_expr("16'0xFFFF"), "0xFFFF")
+
+  def test_suffix_strip(self):
+    self.assertEqual(_expr("0ULL"), "0")
+    self.assertEqual(_expr("1LL"), "1")
+    self.assertEqual(_expr("5U"), "5")
+    self.assertEqual(_expr("3.14F"), "3.14")
+
+  def test_boolean_ops(self):
+    self.assertIn("and", _expr("a && b"))
+    self.assertIn("or", _expr("a || b"))
+    self.assertIn("!=", _expr("a <> b"))
+
+  def test_pack16(self):
+    result = _expr("{ a, b }")
+    self.assertIn("_pack", result)
+
+  def test_type_cast_strip(self):
+    self.assertEqual(_expr("64'U(x)"), "(x)")
+    self.assertEqual(_expr("32'I(y)"), "(y)")
+
+class TestExecContext(unittest.TestCase):
+  def test_float_add(self):
+    ctx = ExecContext(s0=0x40400000, s1=0x40800000)  # 3.0f, 4.0f
+    ctx.D0.f32 = ctx.S0.f32 + ctx.S1.f32
+    self.assertAlmostEqual(_f32(ctx.D0._val), 7.0)
+
+  def test_float_mul(self):
+    ctx = ExecContext(s0=0x40400000, s1=0x40800000)  # 3.0f, 4.0f
+    ctx.run("D0.f32 = S0.f32 * S1.f32")
+    self.assertAlmostEqual(_f32(ctx.D0._val), 12.0)
+
+  def test_scc_comparison(self):
+    ctx = ExecContext(s0=42, s1=42)
+    ctx.run("SCC = S0.u32 == S1.u32")
+    self.assertEqual(ctx.SCC._val, 1)
+
+  def test_scc_comparison_false(self):
+    ctx = ExecContext(s0=42, s1=43)
+    ctx.run("SCC = S0.u32 == S1.u32")
+    self.assertEqual(ctx.SCC._val, 0)
+
+  def test_ternary(self):
+    code = compile_pseudocode("D0.u32 = S0.u32 > S1.u32 ? 1'1U : 1'0U")
+    ctx = ExecContext(s0=5, s1=3)
+    ctx.run(code)
+    self.assertEqual(ctx.D0._val, 1)
+
+  def test_pack(self):
+    code = compile_pseudocode("D0 = { S1[15:0].u16, S0[15:0].u16 }")
+    ctx = ExecContext(s0=0x1234, s1=0x5678)
+    ctx.run(code)
+    self.assertEqual(ctx.D0._val, 0x56781234)
+
+  def test_tmp_with_typed_access(self):
+    code = compile_pseudocode("""tmp = S0.u32 + S1.u32
+D0.u32 = tmp.u32""")
+    ctx = ExecContext(s0=100, s1=200)
+    ctx.run(code)
+    self.assertEqual(ctx.D0._val, 300)
+
+  def test_s_add_u32_pattern(self):
+    # Real pseudocode pattern from S_ADD_U32
+    code = compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
+SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U
+D0.u32 = tmp.u32""")
+    # Test overflow case
+    ctx = ExecContext(s0=0xFFFFFFFF, s1=0x00000001)
+    ctx.run(code)
+    self.assertEqual(ctx.D0._val, 0)  # Wraps to 0
+    self.assertEqual(ctx.SCC._val, 1)  # Carry set
+
+  def test_s_add_u32_no_overflow(self):
+    code = compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
+SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U
+D0.u32 = tmp.u32""")
+    ctx = ExecContext(s0=100, s1=200)
+    ctx.run(code)
+    self.assertEqual(ctx.D0._val, 300)
+    self.assertEqual(ctx.SCC._val, 0)  # No carry
+
+  def test_vcc_lane_read(self):
+    ctx = ExecContext(vcc=0b1010, lane=1)
+    # Lane 1 is set
+    self.assertEqual(ctx.VCC.u64[1], 1)
+    self.assertEqual(ctx.VCC.u64[2], 0)
+
+  def test_vcc_lane_write(self):
+    ctx = ExecContext(vcc=0, lane=0)
+    ctx.VCC.u64[3] = 1
+    ctx.VCC.u64[1] = 1
+    self.assertEqual(ctx.VCC._val, 0b1010)
+
+  def test_for_loop(self):
+    # CTZ pattern - find first set bit
+    code = compile_pseudocode("""tmp = -1
+for i in 0 : 31 do
+  if S0.u32[i] == 1 then
+    tmp = i
+  endif
+endfor
+D0.i32 = tmp""")
+    ctx = ExecContext(s0=0b1000)  # Bit 3 is set
+    ctx.run(code)
+    self.assertEqual(ctx.D0._val & MASK32, 3)
+
+  def test_result_dict(self):
+    ctx = ExecContext(s0=5, s1=3)
+    ctx.D0.u32 = 42
+    ctx.SCC._val = 1
+    result = ctx.result()
+    self.assertEqual(result['d0'], 42)
+    self.assertEqual(result['scc'], 1)
+
+class TestPseudocodeRegressions(unittest.TestCase):
+  """Regression tests for pseudocode instruction emulation bugs."""
+
+  def test_v_div_scale_f32_vcc_always_returned(self):
+    """V_DIV_SCALE_F32 must always return VCC, even when VCC=0 (no scaling needed).
+    Bug: when VCC._val == vcc (both 0), VCC wasn't returned, so VCC bits weren't written.
+    This caused division to produce wrong results for multiple lanes."""
+    # Normal case: 1.0 / 3.0, no scaling needed, VCC should be 0
+    S0 = Reg(0x3f800000)  # 1.0
+    S1 = Reg(0x40400000)  # 3.0
+    S2 = Reg(0x3f800000)  # 1.0 (numerator)
+    D0, SCC, VCC, EXEC = Reg(0), Reg(0), Reg(0), Reg(0xffffffff)
+    result = _VOP3SDOp_V_DIV_SCALE_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    # Must always have VCC in result
+    self.assertIn('VCC', result, "V_DIV_SCALE_F32 must always return VCC")
+    self.assertEqual(result['VCC']._val & 1, 0, "VCC lane 0 should be 0 when no scaling needed")
+
+  def test_v_cmp_class_f32_detects_quiet_nan(self):
+    """V_CMP_CLASS_F32 must correctly identify quiet NaN vs signaling NaN.
+    Bug: isQuietNAN and isSignalNAN both used math.isnan which can't distinguish them."""
+    quiet_nan = 0x7fc00000   # quiet NaN: exponent=255, bit22=1
+    signal_nan = 0x7f800001  # signaling NaN: exponent=255, bit22=0
+    # Test quiet NaN detection (bit 1 in mask)
+    s1_quiet = 0b0000000010  # bit 1 = quiet NaN
+    S0, S1, S2, D0, SCC, VCC, EXEC = Reg(quiet_nan), Reg(s1_quiet), Reg(0), Reg(0), Reg(0), Reg(0), Reg(0xffffffff)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 1, "Should detect quiet NaN with quiet NaN mask")
+    # Test signaling NaN detection (bit 0 in mask)
+    s1_signal = 0b0000000001  # bit 0 = signaling NaN
+    S0, S1 = Reg(signal_nan), Reg(s1_signal)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 1, "Should detect signaling NaN with signaling NaN mask")
+    # Test that quiet NaN doesn't match signaling NaN mask
+    S0, S1 = Reg(quiet_nan), Reg(s1_signal)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 0, "Quiet NaN should not match signaling NaN mask")
+    # Test that signaling NaN doesn't match quiet NaN mask
+    S0, S1 = Reg(signal_nan), Reg(s1_quiet)
+    result = _VOPCOp_V_CMP_CLASS_F32(S0, S1, S2, D0, SCC, VCC, 0, EXEC, 0, None)
+    self.assertEqual(result['D0']._val & 1, 0, "Signaling NaN should not match quiet NaN mask")
+
+  def test_isnan_with_typed_view(self):
+    """_isnan must work with TypedView objects, not just Python floats.
+    Bug: _isnan checked isinstance(x, float) which returned False for TypedView."""
+    nan_reg = Reg(0x7fc00000)  # quiet NaN
+    normal_reg = Reg(0x3f800000)  # 1.0
+    inf_reg = Reg(0x7f800000)  # +inf
+    self.assertTrue(_isnan(nan_reg.f32), "_isnan should return True for NaN TypedView")
+    self.assertFalse(_isnan(normal_reg.f32), "_isnan should return False for normal TypedView")
+    self.assertFalse(_isnan(inf_reg.f32), "_isnan should return False for inf TypedView")
+
+class TestBF16(unittest.TestCase):
+  """Tests for BF16 (bfloat16) support."""
+
+  def test_bf16_conversion(self):
+    """Test bf16 <-> f32 conversion."""
+    # bf16 is just the top 16 bits of f32
+    # 1.0f = 0x3f800000, bf16 = 0x3f80
+    self.assertAlmostEqual(_bf16(0x3f80), 1.0, places=2)
+    self.assertEqual(_ibf16(1.0), 0x3f80)
+    # 2.0f = 0x40000000, bf16 = 0x4000
+    self.assertAlmostEqual(_bf16(0x4000), 2.0, places=2)
+    self.assertEqual(_ibf16(2.0), 0x4000)
+    # -1.0f = 0xbf800000, bf16 = 0xbf80
+    self.assertAlmostEqual(_bf16(0xbf80), -1.0, places=2)
+    self.assertEqual(_ibf16(-1.0), 0xbf80)
+
+  def test_bf16_special_values(self):
+    """Test bf16 special values (inf, nan)."""
+    import math
+    # +inf: f32 = 0x7f800000, bf16 = 0x7f80
+    self.assertTrue(math.isinf(_bf16(0x7f80)))
+    self.assertEqual(_ibf16(float('inf')), 0x7f80)
+    # -inf: f32 = 0xff800000, bf16 = 0xff80
+    self.assertTrue(math.isinf(_bf16(0xff80)))
+    self.assertEqual(_ibf16(float('-inf')), 0xff80)
+    # NaN: quiet NaN bf16 = 0x7fc0
+    self.assertTrue(math.isnan(_bf16(0x7fc0)))
+    self.assertEqual(_ibf16(float('nan')), 0x7fc0)
+
+  def test_bf16_register_property(self):
+    """Test Reg.bf16 property."""
+    r = Reg(0)
+    r.bf16 = 3.0  # 3.0f = 0x40400000, bf16 = 0x4040
+    self.assertEqual(r._val & 0xffff, 0x4040)
+    self.assertAlmostEqual(float(r.bf16), 3.0, places=1)
+
+  def test_bf16_slice_property(self):
+    """Test SliceProxy.bf16 property."""
+    r = Reg(0x40404040)  # Two bf16 3.0 values
+    self.assertAlmostEqual(r[15:0].bf16, 3.0, places=1)
+    self.assertAlmostEqual(r[31:16].bf16, 3.0, places=1)
+
+class TestBytePermute(unittest.TestCase):
+  """Tests for BYTE_PERMUTE helper function (V_PERM_B32)."""
+
+  def test_byte_select_0_to_7(self):
+    """Test selecting bytes 0-7 from 64-bit data."""
+    # data = {s0, s1} where s0 is bytes 0-3, s1 is bytes 4-7
+    # Combined: 0x0706050403020100 (byte 0 = 0x00, byte 7 = 0x07)
+    data = 0x0706050403020100
+    for i in range(8):
+      self.assertEqual(BYTE_PERMUTE(data, i), i, f"byte {i} should be {i}")
+
+  def test_sign_extend_bytes(self):
+    """Test sign extension selectors 8-11."""
+    # sel 8: sign of byte 1 (bits 15:8)
+    # sel 9: sign of byte 3 (bits 31:24)
+    # sel 10: sign of byte 5 (bits 47:40)
+    # sel 11: sign of byte 7 (bits 63:56)
+    data = 0x8000800080008000  # All relevant bytes have sign bit set
+    self.assertEqual(BYTE_PERMUTE(data, 8), 0xff)
+    self.assertEqual(BYTE_PERMUTE(data, 9), 0xff)
+    self.assertEqual(BYTE_PERMUTE(data, 10), 0xff)
+    self.assertEqual(BYTE_PERMUTE(data, 11), 0xff)
+    data = 0x7f007f007f007f00  # No sign bits set
+    self.assertEqual(BYTE_PERMUTE(data, 8), 0x00)
+    self.assertEqual(BYTE_PERMUTE(data, 9), 0x00)
+    self.assertEqual(BYTE_PERMUTE(data, 10), 0x00)
+    self.assertEqual(BYTE_PERMUTE(data, 11), 0x00)
+
+  def test_constant_zero(self):
+    """Test selector 12 returns 0x00."""
+    self.assertEqual(BYTE_PERMUTE(0xffffffffffffffff, 12), 0x00)
+
+  def test_constant_ff(self):
+    """Test selectors >= 13 return 0xFF."""
+    for sel in [13, 14, 15, 255]:
+      self.assertEqual(BYTE_PERMUTE(0, sel), 0xff, f"sel {sel} should be 0xff")
+
+class TestSADHelpers(unittest.TestCase):
+  """Tests for V_SAD_U8 and V_MSAD_U8 helper functions."""
+
+  def test_v_sad_u8_basic(self):
+    """Test v_sad_u8 with simple values."""
+    # s0 = 0x04030201, s1 = 0x04030201 -> diff = 0 for all bytes
+    result = v_sad_u8(0x04030201, 0x04030201, 0)
+    self.assertEqual(result, 0)
+    # s0 = 0x05040302, s1 = 0x04030201 -> diff = 1+1+1+1 = 4
+    result = v_sad_u8(0x05040302, 0x04030201, 0)
+    self.assertEqual(result, 4)
+
+  def test_v_sad_u8_with_accumulator(self):
+    """Test v_sad_u8 with non-zero accumulator."""
+    # s0 = 0x05040302, s1 = 0x04030201, s2 = 100 -> 4 + 100 = 104
+    result = v_sad_u8(0x05040302, 0x04030201, 100)
+    self.assertEqual(result, 104)
+
+  def test_v_sad_u8_large_diff(self):
+    """Test v_sad_u8 with maximum byte differences."""
+    # s0 = 0xffffffff, s1 = 0x00000000 -> diff = 255*4 = 1020
+    result = v_sad_u8(0xffffffff, 0x00000000, 0)
+    self.assertEqual(result, 1020)
+
+  def test_v_msad_u8_basic(self):
+    """Test v_msad_u8 masks when reference byte is 0."""
+    # s0 = 0x10101010, s1 = 0x00000000 -> all masked, result = 0
+    result = v_msad_u8(0x10101010, 0x00000000, 0)
+    self.assertEqual(result, 0)
+    # s0 = 0x10101010, s1 = 0x01010101 -> diff = |0x10-0x01|*4 = 15*4 = 60
+    result = v_msad_u8(0x10101010, 0x01010101, 0)
+    self.assertEqual(result, 60)
+
+  def test_v_msad_u8_partial_mask(self):
+    """Test v_msad_u8 with partial masking."""
+    # s0 = 0x10101010, s1 = 0x00010001 -> bytes 1 and 3 masked
+    # diff = |0x10-0x01| + |0x10-0x01| = 15 + 15 = 30
+    result = v_msad_u8(0x10101010, 0x00010001, 0)
+    self.assertEqual(result, 30)
+
+  def test_v_msad_u8_with_accumulator(self):
+    """Test v_msad_u8 with non-zero accumulator."""
+    result = v_msad_u8(0x10101010, 0x01010101, 50)
+    self.assertEqual(result, 110)  # 60 + 50
+
+if __name__ == '__main__':
+  unittest.main()
@@ -1,48 +0,0 @@
-#!/usr/bin/env python3
-"""Test PDF pseudocode extraction from generate.py."""
-import unittest
-from extra.assembly.amd.generate import extract_pdf_text, extract_pcode, parse_xml, ARCHS, FIXES
-
-EXPECTED_PAGES = {"rdna3": 655, "rdna4": 711, "cdna": 610}
-
-class TestPcodePDF(unittest.TestCase):
-  @classmethod
-  def setUpClass(cls):
-    cls.pages = {arch: extract_pdf_text(cfg["pdf"]) for arch, cfg in ARCHS.items()}
-    cls.enums = {}
-    for arch, cfg in ARCHS.items():
-      _, enums, _, _, _, _ = parse_xml(cfg["xml"])
-      for fmt, ops in FIXES.get(arch, {}).items(): enums.setdefault(fmt, {}).update(ops)
-      cls.enums[arch] = enums
-    cls.pcode = {arch: extract_pcode(cls.pages[arch], {n: op for ops in cls.enums[arch].values() for op, n in ops.items()}) for arch in ARCHS}
-
-  def test_page_counts(self):
-    for name, exp in EXPECTED_PAGES.items():
-      self.assertEqual(len(self.pages[name]), exp, f"{name} page count")
-
-  def test_pcode_extracted(self):
-    """Check we extracted a reasonable number of pcode entries."""
-    for name in ARCHS:
-      self.assertGreater(len(self.pcode[name]), 500, f"{name} pcode count too low")
-
-  def test_pcode_rdna3_tricky(self):
-    """Test specific pseudocode patterns that are tricky to extract correctly."""
-    pcode = self.pcode['rdna3']
-    # BUFFER_ATOMIC_MAX_U64: should have 4 statements (not truncated)
-    self.assertEqual(pcode[('BUFFER_ATOMIC_MAX_U64', 72)],
-      'tmp = MEM[ADDR].u64;\nsrc = DATA.u64;\nMEM[ADDR].u64 = src >= tmp ? src : tmp;\nRETURN_DATA.u64 = tmp')
-    # GLOBAL_STORE_B128: should have 4 MEM stores (not truncated)
-    self.assertEqual(pcode[('GLOBAL_STORE_B128', 29)],
-      'MEM[ADDR].b32 = VDATA[31 : 0];\nMEM[ADDR + 4U].b32 = VDATA[63 : 32];\nMEM[ADDR + 8U].b32 = VDATA[95 : 64];\nMEM[ADDR + 12U].b32 = VDATA[127 : 96]')
-    # S_CMOVK_I32: should have full if/endif block
-    self.assertEqual(pcode[('S_CMOVK_I32', 2)],
-      "if SCC then\nD0.i32 = 32'I(signext(SIMM16.i16))\nendif")
-
-  def test_pcode_no_examples(self):
-    """Pseudocode should not contain example lines with '=>'."""
-    for name in ARCHS:
-      for (op_name, opcode), code in self.pcode[name].items():
-        self.assertNotIn('=>', code, f"{name} {op_name} contains example line with '=>'")
-
-if __name__ == "__main__":
-  unittest.main()
@@ -0,0 +1,150 @@
+#!/usr/bin/env python3
+"""Test that PDF parser correctly extracts format fields."""
+import unittest, os
+from extra.assembly.amd.autogen.rdna3.ins import SOP1, SOP2, SOPK, SOPP, VOP1, VOP2, VOP3SD, VOPC, FLAT, VOPD, SOP1Op, SOP2Op, VOP1Op, VOP3Op
+
+# expected formats with key fields and whether they have ENCODING
+EXPECTED_FORMATS = {
+  'DPP16': (['SRC0', 'DPP_CTRL', 'BANK_MASK', 'ROW_MASK'], False),
+  'DPP8': (['SRC0', 'LANE_SEL0', 'LANE_SEL7'], False),
+  'DS': (['OP', 'ADDR', 'DATA0', 'DATA1', 'VDST'], True),
+  'EXP': (['EN', 'TARGET', 'VSRC0', 'VSRC1', 'VSRC2', 'VSRC3'], True),
+  'FLAT': (['OP', 'ADDR', 'DATA', 'SADDR', 'VDST', 'OFFSET'], True),
+  'LDSDIR': (['VDST', 'OP'], True),
+  'MIMG': (['OP', 'VADDR', 'VDATA', 'SRSRC', 'DMASK'], True),
+  'MTBUF': (['OP', 'VADDR', 'VDATA', 'SRSRC', 'FORMAT', 'SOFFSET'], True),
+  'MUBUF': (['OP', 'VADDR', 'VDATA', 'SRSRC', 'SOFFSET'], True),
+  'SMEM': (['OP', 'SBASE', 'SDATA', 'OFFSET', 'SOFFSET'], True),
+  'SOP1': (['OP', 'SDST', 'SSRC0'], True),
+  'SOP2': (['OP', 'SDST', 'SSRC0', 'SSRC1'], True),
+  'SOPC': (['OP', 'SSRC0', 'SSRC1'], True),
+  'SOPK': (['OP', 'SDST', 'SIMM16'], True),
+  'SOPP': (['OP', 'SIMM16'], True),
+  'VINTERP': (['OP', 'VDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOP1': (['OP', 'VDST', 'SRC0'], True),
+  'VOP2': (['OP', 'VDST', 'SRC0', 'VSRC1'], True),
+  'VOP3': (['OP', 'VDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOP3P': (['OP', 'VDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOP3SD': (['OP', 'VDST', 'SDST', 'SRC0', 'SRC1', 'SRC2'], True),
+  'VOPC': (['OP', 'SRC0', 'VSRC1'], True),
+  'VOPD': (['OPX', 'OPY', 'SRCX0', 'SRCY0', 'VDSTX', 'VDSTY'], True),
+}
+
+# Skip PDF parsing tests by default - only run with TEST_PDF_PARSER=1
+# These are slow (~5s) and only needed when regenerating autogen/
+@unittest.skipUnless(os.environ.get("TEST_PDF_PARSER"), "set TEST_PDF_PARSER=1 to run PDF parser tests")
+class TestPDFParserGenerate(unittest.TestCase):
+  """Test the PDF parser by running generate() and checking results."""
+
+  def test_pdf_parser(self):
+    """Single test that validates all PDF parser outputs."""
+    from extra.assembly.amd.dsl import generate
+    result = generate()
+
+    # test_all_formats_present
+    for fmt_name in EXPECTED_FORMATS:
+      self.assertIn(fmt_name, result["formats"], f"missing format {fmt_name}")
+
+    # test_format_count
+    self.assertEqual(len(result["formats"]), 23)
+
+    # test_no_duplicate_fields
+    for fmt_name, fields in result["formats"].items():
+      field_names = [f[0] for f in fields]
+      self.assertEqual(len(field_names), len(set(field_names)), f"{fmt_name} has duplicate fields: {field_names}")
+
+    # test_expected_fields
+    for fmt_name, (expected_fields, has_encoding) in EXPECTED_FORMATS.items():
+      fields = {f[0] for f in result["formats"].get(fmt_name, [])}
+      for field in expected_fields:
+        self.assertIn(field, fields, f"{fmt_name} missing {field}")
+      if has_encoding:
+        self.assertIn("ENCODING", fields, f"{fmt_name} should have ENCODING")
+      else:
+        self.assertNotIn("ENCODING", fields, f"{fmt_name} should not have ENCODING")
+
+    # test_vopd_no_dpp16_fields
+    vopd_fields = {f[0] for f in result["formats"].get("VOPD", [])}
+    for field in ['DPP_CTRL', 'BANK_MASK', 'ROW_MASK']:
+      self.assertNotIn(field, vopd_fields, f"VOPD should not have {field}")
+
+    # test_dpp16_no_vinterp_fields
+    dpp16_fields = {f[0] for f in result["formats"].get("DPP16", [])}
+    for field in ['VDST', 'WAITEXP']:
+      self.assertNotIn(field, dpp16_fields, f"DPP16 should not have {field}")
+
+    # test_sopp_no_smem_fields
+    sopp_fields = {f[0] for f in result["formats"].get("SOPP", [])}
+    for field in ['SBASE', 'SDATA']:
+      self.assertNotIn(field, sopp_fields, f"SOPP should not have {field}")
+
+class TestPDFParser(unittest.TestCase):
+  """Verify format classes have correct fields from PDF parsing."""
+
+  def test_sop2_fields(self):
+    """SOP2 should have op, sdst, ssrc0, ssrc1."""
+    for field in ['op', 'sdst', 'ssrc0', 'ssrc1']:
+      self.assertIn(field, SOP2._fields)
+    self.assertEqual(SOP2._fields['op'].hi, 29)
+    self.assertEqual(SOP2._fields['op'].lo, 23)
+
+  def test_sop1_fields(self):
+    """SOP1 should have op, sdst, ssrc0 with correct bit positions."""
+    for field in ['op', 'sdst', 'ssrc0']:
+      self.assertIn(field, SOP1._fields)
+    self.assertNotIn('simm16', SOP1._fields)
+    self.assertEqual(SOP1._fields['ssrc0'].hi, 7)
+    self.assertEqual(SOP1._fields['ssrc0'].lo, 0)
+    assert SOP1._encoding is not None
+    self.assertEqual(SOP1._encoding[0].hi, 31)
+    self.assertEqual(SOP1._encoding[1], 0b101111101)
+
+  def test_vop3sd_fields(self):
+    """VOP3SD should have all fields including src0/src1/src2 from page continuation."""
+    for field in ['op', 'vdst', 'sdst', 'src0', 'src1', 'src2']:
+      self.assertIn(field, VOP3SD._fields)
+    self.assertEqual(VOP3SD._fields['src0'].hi, 40)
+    self.assertEqual(VOP3SD._fields['src0'].lo, 32)
+    self.assertEqual(VOP3SD._size(), 8)
+
+  def test_flat_has_vdst(self):
+    """FLAT should have vdst field."""
+    self.assertIn('vdst', FLAT._fields)
+    self.assertEqual(FLAT._fields['vdst'].hi, 63)
+    self.assertEqual(FLAT._fields['vdst'].lo, 56)
+
+  def test_encoding_bits(self):
+    """Verify encoding bits are correct for major formats."""
+    tests = [
+      (SOP2, 31, 30, 0b10),
+      (SOPK, 31, 28, 0b1011),
+      (SOPP, 31, 23, 0b101111111),
+      (VOP1, 31, 25, 0b0111111),
+      (VOP2, 31, 31, 0b0),
+      (VOPC, 31, 25, 0b0111110),
+      (FLAT, 31, 26, 0b110111),
+    ]
+    for cls, hi, lo, val in tests:
+      assert cls._encoding is not None
+      self.assertEqual(cls._encoding[0].hi, hi, f"{cls.__name__} encoding hi")
+      self.assertEqual(cls._encoding[0].lo, lo, f"{cls.__name__} encoding lo")
+      self.assertEqual(cls._encoding[1], val, f"{cls.__name__} encoding val")
+
+  def test_opcode_enums_exist(self):
+    """Verify opcode enums are generated with expected counts."""
+    self.assertGreater(len(SOP1Op), 50)
+    self.assertGreater(len(SOP2Op), 50)
+    self.assertGreater(len(VOP1Op), 50)
+    self.assertGreater(len(VOP3Op), 200)
+
+  def test_vopd_no_duplicate_fields(self):
+    """VOPD should not have duplicate fields and should not include DPP16 fields."""
+    field_names = list(VOPD._fields.keys())
+    self.assertEqual(len(field_names), len(set(field_names)))
+    for field in ['srcx0', 'srcy0', 'opx', 'opy']:
+      self.assertIn(field, VOPD._fields)
+    for field in ['dpp_ctrl', 'bank_mask', 'row_mask']:
+      self.assertNotIn(field, VOPD._fields)
+
+if __name__ == "__main__":
+  unittest.main()
@@ -37,10 +37,10 @@ class TestRDNA3Asm(unittest.TestCase):
      v_add_co_u32(v[2], VCC_LO, s[6], v[2]),
      v_add_co_ci_u32_e32(v[3], s[7], v[3]),
      v_add_co_u32(v[0], VCC_LO, s[4], v[0]),
-      global_load_b32(vdst=v[2], addr=v[2:3], saddr=OFF),
+      global_load_b32(vdst=v[2], addr=v[2], saddr=OFF),
      v_add_co_ci_u32_e32(v[1], s[5], v[1]),
      s_waitcnt(0x03f7),  # vmcnt(0)
-      global_store_b32(addr=v[0:1], data=v[2], saddr=OFF),
+      global_store_b32(addr=v[0], data=v[2], saddr=OFF),
      s_endpgm(),
    ]

@@ -1,98 +0,0 @@
-import unittest, ctypes
-from extra.assembly.amd.autogen.rdna4 import ins as ir4
-from extra.assembly.amd.dsl import v, s
-from extra.assembly.amd.emu import WaveState, decode_program
-from tinygrad.device import Buffer, BufferSpec
-from tinygrad.dtype import dtypes
-
-class TestRDNA4Emu(unittest.TestCase):
-  def _run(self, insts: list, sgprs: dict[int, int] = None, vgprs: dict[tuple[int, int], int] = None) -> WaveState:
-    """Run instructions and return final WaveState."""
-    # Add S_ENDPGM if not present
-    if not any(isinstance(i, ir4.SOPP) and i.op == ir4.SOPPOp.S_ENDPGM for i in insts):
-      insts = list(insts) + [ir4.SOPP(ir4.SOPPOp.S_ENDPGM, simm=0)]
-
-    # Assemble and decode
-    code = b''.join(i.to_bytes() for i in insts)
-    code_buf = (ctypes.c_uint8 * len(code)).from_buffer_copy(code)
-    code_addr = ctypes.addressof(code_buf)
-    program_raw = decode_program(code, "rdna4")
-    program = {code_addr + offset: val for offset, val in program_raw.items()}
-
-    # Setup wave state
-    st = WaveState(n_lanes=1)
-    st.pc = code_addr
-    if sgprs:
-      for idx, val in sgprs.items(): st._write_sgpr(idx, val)
-    if vgprs:
-      for (reg, lane), val in vgprs.items(): st._write_vgpr(reg, lane, val)
-
-    # Setup vmem buffer with external_ptr=0 (maps to address 0, allows any pointer access)
-    vmem_buf = Buffer('CPU', 1 << 40, dtypes.uint32, options=BufferSpec(external_ptr=0)).ensure_allocated()
-
-    # Execute
-    c_bufs = [ctypes.c_uint64(st.sgpr_buf._buf.va_addr), ctypes.c_uint64(st.vgpr_buf._buf.va_addr),
-              ctypes.c_uint64(vmem_buf._buf.va_addr), ctypes.c_uint64(0), ctypes.c_uint64(0)]
-    for _ in range(100):
-      if (pc := st.pc) == 0xFFFFFFFFFFFFFFFF or pc not in program: break
-      _, fxn, globals_list, _ = program[pc]
-      fxn(*[c_bufs[g] for g in globals_list])
-    return st
-
-  def test_vopd_dual_mov(self):
-    """Test VOPD with two V_DUAL_MOV_B32 operations: v[1]=s[1], v[2]=s[2]."""
-    insts = [ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
-                      vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0])]
-    st = self._run(insts, sgprs={1: 0x40e00000, 2: 0x41100000})  # 7.0f, 9.0f
-    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
-    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
-
-  def test_vopd_dual_mov_after_other_vopd(self):
-    """Test VOPD reuse: first VOPD(v[3]=0, v[0]=?), then VOPD(v[1]=s[1], v[2]=s[2])."""
-    # This matches the BEAM kernel sequence that fails
-    insts = [
-      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
-               vdstx=v[3], vdsty=v[0], srcx0=0, srcy0=s[0], vsrcx1=v[0], vsrcy1=v[0]),  # v[3]=0, v[0]=s[0]
-      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
-               vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0]),  # v[1]=s[1], v[2]=s[2]
-    ]
-    st = self._run(insts, sgprs={0: 0x40a00000, 1: 0x40e00000, 2: 0x41100000})  # 5.0f, 7.0f, 9.0f
-    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
-    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
-
-  def test_vopd_with_s_add_f32_sequence(self):
-    """Test full BEAM kernel sequence: s_add_f32 then VOPD."""
-    # This is the exact sequence from the failing BEAM kernel
-    insts = [
-      ir4.SOP2(ir4.SOP2Op.S_ADD_F32, sdst=s[0], ssrc0=s[0], ssrc1=s[8]),   # s[0] = s[0] + s[8]
-      ir4.SOP2(ir4.SOP2Op.S_ADD_F32, sdst=s[1], ssrc0=s[1], ssrc1=s[9]),   # s[1] = s[1] + s[9]
-      ir4.SOP2(ir4.SOP2Op.S_ADD_F32, sdst=s[2], ssrc0=s[2], ssrc1=s[10]),  # s[2] = s[2] + s[10]
-      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
-               vdstx=v[3], vdsty=v[0], srcx0=0, srcy0=s[0], vsrcx1=v[0], vsrcy1=v[0]),
-      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
-               vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0]),
-    ]
-    # Input: s[0:2] = [1,2,3], s[8:10] = [4,5,6]
-    # After s_add_f32: s[0:2] = [5,7,9]
-    st = self._run(insts, sgprs={0: 0x3f800000, 1: 0x40000000, 2: 0x40400000,  # 1.0, 2.0, 3.0
-                                  8: 0x40800000, 9: 0x40a00000, 10: 0x40c00000})  # 4.0, 5.0, 6.0
-    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
-    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
-
-  def test_s_mov_b32_then_vopd(self):
-    """Test s_mov_b32 followed by VOPD - simulates BEAM kernel sequence."""
-    # Use s_mov_b32 with SGPR source (copy from pre-initialized SGPRs)
-    # s[10:12] will have values set by test harness, copy to s[0:2], then VOPD to VGPRs
-    insts = [
-      ir4.SOP1(ir4.SOP1Op.S_MOV_B32, sdst=s[0], ssrc0=s[10]),  # s[0] = s[10]
-      ir4.SOP1(ir4.SOP1Op.S_MOV_B32, sdst=s[1], ssrc0=s[11]),  # s[1] = s[11]
-      ir4.SOP1(ir4.SOP1Op.S_MOV_B32, sdst=s[2], ssrc0=s[12]),  # s[2] = s[12]
-      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
-               vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0]),
-    ]
-    st = self._run(insts, sgprs={10: 0x40a00000, 11: 0x40e00000, 12: 0x41100000})  # 5.0, 7.0, 9.0
-    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
-    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,9 +1,11 @@
 #!/usr/bin/env python3
 """Roundtrip tests: generate tinygrad kernels, decode instructions, re-encode, verify match."""
 import unittest, io, sys, re, subprocess, os
+from extra.assembly.amd.autogen.rdna3.ins import *
 from extra.assembly.amd.dsl import Inst
-from extra.assembly.amd import decode_inst, detect_format
-from extra.assembly.amd.test.helpers import get_llvm_mc, get_llvm_objdump, get_target, get_mattr
+from extra.assembly.amd.asm import asm
+from extra.assembly.amd.asm import detect_format
+from extra.assembly.amd.test.helpers import get_llvm_mc, get_llvm_objdump

 def disassemble_lib(lib: bytes, compiler) -> list[tuple[str, bytes]]:
  """Disassemble ELF binary and return list of (instruction_text, machine_code_bytes)."""
@@ -28,39 +30,61 @@ def disassemble_lib(lib: bytes, compiler) -> list[tuple[str, bytes]]:
      continue
  return results

-def compile_asm(instr: str, arch: str = 'rdna3') -> bytes:
-  """Compile a single instruction using LLVM."""
-  return compile_asm_batch([instr], arch)[0]
+def compile_asm(instr: str, compiler=None) -> bytes:
+  """Compile a single instruction with llvm-mc and return the machine code bytes."""
+  llvm_mc = get_llvm_mc()
+  result = subprocess.run(
+    [llvm_mc, '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+    input=f".text\n{instr}\n", capture_output=True, text=True)
+  if result.returncode != 0: raise RuntimeError(f"llvm-mc failed for '{instr}': {result.stderr.strip()}")
+  # Parse encoding: [0x01,0x39,0x0a,0x7e]
+  for line in result.stdout.split('\n'):
+    if 'encoding:' in line:
+      enc = line.split('encoding:')[1].strip()
+      if enc.startswith('[') and enc.endswith(']'):
+        hex_vals = enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')
+        return bytes.fromhex(hex_vals)
+  raise RuntimeError(f"no encoding found in llvm-mc output for: {instr}")

-def compile_asm_batch(instrs: list[str], arch: str = 'rdna3') -> list[bytes]:
+def compile_asm_batch(instrs: list[str]) -> list[bytes]:
  """Compile multiple instructions with a single llvm-mc call."""
  if not instrs: return []
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={get_target(arch)}', f'-mattr={get_mattr(arch)}', '-show-encoding'],
-                          input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True)
+  llvm_mc = get_llvm_mc()
+  src = ".text\n" + "\n".join(instrs) + "\n"
+  result = subprocess.run(
+    [llvm_mc, '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+    input=src, capture_output=True, text=True)
  if result.returncode != 0: raise RuntimeError(f"llvm-mc batch failed: {result.stderr.strip()}")
+  # Parse all encodings in order
  encodings = []
  for line in result.stdout.split('\n'):
    if 'encoding:' in line:
      enc = line.split('encoding:')[1].strip()
      if enc.startswith('[') and enc.endswith(']'):
-        encodings.append(bytes.fromhex(enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')))
+        hex_vals = enc[1:-1].replace('0x', '').replace(',', '').replace(' ', '')
+        encodings.append(bytes.fromhex(hex_vals))
  if len(encodings) != len(instrs): raise RuntimeError(f"expected {len(instrs)} encodings, got {len(encodings)}")
  return encodings

-def compile_and_disasm_batch(instrs: list[str], arch: str = 'rdna3') -> list[str]:
+def compile_and_disasm_batch(instrs: list[str], compiler) -> list[str]:
  """Compile instructions with LLVM and get LLVM's disassembly."""
-  import tempfile
+  import tempfile, os
  if not instrs: return []
-  mcpu, mattr = get_target(arch), get_mattr(arch)
-  src = ".text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n" + "\n".join(f"  {instr}" for instr in instrs) + "\n"
+  # Build assembly source with all instructions
+  src = ".text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n"
+  src += "\n".join(f"  {instr}" for instr in instrs) + "\n"
+  # Use llvm-mc to assemble to object file
  with tempfile.NamedTemporaryFile(suffix='.o', delete=False) as f:
    obj_path = f.name
  try:
-    result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', f'-mattr={mattr}', '-filetype=obj', '-o', obj_path],
-                            input=src, capture_output=True, text=True)
+    result = subprocess.run(
+      [get_llvm_mc(), '-triple=amdgcn', '-mcpu=gfx1100', '-mattr=+real-true16,+wavefrontsize32', '-filetype=obj', '-o', obj_path],
+      input=src, capture_output=True, text=True)
    if result.returncode != 0: raise RuntimeError(f"llvm-mc failed: {result.stderr.strip()}")
-    result = subprocess.run([get_llvm_objdump(), '-d', f'--mcpu={mcpu}', obj_path], capture_output=True, text=True)
+    # Disassemble with llvm-objdump
+    result = subprocess.run([get_llvm_objdump(), '-d', '--mcpu=gfx1100', obj_path], capture_output=True, text=True)
    if result.returncode != 0: raise RuntimeError(f"llvm-objdump failed: {result.stderr.strip()}")
+    # Parse disassembly output
    results: list[str] = []
    for line in result.stdout.splitlines():
      if '//' not in line: continue
@@ -72,33 +96,26 @@ def compile_and_disasm_batch(instrs: list[str], arch: str = 'rdna3') -> list[str

 class TestTinygradKernelRoundtrip(unittest.TestCase):
  """Test roundtrip on real tinygrad-generated kernels using get_kernels_from_tinygrad pattern."""
-  arch = 'rdna3'

  def _test_kernel_roundtrip(self, op_fn):
    """Generate kernel from op_fn, test:
    1. decode -> reencode matches original bytes
-    2. disasm() -> LLVM asm -> bytes matches original (validates disasm correctness)
-    3. our disasm() matches LLVM's disassembly string (informational)
+    2. asm(disasm()) matches LLVM output
+    3. our disasm() matches LLVM's disassembly string exactly
    """
-    arch = self.arch
-
    from extra.assembly.amd.test.test_compare_emulators import get_kernels_from_tinygrad
-    from tinygrad.runtime.support.elf import elf_loader
-    from tinygrad.runtime.support.compiler_amd import HIPCompiler, AMDLLVMCompiler
-    from tinygrad.helpers import AMD_LLVM
+    from tinygrad.runtime.support.compiler_amd import HIPCompiler

    kernels, _, _ = get_kernels_from_tinygrad(op_fn)
-    # rendered source can be C or llvmir
-    compiler = (AMDLLVMCompiler if AMD_LLVM else HIPCompiler)(get_target(arch))
+    compiler = HIPCompiler('gfx1100')

    # First pass: decode all instructions and collect info
    decoded_instrs: list[tuple] = []  # list of (ki, offset, orig_bytes, decoded, our_disasm, decode_ok, decode_err)
    for ki, kernel in enumerate(kernels):
      offset = 0
-      code = next((s.content for s in elf_loader(compiler.compile(kernel.src))[1] if s.name == ".text"))
-      while offset < len(code):
-        remaining = code[offset:]
-        fmt = detect_format(remaining, arch)
+      while offset < len(kernel.code):
+        remaining = kernel.code[offset:]
+        fmt = detect_format(remaining)
        if fmt is None:
          decoded_instrs.append((ki, offset, None, None, None, False, "no format"))
          offset += 4
@@ -124,22 +141,22 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
        offset += size

    # Collect disasm strings for batched LLVM calls - skip unknown opcodes (op_X) that LLVM can't compile
-    asm_test_instrs: list[tuple[int, str, bytes]] = []  # (idx, our_disasm, orig_bytes) for asm test
+    asm_test_instrs: list[tuple[int, str]] = []  # (idx, our_disasm) for asm test
    disasm_test_instrs: list[tuple[int, str]] = []  # (idx, our_disasm) for disasm comparison test

    for idx, (ki, offset, orig_bytes, decoded, our_disasm, decode_ok, decode_err) in enumerate(decoded_instrs):
      if our_disasm is None: continue
-      # Skip unknown opcodes and malformed instructions
+      # Skip unknown opcodes and malformed instructions for both tests
      if our_disasm.startswith('op_') or re.search(r', \d+, \d+, \d+,', our_disasm): continue
-      asm_test_instrs.append((idx, our_disasm, orig_bytes))
+      asm_test_instrs.append((idx, our_disasm))
      disasm_test_instrs.append((idx, our_disasm))

-    # Batch compile for asm test (our disasm -> LLVM asm -> bytes)
-    asm_llvm_results = compile_asm_batch([d for _, d, _ in asm_test_instrs], arch)
-    asm_llvm_map = {idx: (result, orig) for (idx, _, orig), result in zip(asm_test_instrs, asm_llvm_results)}
+    # Batch compile for asm test
+    asm_llvm_results = compile_asm_batch([d for _, d in asm_test_instrs])
+    asm_llvm_map = {idx: result for (idx, _), result in zip(asm_test_instrs, asm_llvm_results)}

    # Batch compile+disasm for disasm comparison test
-    disasm_llvm_results = compile_and_disasm_batch([d for _, d in disasm_test_instrs], arch)
+    disasm_llvm_results = compile_and_disasm_batch([d for _, d in disasm_test_instrs], compiler)
    disasm_llvm_map = {idx: result for (idx, _), result in zip(disasm_test_instrs, disasm_llvm_results)}

    # Now evaluate results
@@ -160,16 +177,20 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
        decode_failed += 1
        decode_failures.append(f"K{ki}@{offset}: {our_disasm}: {decode_err}")

-      # Asm test: our disasm -> LLVM asm -> compare bytes with original
+      # Asm test
      if our_disasm is None:
        asm_skipped += 1
      elif idx in asm_llvm_map:
-        llvm_bytes, orig = asm_llvm_map[idx]
-        if llvm_bytes == orig[:len(llvm_bytes)]:
-          asm_passed += 1
-        else:
-          asm_failed += 1
-          asm_failures.append(f"K{ki}@{offset}: '{our_disasm}': llvm={llvm_bytes.hex()} orig={orig[:len(llvm_bytes)].hex()}")
+        llvm_bytes = asm_llvm_map[idx]
+        try:
+          our_bytes = asm(our_disasm).to_bytes()
+          if our_bytes[:len(llvm_bytes)] == llvm_bytes:
+            asm_passed += 1
+          else:
+            asm_failed += 1
+            asm_failures.append(f"K{ki}@{offset}: '{our_disasm}': ours={our_bytes[:len(llvm_bytes)].hex()} llvm={llvm_bytes.hex()}")
+        except Exception:
+          asm_skipped += 1
      else:
        asm_skipped += 1

@@ -186,9 +207,9 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
      else:
        disasm_skipped += 1

-    print(f"[{arch}] decode roundtrip: {decode_passed} passed, {decode_failed} failed, {decode_skipped} skipped")
-    print(f"[{arch}] asm via llvm: {asm_passed} passed, {asm_failed} failed, {asm_skipped} skipped")
-    print(f"[{arch}] disasm vs llvm: {disasm_passed} passed, {disasm_failed} failed, {disasm_skipped} skipped")
+    print(f"decode roundtrip: {decode_passed} passed, {decode_failed} failed, {decode_skipped} skipped")
+    print(f"asm vs llvm: {asm_passed} passed, {asm_failed} failed, {asm_skipped} skipped")
+    print(f"disasm vs llvm: {disasm_passed} passed, {disasm_failed} failed, {disasm_skipped} skipped")
    self.assertEqual(decode_failed, 0, f"Decode failures:\n" + "\n".join(decode_failures[:20]))
    self.assertEqual(asm_failed, 0, f"Asm failures:\n" + "\n".join(asm_failures[:20]))
    # Note: disasm string comparison is informational only - formatting differences between LLVM versions are expected
@@ -238,10 +259,5 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
  # Fused ops
  def test_fma(self): self._test_kernel_roundtrip(lambda T: (T([1.0, 2.0]) * T([3.0, 4.0]) + T([5.0, 6.0])))

-class TestTinygradKernelRoundtripRDNA4(TestTinygradKernelRoundtrip): arch = 'rdna4'
-
-@unittest.skip("CDNA decode roundtrip not yet supported")
-class TestTinygradKernelRoundtripCDNA(TestTinygradKernelRoundtrip): arch = 'cdna'
-
 if __name__ == "__main__":
  unittest.main()
@@ -1,224 +0,0 @@
-#!/usr/bin/env python3
-"""Tests for SQTT packet decoding using real captured examples."""
-import pickle, unittest, ctypes, threading
-from pathlib import Path
-from tinygrad.helpers import DEBUG
-from tinygrad.runtime.autogen import rocprof
-from tinygrad.runtime.support.elf import elf_loader
-from extra.assembly.amd import decode_inst
-from extra.assembly.amd.autogen.rdna3.ins import SOPP
-from extra.assembly.amd.autogen.rdna3.enum import SOPPOp
-from extra.assembly.amd.sqtt import (decode, LAYOUT_HEADER, WAVESTART, WAVESTART_L4, WAVEEND, INST, INST_L4, VALUINST, IMMEDIATE, IMMEDIATE_MASK,
-                                     ALUEXEC, VMEMEXEC, PACKET_TYPES_L3, PACKET_TYPES_L4, InstOp, InstOpL4, print_packets)
-from extra.assembly.amd.test.helpers import TARGET_TO_ARCH
-
-EXAMPLES_DIR = Path(__file__).parent.parent.parent.parent / "sqtt/examples"
-# INST ops for non-traced SIMDs (excluded from instruction count)
-OTHER_SIMD_OPS = {InstOp.OTHER_LDS_LOAD, InstOp.OTHER_LDS_STORE, InstOp.OTHER_LDS_STORE_64, InstOp.OTHER_LDS_STORE_128,
-                  InstOp.OTHER_FLAT_LOAD, InstOp.OTHER_FLAT_STORE, InstOp.OTHER_FLAT_STORE_64, InstOp.OTHER_FLAT_STORE_96,
-                  InstOp.OTHER_FLAT_STORE_128, InstOp.OTHER_GLOBAL_LOAD, InstOp.OTHER_GLOBAL_LOAD_VADDR,
-                  InstOp.OTHER_GLOBAL_STORE_64, InstOp.OTHER_GLOBAL_STORE_96, InstOp.OTHER_GLOBAL_STORE_128,
-                  InstOp.OTHER_GLOBAL_STORE_VADDR_128}
-OTHER_SIMD_OPS_L4 = {InstOpL4.OTHER_VMEM, InstOpL4.UNK_60}
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# ROCPROF DECODER
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int, target: str):
-  """Run rocprof decoder on SQTT blobs, returning raw occupancy and instruction records."""
-  image, sections, _ = elf_loader(lib)
-  text = next((sh for sh in sections if sh.name == ".text"), None)
-  assert text is not None, "no .text section found"
-  text_off, text_size = text.header.sh_addr, text.header.sh_size
-
-  blob_iter, current_blob = iter(blobs), [None]
-  occupancy_records: list[tuple[int, int, int, int, bool]] = []  # (wave_id, simd, cu, time, is_start)
-  wave_insts: list[list[tuple[int, int]]] = []  # per-wave list of (time, stall)
-
-  @rocprof.rocprof_trace_decoder_se_data_callback_t
-  def copy_cb(buf, buf_size, _):
-    blob = next(blob_iter, None)
-    if blob is None: return 0
-    current_blob[0] = (ctypes.c_ubyte * len(blob)).from_buffer_copy(blob)
-    buf[0] = ctypes.cast(current_blob[0], ctypes.POINTER(ctypes.c_ubyte))
-    buf_size[0] = len(current_blob[0])
-    return len(current_blob[0])
-
-  @rocprof.rocprof_trace_decoder_trace_callback_t
-  def trace_cb(record_type, events_ptr, n, _):
-    if record_type == rocprof.ROCPROFILER_THREAD_TRACE_DECODER_RECORD_OCCUPANCY:
-      for ev in (rocprof.rocprofiler_thread_trace_decoder_occupancy_t * n).from_address(events_ptr):
-        occupancy_records.append((ev.wave_id, ev.simd, ev.cu, ev.time, ev.start))
-    elif record_type == rocprof.ROCPROFILER_THREAD_TRACE_DECODER_RECORD_WAVE:
-      for ev in (rocprof.rocprofiler_thread_trace_decoder_wave_t * n).from_address(events_ptr):
-        if ev.instructions_size > 0:
-          sz = ev.instructions_size * ctypes.sizeof(rocprof.rocprofiler_thread_trace_decoder_inst_t)
-          insts_blob = bytearray(sz)
-          ctypes.memmove((ctypes.c_char * sz).from_buffer(insts_blob), ev.instructions_array, sz)
-          insts = list((rocprof.rocprofiler_thread_trace_decoder_inst_t * ev.instructions_size).from_buffer(insts_blob))
-          wave_insts.append([(inst.time, inst.stall) for inst in insts])
-    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-
-  arch = TARGET_TO_ARCH[target]
-  @rocprof.rocprof_trace_decoder_isa_callback_t
-  def isa_cb(instr_ptr, mem_size_ptr, size_ptr, pc, _):
-    offset = pc.address - base
-    if offset < text_off or offset >= text_off + text_size:
-      mem_size_ptr[0] = 0
-      return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-    try:
-      inst = decode_inst(image[offset:], arch=arch)
-      mem_size_ptr[0] = inst._size()
-    # this could be an error in our decode_inst
-    except (ValueError, AssertionError):
-      mem_size_ptr[0] = 0
-      return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-    if isinstance(inst, SOPP) and inst.op == SOPPOp.S_ENDPGM: mem_size_ptr[0] = 0
-    # rocprof parses instruction string to determine type; v_nop works for all
-    if (max_sz := size_ptr[0]) == 0: return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_ERROR_OUT_OF_RESOURCES
-    ctypes.memmove(instr_ptr, b"v_nop", min(5, max_sz - 1))
-    size_ptr[0] = min(5, max_sz - 1)
-    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
-
-  exc = None
-  def worker():
-    nonlocal exc
-    try: rocprof.rocprof_trace_decoder_parse_data(copy_cb, trace_cb, isa_cb, None)
-    except Exception as e: exc = e
-  (t:=threading.Thread(target=worker, daemon=True)).start()
-  t.join(timeout=1)
-  if exc is not None: raise exc
-  if t.is_alive(): raise RuntimeError("rocprof decoder timeout")
-  return occupancy_records, wave_insts
-
-class SQTTExamplesTestBase(unittest.TestCase):
-  target: str
-
-  @classmethod
-  def setUpClass(cls):
-    if cls is SQTTExamplesTestBase: raise unittest.SkipTest("base class")
-    cls.examples = {}
-    for pkl_path in sorted((EXAMPLES_DIR/cls.target).glob("*.pkl")):
-      with open(pkl_path, "rb") as f:
-        data = pickle.load(f)
-      sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
-      prg = next((e for e in data if type(e).__name__ == "ProfileProgramEvent"), None)
-      if sqtt_events and prg:
-        cls.examples[pkl_path.stem] = (sqtt_events, prg.lib, prg.base)
-
-  def test_examples_loaded(self):
-    self.assertGreater(len(self.examples), 0, "no example files found")
-
-  def test_decode_all_examples(self):
-    for name, (events, *_) in self.examples.items():
-      for i, event in enumerate(events):
-        with self.subTest(example=name, event=i):
-          packets = list(decode(event.blob))
-          if DEBUG >= 2: print(f"\n=== {name} event {i} ==="); print_packets(packets)
-          self.assertGreater(len(packets), 0, f"no packets decoded from {name} event {i}")
-          self.assertIsInstance(packets[0], LAYOUT_HEADER, f"first packet should be LAYOUT_HEADER in {name}")
-
-  def test_packet_types_valid(self):
-    all_classes = set(PACKET_TYPES_L3.values()) | set(PACKET_TYPES_L4.values())
-    for name, (events, *_) in self.examples.items():
-      for i, event in enumerate(events):
-        with self.subTest(example=name, event=i):
-          for pkt in decode(event.blob):
-            # Use isinstance to handle layout-specific subclasses (e.g., WAVESTART_L4)
-            self.assertTrue(any(isinstance(pkt, cls) for cls in all_classes), f"unknown packet type {type(pkt)} in {name}")
-
-  def test_wave_lifecycle(self):
-    for name, (events, *_) in self.examples.items():
-      if "empty" in name: continue
-      with self.subTest(example=name):
-        all_packets = [p for e in events for p in decode(e.blob)]
-        self.assertGreater(len([p for p in all_packets if isinstance(p, (WAVESTART, WAVESTART_L4))]), 0, f"no WAVESTART in {name}")
-        self.assertGreater(len([p for p in all_packets if isinstance(p, WAVEEND)]), 0, f"no WAVEEND in {name}")
-
-  def test_time_monotonic(self):
-    for name, (events, *_) in self.examples.items():
-      for i, event in enumerate(events):
-        with self.subTest(example=name, event=i):
-          times = [p._time for p in decode(event.blob)]
-          self.assertEqual(times, sorted(times), f"timestamps not monotonic in {name}")
-
-  def test_gemm_has_instructions(self):
-    for name, (events, *_) in self.examples.items():
-      if "gemm" not in name: continue
-      with self.subTest(example=name):
-        all_packets = [p for e in events for p in decode(e.blob)]
-        self.assertGreater(len([p for p in all_packets if isinstance(p, (INST, INST_L4))]), 0, f"no INST packets in {name}")
-
-  expected: dict[str, list[int]] = {}  # override in subclasses
-  def test_packet_counts(self):
-    if not self.expected: self.skipTest("no expected packet counts for this target")
-    for name, (events, *_) in self.examples.items():
-      with self.subTest(example=name):
-        if not self.expected.get(name): continue
-        counts = [len(list(decode(e.blob))) for e in events]
-        self.assertEqual(counts, self.expected[name], f"packet count mismatch in {name}")
-
-  def test_rocprof_wave_times_match(self):
-    """Wave start/end times must match rocprof exactly."""
-    for name, (events, lib, base) in self.examples.items():
-      with self.subTest(example=name):
-        occupancy, _ = run_rocprof_decoder([e.blob for e in events], lib, base, self.target)
-        # extract from rocprof occupancy records
-        roc_starts: dict[tuple[int, int, int], int] = {}
-        roc_waves: list[tuple[int, int]] = []
-        for wave_id, simd, cu, time, is_start in occupancy:
-          key = (wave_id, simd, cu)
-          if is_start: roc_starts[key] = time
-          elif key in roc_starts: roc_waves.append((roc_starts.pop(key), time))
-        # extract from our decoder
-        our_waves: list[tuple[int, int]] = []
-        for event in events:
-          wave_starts: dict[tuple[int, int, int], int] = {}
-          for p in decode(event.blob):
-            if isinstance(p, (WAVESTART, WAVESTART_L4)): wave_starts[(p.wave, p.simd, p.cu)] = p._time
-            elif isinstance(p, WAVEEND) and (key := (p.wave, p.simd, p.cu)) in wave_starts:
-              our_waves.append((wave_starts[key], p._time))
-        self.assertEqual(sorted(our_waves), sorted(roc_waves), f"wave times mismatch in {name}")
-
-  def test_rocprof_inst_times_match(self):
-    """Instruction times must match rocprof exactly (excluding s_endpgm)."""
-    for name, (events, lib, base) in self.examples.items():
-      with self.subTest(example=name):
-        _, wave_insts = run_rocprof_decoder([e.blob for e in events], lib, base, self.target)
-        # skip last inst per wave (s_endpgm) - it needs special handling (time + duration instead of time + stall)
-        roc_insts = [time + stall for insts in wave_insts for time, stall in insts[:-1]]
-        # extract from our decoder
-        our_insts: list[int] = []
-        for event in events:
-          for p in decode(event.blob):
-            if isinstance(p, INST) and p.op not in OTHER_SIMD_OPS: our_insts.append(p._time)
-            elif isinstance(p, INST_L4) and p.op not in OTHER_SIMD_OPS_L4: our_insts.append(p._time)
-            elif isinstance(p, VALUINST): our_insts.append(p._time)
-            elif isinstance(p, IMMEDIATE): our_insts.append(p._time)
-            elif isinstance(p, IMMEDIATE_MASK):
-              for _ in range(bin(p.mask).count('1')): our_insts.append(p._time)
-        self.assertEqual(sorted(our_insts), sorted(roc_insts), f"instruction times mismatch in {name}")
-
-class TestSQTTExamplesRDNA3(SQTTExamplesTestBase):
-  target = "gfx1100"
-  expected = {
-    "profile_empty_run_0": [1844, 1885, 1905, 1956, 1983, 1889],
-    "profile_empty_run_1": [1780, 1885, 1905, 1956, 1983, 1889],
-    "profile_gemm_run_0": [2656, 2025, 2045, 2096, 2123, 2029, 3183, 2019, 2039, 2090, 2117, 2023, 19119, 2013, 2033, 2084, 2111, 2017],
-    "profile_gemm_run_1": [2662, 2025, 2045, 2096, 2123, 2029, 3179, 2019, 2039, 2090, 2117, 2023, 19113, 2071, 2091, 2142, 2169, 2075],
-    "profile_plus_run_0": [1886, 2013, 2033, 2084, 2111, 2017],
-    "profile_plus_run_1": [1988, 2071, 2091, 2142, 2169, 2075],
-  }
-
-class TestSQTTExamplesRDNA4(SQTTExamplesTestBase): target = "gfx1200"
-# CDNA/MI300 (gfx950) uses a completely different 16-bit header packet format, not the nibble-based format.
-# See decode_tt_header_stream in ghidra/librocprof-trace-decoder.c - it reads 16-bit headers and uses
-# pkt_fmt = header & 0xf to look up packet_class (0x10=2bytes, 0x20=4bytes, 0x30=6bytes, 0x40=8bytes).
-# This is NOT implemented yet - the nibble decoder produces garbage for CDNA data.
-@unittest.skip("CDNA/MI300 uses 16-bit header format, not nibble-based - decoder not implemented")
-class TestSQTTExamplesCDNA(SQTTExamplesTestBase):
-  target = "gfx950"
-
-if __name__ == "__main__":
-  unittest.main()
@@ -1,170 +0,0 @@
-"""Tests comparing sqtt.py PACKET_TYPES_L3/L4 against AMD's rocprof-trace-decoder binary."""
-import unittest, struct, ctypes, pickle
-from pathlib import Path
-
-ROCPROF_LIB = Path("/usr/lib/librocprof-trace-decoder.so")
-EXAMPLES_DIR = Path(__file__).parent.parent.parent.parent / "sqtt/examples"
-
-def _find_segment(perms: str):
-  """Find a segment of the loaded library with given permissions (e.g. 'rw-p', 'r--p')."""
-  with open('/proc/self/maps', 'r') as f:
-    for line in f:
-      if 'librocprof-trace-decoder.so' in line and f' {perms} ' in line:
-        parts = line.split()
-        return int(parts[0].split('-')[0], 16), int(parts[2], 16)
-  return None, None
-
-def _read_array(file_offset: int, count: int):
-  """Read an array of uint8 at file_offset from the loaded library."""
-  base, seg_offset = _find_segment('rw-p')
-  if base is None: return None
-  return list((ctypes.c_uint8 * count).from_address(base + (file_offset - seg_offset)))
-
-def _load_lib():
-  if not ROCPROF_LIB.exists(): return False
-  ctypes.CDLL(str(ROCPROF_LIB))
-  return True
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# RDNA EXTRACTION (nibble-based format)
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def extract_bit_tables():
-  """Extract bit budget tables. Returns (layout2, layout3, layout4) or None."""
-  if not _load_lib(): return None
-  return _read_array(0x2d220, 32), _read_array(0x2d280, 32), _read_array(0x2d2c0, 32)
-
-def extract_delta_fields():
-  """Extract delta bitfield tables. Returns (layout2, layout3, layout4) dicts mapping type_id -> (lo, hi)."""
-  if not _load_lib(): return None
-  ro_base, ro_offset = _find_segment('r--p')
-  if ro_base is None: return None
-
-  def read_table(file_offset, num_entries):
-    addr = ro_base + (file_offset - ro_offset)
-    data = bytes((ctypes.c_uint8 * (num_entries * 12)).from_address(addr))
-    return {type_id: (lo, hi) for j in range(0, len(data), 12)
-            for type_id, lo, hi in [struct.unpack('<III', data[j:j+12])] if type_id < 32}
-
-  return read_table(0x26800, 24), read_table(0x26dc0, 25), read_table(0x27300, 27)
-
-def extract_packet_encodings():
-  """Extract packet encodings. Returns (L2, L3, L4) dicts mapping type_id -> (mask, value)."""
-  if not _load_lib(): return None
-  rw_base, rw_offset = _find_segment('rw-p')
-  if rw_base is None: return None
-
-  # Read base encodings from registration vector at 0x2d340
-  vec_start = ctypes.c_void_p.from_address(rw_base + (0x2d340 - rw_offset)).value
-  vec_end = ctypes.c_void_p.from_address(rw_base + (0x2d348 - rw_offset)).value
-  base = {}
-  if vec_start and vec_end:
-    for i in range((vec_end - vec_start) // 32):
-      addr = vec_start + i * 32
-      type_id = ctypes.c_uint8.from_address(addr).value
-      pat_start = ctypes.c_void_p.from_address(addr + 8).value
-      pat_end = ctypes.c_void_p.from_address(addr + 16).value
-      if pat_start and pat_end and 0 < (n := pat_end - pat_start) <= 8:
-        pat = list((ctypes.c_uint8 * n).from_address(pat_start))
-        base[type_id] = (sum(1 << j for j in range(n)), sum(b << j for j, b in enumerate(pat)))
-
-  return {**base, 17: (0x7f, 0x51), 25: (0x7f, 0x31)}, base, {**base}  # L2 has overrides
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# CDNA EXTRACTION (16-bit header format)
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def extract_cdna_packet_sizes():
-  """Extract CDNA pkt_fmt -> size mapping by running rocprof decoder to populate its hash table."""
-  from extra.assembly.amd.test.test_sqtt_examples import run_rocprof_decoder
-
-  if not (pkl_path := next((EXAMPLES_DIR / "gfx950").glob("*.pkl"), None)): return None
-  with open(pkl_path, "rb") as f: data = pickle.load(f)
-  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
-  prg = next((e for e in data if type(e).__name__ == "ProfileProgramEvent"), None)
-  if not sqtt_events or not prg: return None
-
-  # Run decoder to trigger hash table initialization
-  run_rocprof_decoder([e.blob for e in sqtt_events], prg.lib, prg.base, "gfx950")
-
-  # Extract hash table: head at 0x2d4f0, nodes are 16 bytes (next[8], key[4], value[4])
-  rw_base, rw_offset = _find_segment('rw-p')
-  if not (head := ctypes.c_void_p.from_address(rw_base + (0x2d4f0 - rw_offset)).value if rw_base else None): return None
-
-  pkt_sizes, node, seen = {}, head, set()
-  while node and node not in seen and len(pkt_sizes) < 20:
-    seen.add(node)
-    key, val = ctypes.c_uint32.from_address(node + 8).value, ctypes.c_uint32.from_address(node + 12).value
-    if key < 16 and val in (0x10, 0x20, 0x30, 0x40): pkt_sizes[key] = {0x10: 2, 0x20: 4, 0x30: 6, 0x40: 8}[val]
-    node = ctypes.c_void_p.from_address(node).value
-  return pkt_sizes if len(pkt_sizes) == 16 else None
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# TESTS
-# ═══════════════════════════════════════════════════════════════════════════════
-
-class TestSQTTMatchesBinary(unittest.TestCase):
-  def test_bit_counts_match_layout3(self): self._test_bit_counts(3)
-  def test_bit_counts_match_layout4(self): self._test_bit_counts(4)
-  def test_encodings_match_layout3(self): self._test_encodings(3)
-  def test_encodings_match_layout4(self): self._test_encodings(4)
-  def test_delta_fields_match_layout3(self): self._test_delta_fields(3)
-  def test_delta_fields_match_layout4(self): self._test_delta_fields(4)
-
-  def test_cdna_packet_sizes(self):
-    """Extract and verify CDNA pkt_fmt -> size mapping from rocprof's hash table."""
-    if not (EXAMPLES_DIR / "gfx950").exists(): self.skipTest("no CDNA examples")
-    pkt_sizes = extract_cdna_packet_sizes()
-    self.assertIsNotNone(pkt_sizes, "failed to extract CDNA packet sizes")
-    from extra.assembly.amd.sqtt_cdna import CDNA_PKT_SIZES
-    for pkt_fmt, size in CDNA_PKT_SIZES.items():
-      with self.subTest(pkt_fmt=pkt_fmt): self.assertEqual(pkt_sizes.get(pkt_fmt), size)
-
-  def _test_bit_counts(self, layout: int):
-    if not (tables := extract_bit_tables()): self.skipTest("rocprof-trace-decoder not installed")
-    from extra.assembly.amd.sqtt import PACKET_TYPES_L3, PACKET_TYPES_L4
-    for type_id, pkt_cls in {3: PACKET_TYPES_L3, 4: PACKET_TYPES_L4}[layout].items():
-      with self.subTest(packet=pkt_cls.__name__):
-        self.assertEqual(pkt_cls._size_nibbles * 4, tables[layout - 2][type_id])
-
-  def _test_encodings(self, layout: int):
-    if not (encodings := extract_packet_encodings()): self.skipTest("rocprof-trace-decoder not installed")
-    from extra.assembly.amd.sqtt import PACKET_TYPES_L3, PACKET_TYPES_L4
-    for type_id, pkt_cls in {3: PACKET_TYPES_L3, 4: PACKET_TYPES_L4}[layout].items():
-      with self.subTest(packet=pkt_cls.__name__):
-        self.assertEqual((pkt_cls.encoding.mask, pkt_cls.encoding.default), encodings[layout - 2][type_id])
-
-  def _test_delta_fields(self, layout: int):
-    if not (deltas := extract_delta_fields()): self.skipTest("rocprof-trace-decoder not installed")
-    from extra.assembly.amd.sqtt import PACKET_TYPES_L3, PACKET_TYPES_L4
-    for type_id, pkt_cls in {3: PACKET_TYPES_L3, 4: PACKET_TYPES_L4}[layout].items():
-      if type_id not in deltas[layout - 2]: continue
-      delta = getattr(pkt_cls, 'delta', None)
-      actual = (0, 0) if delta is None else (delta.lo, delta.hi + 1)
-      with self.subTest(packet=pkt_cls.__name__): self.assertEqual(actual, deltas[layout - 2][type_id])
-
-if __name__ == "__main__":
-  tables = extract_bit_tables()
-  encodings = extract_packet_encodings()
-  deltas = extract_delta_fields()
-
-  TYPE_NAMES = {1: 'VALUINST', 2: 'VMEMEXEC', 3: 'ALUEXEC', 4: 'IMMEDIATE', 5: 'IMMEDIATE_MASK', 6: 'WAVERDY',
-    7: 'TS_DELTA_S8_W3', 8: 'WAVEEND', 9: 'WAVESTART', 10: 'TS_DELTA_S5_W2', 11: 'WAVEALLOC', 12: 'TS_DELTA_S5_W3',
-    13: 'PERF', 14: 'UTILCTR', 15: 'TS_DELTA_SHORT', 16: 'NOP', 17: 'TS_WAVE_STATE', 18: 'EVENT', 19: 'EVENT_BIG',
-    20: 'REG', 21: 'SNAPSHOT', 22: 'TS_DELTA_OR_MARK', 23: 'LAYOUT_HEADER', 24: 'INST', 25: 'UNK_25'}
-
-  print("L2:", tables[0], "\nL3:", tables[1], "\nL4:", tables[2])
-  if encodings and tables:
-    print(f"\n{'TypeID':>6} {'Name':>18} {'L2 enc':>12} {'L3 enc':>12} {'L4 enc':>12} {'L2':>4} {'L3':>4} {'L4':>4} {'L2 delta':>12} {'L3 delta':>12} {'L4 delta':>12}")
-    print("-" * 140)
-    for type_id in sorted(set(encodings[0]) | set(encodings[1]) | set(encodings[2])):
-      name = TYPE_NAMES.get(type_id, f'UNK_{type_id}')
-      bits = [tables[i][type_id] if type_id < len(tables[i]) else 0 for i in range(3)]
-      enc_strs = [f"0x{encodings[i][type_id][0]:02x}/0x{encodings[i][type_id][1]:02x}" if type_id in encodings[i] else "-" for i in range(3)]
-      delta_strs = [f"[{d[1]-1}:{d[0]}]" if (d := deltas[i].get(type_id, (0, 0)))[1] > d[0] else "-" for i in range(3)]
-      print(f"{type_id:6d} {name:>18} {enc_strs[0]:>12} {enc_strs[1]:>12} {enc_strs[2]:>12} {bits[0]:4d} {bits[1]:4d} {bits[2]:4d} {delta_strs[0]:>12} {delta_strs[1]:>12} {delta_strs[2]:>12}")
-
-  cdna = extract_cdna_packet_sizes()
-  if cdna: print(f"\nCDNA packet sizes: {cdna}")
-
-  unittest.main()
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
geohot	aec4d65241	ds compiled	2025-12-31 15:43:44 -05:00
geohot	f022a7d8a7	assembly/amd: move more instructions to pcode	2025-12-31 15:42:59 -05:00
				`@@ -1 +0,0 @@`
				`"""Hardware-validated emulator tests for RDNA3 instructions."""`