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AM driver (#6923)

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* connect to gpu

* rlc init?

* gfx comp start init

* early init is hardoded, some progress with fw

* gart

* progress, next mqd

* ring setup, still does not execute anything

* ugh write correct reg

* pci2: vm

* pci2: start psp

* vm seems to work

* pci2: gfx start

* pci2: fix psp ring resp

* pci2: try ring

* pci2: mes and some fixes

* pci2: some progress

* pci2: progress

* pci2: mm

* pci2: discovery

* pci2: correct apertures

* pci2: b

* pci2: i

* pci2: l

* pci2: o

* pci2: cmu

* pci2: mes_kiq works

* pci2: mes

* pci2: kcq does not work(

* pci2: unhalt gfx

* ops_am

* minor

* check if amdgpu is there, or we will crash

* bring back graph, it just works

* less prints

* do not init mes (not used)

* remove unused files

* ops_am: start move into core

* ops_am: works

* clcks, but still slower

* faster + no mes_kiq

* vm frags + remove mes

* cleanup fw

* gmc tiny cleanup

* move to ops_amd

* comment out what we dont really need

* driverless

* close in speed

* am clean most of ips

* gmc to ips

* cleaner

* new vm walker

* comment old one

* remove unsued autogens

* last write ups

* remove psp hardcoded values

* more

* add logs

* ih

* p2p and sdma

* vfio hal and interrupts

* smth

* amd dev iface

* minor after rebase

* bind for sdma

* Revert "bind for sdma"

This reverts commit a90766514d.

* tmp

* debug new mm

* ugh, allreduce hangs fixed

* p1

* works

* no pci.py

* cleaner a bit

* smth

* tiny cleanups

* cleaner a bit

* pciiface

* linter

* linter 2

* linter 3

* linter

* pylint

* reverted unrelated changes

* unrelated

* cmp tool

* ugh wrong fw

* clockgating

* unrelated

* alloc smaller chunks

* this

* opt sigs

* collect stat

* ops

* upd

* proclogs

* proclogs2

* vfio

* ruff

* linter pylint

* oops

* mypy p1

* mem fix

* mypy p2

* mypy p3

* mypy p4

* correct

* minor

* more tests

* linter in tests

* pci_regs header

* minor write up

* setup

* do not require libs

---------

Co-authored-by: George Hotz <[email protected]>
This commit is contained in:
nimlgen
2024-12-31 23:06:17 +03:00
committed by GitHub
co-authored by George Hotz
parent d4a1d5211e
commit c18307e749
49 changed files with 529016 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
autogen_stubs.sh
+81 -1
View File
@@ -247,6 +247,83 @@ generate_qcom() {
python3 -c "import tinygrad.runtime.autogen.qcom_dsp"
}
generate_pciaccess() {
clang2py -k cdefstum \
/usr/include/pciaccess.h \
/usr/include/linux/pci_regs.h \
-l /usr/lib/x86_64-linux-gnu/libpciaccess.so \
-o $BASE/libpciaccess.py
sed -i "s\import ctypes\import ctypes, os\g" $BASE/libpciaccess.py
fixup $BASE/libpciaccess.py
sed -i "s/ctypes\.CDLL('\([^']*\)')/ctypes.CDLL('\1') if os.path.exists('\1') else None/g" $BASE/libpciaccess.py
}
generate_vfio() {
clang2py -k cdefstum \
/usr/include/linux/vfio.h \
-o $BASE/vfio.py
fixup $BASE/vfio.py
}
generate_am() {
clang2py -k cdefstum \
extra/amdpci/headers/v11_structs.h \
extra/amdpci/headers/amdgpu_vm.h \
extra/amdpci/headers/discovery.h \
extra/amdpci/headers/amdgpu_ucode.h \
extra/amdpci/headers/soc21_enum.h \
extra/amdpci/headers/psp_gfx_if.h \
extra/amdpci/headers/amdgpu_psp.h \
extra/amdpci/headers/amdgpu_irq.h \
extra/amdpci/headers/amdgpu_doorbell.h \
extra/amdpci/headers/soc15_ih_clientid.h \
-o $BASE/am/am.py
fixup $BASE/am/am.py
clang2py -k cdefstum \
extra/amdpci/headers/mp_13_0_0_offset.h \
extra/amdpci/headers/mp_13_0_0_sh_mask.h \
-o $BASE/am/mp_13_0_0.py
fixup $BASE/am/mp_13_0_0.py
clang2py -k cdefstum \
extra/amdpci/headers/mp_11_0_offset.h \
extra/amdpci/headers/mp_11_0_sh_mask.h \
-o $BASE/am/mp_11_0.py
fixup $BASE/am/mp_11_0.py
clang2py -k cdefstum \
extra/amdpci/headers/gc_11_0_0_offset.h \
extra/amdpci/headers/gc_11_0_0_sh_mask.h \
-o $BASE/am/gc_11_0_0.py
fixup $BASE/am/gc_11_0_0.py
clang2py -k cdefstum \
extra/amdpci/headers/mmhub_3_0_0_offset.h \
extra/amdpci/headers/mmhub_3_0_0_sh_mask.h \
-o $BASE/am/mmhub_3_0_0.py
fixup $BASE/am/mmhub_3_0_0.py
clang2py -k cdefstum \
extra/amdpci/headers/nbio_4_3_0_offset.h \
extra/amdpci/headers/nbio_4_3_0_sh_mask.h \
-o $BASE/am/nbio_4_3_0.py
fixup $BASE/am/nbio_4_3_0.py
clang2py -k cdefstum \
extra/amdpci/headers/osssys_6_0_0_offset.h \
extra/amdpci/headers/osssys_6_0_0_sh_mask.h \
-o $BASE/am/osssys_6_0_0.py
fixup $BASE/am/osssys_6_0_0.py
clang2py -k cdefstum \
extra/amdpci/headers/smu_v13_0_0_ppsmc.h \
extra/amdpci/headers/smu13_driver_if_v13_0_0.h \
extra/amdpci/headers/amdgpu_smu.h \
-o $BASE/am/smu_v13_0_0.py
fixup $BASE/am/smu_v13_0_0.py
}
if [ "$1" == "opencl" ]; then generate_opencl
elif [ "$1" == "hip" ]; then generate_hip
elif [ "$1" == "comgr" ]; then generate_comgr
@@ -256,11 +333,14 @@ elif [ "$1" == "hsa" ]; then generate_hsa
elif [ "$1" == "kfd" ]; then generate_kfd
elif [ "$1" == "nv" ]; then generate_nv
elif [ "$1" == "amd" ]; then generate_amd
elif [ "$1" == "am" ]; then generate_am
elif [ "$1" == "qcom" ]; then generate_qcom
elif [ "$1" == "io_uring" ]; then generate_io_uring
elif [ "$1" == "libc" ]; then generate_libc
elif [ "$1" == "kgsl" ]; then generate_kgsl
elif [ "$1" == "adreno" ]; then generate_adreno
elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_libc
elif [ "$1" == "pci" ]; then generate_pciaccess
elif [ "$1" == "vfio" ]; then generate_vfio
elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_libc; generate_am
else echo "usage: $0 <type>"
fi
extra/amdpci/headers/amdgpu_doorbell.h
+279
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@@ -0,0 +1,279 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef AMDGPU_DOORBELL_H
#define AMDGPU_DOORBELL_H
enum AMDGPU_DOORBELL_ASSIGNMENT {
AMDGPU_DOORBELL_KIQ = 0x000,
AMDGPU_DOORBELL_HIQ = 0x001,
AMDGPU_DOORBELL_DIQ = 0x002,
AMDGPU_DOORBELL_MEC_RING0 = 0x010,
AMDGPU_DOORBELL_MEC_RING1 = 0x011,
AMDGPU_DOORBELL_MEC_RING2 = 0x012,
AMDGPU_DOORBELL_MEC_RING3 = 0x013,
AMDGPU_DOORBELL_MEC_RING4 = 0x014,
AMDGPU_DOORBELL_MEC_RING5 = 0x015,
AMDGPU_DOORBELL_MEC_RING6 = 0x016,
AMDGPU_DOORBELL_MEC_RING7 = 0x017,
AMDGPU_DOORBELL_GFX_RING0 = 0x020,
AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
AMDGPU_DOORBELL_IH = 0x1E8,
AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
AMDGPU_DOORBELL_INVALID = 0xFFFF
};
enum AMDGPU_VEGA20_DOORBELL_ASSIGNMENT {
/* Compute + GFX: 0~255 */
AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
/* SDMA:256~335*/
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
/* IH: 376~391 */
AMDGPU_VEGA20_DOORBELL_IH = 0x178,
/* MMSCH: 392~407
* overlap the doorbell assignment with VCN as they are mutually exclusive
* VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
*/
AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */
AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */
AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D,
AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E,
AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F,
AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
/* kiq/kcq from second XCD. Max 8 XCDs */
AMDGPU_VEGA20_DOORBELL_XCC1_KIQ_START = 0x190,
/* 8 compute rings per GC. Max to 0x1CE */
AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197,
/* AID1 SDMA: 0x1D0 ~ 0x1F7 */
AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0,
AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7,
AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
};
enum AMDGPU_NAVI10_DOORBELL_ASSIGNMENT {
/* Compute + GFX: 0~255 */
AMDGPU_NAVI10_DOORBELL_KIQ = 0x000,
AMDGPU_NAVI10_DOORBELL_HIQ = 0x001,
AMDGPU_NAVI10_DOORBELL_DIQ = 0x002,
AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003,
AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004,
AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005,
AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006,
AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007,
AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008,
AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009,
AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A,
AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B,
AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C,
AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D,
AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A,
AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B,
AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C,
AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D,
AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF,
/* SDMA:256~335*/
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114,
AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E,
/* IH: 376~391 */
AMDGPU_NAVI10_DOORBELL_IH = 0x178,
/* MMSCH: 392~407
* overlap the doorbell assignment with VCN as they are mutually exclusive
* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
*/
AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189,
AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A,
AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B,
AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C,
AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D,
AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E,
AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F,
AMDGPU_NAVI10_DOORBELL64_VPE = 0x190,
AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VPE,
AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = AMDGPU_NAVI10_DOORBELL64_VPE,
AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF
};
/*
* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
*/
enum AMDGPU_DOORBELL64_ASSIGNMENT {
/*
* All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
* a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
* Compute related doorbells are allocated from 0x00 to 0x8a
*/
/* kernel scheduling */
AMDGPU_DOORBELL64_KIQ = 0x00,
/* HSA interface queue and debug queue */
AMDGPU_DOORBELL64_HIQ = 0x01,
AMDGPU_DOORBELL64_DIQ = 0x02,
/* Compute engines */
AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
/* User queue doorbell range (128 doorbells) */
AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
/* Graphics engine */
AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
/*
* Other graphics doorbells can be allocated here: from 0x8c to 0xdf
* Graphics voltage island aperture 1
* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
*/
/* For vega10 sriov, the sdma doorbell must be fixed as follow
* to keep the same setting with host driver, or it will
* happen conflicts
*/
AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
/* Interrupt handler */
AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
/* VCN engine use 32 bits doorbell */
AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
/* overlap the doorbell assignment with VCN as they are mutually exclusive
* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
*/
AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0,
AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
AMDGPU_DOORBELL64_INVALID = 0xFFFF
};
enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 {
/* XCC0: 0x00 ~20, XCC1: 20 ~ 2F ... */
/* KIQ/HIQ/DIQ */
AMDGPU_DOORBELL_LAYOUT1_KIQ_START = 0x000,
AMDGPU_DOORBELL_LAYOUT1_HIQ = 0x001,
AMDGPU_DOORBELL_LAYOUT1_DIQ = 0x002,
/* Compute: 0x08 ~ 0x20 */
AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START = 0x008,
AMDGPU_DOORBELL_LAYOUT1_MEC_RING_END = 0x00F,
AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START = 0x010,
AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END = 0x01F,
AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE = 0x020,
/* SDMA: 0x100 ~ 0x19F */
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START = 0x100,
AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END = 0x19F,
/* IH: 0x1A0 ~ 0x1AF */
AMDGPU_DOORBELL_LAYOUT1_IH = 0x1A0,
/* VCN: 0x1B0 ~ 0x1E8 */
AMDGPU_DOORBELL_LAYOUT1_VCN_START = 0x1B0,
AMDGPU_DOORBELL_LAYOUT1_VCN_END = 0x1E8,
AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START,
AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP = AMDGPU_DOORBELL_LAYOUT1_VCN_END,
AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT = 0x1E8,
AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF
};
#endif
extra/amdpci/headers/amdgpu_irq.h
+87
View File
@@ -0,0 +1,87 @@
/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMDGPU_IRQ_H__
#define __AMDGPU_IRQ_H__
// #include <linux/irqdomain.h>
// #include "soc15_ih_clientid.h"
// #include "amdgpu_ih.h"
#define int32_t int
#define uint32_t unsigned int
#define int8_t signed char
#define uint8_t unsigned char
#define uint16_t unsigned short
#define int16_t short
#define uint64_t unsigned long long
#define bool _Bool
#define u32 unsigned int
#define AMDGPU_MAX_IRQ_SRC_ID 0x100
#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
#define AMDGPU_IRQ_CLIENTID_LEGACY 0
#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
struct amdgpu_device;
enum amdgpu_interrupt_state {
AMDGPU_IRQ_STATE_DISABLE,
AMDGPU_IRQ_STATE_ENABLE,
};
struct amdgpu_iv_entry {
// struct amdgpu_ih_ring *ih;
unsigned client_id;
unsigned src_id;
unsigned ring_id;
unsigned vmid;
unsigned vmid_src;
uint64_t timestamp;
unsigned timestamp_src;
unsigned pasid;
unsigned node_id;
unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
const uint32_t *iv_entry;
};
enum interrupt_node_id_per_aid {
AID0_NODEID = 0,
XCD0_NODEID = 1,
XCD1_NODEID = 2,
AID1_NODEID = 4,
XCD2_NODEID = 5,
XCD3_NODEID = 6,
AID2_NODEID = 8,
XCD4_NODEID = 9,
XCD5_NODEID = 10,
AID3_NODEID = 12,
XCD6_NODEID = 13,
XCD7_NODEID = 14,
NODEID_MAX,
};
#endif
extra/amdpci/headers/amdgpu_psp.h
+559
View File
@@ -0,0 +1,559 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Author: Huang Rui
*
*/
#ifndef __AMDGPU_PSP_H__
#define __AMDGPU_PSP_H__
// #include "amdgpu.h"
// #include "psp_gfx_if.h"
// #include "ta_xgmi_if.h"
// #include "ta_ras_if.h"
// #include "ta_rap_if.h"
// #include "ta_secureDisplay_if.h"
#define PSP_FENCE_BUFFER_SIZE 0x1000
#define PSP_CMD_BUFFER_SIZE 0x1000
#define PSP_1_MEG 0x100000
#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
#define PSP_TMR_ALIGNMENT 0x100000
#define PSP_FW_NAME_LEN 0x24
// extern const struct attribute_group amdgpu_flash_attr_group;
enum psp_shared_mem_size {
PSP_ASD_SHARED_MEM_SIZE = 0x0,
PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
PSP_RAS_SHARED_MEM_SIZE = 0x4000,
PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
PSP_DTM_SHARED_MEM_SIZE = 0x4000,
PSP_RAP_SHARED_MEM_SIZE = 0x4000,
PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
};
enum ta_type_id {
TA_TYPE_XGMI = 1,
TA_TYPE_RAS,
TA_TYPE_HDCP,
TA_TYPE_DTM,
TA_TYPE_RAP,
TA_TYPE_SECUREDISPLAY,
TA_TYPE_MAX_INDEX,
};
struct psp_context;
struct psp_xgmi_node_info;
struct psp_xgmi_topology_info;
struct psp_bin_desc;
enum psp_bootloader_cmd {
PSP_BL__LOAD_SYSDRV = 0x10000,
PSP_BL__LOAD_SOSDRV = 0x20000,
PSP_BL__LOAD_KEY_DATABASE = 0x80000,
PSP_BL__LOAD_SOCDRV = 0xB0000,
PSP_BL__LOAD_DBGDRV = 0xC0000,
PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV,
PSP_BL__LOAD_INTFDRV = 0xD0000,
PSP_BL__LOAD_RASDRV = 0xE0000,
PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000,
PSP_BL__DRAM_LONG_TRAIN = 0x100000,
PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
};
enum psp_ring_type {
PSP_RING_TYPE__INVALID = 0,
/*
* These values map to the way the PSP kernel identifies the
* rings.
*/
PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
};
// struct psp_ring {
// enum psp_ring_type ring_type;
// struct psp_gfx_rb_frame *ring_mem;
// uint64_t ring_mem_mc_addr;
// void *ring_mem_handle;
// uint32_t ring_size;
// uint32_t ring_wptr;
// };
/* More registers may will be supported */
enum psp_reg_prog_id {
PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
PSP_REG_LAST
};
// struct psp_funcs {
// int (*init_microcode)(struct psp_context *psp);
// int (*wait_for_bootloader)(struct psp_context *psp);
// int (*bootloader_load_kdb)(struct psp_context *psp);
// int (*bootloader_load_spl)(struct psp_context *psp);
// int (*bootloader_load_sysdrv)(struct psp_context *psp);
// int (*bootloader_load_soc_drv)(struct psp_context *psp);
// int (*bootloader_load_intf_drv)(struct psp_context *psp);
// int (*bootloader_load_dbg_drv)(struct psp_context *psp);
// int (*bootloader_load_ras_drv)(struct psp_context *psp);
// int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp);
// int (*bootloader_load_sos)(struct psp_context *psp);
// int (*ring_create)(struct psp_context *psp,
// enum psp_ring_type ring_type);
// int (*ring_stop)(struct psp_context *psp,
// enum psp_ring_type ring_type);
// int (*ring_destroy)(struct psp_context *psp,
// enum psp_ring_type ring_type);
// bool (*smu_reload_quirk)(struct psp_context *psp);
// int (*mode1_reset)(struct psp_context *psp);
// int (*mem_training)(struct psp_context *psp, uint32_t ops);
// uint32_t (*ring_get_wptr)(struct psp_context *psp);
// void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
// int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
// int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
// int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
// int (*vbflash_stat)(struct psp_context *psp);
// int (*fatal_error_recovery_quirk)(struct psp_context *psp);
// bool (*get_ras_capability)(struct psp_context *psp);
// bool (*is_aux_sos_load_required)(struct psp_context *psp);
// };
// struct ta_funcs {
// int (*fn_ta_initialize)(struct psp_context *psp);
// int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
// int (*fn_ta_terminate)(struct psp_context *psp);
// };
#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
// struct psp_xgmi_node_info {
// uint64_t node_id;
// uint8_t num_hops;
// uint8_t is_sharing_enabled;
// enum ta_xgmi_assigned_sdma_engine sdma_engine;
// uint8_t num_links;
// struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM];
// };
// struct psp_xgmi_topology_info {
// uint32_t num_nodes;
// struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
// };
// struct psp_bin_desc {
// uint32_t fw_version;
// uint32_t feature_version;
// uint32_t size_bytes;
// uint8_t *start_addr;
// };
// struct ta_mem_context {
// struct amdgpu_bo *shared_bo;
// uint64_t shared_mc_addr;
// void *shared_buf;
// enum psp_shared_mem_size shared_mem_size;
// };
// struct ta_context {
// bool initialized;
// uint32_t session_id;
// uint32_t resp_status;
// struct ta_mem_context mem_context;
// struct psp_bin_desc bin_desc;
// enum psp_gfx_cmd_id ta_load_type;
// enum ta_type_id ta_type;
// };
// struct ta_cp_context {
// struct ta_context context;
// struct mutex mutex;
// };
// struct psp_xgmi_context {
// struct ta_context context;
// struct psp_xgmi_topology_info top_info;
// bool supports_extended_data;
// uint8_t xgmi_ta_caps;
// };
// struct psp_ras_context {
// struct ta_context context;
// struct amdgpu_ras *ras;
// };
#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
#define GDDR6_MEM_TRAINING_OFFSET 0x8000
/*Define the VRAM size that will be encroached by BIST training.*/
#define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
enum psp_memory_training_init_flag {
PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
PSP_MEM_TRAIN_SUPPORT = 0x1,
PSP_MEM_TRAIN_INIT_FAILED = 0x2,
PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
};
enum psp_memory_training_ops {
PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
PSP_MEM_TRAIN_SAVE = 0x2,
PSP_MEM_TRAIN_RESTORE = 0x4,
PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
};
// struct psp_memory_training_context {
// /*training data size*/
// u64 train_data_size;
// /*
// * sys_cache
// * cpu virtual address
// * system memory buffer that used to store the training data.
// */
// void *sys_cache;
// /*vram offset of the p2c training data*/
// u64 p2c_train_data_offset;
// /*vram offset of the c2p training data*/
// u64 c2p_train_data_offset;
// struct amdgpu_bo *c2p_bo;
// enum psp_memory_training_init_flag init;
// u32 training_cnt;
// bool enable_mem_training;
// };
/** PSP runtime DB **/
#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
#define PSP_RUNTIME_DB_OFFSET 0x100000
#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
#define PSP_RUNTIME_DB_VER_1 0x0100
#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
enum psp_runtime_entry_type {
PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
};
/* PSP runtime DB header */
// struct psp_runtime_data_header {
// /* determine the existence of runtime db */
// uint16_t cookie;
// /* version of runtime db */
// uint16_t version;
// };
// /* PSP runtime DB entry */
// struct psp_runtime_entry {
// /* type of runtime db entry */
// uint32_t entry_type;
// /* offset of entry in bytes */
// uint16_t offset;
// /* size of entry in bytes */
// uint16_t size;
// };
// /* PSP runtime DB directory */
// struct psp_runtime_data_directory {
// /* number of valid entries */
// uint16_t entry_count;
// /* db entries*/
// struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
// };
/* PSP runtime DB boot config feature bitmask */
enum psp_runtime_boot_cfg_feature {
BOOT_CFG_FEATURE_GECC = 0x1,
BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
};
/* PSP run time DB SCPM authentication defines */
enum psp_runtime_scpm_authentication {
SCPM_DISABLE = 0x0,
SCPM_ENABLE = 0x1,
SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
};
/* PSP runtime DB boot config entry */
// struct psp_runtime_boot_cfg_entry {
// uint32_t boot_cfg_bitmask;
// uint32_t reserved;
// };
// /* PSP runtime DB SCPM entry */
// struct psp_runtime_scpm_entry {
// enum psp_runtime_scpm_authentication scpm_status;
// };
// struct psp_context {
// struct amdgpu_device *adev;
// struct psp_ring km_ring;
// struct psp_gfx_cmd_resp *cmd;
// const struct psp_funcs *funcs;
// const struct ta_funcs *ta_funcs;
// /* firmware buffer */
// struct amdgpu_bo *fw_pri_bo;
// uint64_t fw_pri_mc_addr;
// void *fw_pri_buf;
// /* sos firmware */
// const struct firmware *sos_fw;
// struct psp_bin_desc sys;
// struct psp_bin_desc sos;
// struct psp_bin_desc toc;
// struct psp_bin_desc kdb;
// struct psp_bin_desc spl;
// struct psp_bin_desc rl;
// struct psp_bin_desc soc_drv;
// struct psp_bin_desc intf_drv;
// struct psp_bin_desc dbg_drv;
// struct psp_bin_desc ras_drv;
// struct psp_bin_desc ipkeymgr_drv;
// /* tmr buffer */
// struct amdgpu_bo *tmr_bo;
// uint64_t tmr_mc_addr;
// /* asd firmware */
// const struct firmware *asd_fw;
// /* toc firmware */
// const struct firmware *toc_fw;
// /* cap firmware */
// const struct firmware *cap_fw;
// /* fence buffer */
// struct amdgpu_bo *fence_buf_bo;
// uint64_t fence_buf_mc_addr;
// void *fence_buf;
// /* cmd buffer */
// struct amdgpu_bo *cmd_buf_bo;
// uint64_t cmd_buf_mc_addr;
// struct psp_gfx_cmd_resp *cmd_buf_mem;
// /* fence value associated with cmd buffer */
// atomic_t fence_value;
// /* flag to mark whether gfx fw autoload is supported or not */
// bool autoload_supported;
// /* flag to mark whether psp use runtime TMR or boottime TMR */
// bool boot_time_tmr;
// /* flag to mark whether df cstate management centralized to PMFW */
// bool pmfw_centralized_cstate_management;
// /* xgmi ta firmware and buffer */
// const struct firmware *ta_fw;
// uint32_t ta_fw_version;
// uint32_t cap_fw_version;
// uint32_t cap_feature_version;
// uint32_t cap_ucode_size;
// struct ta_context asd_context;
// struct psp_xgmi_context xgmi_context;
// struct psp_ras_context ras_context;
// struct ta_cp_context hdcp_context;
// struct ta_cp_context dtm_context;
// struct ta_cp_context rap_context;
// struct ta_cp_context securedisplay_context;
// struct mutex mutex;
// struct psp_memory_training_context mem_train_ctx;
// uint32_t boot_cfg_bitmask;
// /* firmware upgrades supported */
// bool sup_pd_fw_up;
// bool sup_ifwi_up;
// char *vbflash_tmp_buf;
// size_t vbflash_image_size;
// bool vbflash_done;
// };
// struct amdgpu_psp_funcs {
// bool (*check_fw_loading_status)(struct amdgpu_device *adev,
// enum AMDGPU_UCODE_ID);
// };
// #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
// #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
// #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
// #define psp_init_microcode(psp) \
// ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
// #define psp_bootloader_load_kdb(psp) \
// ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
// #define psp_bootloader_load_spl(psp) \
// ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
// #define psp_bootloader_load_sysdrv(psp) \
// ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
// #define psp_bootloader_load_soc_drv(psp) \
// ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
// #define psp_bootloader_load_intf_drv(psp) \
// ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
// #define psp_bootloader_load_dbg_drv(psp) \
// ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
// #define psp_bootloader_load_ras_drv(psp) \
// ((psp)->funcs->bootloader_load_ras_drv ? \
// (psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
// #define psp_bootloader_load_ipkeymgr_drv(psp) \
// ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \
// (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0)
// #define psp_bootloader_load_sos(psp) \
// ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
// #define psp_smu_reload_quirk(psp) \
// ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
// #define psp_mode1_reset(psp) \
// ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
// #define psp_mem_training(psp, ops) \
// ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
// #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
// #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
// #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
// ((psp)->funcs->load_usbc_pd_fw ? \
// (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
// #define psp_read_usbc_pd_fw(psp, fw_ver) \
// ((psp)->funcs->read_usbc_pd_fw ? \
// (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
// #define psp_update_spirom(psp, fw_pri_mc_addr) \
// ((psp)->funcs->update_spirom ? \
// (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
// #define psp_vbflash_status(psp) \
// ((psp)->funcs->vbflash_stat ? \
// (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
// #define psp_fatal_error_recovery_quirk(psp) \
// ((psp)->funcs->fatal_error_recovery_quirk ? \
// (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
// #define psp_is_aux_sos_load_required(psp) \
// ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0)
// extern const struct amd_ip_funcs psp_ip_funcs;
// extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
// extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
// extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
// extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
// extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
// extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
// extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
// extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
// extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
// uint32_t field_val, uint32_t mask, bool check_changed);
// extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
// uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
// int psp_execute_ip_fw_load(struct psp_context *psp,
// struct amdgpu_firmware_info *ucode);
// int psp_gpu_reset(struct amdgpu_device *adev);
// int psp_ta_init_shared_buf(struct psp_context *psp,
// struct ta_mem_context *mem_ctx);
// void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
// int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
// int psp_ta_load(struct psp_context *psp, struct ta_context *context);
// int psp_ta_invoke(struct psp_context *psp,
// uint32_t ta_cmd_id,
// struct ta_context *context);
// int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
// int psp_xgmi_terminate(struct psp_context *psp);
// int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
// int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
// int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
// int psp_xgmi_get_topology_info(struct psp_context *psp,
// int number_devices,
// struct psp_xgmi_topology_info *topology,
// bool get_extended_data);
// int psp_xgmi_set_topology_info(struct psp_context *psp,
// int number_devices,
// struct psp_xgmi_topology_info *topology);
// int psp_ras_initialize(struct psp_context *psp);
// int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
// int psp_ras_enable_features(struct psp_context *psp,
// union ta_ras_cmd_input *info, bool enable);
// int psp_ras_trigger_error(struct psp_context *psp,
// struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
// int psp_ras_terminate(struct psp_context *psp);
// int psp_ras_query_address(struct psp_context *psp,
// struct ta_ras_query_address_input *addr_in,
// struct ta_ras_query_address_output *addr_out);
// int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
// int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
// int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
// int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
// int psp_rlc_autoload_start(struct psp_context *psp);
// int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
// uint32_t value);
// int psp_ring_cmd_submit(struct psp_context *psp,
// uint64_t cmd_buf_mc_addr,
// uint64_t fence_mc_addr,
// int index);
// int psp_init_asd_microcode(struct psp_context *psp,
// const char *chip_name);
// int psp_init_toc_microcode(struct psp_context *psp,
// const char *chip_name);
// int psp_init_sos_microcode(struct psp_context *psp,
// const char *chip_name);
// int psp_init_ta_microcode(struct psp_context *psp,
// const char *chip_name);
// int psp_init_cap_microcode(struct psp_context *psp,
// const char *chip_name);
// int psp_get_fw_attestation_records_addr(struct psp_context *psp,
// uint64_t *output_ptr);
// int psp_load_fw_list(struct psp_context *psp,
// struct amdgpu_firmware_info **ucode_list, int ucode_count);
// void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
// int psp_spatial_partition(struct psp_context *psp, int mode);
// int is_psp_fw_valid(struct psp_bin_desc bin);
// int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
// bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
#endif
extra/amdpci/headers/amdgpu_smu.h
+347
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/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AMDGPU_SMU_H__
#define __AMDGPU_SMU_H__
#define int32_t int
#define uint32_t unsigned int
#define int8_t signed char
#define uint8_t unsigned char
#define uint16_t unsigned short
#define int16_t short
#define uint64_t unsigned long long
#define bool _Bool
#define u32 unsigned int
#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
#define SMU_FW_NAME_LEN 0x24
#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1)
#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2)
// Power Throttlers
#define SMU_THROTTLER_PPT0_BIT 0
#define SMU_THROTTLER_PPT1_BIT 1
#define SMU_THROTTLER_PPT2_BIT 2
#define SMU_THROTTLER_PPT3_BIT 3
#define SMU_THROTTLER_SPL_BIT 4
#define SMU_THROTTLER_FPPT_BIT 5
#define SMU_THROTTLER_SPPT_BIT 6
#define SMU_THROTTLER_SPPT_APU_BIT 7
// Current Throttlers
#define SMU_THROTTLER_TDC_GFX_BIT 16
#define SMU_THROTTLER_TDC_SOC_BIT 17
#define SMU_THROTTLER_TDC_MEM_BIT 18
#define SMU_THROTTLER_TDC_VDD_BIT 19
#define SMU_THROTTLER_TDC_CVIP_BIT 20
#define SMU_THROTTLER_EDC_CPU_BIT 21
#define SMU_THROTTLER_EDC_GFX_BIT 22
#define SMU_THROTTLER_APCC_BIT 23
// Temperature
#define SMU_THROTTLER_TEMP_GPU_BIT 32
#define SMU_THROTTLER_TEMP_CORE_BIT 33
#define SMU_THROTTLER_TEMP_MEM_BIT 34
#define SMU_THROTTLER_TEMP_EDGE_BIT 35
#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
#define SMU_THROTTLER_TEMP_SOC_BIT 37
#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
#define SMU_THROTTLER_VRHOT0_BIT 44
#define SMU_THROTTLER_VRHOT1_BIT 45
#define SMU_THROTTLER_PROCHOT_CPU_BIT 46
#define SMU_THROTTLER_PROCHOT_GFX_BIT 47
// Other
#define SMU_THROTTLER_PPM_BIT 56
#define SMU_THROTTLER_FIT_BIT 57
struct smu_hw_power_state {
unsigned int magic;
};
struct smu_power_state;
enum smu_state_ui_label {
SMU_STATE_UI_LABEL_NONE,
SMU_STATE_UI_LABEL_BATTERY,
SMU_STATE_UI_TABEL_MIDDLE_LOW,
SMU_STATE_UI_LABEL_BALLANCED,
SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
SMU_STATE_UI_LABEL_PERFORMANCE,
SMU_STATE_UI_LABEL_BACO,
};
enum smu_state_classification_flag {
SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
};
struct smu_state_classification_block {
enum smu_state_ui_label ui_label;
enum smu_state_classification_flag flags;
int bios_index;
bool temporary_state;
bool to_be_deleted;
};
struct smu_state_pcie_block {
unsigned int lanes;
};
enum smu_refreshrate_source {
SMU_REFRESHRATE_SOURCE_EDID,
SMU_REFRESHRATE_SOURCE_EXPLICIT
};
struct smu_state_display_block {
bool disable_frame_modulation;
bool limit_refreshrate;
enum smu_refreshrate_source refreshrate_source;
int explicit_refreshrate;
int edid_refreshrate_index;
bool enable_vari_bright;
};
struct smu_state_memory_block {
bool dll_off;
uint8_t m3arb;
uint8_t unused[3];
};
struct smu_state_software_algorithm_block {
bool disable_load_balancing;
bool enable_sleep_for_timestamps;
};
struct smu_temperature_range {
int min;
int max;
int edge_emergency_max;
int hotspot_min;
int hotspot_crit_max;
int hotspot_emergency_max;
int mem_min;
int mem_crit_max;
int mem_emergency_max;
int software_shutdown_temp;
int software_shutdown_temp_offset;
};
struct smu_state_validation_block {
bool single_display_only;
bool disallow_on_dc;
uint8_t supported_power_levels;
};
struct smu_uvd_clocks {
uint32_t vclk;
uint32_t dclk;
};
/**
* Structure to hold a SMU Power State.
*/
enum smu_power_src_type {
SMU_POWER_SOURCE_AC,
SMU_POWER_SOURCE_DC,
SMU_POWER_SOURCE_COUNT,
};
enum smu_ppt_limit_type {
SMU_DEFAULT_PPT_LIMIT = 0,
SMU_FAST_PPT_LIMIT,
};
enum smu_ppt_limit_level {
SMU_PPT_LIMIT_MIN = -1,
SMU_PPT_LIMIT_CURRENT,
SMU_PPT_LIMIT_DEFAULT,
SMU_PPT_LIMIT_MAX,
};
enum smu_memory_pool_size {
SMU_MEMORY_POOL_SIZE_ZERO = 0,
SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
};
enum smu_clk_type {
SMU_GFXCLK,
SMU_VCLK,
SMU_DCLK,
SMU_VCLK1,
SMU_DCLK1,
SMU_ECLK,
SMU_SOCCLK,
SMU_UCLK,
SMU_DCEFCLK,
SMU_DISPCLK,
SMU_PIXCLK,
SMU_PHYCLK,
SMU_FCLK,
SMU_SCLK,
SMU_MCLK,
SMU_PCIE,
SMU_LCLK,
SMU_OD_CCLK,
SMU_OD_SCLK,
SMU_OD_MCLK,
SMU_OD_VDDC_CURVE,
SMU_OD_RANGE,
SMU_OD_VDDGFX_OFFSET,
SMU_OD_FAN_CURVE,
SMU_OD_ACOUSTIC_LIMIT,
SMU_OD_ACOUSTIC_TARGET,
SMU_OD_FAN_TARGET_TEMPERATURE,
SMU_OD_FAN_MINIMUM_PWM,
SMU_CLK_COUNT,
};
struct smu_user_dpm_profile {
uint32_t fan_mode;
uint32_t power_limit;
uint32_t fan_speed_pwm;
uint32_t fan_speed_rpm;
uint32_t flags;
uint32_t user_od;
/* user clock state information */
uint32_t clk_mask[SMU_CLK_COUNT];
uint32_t clk_dependency;
};
#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
do { \
tables[table_id].size = s; \
tables[table_id].align = a; \
tables[table_id].domain = d; \
} while (0)
struct smu_table {
uint64_t size;
uint32_t align;
uint8_t domain;
uint64_t mc_address;
void *cpu_addr;
struct amdgpu_bo *bo;
uint32_t version;
};
enum smu_perf_level_designation {
PERF_LEVEL_ACTIVITY,
PERF_LEVEL_POWER_CONTAINMENT,
};
struct smu_performance_level {
uint32_t core_clock;
uint32_t memory_clock;
uint32_t vddc;
uint32_t vddci;
uint32_t non_local_mem_freq;
uint32_t non_local_mem_width;
};
struct smu_clock_info {
uint32_t min_mem_clk;
uint32_t max_mem_clk;
uint32_t min_eng_clk;
uint32_t max_eng_clk;
uint32_t min_bus_bandwidth;
uint32_t max_bus_bandwidth;
};
struct smu_bios_boot_up_values {
uint32_t revision;
uint32_t gfxclk;
uint32_t uclk;
uint32_t socclk;
uint32_t dcefclk;
uint32_t eclk;
uint32_t vclk;
uint32_t dclk;
uint16_t vddc;
uint16_t vddci;
uint16_t mvddc;
uint16_t vdd_gfx;
uint8_t cooling_id;
uint32_t pp_table_id;
uint32_t format_revision;
uint32_t content_revision;
uint32_t fclk;
uint32_t lclk;
uint32_t firmware_caps;
};
enum smu_table_id {
SMU_TABLE_PPTABLE = 0,
SMU_TABLE_WATERMARKS,
SMU_TABLE_CUSTOM_DPM,
SMU_TABLE_DPMCLOCKS,
SMU_TABLE_AVFS,
SMU_TABLE_AVFS_PSM_DEBUG,
SMU_TABLE_AVFS_FUSE_OVERRIDE,
SMU_TABLE_PMSTATUSLOG,
SMU_TABLE_SMU_METRICS,
SMU_TABLE_DRIVER_SMU_CONFIG,
SMU_TABLE_ACTIVITY_MONITOR_COEFF,
SMU_TABLE_OVERDRIVE,
SMU_TABLE_I2C_COMMANDS,
SMU_TABLE_PACE,
SMU_TABLE_ECCINFO,
SMU_TABLE_COMBO_PPTABLE,
SMU_TABLE_WIFIBAND,
SMU_TABLE_COUNT,
};
#endif
extra/amdpci/headers/amdgpu_ucode.h
+634
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@@ -0,0 +1,634 @@
/*
* Copyright 2012 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMDGPU_UCODE_H__
#define __AMDGPU_UCODE_H__
// #include "amdgpu_socbb.h"
#define int32_t int
#define uint32_t unsigned int
#define int8_t signed char
#define uint8_t unsigned char
#define uint16_t unsigned short
#define int16_t short
#define uint64_t unsigned long long
#define bool _Bool
#define u32 unsigned int
struct common_firmware_header {
uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
uint32_t header_size_bytes; /* size of just the header in bytes */
uint16_t header_version_major; /* header version */
uint16_t header_version_minor; /* header version */
uint16_t ip_version_major; /* IP version */
uint16_t ip_version_minor; /* IP version */
uint32_t ucode_version;
uint32_t ucode_size_bytes; /* size of ucode in bytes */
uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
uint32_t crc32; /* crc32 checksum of the payload */
};
/* version_major=1, version_minor=0 */
struct mc_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t io_debug_size_bytes; /* size of debug array in dwords */
uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
};
/* version_major=1, version_minor=0 */
struct smc_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_start_addr;
};
/* version_major=2, version_minor=0 */
struct smc_firmware_header_v2_0 {
struct smc_firmware_header_v1_0 v1_0;
uint32_t ppt_offset_bytes; /* soft pptable offset */
uint32_t ppt_size_bytes; /* soft pptable size */
};
struct smc_soft_pptable_entry {
uint32_t id;
uint32_t ppt_offset_bytes;
uint32_t ppt_size_bytes;
};
/* version_major=2, version_minor=1 */
struct smc_firmware_header_v2_1 {
struct smc_firmware_header_v1_0 v1_0;
uint32_t pptable_count;
uint32_t pptable_entry_offset;
};
struct psp_fw_legacy_bin_desc {
uint32_t fw_version;
uint32_t offset_bytes;
uint32_t size_bytes;
};
/* version_major=1, version_minor=0 */
struct psp_firmware_header_v1_0 {
struct common_firmware_header header;
struct psp_fw_legacy_bin_desc sos;
};
/* version_major=1, version_minor=1 */
struct psp_firmware_header_v1_1 {
struct psp_firmware_header_v1_0 v1_0;
struct psp_fw_legacy_bin_desc toc;
struct psp_fw_legacy_bin_desc kdb;
};
/* version_major=1, version_minor=2 */
struct psp_firmware_header_v1_2 {
struct psp_firmware_header_v1_0 v1_0;
struct psp_fw_legacy_bin_desc res;
struct psp_fw_legacy_bin_desc kdb;
};
/* version_major=1, version_minor=3 */
struct psp_firmware_header_v1_3 {
struct psp_firmware_header_v1_1 v1_1;
struct psp_fw_legacy_bin_desc spl;
struct psp_fw_legacy_bin_desc rl;
struct psp_fw_legacy_bin_desc sys_drv_aux;
struct psp_fw_legacy_bin_desc sos_aux;
};
struct psp_fw_bin_desc {
uint32_t fw_type;
uint32_t fw_version;
uint32_t offset_bytes;
uint32_t size_bytes;
};
enum psp_fw_type {
PSP_FW_TYPE_UNKOWN,
PSP_FW_TYPE_PSP_SOS,
PSP_FW_TYPE_PSP_SYS_DRV,
PSP_FW_TYPE_PSP_KDB,
PSP_FW_TYPE_PSP_TOC,
PSP_FW_TYPE_PSP_SPL,
PSP_FW_TYPE_PSP_RL,
PSP_FW_TYPE_PSP_SOC_DRV,
PSP_FW_TYPE_PSP_INTF_DRV,
PSP_FW_TYPE_PSP_DBG_DRV,
PSP_FW_TYPE_PSP_RAS_DRV,
PSP_FW_TYPE_PSP_IPKEYMGR_DRV,
PSP_FW_TYPE_MAX_INDEX,
};
/* version_major=2, version_minor=0 */
struct psp_firmware_header_v2_0 {
struct common_firmware_header header;
uint32_t psp_fw_bin_count;
struct psp_fw_bin_desc psp_fw_bin[1];
};
/* version_major=2, version_minor=1 */
struct psp_firmware_header_v2_1 {
struct common_firmware_header header;
uint32_t psp_fw_bin_count;
uint32_t psp_aux_fw_bin_index;
struct psp_fw_bin_desc psp_fw_bin[1];
};
/* version_major=1, version_minor=0 */
struct ta_firmware_header_v1_0 {
struct common_firmware_header header;
struct psp_fw_legacy_bin_desc xgmi;
struct psp_fw_legacy_bin_desc ras;
struct psp_fw_legacy_bin_desc hdcp;
struct psp_fw_legacy_bin_desc dtm;
struct psp_fw_legacy_bin_desc securedisplay;
};
enum ta_fw_type {
TA_FW_TYPE_UNKOWN,
TA_FW_TYPE_PSP_ASD,
TA_FW_TYPE_PSP_XGMI,
TA_FW_TYPE_PSP_RAS,
TA_FW_TYPE_PSP_HDCP,
TA_FW_TYPE_PSP_DTM,
TA_FW_TYPE_PSP_RAP,
TA_FW_TYPE_PSP_SECUREDISPLAY,
TA_FW_TYPE_MAX_INDEX,
};
/* version_major=2, version_minor=0 */
struct ta_firmware_header_v2_0 {
struct common_firmware_header header;
uint32_t ta_fw_bin_count;
struct psp_fw_bin_desc ta_fw_bin[1];
};
/* version_major=1, version_minor=0 */
struct gfx_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t jt_offset; /* jt location */
uint32_t jt_size; /* size of jt */
};
/* version_major=2, version_minor=0 */
struct gfx_firmware_header_v2_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t ucode_size_bytes;
uint32_t ucode_offset_bytes;
uint32_t data_size_bytes;
uint32_t data_offset_bytes;
uint32_t ucode_start_addr_lo;
uint32_t ucode_start_addr_hi;
};
/* version_major=1, version_minor=0 */
struct mes_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t mes_ucode_version;
uint32_t mes_ucode_size_bytes;
uint32_t mes_ucode_offset_bytes;
uint32_t mes_ucode_data_version;
uint32_t mes_ucode_data_size_bytes;
uint32_t mes_ucode_data_offset_bytes;
uint32_t mes_uc_start_addr_lo;
uint32_t mes_uc_start_addr_hi;
uint32_t mes_data_start_addr_lo;
uint32_t mes_data_start_addr_hi;
};
/* version_major=1, version_minor=0 */
struct rlc_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t save_and_restore_offset;
uint32_t clear_state_descriptor_offset;
uint32_t avail_scratch_ram_locations;
uint32_t master_pkt_description_offset;
};
/* version_major=2, version_minor=0 */
struct rlc_firmware_header_v2_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t jt_offset; /* jt location */
uint32_t jt_size; /* size of jt */
uint32_t save_and_restore_offset;
uint32_t clear_state_descriptor_offset;
uint32_t avail_scratch_ram_locations;
uint32_t reg_restore_list_size;
uint32_t reg_list_format_start;
uint32_t reg_list_format_separate_start;
uint32_t starting_offsets_start;
uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
};
/* version_major=2, version_minor=1 */
struct rlc_firmware_header_v2_1 {
struct rlc_firmware_header_v2_0 v2_0;
uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
uint32_t save_restore_list_cntl_ucode_ver;
uint32_t save_restore_list_cntl_feature_ver;
uint32_t save_restore_list_cntl_size_bytes;
uint32_t save_restore_list_cntl_offset_bytes;
uint32_t save_restore_list_gpm_ucode_ver;
uint32_t save_restore_list_gpm_feature_ver;
uint32_t save_restore_list_gpm_size_bytes;
uint32_t save_restore_list_gpm_offset_bytes;
uint32_t save_restore_list_srm_ucode_ver;
uint32_t save_restore_list_srm_feature_ver;
uint32_t save_restore_list_srm_size_bytes;
uint32_t save_restore_list_srm_offset_bytes;
};
/* version_major=2, version_minor=2 */
struct rlc_firmware_header_v2_2 {
struct rlc_firmware_header_v2_1 v2_1;
uint32_t rlc_iram_ucode_size_bytes;
uint32_t rlc_iram_ucode_offset_bytes;
uint32_t rlc_dram_ucode_size_bytes;
uint32_t rlc_dram_ucode_offset_bytes;
};
/* version_major=2, version_minor=3 */
struct rlc_firmware_header_v2_3 {
struct rlc_firmware_header_v2_2 v2_2;
uint32_t rlcp_ucode_version;
uint32_t rlcp_ucode_feature_version;
uint32_t rlcp_ucode_size_bytes;
uint32_t rlcp_ucode_offset_bytes;
uint32_t rlcv_ucode_version;
uint32_t rlcv_ucode_feature_version;
uint32_t rlcv_ucode_size_bytes;
uint32_t rlcv_ucode_offset_bytes;
};
/* version_major=2, version_minor=4 */
struct rlc_firmware_header_v2_4 {
struct rlc_firmware_header_v2_3 v2_3;
uint32_t global_tap_delays_ucode_size_bytes;
uint32_t global_tap_delays_ucode_offset_bytes;
uint32_t se0_tap_delays_ucode_size_bytes;
uint32_t se0_tap_delays_ucode_offset_bytes;
uint32_t se1_tap_delays_ucode_size_bytes;
uint32_t se1_tap_delays_ucode_offset_bytes;
uint32_t se2_tap_delays_ucode_size_bytes;
uint32_t se2_tap_delays_ucode_offset_bytes;
uint32_t se3_tap_delays_ucode_size_bytes;
uint32_t se3_tap_delays_ucode_offset_bytes;
};
/* version_major=1, version_minor=0 */
struct sdma_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t ucode_change_version;
uint32_t jt_offset; /* jt location */
uint32_t jt_size; /* size of jt */
};
/* version_major=1, version_minor=1 */
struct sdma_firmware_header_v1_1 {
struct sdma_firmware_header_v1_0 v1_0;
uint32_t digest_size;
};
/* version_major=2, version_minor=0 */
struct sdma_firmware_header_v2_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
uint32_t ctx_jt_offset; /* context thread jt location */
uint32_t ctx_jt_size; /* context thread size of jt */
uint32_t ctl_ucode_offset;
uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
uint32_t ctl_jt_offset; /* control thread jt location */
uint32_t ctl_jt_size; /* control thread size of jt */
};
/* version_major=1, version_minor=0 */
struct vpe_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
uint32_t ctx_jt_offset; /* context thread jt location */
uint32_t ctx_jt_size; /* context thread size of jt */
uint32_t ctl_ucode_offset;
uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
uint32_t ctl_jt_offset; /* control thread jt location */
uint32_t ctl_jt_size; /* control thread size of jt */
};
/* version_major=1, version_minor=0 */
struct umsch_mm_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t umsch_mm_ucode_version;
uint32_t umsch_mm_ucode_size_bytes;
uint32_t umsch_mm_ucode_offset_bytes;
uint32_t umsch_mm_ucode_data_version;
uint32_t umsch_mm_ucode_data_size_bytes;
uint32_t umsch_mm_ucode_data_offset_bytes;
uint32_t umsch_mm_irq_start_addr_lo;
uint32_t umsch_mm_irq_start_addr_hi;
uint32_t umsch_mm_uc_start_addr_lo;
uint32_t umsch_mm_uc_start_addr_hi;
uint32_t umsch_mm_data_start_addr_lo;
uint32_t umsch_mm_data_start_addr_hi;
};
/* version_major=3, version_minor=0 */
struct sdma_firmware_header_v3_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
uint32_t ucode_offset_bytes;
uint32_t ucode_size_bytes;
};
/* gpu info payload */
struct gpu_info_firmware_v1_0 {
uint32_t gc_num_se;
uint32_t gc_num_cu_per_sh;
uint32_t gc_num_sh_per_se;
uint32_t gc_num_rb_per_se;
uint32_t gc_num_tccs;
uint32_t gc_num_gprs;
uint32_t gc_num_max_gs_thds;
uint32_t gc_gs_table_depth;
uint32_t gc_gsprim_buff_depth;
uint32_t gc_parameter_cache_depth;
uint32_t gc_double_offchip_lds_buffer;
uint32_t gc_wave_size;
uint32_t gc_max_waves_per_simd;
uint32_t gc_max_scratch_slots_per_cu;
uint32_t gc_lds_size;
};
struct gpu_info_firmware_v1_1 {
struct gpu_info_firmware_v1_0 v1_0;
uint32_t num_sc_per_sh;
uint32_t num_packer_per_sc;
};
/* gpu info payload
* version_major=1, version_minor=1 */
// struct gpu_info_firmware_v1_2 {
// struct gpu_info_firmware_v1_1 v1_1;
// struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
// };
/* version_major=1, version_minor=0 */
struct gpu_info_firmware_header_v1_0 {
struct common_firmware_header header;
uint16_t version_major; /* version */
uint16_t version_minor; /* version */
};
/* version_major=1, version_minor=0 */
struct dmcu_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
};
/* version_major=1, version_minor=0 */
struct dmcub_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t inst_const_bytes; /* size of instruction region, in bytes */
uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
};
/* version_major=1, version_minor=0 */
struct imu_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t imu_iram_ucode_size_bytes;
uint32_t imu_iram_ucode_offset_bytes;
uint32_t imu_dram_ucode_size_bytes;
uint32_t imu_dram_ucode_offset_bytes;
};
/* header is fixed size */
union amdgpu_firmware_header {
struct common_firmware_header common;
struct mc_firmware_header_v1_0 mc;
struct smc_firmware_header_v1_0 smc;
struct smc_firmware_header_v2_0 smc_v2_0;
struct psp_firmware_header_v1_0 psp;
struct psp_firmware_header_v1_1 psp_v1_1;
struct psp_firmware_header_v1_3 psp_v1_3;
struct psp_firmware_header_v2_0 psp_v2_0;
struct psp_firmware_header_v2_0 psp_v2_1;
struct ta_firmware_header_v1_0 ta;
struct ta_firmware_header_v2_0 ta_v2_0;
struct gfx_firmware_header_v1_0 gfx;
struct gfx_firmware_header_v2_0 gfx_v2_0;
struct rlc_firmware_header_v1_0 rlc;
struct rlc_firmware_header_v2_0 rlc_v2_0;
struct rlc_firmware_header_v2_1 rlc_v2_1;
struct rlc_firmware_header_v2_2 rlc_v2_2;
struct rlc_firmware_header_v2_3 rlc_v2_3;
struct rlc_firmware_header_v2_4 rlc_v2_4;
struct sdma_firmware_header_v1_0 sdma;
struct sdma_firmware_header_v1_1 sdma_v1_1;
struct sdma_firmware_header_v2_0 sdma_v2_0;
struct sdma_firmware_header_v3_0 sdma_v3_0;
struct gpu_info_firmware_header_v1_0 gpu_info;
struct dmcu_firmware_header_v1_0 dmcu;
struct dmcub_firmware_header_v1_0 dmcub;
struct imu_firmware_header_v1_0 imu;
uint8_t raw[0x100];
};
#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2)
/*
* fw loading support
*/
enum AMDGPU_UCODE_ID {
AMDGPU_UCODE_ID_CAP = 0,
AMDGPU_UCODE_ID_SDMA0,
AMDGPU_UCODE_ID_SDMA1,
AMDGPU_UCODE_ID_SDMA2,
AMDGPU_UCODE_ID_SDMA3,
AMDGPU_UCODE_ID_SDMA4,
AMDGPU_UCODE_ID_SDMA5,
AMDGPU_UCODE_ID_SDMA6,
AMDGPU_UCODE_ID_SDMA7,
AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
AMDGPU_UCODE_ID_SDMA_RS64,
AMDGPU_UCODE_ID_CP_CE,
AMDGPU_UCODE_ID_CP_PFP,
AMDGPU_UCODE_ID_CP_ME,
AMDGPU_UCODE_ID_CP_RS64_PFP,
AMDGPU_UCODE_ID_CP_RS64_ME,
AMDGPU_UCODE_ID_CP_RS64_MEC,
AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
AMDGPU_UCODE_ID_CP_MEC1,
AMDGPU_UCODE_ID_CP_MEC1_JT,
AMDGPU_UCODE_ID_CP_MEC2,
AMDGPU_UCODE_ID_CP_MEC2_JT,
AMDGPU_UCODE_ID_CP_MES,
AMDGPU_UCODE_ID_CP_MES_DATA,
AMDGPU_UCODE_ID_CP_MES1,
AMDGPU_UCODE_ID_CP_MES1_DATA,
AMDGPU_UCODE_ID_IMU_I,
AMDGPU_UCODE_ID_IMU_D,
AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
AMDGPU_UCODE_ID_RLC_IRAM,
AMDGPU_UCODE_ID_RLC_DRAM,
AMDGPU_UCODE_ID_RLC_P,
AMDGPU_UCODE_ID_RLC_V,
AMDGPU_UCODE_ID_RLC_G,
AMDGPU_UCODE_ID_STORAGE,
AMDGPU_UCODE_ID_SMC,
AMDGPU_UCODE_ID_PPTABLE,
AMDGPU_UCODE_ID_UVD,
AMDGPU_UCODE_ID_UVD1,
AMDGPU_UCODE_ID_VCE,
AMDGPU_UCODE_ID_VCN,
AMDGPU_UCODE_ID_VCN1,
AMDGPU_UCODE_ID_DMCU_ERAM,
AMDGPU_UCODE_ID_DMCU_INTV,
AMDGPU_UCODE_ID_VCN0_RAM,
AMDGPU_UCODE_ID_VCN1_RAM,
AMDGPU_UCODE_ID_DMCUB,
AMDGPU_UCODE_ID_VPE_CTX,
AMDGPU_UCODE_ID_VPE_CTL,
AMDGPU_UCODE_ID_VPE,
AMDGPU_UCODE_ID_UMSCH_MM_UCODE,
AMDGPU_UCODE_ID_UMSCH_MM_DATA,
AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
AMDGPU_UCODE_ID_P2S_TABLE,
AMDGPU_UCODE_ID_JPEG_RAM,
AMDGPU_UCODE_ID_ISP,
AMDGPU_UCODE_ID_MAXIMUM,
};
/* engine firmware status */
enum AMDGPU_UCODE_STATUS {
AMDGPU_UCODE_STATUS_INVALID,
AMDGPU_UCODE_STATUS_NOT_LOADED,
AMDGPU_UCODE_STATUS_LOADED,
};
enum amdgpu_firmware_load_type {
AMDGPU_FW_LOAD_DIRECT = 0,
AMDGPU_FW_LOAD_PSP,
AMDGPU_FW_LOAD_SMU,
AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
};
/* conform to smu_ucode_xfer_cz.h */
#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
#define AMDGPU_CPME_UCODE_LOADED 0x00000010
#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
/* amdgpu firmware info */
struct amdgpu_firmware_info {
/* ucode ID */
enum AMDGPU_UCODE_ID ucode_id;
/* request_firmware */
const struct firmware *fw;
/* starting mc address */
uint64_t mc_addr;
/* kernel linear address */
void *kaddr;
/* ucode_size_bytes */
uint32_t ucode_size;
/* starting tmr mc address */
uint32_t tmr_mc_addr_lo;
uint32_t tmr_mc_addr_hi;
};
// struct amdgpu_firmware {
// struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
// enum amdgpu_firmware_load_type load_type;
// struct amdgpu_bo *fw_buf;
// unsigned int fw_size;
// unsigned int max_ucodes;
// /* firmwares are loaded by psp instead of smu from vega10 */
// const struct amdgpu_psp_funcs *funcs;
// struct amdgpu_bo *rbuf;
// struct mutex mutex;
// /* gpu info firmware data pointer */
// const struct firmware *gpu_info_fw;
// void *fw_buf_ptr;
// uint64_t fw_buf_mc;
// };
// void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
// void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
// int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
// const char *fw_name);
// void amdgpu_ucode_release(const struct firmware **fw);
// bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
// uint16_t hdr_major, uint16_t hdr_minor);
// int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
// int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
// int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
// void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
// void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
// enum amdgpu_firmware_load_type
// amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
// const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
// void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
#endif
extra/amdpci/headers/amdgpu_vm.h
+665
View File
@@ -0,0 +1,665 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Christian König
*/
#ifndef __AMDGPU_VM_H__
#define __AMDGPU_VM_H__
// #include <linux/idr.h>
// #include <linux/kfifo.h>
// #include <linux/rbtree.h>
// #include <drm/gpu_scheduler.h>
// #include <drm/drm_file.h>
// #include <drm/ttm/ttm_bo.h>
// #include <linux/sched/mm.h>
// #include "amdgpu_sync.h"
// #include "amdgpu_ring.h"
// #include "amdgpu_ids.h"
// struct drm_exec;
// struct amdgpu_bo_va;
// struct amdgpu_job;
// struct amdgpu_bo_list_entry;
// struct amdgpu_bo_vm;
// struct amdgpu_mem_stats;
/*
* GPUVM handling
*/
/* Maximum number of PTEs the hardware can write with one command */
#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
/* number of entries in page table */
#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
#define AMDGPU_PTE_VALID (1ULL << 0)
#define AMDGPU_PTE_SYSTEM (1ULL << 1)
#define AMDGPU_PTE_SNOOPED (1ULL << 2)
/* RV+ */
#define AMDGPU_PTE_TMZ (1ULL << 3)
/* VI only */
#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
#define AMDGPU_PTE_READABLE (1ULL << 5)
#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
/* TILED for VEGA10, reserved for older ASICs */
#define AMDGPU_PTE_PRT (1ULL << 51)
/* PDE is handled as PTE for VEGA10 */
#define AMDGPU_PDE_PTE (1ULL << 54)
#define AMDGPU_PTE_LOG (1ULL << 55)
/* PTE is handled as PDE for VEGA10 (Translate Further) */
#define AMDGPU_PTE_TF (1ULL << 56)
/* MALL noalloc for sienna_cichlid, reserved for older ASICs */
#define AMDGPU_PTE_NOALLOC (1ULL << 58)
/* PDE Block Fragment Size for VEGA10 */
#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
/* Flag combination to set no-retry with TF disabled */
#define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \
AMDGPU_PTE_TF)
/* Flag combination to set no-retry with TF enabled */
#define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \
AMDGPU_PTE_PRT)
/* For GFX9 */
#define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57)
#define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL)
#define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \
(((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \
AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
#define AMDGPU_MTYPE_NC 0
#define AMDGPU_MTYPE_CC 2
#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
| AMDGPU_PTE_SNOOPED \
| AMDGPU_PTE_EXECUTABLE \
| AMDGPU_PTE_READABLE \
| AMDGPU_PTE_WRITEABLE \
| AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
/* gfx10 */
#define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48)
#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL)
#define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \
(((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \
AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype))
/* gfx12 */
#define AMDGPU_PTE_PRT_GFX12 (1ULL << 56)
#define AMDGPU_PTE_PRT_FLAG(adev) \
((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)
#define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54)
#define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL)
#define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \
(((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \
AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype))
#define AMDGPU_PTE_IS_PTE (1ULL << 63)
/* PDE Block Fragment Size for gfx v12 */
#define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58)
#define AMDGPU_PDE_BFS_FLAG(adev, a) \
((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a))
/* PDE is handled as PTE for gfx v12 */
#define AMDGPU_PDE_PTE_GFX12 (1ULL << 63)
#define AMDGPU_PDE_PTE_FLAG(adev) \
((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE)
/* How to program VM fault handling */
#define AMDGPU_VM_FAULT_STOP_NEVER 0
#define AMDGPU_VM_FAULT_STOP_FIRST 1
#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
/* How much VRAM be reserved for page tables */
#define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
/*
* max number of VMHUB
* layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1
*/
#define AMDGPU_MAX_VMHUBS 13
#define AMDGPU_GFXHUB_START 0
#define AMDGPU_MMHUB0_START 8
#define AMDGPU_MMHUB1_START 12
#define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x))
#define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x))
#define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x))
#define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START)
#define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START)
#define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS)
/* Reserve space at top/bottom of address space for kernel use */
#define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20)
#define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
<< AMDGPU_GPU_PAGE_SHIFT) \
- AMDGPU_VA_RESERVED_CSA_SIZE)
#define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20)
#define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \
- AMDGPU_VA_RESERVED_SEQ64_SIZE)
#define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12)
#define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \
- AMDGPU_VA_RESERVED_TRAP_SIZE)
#define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16)
#define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \
AMDGPU_VA_RESERVED_SEQ64_SIZE + \
AMDGPU_VA_RESERVED_CSA_SIZE)
/* See vm_update_mode */
#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
/* VMPT level enumerate, and the hiberachy is:
* PDB2->PDB1->PDB0->PTB
*/
enum amdgpu_vm_level {
AMDGPU_VM_PDB2,
AMDGPU_VM_PDB1,
AMDGPU_VM_PDB0,
AMDGPU_VM_PTB
};
// /* base structure for tracking BO usage in a VM */
// struct amdgpu_vm_bo_base {
// /* constant after initialization */
// struct amdgpu_vm *vm;
// struct amdgpu_bo *bo;
// /* protected by bo being reserved */
// struct amdgpu_vm_bo_base *next;
// /* protected by spinlock */
// struct list_head vm_status;
// /* protected by the BO being reserved */
// bool moved;
// };
// /* provided by hw blocks that can write ptes, e.g., sdma */
// struct amdgpu_vm_pte_funcs {
// /* number of dw to reserve per operation */
// unsigned copy_pte_num_dw;
// /* copy pte entries from GART */
// void (*copy_pte)(struct amdgpu_ib *ib,
// uint64_t pe, uint64_t src,
// unsigned count);
// /* write pte one entry at a time with addr mapping */
// void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
// uint64_t value, unsigned count,
// uint32_t incr);
// /* for linear pte/pde updates without addr mapping */
// void (*set_pte_pde)(struct amdgpu_ib *ib,
// uint64_t pe,
// uint64_t addr, unsigned count,
// uint32_t incr, uint64_t flags);
// };
// struct amdgpu_task_info {
// char process_name[TASK_COMM_LEN];
// char task_name[TASK_COMM_LEN];
// pid_t pid;
// pid_t tgid;
// struct kref refcount;
// };
// /**
// * struct amdgpu_vm_update_params
// *
// * Encapsulate some VM table update parameters to reduce
// * the number of function parameters
// *
// */
// struct amdgpu_vm_update_params {
// /**
// * @adev: amdgpu device we do this update for
// */
// struct amdgpu_device *adev;
// /**
// * @vm: optional amdgpu_vm we do this update for
// */
// struct amdgpu_vm *vm;
// /**
// * @immediate: if changes should be made immediately
// */
// bool immediate;
// /**
// * @unlocked: true if the root BO is not locked
// */
// bool unlocked;
// /**
// * @pages_addr:
// *
// * DMA addresses to use for mapping
// */
// dma_addr_t *pages_addr;
// /**
// * @job: job to used for hw submission
// */
// struct amdgpu_job *job;
// /**
// * @num_dw_left: number of dw left for the IB
// */
// unsigned int num_dw_left;
// /**
// * @needs_flush: true whenever we need to invalidate the TLB
// */
// bool needs_flush;
// /**
// * @allow_override: true for memory that is not uncached: allows MTYPE
// * to be overridden for NUMA local memory.
// */
// bool allow_override;
// /**
// * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush
// */
// struct list_head tlb_flush_waitlist;
// };
// struct amdgpu_vm_update_funcs {
// int (*map_table)(struct amdgpu_bo_vm *bo);
// int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
// enum amdgpu_sync_mode sync_mode);
// int (*update)(struct amdgpu_vm_update_params *p,
// struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
// unsigned count, uint32_t incr, uint64_t flags);
// int (*commit)(struct amdgpu_vm_update_params *p,
// struct dma_fence **fence);
// };
// struct amdgpu_vm_fault_info {
// /* fault address */
// uint64_t addr;
// /* fault status register */
// uint32_t status;
// /* which vmhub? gfxhub, mmhub, etc. */
// unsigned int vmhub;
// };
// struct amdgpu_vm {
// /* tree of virtual addresses mapped */
// #ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED
// struct rb_root va;
// #else
// struct rb_root_cached va;
// #endif
// /* Lock to prevent eviction while we are updating page tables
// * use vm_eviction_lock/unlock(vm)
// */
// struct mutex eviction_lock;
// bool evicting;
// unsigned int saved_flags;
// /* Lock to protect vm_bo add/del/move on all lists of vm */
// spinlock_t status_lock;
// /* Per-VM and PT BOs who needs a validation */
// struct list_head evicted;
// /* BOs for user mode queues that need a validation */
// struct list_head evicted_user;
// /* PT BOs which relocated and their parent need an update */
// struct list_head relocated;
// /* per VM BOs moved, but not yet updated in the PT */
// struct list_head moved;
// /* All BOs of this VM not currently in the state machine */
// struct list_head idle;
// /* regular invalidated BOs, but not yet updated in the PT */
// struct list_head invalidated;
// /* BO mappings freed, but not yet updated in the PT */
// struct list_head freed;
// /* BOs which are invalidated, has been updated in the PTs */
// struct list_head done;
// /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
// struct list_head pt_freed;
// struct work_struct pt_free_work;
// /* contains the page directory */
// struct amdgpu_vm_bo_base root;
// struct dma_fence *last_update;
// /* Scheduler entities for page table updates */
// struct drm_sched_entity immediate;
// struct drm_sched_entity delayed;
// /* Last finished delayed update */
// atomic64_t tlb_seq;
// struct dma_fence *last_tlb_flush;
// atomic64_t kfd_last_flushed_seq;
// uint64_t tlb_fence_context;
// /* How many times we had to re-generate the page tables */
// uint64_t generation;
// /* Last unlocked submission to the scheduler entities */
// struct dma_fence *last_unlocked;
// unsigned int pasid;
// bool reserved_vmid[AMDGPU_MAX_VMHUBS];
// /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
// bool use_cpu_for_update;
// /* Functions to use for VM table updates */
// const struct amdgpu_vm_update_funcs *update_funcs;
// /* Up to 128 pending retry page faults */
// DECLARE_KFIFO(faults, u64, 128);
// /* Points to the KFD process VM info */
// struct amdkfd_process_info *process_info;
// /* List node in amdkfd_process_info.vm_list_head */
// struct list_head vm_list_node;
// /* Valid while the PD is reserved or fenced */
// uint64_t pd_phys_addr;
// /* Some basic info about the task */
// struct amdgpu_task_info *task_info;
// /* Store positions of group of BOs */
// struct ttm_lru_bulk_move lru_bulk_move;
// /* Flag to indicate if VM is used for compute */
// bool is_compute_context;
// /* Memory partition number, -1 means any partition */
// int8_t mem_id;
// /* cached fault info */
// struct amdgpu_vm_fault_info fault_info;
// };
// struct amdgpu_vm_manager {
// /* Handling of VMIDs */
// struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
// unsigned int first_kfd_vmid;
// bool concurrent_flush;
// /* Handling of VM fences */
// u64 fence_context;
// unsigned seqno[AMDGPU_MAX_RINGS];
// uint64_t max_pfn;
// uint32_t num_level;
// uint32_t block_size;
// uint32_t fragment_size;
// enum amdgpu_vm_level root_level;
// /* vram base address for page table entry */
// u64 vram_base_offset;
// /* vm pte handling */
// const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
// struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
// unsigned vm_pte_num_scheds;
// struct amdgpu_ring *page_fault;
// /* partial resident texture handling */
// spinlock_t prt_lock;
// atomic_t num_prt_users;
// /* controls how VM page tables are updated for Graphics and Compute.
// * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
// * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
// */
// int vm_update_mode;
// /* PASID to VM mapping, will be used in interrupt context to
// * look up VM of a page fault
// */
// #ifdef HAVE_STRUCT_XARRAY
// struct xarray pasids;
// #else
// struct idr pasid_idr;
// spinlock_t pasid_lock;
// #endif
// /* Global registration of recent page fault information */
// struct amdgpu_vm_fault_info fault_info;
// };
// struct amdgpu_bo_va_mapping;
// #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
// #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
// #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
// extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
// extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
// void amdgpu_vm_manager_init(struct amdgpu_device *adev);
// void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
// int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
// u32 pasid);
// long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
// int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id);
// int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
// void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
// void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
// int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
// unsigned int num_fences);
// bool amdgpu_vm_ready(struct amdgpu_vm *vm);
// uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);
// int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
// struct ww_acquire_ctx *ticket,
// int (*callback)(void *p, struct amdgpu_bo *bo),
// void *param);
// int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
// int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
// struct amdgpu_vm *vm, bool immediate);
// int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
// struct amdgpu_vm *vm,
// struct dma_fence **fence);
// int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
// struct amdgpu_vm *vm,
// struct ww_acquire_ctx *ticket);
// int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
// struct amdgpu_vm *vm,
// uint32_t flush_type,
// uint32_t xcc_mask);
// void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
// struct amdgpu_vm *vm, struct amdgpu_bo *bo);
// int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
// bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
// struct dma_resv *resv, uint64_t start, uint64_t last,
// uint64_t flags, uint64_t offset, uint64_t vram_base,
// struct ttm_resource *res, dma_addr_t *pages_addr,
// struct dma_fence **fence);
// int amdgpu_vm_bo_update(struct amdgpu_device *adev,
// struct amdgpu_bo_va *bo_va,
// bool clear);
// bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
// void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
// struct amdgpu_bo *bo, bool evicted);
// uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
// struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
// struct amdgpu_bo *bo);
// struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
// struct amdgpu_vm *vm,
// struct amdgpu_bo *bo);
// int amdgpu_vm_bo_map(struct amdgpu_device *adev,
// struct amdgpu_bo_va *bo_va,
// uint64_t addr, uint64_t offset,
// uint64_t size, uint64_t flags);
// int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
// struct amdgpu_bo_va *bo_va,
// uint64_t addr, uint64_t offset,
// uint64_t size, uint64_t flags);
// int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
// struct amdgpu_bo_va *bo_va,
// uint64_t addr);
// int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
// struct amdgpu_vm *vm,
// uint64_t saddr, uint64_t size);
// struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
// uint64_t addr);
// void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
// void amdgpu_vm_bo_del(struct amdgpu_device *adev,
// struct amdgpu_bo_va *bo_va);
// void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
// uint32_t fragment_size_default, unsigned max_level,
// unsigned max_bits);
// int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
// bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
// struct amdgpu_job *job);
// void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
// struct amdgpu_task_info *
// amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid);
// struct amdgpu_task_info *
// amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm);
// void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info);
// bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
// u32 vmid, u32 node_id, uint64_t addr,
// bool write_fault);
// void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
// void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
// struct amdgpu_vm *vm);
// void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
// struct amdgpu_mem_stats *stats);
// int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
// struct amdgpu_bo_vm *vmbo, bool immediate);
// int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
// int level, bool immediate, struct amdgpu_bo_vm **vmbo,
// int32_t xcp_id);
// void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm);
// int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,
// struct amdgpu_vm_bo_base *entry);
// int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
// uint64_t start, uint64_t end,
// uint64_t dst, uint64_t flags);
// void amdgpu_vm_pt_free_work(struct work_struct *work);
// void amdgpu_vm_pt_free_list(struct amdgpu_device *adev,
// struct amdgpu_vm_update_params *params);
// #if defined(CONFIG_DEBUG_FS)
// void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
// #endif
// int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm);
// bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo);
// /**
// * amdgpu_vm_tlb_seq - return tlb flush sequence number
// * @vm: the amdgpu_vm structure to query
// *
// * Returns the tlb flush sequence number which indicates that the VM TLBs needs
// * to be invalidated whenever the sequence number change.
// */
// static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
// {
// unsigned long flags;
// spinlock_t *lock;
// /*
// * Workaround to stop racing between the fence signaling and handling
// * the cb. The lock is static after initially setting it up, just make
// * sure that the dma_fence structure isn't freed up.
// */
// rcu_read_lock();
// lock = vm->last_tlb_flush->lock;
// rcu_read_unlock();
// spin_lock_irqsave(lock, flags);
// spin_unlock_irqrestore(lock, flags);
// return atomic64_read(&vm->tlb_seq);
// }
// /*
// * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
// * happens while holding this lock anywhere to prevent deadlocks when
// * an MMU notifier runs in reclaim-FS context.
// */
// static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
// {
// mutex_lock(&vm->eviction_lock);
// vm->saved_flags = memalloc_noreclaim_save();
// }
// static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
// {
// if (mutex_trylock(&vm->eviction_lock)) {
// vm->saved_flags = memalloc_noreclaim_save();
// return true;
// }
// return false;
// }
// static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
// {
// memalloc_noreclaim_restore(vm->saved_flags);
// mutex_unlock(&vm->eviction_lock);
// }
// void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
// unsigned int pasid,
// uint64_t addr,
// uint32_t status,
// unsigned int vmhub);
// void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
// struct amdgpu_vm *vm,
// struct dma_fence **fence);
#endif
extra/amdpci/headers/discovery.h
+567
View File
@@ -0,0 +1,567 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _DISCOVERY_H_
#define _DISCOVERY_H_
#define uint32_t unsigned int
#define uint8_t unsigned char
#define uint16_t unsigned short
#define uint64_t unsigned long long
#define u32 unsigned int
#define u8 unsigned char
#define u16 unsigned short
#define u64 unsigned long long
#define bool unsigned char
#define PSP_HEADER_SIZE 256
#define BINARY_SIGNATURE 0x28211407
#define DISCOVERY_TABLE_SIGNATURE 0x53445049
#define GC_TABLE_ID 0x4347
#define HARVEST_TABLE_SIGNATURE 0x56524148
#define VCN_INFO_TABLE_ID 0x004E4356
#define MALL_INFO_TABLE_ID 0x4C4C414D
#define NPS_INFO_TABLE_ID 0x0053504E
typedef enum {
IP_DISCOVERY = 0,
GC,
HARVEST_INFO,
VCN_INFO,
MALL_INFO,
NPS_INFO,
TOTAL_TABLES = 6
} table;
#pragma pack(1)
typedef struct table_info
{
uint16_t offset; /* Byte offset */
uint16_t checksum; /* Byte sum of the table */
uint16_t size; /* Table size */
uint16_t padding;
} table_info;
typedef struct binary_header
{
/* psp structure should go at the top of this structure */
uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
uint16_t version_major;
uint16_t version_minor;
uint16_t binary_checksum; /* Byte sum of the binary after this field */
uint16_t binary_size; /* Binary Size*/
table_info table_list[TOTAL_TABLES];
} binary_header;
typedef struct die_info
{
uint16_t die_id;
uint16_t die_offset; /* Points to the corresponding die_header structure */
} die_info;
typedef struct ip_discovery_header
{
uint32_t signature; /* Table Signature */
uint16_t version; /* Table Version */
uint16_t size; /* Table Size */
uint32_t id; /* Table ID */
uint16_t num_dies; /* Number of Dies */
die_info die_info[16]; /* list die information for up to 16 dies */
union {
uint16_t padding[1]; /* version <= 3 */
struct { /* version == 4 */
uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */
uint8_t reserved : 7;
uint8_t reserved2;
};
};
} ip_discovery_header;
typedef struct ip
{
uint16_t hw_id; /* Hardware ID */
uint8_t number_instance; /* instance of the IP */
uint8_t num_base_address; /* Number of Base Addresses */
uint8_t major; /* HCID Major */
uint8_t minor; /* HCID Minor */
uint8_t revision; /* HCID Revision */
#if defined(__BIG_ENDIAN)
uint8_t reserved : 4; /* Placeholder field */
uint8_t harvest : 4; /* Harvest */
#else
uint8_t harvest : 4; /* Harvest */
uint8_t reserved : 4; /* Placeholder field */
#endif
uint32_t base_address[1]; /* variable number of Addresses */
} ip;
typedef struct ip_v3
{
uint16_t hw_id; /* Hardware ID */
uint8_t instance_number; /* Instance number for the IP */
uint8_t num_base_address; /* Number of base addresses*/
uint8_t major; /* Hardware ID.major version */
uint8_t minor; /* Hardware ID.minor version */
uint8_t revision; /* Hardware ID.revision version */
#if defined(__BIG_ENDIAN)
uint8_t variant : 4; /* HW variant */
uint8_t sub_revision : 4; /* HCID Sub-Revision */
#else
uint8_t sub_revision : 4; /* HCID Sub-Revision */
uint8_t variant : 4; /* HW variant */
#endif
uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address field*/
} ip_v3;
typedef struct ip_v4 {
uint16_t hw_id; /* Hardware ID */
uint8_t instance_number; /* Instance number for the IP */
uint8_t num_base_address; /* Number of base addresses*/
uint8_t major; /* Hardware ID.major version */
uint8_t minor; /* Hardware ID.minor version */
uint8_t revision; /* Hardware ID.revision version */
#if defined(LITTLEENDIAN_CPU)
uint8_t sub_revision : 4; /* HCID Sub-Revision */
uint8_t variant : 4; /* HW variant */
#elif defined(BIGENDIAN_CPU)
uint8_t variant : 4; /* HW variant */
uint8_t sub_revision : 4; /* HCID Sub-Revision */
#endif
uint64_t base_address_64[1];
} ip_v4;
typedef struct die_header
{
uint16_t die_id;
uint16_t num_ips;
} die_header;
typedef struct ip_structure
{
ip_discovery_header* header;
struct die
{
die_header *die_header;
union
{
ip *ip_list;
ip_v3 *ip_v3_list;
ip_v4 *ip_v4_list;
}; /* IP list. Variable size*/
} die;
} ip_structure;
struct gpu_info_header {
uint32_t table_id; /* table ID */
uint16_t version_major; /* table version */
uint16_t version_minor; /* table version */
uint32_t size; /* size of the entire header+data in bytes */
};
struct gc_info_v1_0 {
struct gpu_info_header header;
uint32_t gc_num_se;
uint32_t gc_num_wgp0_per_sa;
uint32_t gc_num_wgp1_per_sa;
uint32_t gc_num_rb_per_se;
uint32_t gc_num_gl2c;
uint32_t gc_num_gprs;
uint32_t gc_num_max_gs_thds;
uint32_t gc_gs_table_depth;
uint32_t gc_gsprim_buff_depth;
uint32_t gc_parameter_cache_depth;
uint32_t gc_double_offchip_lds_buffer;
uint32_t gc_wave_size;
uint32_t gc_max_waves_per_simd;
uint32_t gc_max_scratch_slots_per_cu;
uint32_t gc_lds_size;
uint32_t gc_num_sc_per_se;
uint32_t gc_num_sa_per_se;
uint32_t gc_num_packer_per_sc;
uint32_t gc_num_gl2a;
};
struct gc_info_v1_1 {
struct gpu_info_header header;
uint32_t gc_num_se;
uint32_t gc_num_wgp0_per_sa;
uint32_t gc_num_wgp1_per_sa;
uint32_t gc_num_rb_per_se;
uint32_t gc_num_gl2c;
uint32_t gc_num_gprs;
uint32_t gc_num_max_gs_thds;
uint32_t gc_gs_table_depth;
uint32_t gc_gsprim_buff_depth;
uint32_t gc_parameter_cache_depth;
uint32_t gc_double_offchip_lds_buffer;
uint32_t gc_wave_size;
uint32_t gc_max_waves_per_simd;
uint32_t gc_max_scratch_slots_per_cu;
uint32_t gc_lds_size;
uint32_t gc_num_sc_per_se;
uint32_t gc_num_sa_per_se;
uint32_t gc_num_packer_per_sc;
uint32_t gc_num_gl2a;
uint32_t gc_num_tcp_per_sa;
uint32_t gc_num_sdp_interface;
uint32_t gc_num_tcps;
};
struct gc_info_v1_2 {
struct gpu_info_header header;
uint32_t gc_num_se;
uint32_t gc_num_wgp0_per_sa;
uint32_t gc_num_wgp1_per_sa;
uint32_t gc_num_rb_per_se;
uint32_t gc_num_gl2c;
uint32_t gc_num_gprs;
uint32_t gc_num_max_gs_thds;
uint32_t gc_gs_table_depth;
uint32_t gc_gsprim_buff_depth;
uint32_t gc_parameter_cache_depth;
uint32_t gc_double_offchip_lds_buffer;
uint32_t gc_wave_size;
uint32_t gc_max_waves_per_simd;
uint32_t gc_max_scratch_slots_per_cu;
uint32_t gc_lds_size;
uint32_t gc_num_sc_per_se;
uint32_t gc_num_sa_per_se;
uint32_t gc_num_packer_per_sc;
uint32_t gc_num_gl2a;
uint32_t gc_num_tcp_per_sa;
uint32_t gc_num_sdp_interface;
uint32_t gc_num_tcps;
uint32_t gc_num_tcp_per_wpg;
uint32_t gc_tcp_l1_size;
uint32_t gc_num_sqc_per_wgp;
uint32_t gc_l1_instruction_cache_size_per_sqc;
uint32_t gc_l1_data_cache_size_per_sqc;
uint32_t gc_gl1c_per_sa;
uint32_t gc_gl1c_size_per_instance;
uint32_t gc_gl2c_per_gpu;
};
struct gc_info_v2_0 {
struct gpu_info_header header;
uint32_t gc_num_se;
uint32_t gc_num_cu_per_sh;
uint32_t gc_num_sh_per_se;
uint32_t gc_num_rb_per_se;
uint32_t gc_num_tccs;
uint32_t gc_num_gprs;
uint32_t gc_num_max_gs_thds;
uint32_t gc_gs_table_depth;
uint32_t gc_gsprim_buff_depth;
uint32_t gc_parameter_cache_depth;
uint32_t gc_double_offchip_lds_buffer;
uint32_t gc_wave_size;
uint32_t gc_max_waves_per_simd;
uint32_t gc_max_scratch_slots_per_cu;
uint32_t gc_lds_size;
uint32_t gc_num_sc_per_se;
uint32_t gc_num_packer_per_sc;
};
struct gc_info_v2_1 {
struct gpu_info_header header;
uint32_t gc_num_se;
uint32_t gc_num_cu_per_sh;
uint32_t gc_num_sh_per_se;
uint32_t gc_num_rb_per_se;
uint32_t gc_num_tccs;
uint32_t gc_num_gprs;
uint32_t gc_num_max_gs_thds;
uint32_t gc_gs_table_depth;
uint32_t gc_gsprim_buff_depth;
uint32_t gc_parameter_cache_depth;
uint32_t gc_double_offchip_lds_buffer;
uint32_t gc_wave_size;
uint32_t gc_max_waves_per_simd;
uint32_t gc_max_scratch_slots_per_cu;
uint32_t gc_lds_size;
uint32_t gc_num_sc_per_se;
uint32_t gc_num_packer_per_sc;
/* new for v2_1 */
uint32_t gc_num_tcp_per_sh;
uint32_t gc_tcp_size_per_cu;
uint32_t gc_num_sdp_interface;
uint32_t gc_num_cu_per_sqc;
uint32_t gc_instruction_cache_size_per_sqc;
uint32_t gc_scalar_data_cache_size_per_sqc;
uint32_t gc_tcc_size;
};
typedef struct harvest_info_header {
uint32_t signature; /* Table Signature */
uint32_t version; /* Table Version */
} harvest_info_header;
typedef struct harvest_info {
uint16_t hw_id; /* Hardware ID */
uint8_t number_instance; /* Instance of the IP */
uint8_t reserved; /* Reserved for alignment */
} harvest_info;
typedef struct harvest_table {
harvest_info_header header;
harvest_info list[32];
} harvest_table;
struct mall_info_header {
uint32_t table_id; /* table ID */
uint16_t version_major; /* table version */
uint16_t version_minor; /* table version */
uint32_t size_bytes; /* size of the entire header+data in bytes */
};
struct mall_info_v1_0 {
struct mall_info_header header;
uint32_t mall_size_per_m;
uint32_t m_s_present;
uint32_t m_half_use;
uint32_t m_mall_config;
uint32_t reserved[5];
};
struct mall_info_v2_0 {
struct mall_info_header header;
uint32_t mall_size_per_umc;
uint32_t reserved[8];
};
#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
struct vcn_info_header {
uint32_t table_id; /* table ID */
uint16_t version_major; /* table version */
uint16_t version_minor; /* table version */
uint32_t size_bytes; /* size of the entire header+data in bytes */
};
struct vcn_instance_info_v1_0
{
uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
union _fuse_data {
struct {
uint32_t av1_disabled : 1;
uint32_t vp9_disabled : 1;
uint32_t hevc_disabled : 1;
uint32_t h264_disabled : 1;
uint32_t reserved : 28;
} bits;
uint32_t all_bits;
} fuse_data;
uint32_t reserved[2];
};
struct vcn_info_v1_0 {
struct vcn_info_header header;
uint32_t num_of_instances; /* number of entries used in instance_info below*/
struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
uint32_t reserved[4];
};
#define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12
struct nps_info_header {
uint32_t table_id; /* table ID */
uint16_t version_major; /* table version */
uint16_t version_minor; /* table version */
uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */
};
struct nps_instance_info_v1_0 {
uint64_t base_address;
uint64_t limit_address;
};
struct nps_info_v1_0 {
struct nps_info_header header;
uint32_t nps_type;
uint32_t count;
struct nps_instance_info_v1_0
instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES];
};
enum amd_hw_ip_block_type {
GC_HWIP = 1,
HDP_HWIP,
SDMA0_HWIP,
SDMA1_HWIP,
SDMA2_HWIP,
SDMA3_HWIP,
SDMA4_HWIP,
SDMA5_HWIP,
SDMA6_HWIP,
SDMA7_HWIP,
LSDMA_HWIP,
MMHUB_HWIP,
ATHUB_HWIP,
NBIO_HWIP,
MP0_HWIP,
MP1_HWIP,
UVD_HWIP,
VCN_HWIP = UVD_HWIP,
JPEG_HWIP = VCN_HWIP,
VCN1_HWIP,
VCE_HWIP,
VPE_HWIP,
DF_HWIP,
DCE_HWIP,
OSSSYS_HWIP,
SMUIO_HWIP,
PWR_HWIP,
NBIF_HWIP,
THM_HWIP,
CLK_HWIP,
UMC_HWIP,
RSMU_HWIP,
XGMI_HWIP,
DCI_HWIP,
PCIE_HWIP,
ISP_HWIP,
MAX_HWIP
};
#define HWIP_MAX_INSTANCE 44
#define HW_ID_MAX 300
// HW ID
#define MP1_HWID 1
#define MP2_HWID 2
#define THM_HWID 3
#define SMUIO_HWID 4
#define FUSE_HWID 5
#define CLKA_HWID 6
#define PWR_HWID 10
#define GC_HWID 11
#define UVD_HWID 12
#define VCN_HWID UVD_HWID
#define AUDIO_AZ_HWID 13
#define ACP_HWID 14
#define DCI_HWID 15
#define DMU_HWID 271
#define DCO_HWID 16
#define DIO_HWID 272
#define XDMA_HWID 17
#define DCEAZ_HWID 18
#define DAZ_HWID 274
#define SDPMUX_HWID 19
#define NTB_HWID 20
#define VPE_HWID 21
#define IOHC_HWID 24
#define L2IMU_HWID 28
#define VCE_HWID 32
#define MMHUB_HWID 34
#define ATHUB_HWID 35
#define DBGU_NBIO_HWID 36
#define DFX_HWID 37
#define DBGU0_HWID 38
#define DBGU1_HWID 39
#define OSSSYS_HWID 40
#define HDP_HWID 41
#define SDMA0_HWID 42
#define SDMA1_HWID 43
#define ISP_HWID 44
#define DBGU_IO_HWID 45
#define DF_HWID 46
#define CLKB_HWID 47
#define FCH_HWID 48
#define DFX_DAP_HWID 49
#define L1IMU_PCIE_HWID 50
#define L1IMU_NBIF_HWID 51
#define L1IMU_IOAGR_HWID 52
#define L1IMU3_HWID 53
#define L1IMU4_HWID 54
#define L1IMU5_HWID 55
#define L1IMU6_HWID 56
#define L1IMU7_HWID 57
#define L1IMU8_HWID 58
#define L1IMU9_HWID 59
#define L1IMU10_HWID 60
#define L1IMU11_HWID 61
#define L1IMU12_HWID 62
#define L1IMU13_HWID 63
#define L1IMU14_HWID 64
#define L1IMU15_HWID 65
#define WAFLC_HWID 66
#define FCH_USB_PD_HWID 67
#define SDMA2_HWID 68
#define SDMA3_HWID 69
#define PCIE_HWID 70
#define PCS_HWID 80
#define DDCL_HWID 89
#define SST_HWID 90
#define LSDMA_HWID 91
#define IOAGR_HWID 100
#define NBIF_HWID 108
#define IOAPIC_HWID 124
#define SYSTEMHUB_HWID 128
#define NTBCCP_HWID 144
#define UMC_HWID 150
#define SATA_HWID 168
#define USB_HWID 170
#define CCXSEC_HWID 176
#define XGMI_HWID 200
#define XGBE_HWID 216
#define MP0_HWID 255
static int hw_id_map[MAX_HWIP] = {
[GC_HWIP] = GC_HWID,
[HDP_HWIP] = HDP_HWID,
[SDMA0_HWIP] = SDMA0_HWID,
[SDMA1_HWIP] = SDMA1_HWID,
[SDMA2_HWIP] = SDMA2_HWID,
[SDMA3_HWIP] = SDMA3_HWID,
[LSDMA_HWIP] = LSDMA_HWID,
[MMHUB_HWIP] = MMHUB_HWID,
[ATHUB_HWIP] = ATHUB_HWID,
[NBIO_HWIP] = NBIF_HWID,
[MP0_HWIP] = MP0_HWID,
[MP1_HWIP] = MP1_HWID,
[UVD_HWIP] = UVD_HWID,
[VCE_HWIP] = VCE_HWID,
[DF_HWIP] = DF_HWID,
[DCE_HWIP] = DMU_HWID,
[OSSSYS_HWIP] = OSSSYS_HWID,
[SMUIO_HWIP] = SMUIO_HWID,
[PWR_HWIP] = PWR_HWID,
[NBIF_HWIP] = NBIF_HWID,
[THM_HWIP] = THM_HWID,
[CLK_HWIP] = CLKA_HWID,
[UMC_HWIP] = UMC_HWID,
[XGMI_HWIP] = XGMI_HWID,
[DCI_HWIP] = DCI_HWID,
[PCIE_HWIP] = PCIE_HWID,
[VPE_HWIP] = VPE_HWID,
[ISP_HWIP] = ISP_HWID,
};
#endif
extra/amdpci/headers/gc_11_0_0_offset.h
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extra/amdpci/headers/gc_11_0_0_sh_mask.h
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extra/amdpci/headers/mmhub_3_0_0_offset.h
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extra/amdpci/headers/mmhub_3_0_0_sh_mask.h
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extra/amdpci/headers/mp_11_0_offset.h
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@@ -0,0 +1,365 @@
/*
* Copyright (C) 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _mp_11_0_2_OFFSET_HEADER
#define _mp_11_0_2_OFFSET_HEADER
// addressBlock: mp_SmuMp0_SmnDec
// base address: 0x0
#define mmMP0_SMN_C2PMSG_32 0x0060
#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_33 0x0061
#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_34 0x0062
#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_35 0x0063
#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_36 0x0064
#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_37 0x0065
#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_38 0x0066
#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_39 0x0067
#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_40 0x0068
#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_41 0x0069
#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_42 0x006a
#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_43 0x006b
#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_44 0x006c
#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_45 0x006d
#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_46 0x006e
#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_47 0x006f
#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_48 0x0070
#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_49 0x0071
#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_50 0x0072
#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_51 0x0073
#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_52 0x0074
#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_53 0x0075
#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_54 0x0076
#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_55 0x0077
#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_56 0x0078
#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_57 0x0079
#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_58 0x007a
#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_59 0x007b
#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_60 0x007c
#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_61 0x007d
#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_62 0x007e
#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_63 0x007f
#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_64 0x0080
#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_65 0x0081
#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_66 0x0082
#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_67 0x0083
#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_68 0x0084
#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_69 0x0085
#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_70 0x0086
#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_71 0x0087
#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_72 0x0088
#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_73 0x0089
#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_74 0x008a
#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_75 0x008b
#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_76 0x008c
#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_77 0x008d
#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_78 0x008e
#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_79 0x008f
#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_80 0x0090
#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_81 0x0091
#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_82 0x0092
#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_83 0x0093
#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_84 0x0094
#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_85 0x0095
#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_86 0x0096
#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_87 0x0097
#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_88 0x0098
#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_89 0x0099
#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_90 0x009a
#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_91 0x009b
#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_92 0x009c
#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_93 0x009d
#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_94 0x009e
#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_95 0x009f
#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_96 0x00a0
#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_97 0x00a1
#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_98 0x00a2
#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_99 0x00a3
#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_100 0x00a4
#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_101 0x00a5
#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_102 0x00a6
#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0
#define mmMP0_SMN_C2PMSG_103 0x00a7
#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0
#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0
#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0
#define mmMP0_SMN_IH_CREDIT 0x00c1
#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0
#define mmMP0_SMN_IH_SW_INT 0x00c2
#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0
#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3
#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define mmMP1_SMN_C2PMSG_32 0x0260
#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_33 0x0261
#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_34 0x0262
#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_35 0x0263
#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_36 0x0264
#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_37 0x0265
#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_38 0x0266
#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_39 0x0267
#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_40 0x0268
#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_41 0x0269
#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_42 0x026a
#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_43 0x026b
#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_44 0x026c
#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_45 0x026d
#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_46 0x026e
#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_47 0x026f
#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_48 0x0270
#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_49 0x0271
#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_50 0x0272
#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_51 0x0273
#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_52 0x0274
#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_53 0x0275
#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_54 0x0276
#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_55 0x0277
#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_56 0x0278
#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_57 0x0279
#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_58 0x027a
#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_59 0x027b
#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_60 0x027c
#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_61 0x027d
#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_62 0x027e
#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_63 0x027f
#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_64 0x0280
#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_65 0x0281
#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_66 0x0282
#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_67 0x0283
#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_68 0x0284
#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_69 0x0285
#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_70 0x0286
#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_71 0x0287
#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_72 0x0288
#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_73 0x0289
#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_74 0x028a
#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_75 0x028b
#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_76 0x028c
#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_77 0x028d
#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_78 0x028e
#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_79 0x028f
#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_80 0x0290
#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_81 0x0291
#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_82 0x0292
#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_83 0x0293
#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_84 0x0294
#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_85 0x0295
#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_86 0x0296
#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_87 0x0297
#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_88 0x0298
#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_89 0x0299
#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_90 0x029a
#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_91 0x029b
#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_92 0x029c
#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_93 0x029d
#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_94 0x029e
#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_95 0x029f
#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_96 0x02a0
#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_97 0x02a1
#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_98 0x02a2
#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_99 0x02a3
#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_100 0x02a4
#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_101 0x02a5
#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_102 0x02a6
#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0
#define mmMP1_SMN_C2PMSG_103 0x02a7
#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0
#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0
#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0
#define mmMP1_SMN_IH_CREDIT 0x02c1
#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0
#define mmMP1_SMN_IH_SW_INT 0x02c2
#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0
#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3
#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
#define mmMP1_SMN_FPS_CNT 0x02c4
#define mmMP1_SMN_FPS_CNT_BASE_IDX 0
#define mmMP1_SMN_PUB_CTRL 0x02c5
#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH0 0x03c0
#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH1 0x03c1
#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH2 0x03c2
#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH3 0x03c3
#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH4 0x03c4
#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH5 0x03c5
#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH6 0x03c6
#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
#define mmMP1_SMN_EXT_SCRATCH7 0x03c7
#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
/*
* addressBlock: mp_SmuMp1Pub_MmuDec
* base address: 0x0
*/
#define smnMP1_PMI_3_START 0x3030204
#define smnMP1_PMI_3_FIFO 0x3030208
#define smnMP1_PMI_3 0x3030600
#endif
extra/amdpci/headers/mp_11_0_sh_mask.h
+975
View File
@@ -0,0 +1,975 @@
/*
* Copyright (C) 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _mp_11_0_2_SH_MASK_HEADER
#define _mp_11_0_2_SH_MASK_HEADER
// addressBlock: mp_SmuMp0_SmnDec
//MP0_SMN_C2PMSG_32
#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_33
#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_34
#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_35
#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_36
#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_37
#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_38
#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_39
#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_40
#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_41
#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_42
#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_43
#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_44
#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_45
#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_46
#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_47
#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_48
#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_49
#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_50
#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_51
#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_52
#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_53
#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_54
#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_55
#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_56
#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_57
#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_58
#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_59
#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_60
#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_61
#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_62
#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_63
#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_64
#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_65
#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_66
#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_67
#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_68
#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_69
#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_70
#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_71
#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_72
#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_73
#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_74
#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_75
#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_76
#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_77
#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_78
#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_79
#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_80
#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_81
#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_82
#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_83
#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_84
#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_85
#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_86
#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_87
#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_88
#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_89
#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_90
#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_91
#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_92
#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_93
#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_94
#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_95
#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_96
#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_97
#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_98
#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_99
#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_100
#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_101
#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_102
#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_103
#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_ACTIVE_FCN_ID
#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
//MP0_SMN_IH_CREDIT
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP0_SMN_IH_SW_INT
#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP0_SMN_IH_SW_INT_CTRL
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_FIRMWARE_FLAGS
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
//MP1_PUB_SCRATCH0
#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0
#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_PUB_SCRATCH1
#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0
#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_PUB_SCRATCH2
#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0
#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_PUB_SCRATCH3
#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0
#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_C2PMSG_0
#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_1
#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_2
#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_3
#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_4
#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_5
#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_6
#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_7
#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_8
#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_9
#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_10
#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_11
#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_12
#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_13
#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_14
#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_15
#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_16
#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_17
#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_18
#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_19
#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_20
#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_21
#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_22
#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_23
#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_24
#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_25
#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_26
#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_27
#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_28
#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_29
#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_30
#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_31
#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2CMSG_0
#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0
#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2CMSG_1
#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0
#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2CMSG_2
#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0
#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2CMSG_3
#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0
#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2CMSG_INTEN
#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0
#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL
//MP1_P2CMSG_INTSTS
#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0
#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1
#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2
#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3
#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L
#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L
#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L
#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L
//MP1_P2SMSG_0
#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0
#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2SMSG_1
#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0
#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2SMSG_2
#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0
#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2SMSG_3
#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0
#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL
//MP1_P2SMSG_INTSTS
#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0
#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1
#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2
#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3
#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L
#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L
#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L
#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L
//MP1_S2PMSG_0
#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0
#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_32
#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_33
#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_34
#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_35
#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_36
#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_37
#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_38
#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_39
#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_40
#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_41
#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_42
#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_43
#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_44
#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_45
#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_46
#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_47
#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_48
#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_49
#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_50
#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_51
#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_52
#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_53
#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_54
#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_55
#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_56
#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_57
#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_58
#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_59
#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_60
#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_61
#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_62
#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_63
#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_64
#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_65
#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_66
#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_67
#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_68
#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_69
#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_70
#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_71
#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_72
#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_73
#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_74
#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_75
#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_76
#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_77
#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_78
#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_79
#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_80
#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_81
#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_82
#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_83
#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_84
#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_85
#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_86
#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_87
#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_88
#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_89
#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_90
#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_91
#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_92
#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_93
#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_94
#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_95
#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_96
#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_97
#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_98
#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_99
#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_100
#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_101
#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_102
#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP1_C2PMSG_103
#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP1_ACTIVE_FCN_ID
#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L
//MP1_IH_CREDIT
#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP1_IH_SW_INT
#define MP1_IH_SW_INT__ID__SHIFT 0x0
#define MP1_IH_SW_INT__VALID__SHIFT 0x8
#define MP1_IH_SW_INT__ID_MASK 0x000000FFL
#define MP1_IH_SW_INT__VALID_MASK 0x00000100L
//MP1_IH_SW_INT_CTRL
#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_FPS_CNT
#define MP1_FPS_CNT__COUNT__SHIFT 0x0
#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
//MP1_PUB_CTRL
#define MP1_PUB_CTRL__RESET__SHIFT 0x0
#define MP1_PUB_CTRL__RESET_MASK 0x00000001L
//MP1_EXT_SCRATCH0
#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH1
#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH2
#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH3
#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH4
#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH5
#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH6
#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
//MP1_EXT_SCRATCH7
#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0
#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_32
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_33
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_34
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_35
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_36
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_37
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_38
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_39
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_40
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_41
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_42
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_43
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_44
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_45
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_46
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_47
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_48
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_49
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_50
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_51
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_52
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_53
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_54
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_55
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_56
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_57
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_58
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_59
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_60
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_61
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_62
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_63
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_64
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_65
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_66
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_67
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_68
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_69
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_70
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_71
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_72
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_73
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_74
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_75
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_76
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_77
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_78
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_79
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_80
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_81
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_82
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_83
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_84
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_85
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_86
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_87
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_88
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_89
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_90
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_91
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_92
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_93
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_94
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_95
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_96
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_97
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_98
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_99
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_100
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_101
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_102
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_103
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_ACTIVE_FCN_ID
#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0
#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f
#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL
#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L
//MP1_SMN_IH_CREDIT
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP1_SMN_IH_SW_INT
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP1_SMN_IH_SW_INT_CTRL
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_SMN_FPS_CNT
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
//MP1_SMN_PUB_CTRL
#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0
#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L
//MP1_SMN_EXT_SCRATCH0
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH1
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH2
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH3
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH4
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH5
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH6
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH7
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
// MP1_PMI_3_START
#define MP1_PMI_3_START__ENABLE_MASK 0x80000000L
// MP1_PMI_3_FIFO
#define MP1_PMI_3_FIFO__DEPTH_MASK 0x00000fffL
// MP1_PMI_3_START
#define MP1_PMI_3_START__ENABLE__SHIFT 0x0000001f
// MP1_PMI_3_FIFO
#define MP1_PMI_3_FIFO__DEPTH__SHIFT 0x00000000
#endif
extra/amdpci/headers/mp_13_0_0_offset.h
+461
View File
@@ -0,0 +1,461 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mp_13_0_0_OFFSET_HEADER
#define _mp_13_0_0_OFFSET_HEADER
// addressBlock: mp_SmuMp0_SmnDec
// base address: 0x0
#define regMP0_SMN_C2PMSG_32 0x0060
#define regMP0_SMN_C2PMSG_32_BASE_IDX 0
#define regMP0_SMN_C2PMSG_33 0x0061
#define regMP0_SMN_C2PMSG_33_BASE_IDX 0
#define regMP0_SMN_C2PMSG_34 0x0062
#define regMP0_SMN_C2PMSG_34_BASE_IDX 0
#define regMP0_SMN_C2PMSG_35 0x0063
#define regMP0_SMN_C2PMSG_35_BASE_IDX 0
#define regMP0_SMN_C2PMSG_36 0x0064
#define regMP0_SMN_C2PMSG_36_BASE_IDX 0
#define regMP0_SMN_C2PMSG_37 0x0065
#define regMP0_SMN_C2PMSG_37_BASE_IDX 0
#define regMP0_SMN_C2PMSG_38 0x0066
#define regMP0_SMN_C2PMSG_38_BASE_IDX 0
#define regMP0_SMN_C2PMSG_39 0x0067
#define regMP0_SMN_C2PMSG_39_BASE_IDX 0
#define regMP0_SMN_C2PMSG_40 0x0068
#define regMP0_SMN_C2PMSG_40_BASE_IDX 0
#define regMP0_SMN_C2PMSG_41 0x0069
#define regMP0_SMN_C2PMSG_41_BASE_IDX 0
#define regMP0_SMN_C2PMSG_42 0x006a
#define regMP0_SMN_C2PMSG_42_BASE_IDX 0
#define regMP0_SMN_C2PMSG_43 0x006b
#define regMP0_SMN_C2PMSG_43_BASE_IDX 0
#define regMP0_SMN_C2PMSG_44 0x006c
#define regMP0_SMN_C2PMSG_44_BASE_IDX 0
#define regMP0_SMN_C2PMSG_45 0x006d
#define regMP0_SMN_C2PMSG_45_BASE_IDX 0
#define regMP0_SMN_C2PMSG_46 0x006e
#define regMP0_SMN_C2PMSG_46_BASE_IDX 0
#define regMP0_SMN_C2PMSG_47 0x006f
#define regMP0_SMN_C2PMSG_47_BASE_IDX 0
#define regMP0_SMN_C2PMSG_48 0x0070
#define regMP0_SMN_C2PMSG_48_BASE_IDX 0
#define regMP0_SMN_C2PMSG_49 0x0071
#define regMP0_SMN_C2PMSG_49_BASE_IDX 0
#define regMP0_SMN_C2PMSG_50 0x0072
#define regMP0_SMN_C2PMSG_50_BASE_IDX 0
#define regMP0_SMN_C2PMSG_51 0x0073
#define regMP0_SMN_C2PMSG_51_BASE_IDX 0
#define regMP0_SMN_C2PMSG_52 0x0074
#define regMP0_SMN_C2PMSG_52_BASE_IDX 0
#define regMP0_SMN_C2PMSG_53 0x0075
#define regMP0_SMN_C2PMSG_53_BASE_IDX 0
#define regMP0_SMN_C2PMSG_54 0x0076
#define regMP0_SMN_C2PMSG_54_BASE_IDX 0
#define regMP0_SMN_C2PMSG_55 0x0077
#define regMP0_SMN_C2PMSG_55_BASE_IDX 0
#define regMP0_SMN_C2PMSG_56 0x0078
#define regMP0_SMN_C2PMSG_56_BASE_IDX 0
#define regMP0_SMN_C2PMSG_57 0x0079
#define regMP0_SMN_C2PMSG_57_BASE_IDX 0
#define regMP0_SMN_C2PMSG_58 0x007a
#define regMP0_SMN_C2PMSG_58_BASE_IDX 0
#define regMP0_SMN_C2PMSG_59 0x007b
#define regMP0_SMN_C2PMSG_59_BASE_IDX 0
#define regMP0_SMN_C2PMSG_60 0x007c
#define regMP0_SMN_C2PMSG_60_BASE_IDX 0
#define regMP0_SMN_C2PMSG_61 0x007d
#define regMP0_SMN_C2PMSG_61_BASE_IDX 0
#define regMP0_SMN_C2PMSG_62 0x007e
#define regMP0_SMN_C2PMSG_62_BASE_IDX 0
#define regMP0_SMN_C2PMSG_63 0x007f
#define regMP0_SMN_C2PMSG_63_BASE_IDX 0
#define regMP0_SMN_C2PMSG_64 0x0080
#define regMP0_SMN_C2PMSG_64_BASE_IDX 0
#define regMP0_SMN_C2PMSG_65 0x0081
#define regMP0_SMN_C2PMSG_65_BASE_IDX 0
#define regMP0_SMN_C2PMSG_66 0x0082
#define regMP0_SMN_C2PMSG_66_BASE_IDX 0
#define regMP0_SMN_C2PMSG_67 0x0083
#define regMP0_SMN_C2PMSG_67_BASE_IDX 0
#define regMP0_SMN_C2PMSG_68 0x0084
#define regMP0_SMN_C2PMSG_68_BASE_IDX 0
#define regMP0_SMN_C2PMSG_69 0x0085
#define regMP0_SMN_C2PMSG_69_BASE_IDX 0
#define regMP0_SMN_C2PMSG_70 0x0086
#define regMP0_SMN_C2PMSG_70_BASE_IDX 0
#define regMP0_SMN_C2PMSG_71 0x0087
#define regMP0_SMN_C2PMSG_71_BASE_IDX 0
#define regMP0_SMN_C2PMSG_72 0x0088
#define regMP0_SMN_C2PMSG_72_BASE_IDX 0
#define regMP0_SMN_C2PMSG_73 0x0089
#define regMP0_SMN_C2PMSG_73_BASE_IDX 0
#define regMP0_SMN_C2PMSG_74 0x008a
#define regMP0_SMN_C2PMSG_74_BASE_IDX 0
#define regMP0_SMN_C2PMSG_75 0x008b
#define regMP0_SMN_C2PMSG_75_BASE_IDX 0
#define regMP0_SMN_C2PMSG_76 0x008c
#define regMP0_SMN_C2PMSG_76_BASE_IDX 0
#define regMP0_SMN_C2PMSG_77 0x008d
#define regMP0_SMN_C2PMSG_77_BASE_IDX 0
#define regMP0_SMN_C2PMSG_78 0x008e
#define regMP0_SMN_C2PMSG_78_BASE_IDX 0
#define regMP0_SMN_C2PMSG_79 0x008f
#define regMP0_SMN_C2PMSG_79_BASE_IDX 0
#define regMP0_SMN_C2PMSG_80 0x0090
#define regMP0_SMN_C2PMSG_80_BASE_IDX 0
#define regMP0_SMN_C2PMSG_81 0x0091
#define regMP0_SMN_C2PMSG_81_BASE_IDX 0
#define regMP0_SMN_C2PMSG_82 0x0092
#define regMP0_SMN_C2PMSG_82_BASE_IDX 0
#define regMP0_SMN_C2PMSG_83 0x0093
#define regMP0_SMN_C2PMSG_83_BASE_IDX 0
#define regMP0_SMN_C2PMSG_84 0x0094
#define regMP0_SMN_C2PMSG_84_BASE_IDX 0
#define regMP0_SMN_C2PMSG_85 0x0095
#define regMP0_SMN_C2PMSG_85_BASE_IDX 0
#define regMP0_SMN_C2PMSG_86 0x0096
#define regMP0_SMN_C2PMSG_86_BASE_IDX 0
#define regMP0_SMN_C2PMSG_87 0x0097
#define regMP0_SMN_C2PMSG_87_BASE_IDX 0
#define regMP0_SMN_C2PMSG_88 0x0098
#define regMP0_SMN_C2PMSG_88_BASE_IDX 0
#define regMP0_SMN_C2PMSG_89 0x0099
#define regMP0_SMN_C2PMSG_89_BASE_IDX 0
#define regMP0_SMN_C2PMSG_90 0x009a
#define regMP0_SMN_C2PMSG_90_BASE_IDX 0
#define regMP0_SMN_C2PMSG_91 0x009b
#define regMP0_SMN_C2PMSG_91_BASE_IDX 0
#define regMP0_SMN_C2PMSG_92 0x009c
#define regMP0_SMN_C2PMSG_92_BASE_IDX 0
#define regMP0_SMN_C2PMSG_93 0x009d
#define regMP0_SMN_C2PMSG_93_BASE_IDX 0
#define regMP0_SMN_C2PMSG_94 0x009e
#define regMP0_SMN_C2PMSG_94_BASE_IDX 0
#define regMP0_SMN_C2PMSG_95 0x009f
#define regMP0_SMN_C2PMSG_95_BASE_IDX 0
#define regMP0_SMN_C2PMSG_96 0x00a0
#define regMP0_SMN_C2PMSG_96_BASE_IDX 0
#define regMP0_SMN_C2PMSG_97 0x00a1
#define regMP0_SMN_C2PMSG_97_BASE_IDX 0
#define regMP0_SMN_C2PMSG_98 0x00a2
#define regMP0_SMN_C2PMSG_98_BASE_IDX 0
#define regMP0_SMN_C2PMSG_99 0x00a3
#define regMP0_SMN_C2PMSG_99_BASE_IDX 0
#define regMP0_SMN_C2PMSG_100 0x00a4
#define regMP0_SMN_C2PMSG_100_BASE_IDX 0
#define regMP0_SMN_C2PMSG_101 0x00a5
#define regMP0_SMN_C2PMSG_101_BASE_IDX 0
#define regMP0_SMN_C2PMSG_102 0x00a6
#define regMP0_SMN_C2PMSG_102_BASE_IDX 0
#define regMP0_SMN_C2PMSG_103 0x00a7
#define regMP0_SMN_C2PMSG_103_BASE_IDX 0
#define regMP0_SMN_IH_CREDIT 0x00c1
#define regMP0_SMN_IH_CREDIT_BASE_IDX 0
#define regMP0_SMN_IH_SW_INT 0x00c2
#define regMP0_SMN_IH_SW_INT_BASE_IDX 0
#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3
#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_32 0x0260
#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
#define regMP1_SMN_C2PMSG_33 0x0261
#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
#define regMP1_SMN_C2PMSG_34 0x0262
#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
#define regMP1_SMN_C2PMSG_35 0x0263
#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
#define regMP1_SMN_C2PMSG_36 0x0264
#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
#define regMP1_SMN_C2PMSG_37 0x0265
#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
#define regMP1_SMN_C2PMSG_38 0x0266
#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
#define regMP1_SMN_C2PMSG_39 0x0267
#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
#define regMP1_SMN_C2PMSG_40 0x0268
#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
#define regMP1_SMN_C2PMSG_41 0x0269
#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
#define regMP1_SMN_C2PMSG_42 0x026a
#define regMP1_SMN_C2PMSG_42_BASE_IDX 0
#define regMP1_SMN_C2PMSG_43 0x026b
#define regMP1_SMN_C2PMSG_43_BASE_IDX 0
#define regMP1_SMN_C2PMSG_44 0x026c
#define regMP1_SMN_C2PMSG_44_BASE_IDX 0
#define regMP1_SMN_C2PMSG_45 0x026d
#define regMP1_SMN_C2PMSG_45_BASE_IDX 0
#define regMP1_SMN_C2PMSG_46 0x026e
#define regMP1_SMN_C2PMSG_46_BASE_IDX 0
#define regMP1_SMN_C2PMSG_47 0x026f
#define regMP1_SMN_C2PMSG_47_BASE_IDX 0
#define regMP1_SMN_C2PMSG_48 0x0270
#define regMP1_SMN_C2PMSG_48_BASE_IDX 0
#define regMP1_SMN_C2PMSG_49 0x0271
#define regMP1_SMN_C2PMSG_49_BASE_IDX 0
#define regMP1_SMN_C2PMSG_50 0x0272
#define regMP1_SMN_C2PMSG_50_BASE_IDX 0
#define regMP1_SMN_C2PMSG_51 0x0273
#define regMP1_SMN_C2PMSG_51_BASE_IDX 0
#define regMP1_SMN_C2PMSG_52 0x0274
#define regMP1_SMN_C2PMSG_52_BASE_IDX 0
#define regMP1_SMN_C2PMSG_53 0x0275
#define regMP1_SMN_C2PMSG_53_BASE_IDX 0
#define regMP1_SMN_C2PMSG_54 0x0276
#define regMP1_SMN_C2PMSG_54_BASE_IDX 0
#define regMP1_SMN_C2PMSG_55 0x0277
#define regMP1_SMN_C2PMSG_55_BASE_IDX 0
#define regMP1_SMN_C2PMSG_56 0x0278
#define regMP1_SMN_C2PMSG_56_BASE_IDX 0
#define regMP1_SMN_C2PMSG_57 0x0279
#define regMP1_SMN_C2PMSG_57_BASE_IDX 0
#define regMP1_SMN_C2PMSG_58 0x027a
#define regMP1_SMN_C2PMSG_58_BASE_IDX 0
#define regMP1_SMN_C2PMSG_59 0x027b
#define regMP1_SMN_C2PMSG_59_BASE_IDX 0
#define regMP1_SMN_C2PMSG_60 0x027c
#define regMP1_SMN_C2PMSG_60_BASE_IDX 0
#define regMP1_SMN_C2PMSG_61 0x027d
#define regMP1_SMN_C2PMSG_61_BASE_IDX 0
#define regMP1_SMN_C2PMSG_62 0x027e
#define regMP1_SMN_C2PMSG_62_BASE_IDX 0
#define regMP1_SMN_C2PMSG_63 0x027f
#define regMP1_SMN_C2PMSG_63_BASE_IDX 0
#define regMP1_SMN_C2PMSG_64 0x0280
#define regMP1_SMN_C2PMSG_64_BASE_IDX 0
#define regMP1_SMN_C2PMSG_65 0x0281
#define regMP1_SMN_C2PMSG_65_BASE_IDX 0
#define regMP1_SMN_C2PMSG_66 0x0282
#define regMP1_SMN_C2PMSG_66_BASE_IDX 0
#define regMP1_SMN_C2PMSG_67 0x0283
#define regMP1_SMN_C2PMSG_67_BASE_IDX 0
#define regMP1_SMN_C2PMSG_68 0x0284
#define regMP1_SMN_C2PMSG_68_BASE_IDX 0
#define regMP1_SMN_C2PMSG_69 0x0285
#define regMP1_SMN_C2PMSG_69_BASE_IDX 0
#define regMP1_SMN_C2PMSG_70 0x0286
#define regMP1_SMN_C2PMSG_70_BASE_IDX 0
#define regMP1_SMN_C2PMSG_71 0x0287
#define regMP1_SMN_C2PMSG_71_BASE_IDX 0
#define regMP1_SMN_C2PMSG_72 0x0288
#define regMP1_SMN_C2PMSG_72_BASE_IDX 0
#define regMP1_SMN_C2PMSG_73 0x0289
#define regMP1_SMN_C2PMSG_73_BASE_IDX 0
#define regMP1_SMN_C2PMSG_74 0x028a
#define regMP1_SMN_C2PMSG_74_BASE_IDX 0
#define regMP1_SMN_C2PMSG_75 0x028b
#define regMP1_SMN_C2PMSG_75_BASE_IDX 0
#define regMP1_SMN_C2PMSG_76 0x028c
#define regMP1_SMN_C2PMSG_76_BASE_IDX 0
#define regMP1_SMN_C2PMSG_77 0x028d
#define regMP1_SMN_C2PMSG_77_BASE_IDX 0
#define regMP1_SMN_C2PMSG_78 0x028e
#define regMP1_SMN_C2PMSG_78_BASE_IDX 0
#define regMP1_SMN_C2PMSG_79 0x028f
#define regMP1_SMN_C2PMSG_79_BASE_IDX 0
#define regMP1_SMN_C2PMSG_80 0x0290
#define regMP1_SMN_C2PMSG_80_BASE_IDX 0
#define regMP1_SMN_C2PMSG_81 0x0291
#define regMP1_SMN_C2PMSG_81_BASE_IDX 0
#define regMP1_SMN_C2PMSG_82 0x0292
#define regMP1_SMN_C2PMSG_82_BASE_IDX 0
#define regMP1_SMN_C2PMSG_83 0x0293
#define regMP1_SMN_C2PMSG_83_BASE_IDX 0
#define regMP1_SMN_C2PMSG_84 0x0294
#define regMP1_SMN_C2PMSG_84_BASE_IDX 0
#define regMP1_SMN_C2PMSG_85 0x0295
#define regMP1_SMN_C2PMSG_85_BASE_IDX 0
#define regMP1_SMN_C2PMSG_86 0x0296
#define regMP1_SMN_C2PMSG_86_BASE_IDX 0
#define regMP1_SMN_C2PMSG_87 0x0297
#define regMP1_SMN_C2PMSG_87_BASE_IDX 0
#define regMP1_SMN_C2PMSG_88 0x0298
#define regMP1_SMN_C2PMSG_88_BASE_IDX 0
#define regMP1_SMN_C2PMSG_89 0x0299
#define regMP1_SMN_C2PMSG_89_BASE_IDX 0
#define regMP1_SMN_C2PMSG_90 0x029a
#define regMP1_SMN_C2PMSG_90_BASE_IDX 0
#define regMP1_SMN_C2PMSG_91 0x029b
#define regMP1_SMN_C2PMSG_91_BASE_IDX 0
#define regMP1_SMN_C2PMSG_92 0x029c
#define regMP1_SMN_C2PMSG_92_BASE_IDX 0
#define regMP1_SMN_C2PMSG_93 0x029d
#define regMP1_SMN_C2PMSG_93_BASE_IDX 0
#define regMP1_SMN_C2PMSG_94 0x029e
#define regMP1_SMN_C2PMSG_94_BASE_IDX 0
#define regMP1_SMN_C2PMSG_95 0x029f
#define regMP1_SMN_C2PMSG_95_BASE_IDX 0
#define regMP1_SMN_C2PMSG_96 0x02a0
#define regMP1_SMN_C2PMSG_96_BASE_IDX 0
#define regMP1_SMN_C2PMSG_97 0x02a1
#define regMP1_SMN_C2PMSG_97_BASE_IDX 0
#define regMP1_SMN_C2PMSG_98 0x02a2
#define regMP1_SMN_C2PMSG_98_BASE_IDX 0
#define regMP1_SMN_C2PMSG_99 0x02a3
#define regMP1_SMN_C2PMSG_99_BASE_IDX 0
#define regMP1_SMN_C2PMSG_100 0x02a4
#define regMP1_SMN_C2PMSG_100_BASE_IDX 0
#define regMP1_SMN_C2PMSG_101 0x02a5
#define regMP1_SMN_C2PMSG_101_BASE_IDX 0
#define regMP1_SMN_C2PMSG_102 0x02a6
#define regMP1_SMN_C2PMSG_102_BASE_IDX 0
#define regMP1_SMN_C2PMSG_103 0x02a7
#define regMP1_SMN_C2PMSG_103_BASE_IDX 0
#define regMP1_SMN_C2PMSG_104 0x02a8
#define regMP1_SMN_C2PMSG_104_BASE_IDX 0
#define regMP1_SMN_C2PMSG_105 0x02a9
#define regMP1_SMN_C2PMSG_105_BASE_IDX 0
#define regMP1_SMN_C2PMSG_106 0x02aa
#define regMP1_SMN_C2PMSG_106_BASE_IDX 0
#define regMP1_SMN_C2PMSG_107 0x02ab
#define regMP1_SMN_C2PMSG_107_BASE_IDX 0
#define regMP1_SMN_C2PMSG_108 0x02ac
#define regMP1_SMN_C2PMSG_108_BASE_IDX 0
#define regMP1_SMN_C2PMSG_109 0x02ad
#define regMP1_SMN_C2PMSG_109_BASE_IDX 0
#define regMP1_SMN_C2PMSG_110 0x02ae
#define regMP1_SMN_C2PMSG_110_BASE_IDX 0
#define regMP1_SMN_C2PMSG_111 0x02af
#define regMP1_SMN_C2PMSG_111_BASE_IDX 0
#define regMP1_SMN_C2PMSG_112 0x02b0
#define regMP1_SMN_C2PMSG_112_BASE_IDX 0
#define regMP1_SMN_C2PMSG_113 0x02b1
#define regMP1_SMN_C2PMSG_113_BASE_IDX 0
#define regMP1_SMN_C2PMSG_114 0x02b2
#define regMP1_SMN_C2PMSG_114_BASE_IDX 0
#define regMP1_SMN_C2PMSG_115 0x02b3
#define regMP1_SMN_C2PMSG_115_BASE_IDX 0
#define regMP1_SMN_C2PMSG_116 0x02b4
#define regMP1_SMN_C2PMSG_116_BASE_IDX 0
#define regMP1_SMN_C2PMSG_117 0x02b5
#define regMP1_SMN_C2PMSG_117_BASE_IDX 0
#define regMP1_SMN_C2PMSG_118 0x02b6
#define regMP1_SMN_C2PMSG_118_BASE_IDX 0
#define regMP1_SMN_C2PMSG_119 0x02b7
#define regMP1_SMN_C2PMSG_119_BASE_IDX 0
#define regMP1_SMN_C2PMSG_120 0x02b8
#define regMP1_SMN_C2PMSG_120_BASE_IDX 0
#define regMP1_SMN_C2PMSG_121 0x02b9
#define regMP1_SMN_C2PMSG_121_BASE_IDX 0
#define regMP1_SMN_C2PMSG_122 0x02ba
#define regMP1_SMN_C2PMSG_122_BASE_IDX 0
#define regMP1_SMN_C2PMSG_123 0x02bb
#define regMP1_SMN_C2PMSG_123_BASE_IDX 0
#define regMP1_SMN_C2PMSG_124 0x02bc
#define regMP1_SMN_C2PMSG_124_BASE_IDX 0
#define regMP1_SMN_C2PMSG_125 0x02bd
#define regMP1_SMN_C2PMSG_125_BASE_IDX 0
#define regMP1_SMN_C2PMSG_126 0x02be
#define regMP1_SMN_C2PMSG_126_BASE_IDX 0
#define regMP1_SMN_C2PMSG_127 0x02bf
#define regMP1_SMN_C2PMSG_127_BASE_IDX 0
#define regMP1_SMN_IH_CREDIT 0x02c1
#define regMP1_SMN_IH_CREDIT_BASE_IDX 0
#define regMP1_SMN_IH_SW_INT 0x02c2
#define regMP1_SMN_IH_SW_INT_BASE_IDX 0
#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
#define regMP1_SMN_FPS_CNT 0x02c4
#define regMP1_SMN_FPS_CNT_BASE_IDX 0
#define regMP1_SMN_PUB_CTRL 0x02c5
#define regMP1_SMN_PUB_CTRL_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH0 0x0340
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH1 0x0341
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH2 0x0342
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH3 0x0343
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH4 0x0344
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH5 0x0345
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH6 0x0346
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH7 0x0347
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH8 0x0348
#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH10 0x034a
#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH11 0x034b
#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH12 0x034c
#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH13 0x034d
#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH14 0x034e
#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH15 0x034f
#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH16 0x0350
#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH17 0x0351
#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH18 0x0352
#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH19 0x0353
#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH20 0x0354
#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH21 0x0355
#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH22 0x0356
#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH23 0x0357
#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH24 0x0358
#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH25 0x0359
#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH26 0x035a
#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH27 0x035b
#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH28 0x035c
#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH29 0x035d
#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH30 0x035e
#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH31 0x035f
#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0
// addressBlock: mp_SmuMp1Pub_CruDec
// base address: 0x0
#define regMP1_FIRMWARE_FLAGS 0xbee009
#define regMP1_FIRMWARE_FLAGS_BASE_IDX 0
// addressBlock: mp_SmuMpIOPub_CruDec
// base address: 0x0
#define regMPIO_FIRMWARE_FLAGS 0xbee009
#define regMPIO_FIRMWARE_FLAGS_BASE_IDX 0
#endif
extra/amdpci/headers/mp_13_0_0_sh_mask.h
+682
View File
@@ -0,0 +1,682 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mp_13_0_0_SH_MASK_HEADER
#define _mp_13_0_0_SH_MASK_HEADER
// addressBlock: mp_SmuMp0_SmnDec
//MP0_SMN_C2PMSG_32
#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_33
#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_34
#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_35
#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_36
#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_37
#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_38
#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_39
#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_40
#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_41
#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_42
#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_43
#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_44
#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_45
#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_46
#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_47
#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_48
#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_49
#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_50
#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_51
#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_52
#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_53
#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_54
#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_55
#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_56
#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_57
#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_58
#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_59
#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_60
#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_61
#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_62
#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_63
#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_64
#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_65
#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_66
#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_67
#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_68
#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_69
#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_70
#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_71
#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_72
#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_73
#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_74
#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_75
#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_76
#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_77
#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_78
#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_79
#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_80
#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_81
#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_82
#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_83
#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_84
#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_85
#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_86
#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_87
#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_88
#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_89
#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_90
#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_91
#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_92
#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_93
#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_94
#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_95
#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_96
#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_97
#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_98
#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_99
#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_100
#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_101
#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_102
#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_103
#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_IH_CREDIT
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP0_SMN_IH_SW_INT
#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP0_SMN_IH_SW_INT_CTRL
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_32
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_33
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_34
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_35
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_36
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_37
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_38
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_39
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_40
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_41
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_42
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_43
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_44
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_45
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_46
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_47
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_48
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_49
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_50
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_51
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_52
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_53
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_54
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_55
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_56
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_57
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_58
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_59
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_60
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_61
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_62
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_63
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_64
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_65
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_66
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_67
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_68
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_69
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_70
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_71
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_72
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_73
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_74
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_75
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_76
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_77
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_78
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_79
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_80
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_81
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_82
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_83
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_84
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_85
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_86
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_87
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_88
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_89
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_90
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_91
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_92
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_93
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_94
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_95
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_96
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_97
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_98
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_99
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_100
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_101
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_102
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_103
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_104
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_105
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_106
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_107
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_108
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_109
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_110
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_111
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_112
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_113
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_114
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_115
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_116
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_117
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_118
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_119
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_120
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_121
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_122
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_123
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_124
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_125
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_126
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_127
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_IH_CREDIT
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP1_SMN_IH_SW_INT
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP1_SMN_IH_SW_INT_CTRL
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_SMN_FPS_CNT
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
//MP1_SMN_PUB_CTRL
#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT 0x0
#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK 0x00000001L
//MP1_SMN_EXT_SCRATCH0
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH1
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH2
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH3
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH4
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH5
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH6
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH7
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH8
#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH10
#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH11
#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH12
#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH13
#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH14
#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH15
#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH16
#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH17
#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH18
#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH19
#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH20
#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH21
#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH22
#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH23
#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH24
#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH25
#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH26
#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH27
#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH28
#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH29
#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH30
#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH31
#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL
// addressBlock: mp_SmuMp1Pub_CruDec
//MP1_FIRMWARE_FLAGS
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
// addressBlock: mp_SmuMpIOPub_CruDec
//MPIO_FIRMWARE_FLAGS
#define MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MPIO_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
#endif
extra/amdpci/headers/nbio_4_3_0_offset.h
+17381
View File
File diff suppressed because it is too large Load Diff
extra/amdpci/headers/nbio_4_3_0_sh_mask.h
+82050
View File
File diff suppressed because it is too large Load Diff
extra/amdpci/headers/osssys_6_0_0_offset.h
+267
View File
@@ -0,0 +1,267 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _osssys_6_0_0_OFFSET_HEADER
#define _osssys_6_0_0_OFFSET_HEADER
// addressBlock: osssys_osssysdec
// base address: 0x4280
#define regIH_VMID_0_LUT 0x0000
#define regIH_VMID_0_LUT_BASE_IDX 0
#define regIH_VMID_1_LUT 0x0001
#define regIH_VMID_1_LUT_BASE_IDX 0
#define regIH_VMID_2_LUT 0x0002
#define regIH_VMID_2_LUT_BASE_IDX 0
#define regIH_VMID_3_LUT 0x0003
#define regIH_VMID_3_LUT_BASE_IDX 0
#define regIH_VMID_4_LUT 0x0004
#define regIH_VMID_4_LUT_BASE_IDX 0
#define regIH_VMID_5_LUT 0x0005
#define regIH_VMID_5_LUT_BASE_IDX 0
#define regIH_VMID_6_LUT 0x0006
#define regIH_VMID_6_LUT_BASE_IDX 0
#define regIH_VMID_7_LUT 0x0007
#define regIH_VMID_7_LUT_BASE_IDX 0
#define regIH_VMID_8_LUT 0x0008
#define regIH_VMID_8_LUT_BASE_IDX 0
#define regIH_VMID_9_LUT 0x0009
#define regIH_VMID_9_LUT_BASE_IDX 0
#define regIH_VMID_10_LUT 0x000a
#define regIH_VMID_10_LUT_BASE_IDX 0
#define regIH_VMID_11_LUT 0x000b
#define regIH_VMID_11_LUT_BASE_IDX 0
#define regIH_VMID_12_LUT 0x000c
#define regIH_VMID_12_LUT_BASE_IDX 0
#define regIH_VMID_13_LUT 0x000d
#define regIH_VMID_13_LUT_BASE_IDX 0
#define regIH_VMID_14_LUT 0x000e
#define regIH_VMID_14_LUT_BASE_IDX 0
#define regIH_VMID_15_LUT 0x000f
#define regIH_VMID_15_LUT_BASE_IDX 0
#define regIH_VMID_0_LUT_MM 0x0010
#define regIH_VMID_0_LUT_MM_BASE_IDX 0
#define regIH_VMID_1_LUT_MM 0x0011
#define regIH_VMID_1_LUT_MM_BASE_IDX 0
#define regIH_VMID_2_LUT_MM 0x0012
#define regIH_VMID_2_LUT_MM_BASE_IDX 0
#define regIH_VMID_3_LUT_MM 0x0013
#define regIH_VMID_3_LUT_MM_BASE_IDX 0
#define regIH_VMID_4_LUT_MM 0x0014
#define regIH_VMID_4_LUT_MM_BASE_IDX 0
#define regIH_VMID_5_LUT_MM 0x0015
#define regIH_VMID_5_LUT_MM_BASE_IDX 0
#define regIH_VMID_6_LUT_MM 0x0016
#define regIH_VMID_6_LUT_MM_BASE_IDX 0
#define regIH_VMID_7_LUT_MM 0x0017
#define regIH_VMID_7_LUT_MM_BASE_IDX 0
#define regIH_VMID_8_LUT_MM 0x0018
#define regIH_VMID_8_LUT_MM_BASE_IDX 0
#define regIH_VMID_9_LUT_MM 0x0019
#define regIH_VMID_9_LUT_MM_BASE_IDX 0
#define regIH_VMID_10_LUT_MM 0x001a
#define regIH_VMID_10_LUT_MM_BASE_IDX 0
#define regIH_VMID_11_LUT_MM 0x001b
#define regIH_VMID_11_LUT_MM_BASE_IDX 0
#define regIH_VMID_12_LUT_MM 0x001c
#define regIH_VMID_12_LUT_MM_BASE_IDX 0
#define regIH_VMID_13_LUT_MM 0x001d
#define regIH_VMID_13_LUT_MM_BASE_IDX 0
#define regIH_VMID_14_LUT_MM 0x001e
#define regIH_VMID_14_LUT_MM_BASE_IDX 0
#define regIH_VMID_15_LUT_MM 0x001f
#define regIH_VMID_15_LUT_MM_BASE_IDX 0
#define regIH_COOKIE_0 0x0020
#define regIH_COOKIE_0_BASE_IDX 0
#define regIH_COOKIE_1 0x0021
#define regIH_COOKIE_1_BASE_IDX 0
#define regIH_COOKIE_2 0x0022
#define regIH_COOKIE_2_BASE_IDX 0
#define regIH_COOKIE_3 0x0023
#define regIH_COOKIE_3_BASE_IDX 0
#define regIH_COOKIE_4 0x0024
#define regIH_COOKIE_4_BASE_IDX 0
#define regIH_COOKIE_5 0x0025
#define regIH_COOKIE_5_BASE_IDX 0
#define regIH_COOKIE_6 0x0026
#define regIH_COOKIE_6_BASE_IDX 0
#define regIH_COOKIE_7 0x0027
#define regIH_COOKIE_7_BASE_IDX 0
#define regIH_REGISTER_LAST_PART0 0x003f
#define regIH_REGISTER_LAST_PART0_BASE_IDX 0
#define regIH_RB_CNTL 0x0080
#define regIH_RB_CNTL_BASE_IDX 0
#define regIH_RB_BASE 0x0081
#define regIH_RB_BASE_BASE_IDX 0
#define regIH_RB_BASE_HI 0x0082
#define regIH_RB_BASE_HI_BASE_IDX 0
#define regIH_RB_RPTR 0x0083
#define regIH_RB_RPTR_BASE_IDX 0
#define regIH_RB_WPTR 0x0084
#define regIH_RB_WPTR_BASE_IDX 0
#define regIH_RB_WPTR_ADDR_HI 0x0085
#define regIH_RB_WPTR_ADDR_HI_BASE_IDX 0
#define regIH_RB_WPTR_ADDR_LO 0x0086
#define regIH_RB_WPTR_ADDR_LO_BASE_IDX 0
#define regIH_DOORBELL_RPTR 0x0087
#define regIH_DOORBELL_RPTR_BASE_IDX 0
#define regIH_DOORBELL_RETRY_CAM 0x0088
#define regIH_DOORBELL_RETRY_CAM_BASE_IDX 0
#define regIH_RB_CNTL_RING1 0x008c
#define regIH_RB_CNTL_RING1_BASE_IDX 0
#define regIH_RB_BASE_RING1 0x008d
#define regIH_RB_BASE_RING1_BASE_IDX 0
#define regIH_RB_BASE_HI_RING1 0x008e
#define regIH_RB_BASE_HI_RING1_BASE_IDX 0
#define regIH_RB_RPTR_RING1 0x008f
#define regIH_RB_RPTR_RING1_BASE_IDX 0
#define regIH_RB_WPTR_RING1 0x0090
#define regIH_RB_WPTR_RING1_BASE_IDX 0
#define regIH_DOORBELL_RPTR_RING1 0x0093
#define regIH_DOORBELL_RPTR_RING1_BASE_IDX 0
#define regIH_RETRY_CAM_ACK 0x00a4
#define regIH_RETRY_CAM_ACK_BASE_IDX 0
#define regIH_VERSION 0x00a5
#define regIH_VERSION_BASE_IDX 0
#define regIH_CNTL 0x00c0
#define regIH_CNTL_BASE_IDX 0
#define regIH_CNTL2 0x00c1
#define regIH_CNTL2_BASE_IDX 0
#define regIH_STATUS 0x00c2
#define regIH_STATUS_BASE_IDX 0
#define regIH_PERFMON_CNTL 0x00c3
#define regIH_PERFMON_CNTL_BASE_IDX 0
#define regIH_PERFCOUNTER0_RESULT 0x00c4
#define regIH_PERFCOUNTER0_RESULT_BASE_IDX 0
#define regIH_PERFCOUNTER1_RESULT 0x00c5
#define regIH_PERFCOUNTER1_RESULT_BASE_IDX 0
#define regIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
#define regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
#define regIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
#define regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
#define regIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
#define regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
#define regIH_DSM_MATCH_FIELD_CONTROL 0x00ca
#define regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
#define regIH_DSM_MATCH_DATA_CONTROL 0x00cb
#define regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
#define regIH_DSM_MATCH_FCN_ID 0x00cc
#define regIH_DSM_MATCH_FCN_ID_BASE_IDX 0
#define regIH_LIMIT_INT_RATE_CNTL 0x00cd
#define regIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
#define regIH_VF_RB_STATUS 0x00ce
#define regIH_VF_RB_STATUS_BASE_IDX 0
#define regIH_VF_RB_STATUS2 0x00cf
#define regIH_VF_RB_STATUS2_BASE_IDX 0
#define regIH_VF_RB1_STATUS 0x00d0
#define regIH_VF_RB1_STATUS_BASE_IDX 0
#define regIH_VF_RB1_STATUS2 0x00d1
#define regIH_VF_RB1_STATUS2_BASE_IDX 0
#define regIH_RB_STATUS 0x00d4
#define regIH_RB_STATUS_BASE_IDX 0
#define regIH_INT_FLOOD_CNTL 0x00d5
#define regIH_INT_FLOOD_CNTL_BASE_IDX 0
#define regIH_RB0_INT_FLOOD_STATUS 0x00d6
#define regIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
#define regIH_RB1_INT_FLOOD_STATUS 0x00d7
#define regIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
#define regIH_INT_FLOOD_STATUS 0x00d9
#define regIH_INT_FLOOD_STATUS_BASE_IDX 0
#define regIH_STORM_CLIENT_LIST_CNTL 0x00da
#define regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
#define regIH_CLK_CTRL 0x00db
#define regIH_CLK_CTRL_BASE_IDX 0
#define regIH_INT_FLAGS 0x00dc
#define regIH_INT_FLAGS_BASE_IDX 0
#define regIH_LAST_INT_INFO0 0x00dd
#define regIH_LAST_INT_INFO0_BASE_IDX 0
#define regIH_LAST_INT_INFO1 0x00de
#define regIH_LAST_INT_INFO1_BASE_IDX 0
#define regIH_LAST_INT_INFO2 0x00df
#define regIH_LAST_INT_INFO2_BASE_IDX 0
#define regIH_SCRATCH 0x00e0
#define regIH_SCRATCH_BASE_IDX 0
#define regIH_CLIENT_CREDIT_ERROR 0x00e1
#define regIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
#define regIH_COOKIE_REC_VIOLATION_LOG 0x00e4
#define regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
#define regIH_CREDIT_STATUS 0x00e5
#define regIH_CREDIT_STATUS_BASE_IDX 0
#define regIH_MMHUB_ERROR 0x00e6
#define regIH_MMHUB_ERROR_BASE_IDX 0
#define regIH_MEM_POWER_CTRL 0x00e9
#define regIH_MEM_POWER_CTRL_BASE_IDX 0
#define regIH_VF_RB_STATUS3 0x00ea
#define regIH_VF_RB_STATUS3_BASE_IDX 0
#define regIH_VF_RB_STATUS4 0x00eb
#define regIH_VF_RB_STATUS4_BASE_IDX 0
#define regIH_VF_RB1_STATUS3 0x00ec
#define regIH_VF_RB1_STATUS3_BASE_IDX 0
#define regIH_RETRY_INT_CAM_CNTL 0x00ef
#define regIH_RETRY_INT_CAM_CNTL_BASE_IDX 0
#define regIH_MEM_POWER_CTRL2 0x00f0
#define regIH_MEM_POWER_CTRL2_BASE_IDX 0
#define regIH_MSI_STORM_CTRL 0x00f1
#define regIH_MSI_STORM_CTRL_BASE_IDX 0
#define regIH_MSI_STORM_CLIENT_INDEX 0x00f2
#define regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX 0
#define regIH_MSI_STORM_CLIENT_DATA 0x00f3
#define regIH_MSI_STORM_CLIENT_DATA_BASE_IDX 0
#define regIH_REGISTER_LAST_PART2 0x00ff
#define regIH_REGISTER_LAST_PART2_BASE_IDX 0
#define regSEM_MAILBOX 0x010a
#define regSEM_MAILBOX_BASE_IDX 0
#define regSEM_MAILBOX_CLEAR 0x010b
#define regSEM_MAILBOX_CLEAR_BASE_IDX 0
#define regSEM_REGISTER_LAST_PART2 0x017f
#define regSEM_REGISTER_LAST_PART2_BASE_IDX 0
#define regIH_CLIENT_CFG 0x0184
#define regIH_CLIENT_CFG_BASE_IDX 0
#define regIH_RING1_CLIENT_CFG_INDEX 0x0185
#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX 0
#define regIH_RING1_CLIENT_CFG_DATA 0x0186
#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX 0
#define regIH_CLIENT_CFG_INDEX 0x0188
#define regIH_CLIENT_CFG_INDEX_BASE_IDX 0
#define regIH_CLIENT_CFG_DATA 0x0189
#define regIH_CLIENT_CFG_DATA_BASE_IDX 0
#define regIH_CID_REMAP_INDEX 0x018b
#define regIH_CID_REMAP_INDEX_BASE_IDX 0
#define regIH_CID_REMAP_DATA 0x018c
#define regIH_CID_REMAP_DATA_BASE_IDX 0
#define regIH_CHICKEN 0x018d
#define regIH_CHICKEN_BASE_IDX 0
#define regIH_INT_DROP_CNTL 0x018f
#define regIH_INT_DROP_CNTL_BASE_IDX 0
#define regIH_INT_DROP_MATCH_VALUE0 0x0190
#define regIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0
#define regIH_INT_DROP_MATCH_VALUE1 0x0191
#define regIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0
#define regIH_INT_DROP_MATCH_MASK0 0x0192
#define regIH_INT_DROP_MATCH_MASK0_BASE_IDX 0
#define regIH_INT_DROP_MATCH_MASK1 0x0193
#define regIH_INT_DROP_MATCH_MASK1_BASE_IDX 0
#define regIH_REGISTER_LAST_PART1 0x019f
#define regIH_REGISTER_LAST_PART1_BASE_IDX 0
#endif
extra/amdpci/headers/osssys_6_0_0_sh_mask.h
+979
View File
@@ -0,0 +1,979 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _osssys_6_0_0_SH_MASK_HEADER
#define _osssys_6_0_0_SH_MASK_HEADER
// addressBlock: osssys_osssysdec
//IH_VMID_0_LUT
#define IH_VMID_0_LUT__PASID__SHIFT 0x0
#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_1_LUT
#define IH_VMID_1_LUT__PASID__SHIFT 0x0
#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_2_LUT
#define IH_VMID_2_LUT__PASID__SHIFT 0x0
#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_3_LUT
#define IH_VMID_3_LUT__PASID__SHIFT 0x0
#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_4_LUT
#define IH_VMID_4_LUT__PASID__SHIFT 0x0
#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_5_LUT
#define IH_VMID_5_LUT__PASID__SHIFT 0x0
#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_6_LUT
#define IH_VMID_6_LUT__PASID__SHIFT 0x0
#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_7_LUT
#define IH_VMID_7_LUT__PASID__SHIFT 0x0
#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_8_LUT
#define IH_VMID_8_LUT__PASID__SHIFT 0x0
#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_9_LUT
#define IH_VMID_9_LUT__PASID__SHIFT 0x0
#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_10_LUT
#define IH_VMID_10_LUT__PASID__SHIFT 0x0
#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_11_LUT
#define IH_VMID_11_LUT__PASID__SHIFT 0x0
#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_12_LUT
#define IH_VMID_12_LUT__PASID__SHIFT 0x0
#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_13_LUT
#define IH_VMID_13_LUT__PASID__SHIFT 0x0
#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_14_LUT
#define IH_VMID_14_LUT__PASID__SHIFT 0x0
#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_15_LUT
#define IH_VMID_15_LUT__PASID__SHIFT 0x0
#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL
//IH_VMID_0_LUT_MM
#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_1_LUT_MM
#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_2_LUT_MM
#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_3_LUT_MM
#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_4_LUT_MM
#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_5_LUT_MM
#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_6_LUT_MM
#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_7_LUT_MM
#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_8_LUT_MM
#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_9_LUT_MM
#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_10_LUT_MM
#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_11_LUT_MM
#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_12_LUT_MM
#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_13_LUT_MM
#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_14_LUT_MM
#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_VMID_15_LUT_MM
#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0
#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL
//IH_COOKIE_0
#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0
#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8
#define IH_COOKIE_0__RING_ID__SHIFT 0x10
#define IH_COOKIE_0__VM_ID__SHIFT 0x18
#define IH_COOKIE_0__RESERVED__SHIFT 0x1c
#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f
#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL
#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L
#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L
#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L
#define IH_COOKIE_0__RESERVED_MASK 0x70000000L
#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L
//IH_COOKIE_1
#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0
#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL
//IH_COOKIE_2
#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0
#define IH_COOKIE_2__RESERVED__SHIFT 0x10
#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f
#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL
#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L
#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L
//IH_COOKIE_3
#define IH_COOKIE_3__PAS_ID__SHIFT 0x0
#define IH_COOKIE_3__RESERVED__SHIFT 0x10
#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f
#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL
#define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L
#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L
//IH_COOKIE_4
#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0
#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL
//IH_COOKIE_5
#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0
#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL
//IH_COOKIE_6
#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0
#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL
//IH_COOKIE_7
#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0
#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL
//IH_REGISTER_LAST_PART0
#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0
#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL
//IH_RB_CNTL
#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa
#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb
#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc
#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11
#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12
#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14
#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15
#define IH_RB_CNTL__MC_RO__SHIFT 0x16
#define IH_RB_CNTL__MC_VMID__SHIFT 0x18
#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL
#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L
#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L
#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L
#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L
#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L
#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L
#define IH_RB_CNTL__MC_RO_MASK 0x00400000L
#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L
#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
//IH_RB_BASE
#define IH_RB_BASE__ADDR__SHIFT 0x0
#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL
//IH_RB_BASE_HI
#define IH_RB_BASE_HI__ADDR__SHIFT 0x0
#define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL
//IH_RB_RPTR
#define IH_RB_RPTR__OFFSET__SHIFT 0x2
#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL
//IH_RB_WPTR
#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
#define IH_RB_WPTR__OFFSET__SHIFT 0x2
#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL
#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L
#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L
//IH_RB_WPTR_ADDR_HI
#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL
//IH_RB_WPTR_ADDR_LO
#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
//IH_DOORBELL_RPTR
#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0
#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c
#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL
#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L
//IH_DOORBELL_RETRY_CAM
#define IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT 0x0
#define IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT 0x1c
#define IH_DOORBELL_RETRY_CAM__OFFSET_MASK 0x03FFFFFFL
#define IH_DOORBELL_RETRY_CAM__ENABLE_MASK 0x10000000L
//IH_RB_CNTL_RING1
#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0
#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1
#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9
#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa
#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb
#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc
#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12
#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14
#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16
#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18
#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c
#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L
#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL
#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L
#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L
#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L
#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L
#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L
#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L
#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L
#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L
#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L
#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
//IH_RB_BASE_RING1
#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0
#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL
//IH_RB_BASE_HI_RING1
#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0
#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL
//IH_RB_RPTR_RING1
#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2
#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL
//IH_RB_WPTR_RING1
#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0
#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2
#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12
#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13
#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L
#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL
#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L
#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L
//IH_DOORBELL_RPTR_RING1
#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0
#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c
#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL
#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L
//IH_RETRY_CAM_ACK
#define IH_RETRY_CAM_ACK__INDEX__SHIFT 0x0
#define IH_RETRY_CAM_ACK__INDEX_MASK 0x000003FFL
//IH_VERSION
#define IH_VERSION__MINVER__SHIFT 0x0
#define IH_VERSION__MAJVER__SHIFT 0x8
#define IH_VERSION__REV__SHIFT 0x10
#define IH_VERSION__MINVER_MASK 0x0000007FL
#define IH_VERSION__MAJVER_MASK 0x00007F00L
#define IH_VERSION__REV_MASK 0x003F0000L
//IH_CNTL
#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0
#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6
#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8
#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL
#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L
#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L
#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L
//IH_CNTL2
#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0
#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8
#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL
#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L
//IH_STATUS
#define IH_STATUS__IDLE__SHIFT 0x0
#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2
#define IH_STATUS__RB_FULL__SHIFT 0x3
#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
#define IH_STATUS__SWITCH_READY__SHIFT 0xb
#define IH_STATUS__RB1_FULL__SHIFT 0xc
#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd
#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe
#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12
#define IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT 0x13
#define IH_STATUS__ZSTATES_FENCE__SHIFT 0x14
#define IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT 0x15
#define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT 0x16
#define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT 0x17
#define IH_STATUS__IDLE_MASK 0x00000001L
#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L
#define IH_STATUS__RB_FULL_MASK 0x00000008L
#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
#define IH_STATUS__SWITCH_READY_MASK 0x00000800L
#define IH_STATUS__RB1_FULL_MASK 0x00001000L
#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L
#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L
#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L
#define IH_STATUS__RETRY_INT_CAM_IDLE_MASK 0x00080000L
#define IH_STATUS__ZSTATES_FENCE_MASK 0x00100000L
#define IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK 0x00200000L
#define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK 0x00400000L
#define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK 0x00800000L
//IH_PERFMON_CNTL
#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10
#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11
#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12
#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL
#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L
#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L
#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L
//IH_PERFCOUNTER0_RESULT
#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
//IH_PERFCOUNTER1_RESULT
#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL
//IH_DSM_MATCH_VALUE_BIT_31_0
#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL
//IH_DSM_MATCH_VALUE_BIT_63_32
#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL
//IH_DSM_MATCH_VALUE_BIT_95_64
#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL
//IH_DSM_MATCH_FIELD_CONTROL
#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6
#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L
#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L
#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L
#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L
#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L
#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L
#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L
//IH_DSM_MATCH_DATA_CONTROL
#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL
//IH_DSM_MATCH_FCN_ID
#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0
#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7
#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000000FL
#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L
//IH_LIMIT_INT_RATE_CNTL
#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0
#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1
#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5
#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11
#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15
#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L
#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL
#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L
#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L
#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L
//IH_VF_RB_STATUS
#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
//IH_VF_RB_STATUS2
#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0
#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
//IH_VF_RB1_STATUS
#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL
//IH_VF_RB1_STATUS2
#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0
#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL
//IH_RB_STATUS
#define IH_RB_STATUS__RB_FULL__SHIFT 0x0
#define IH_RB_STATUS__RB_FULL_DRAIN__SHIFT 0x1
#define IH_RB_STATUS__RB_OVERFLOW__SHIFT 0x2
#define IH_RB_STATUS__RB1_FULL__SHIFT 0x4
#define IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT 0x5
#define IH_RB_STATUS__RB1_OVERFLOW__SHIFT 0x6
#define IH_RB_STATUS__RB_FULL_MASK 0x00000001L
#define IH_RB_STATUS__RB_FULL_DRAIN_MASK 0x00000002L
#define IH_RB_STATUS__RB_OVERFLOW_MASK 0x00000004L
#define IH_RB_STATUS__RB1_FULL_MASK 0x00000010L
#define IH_RB_STATUS__RB1_FULL_DRAIN_MASK 0x00000020L
#define IH_RB_STATUS__RB1_OVERFLOW_MASK 0x00000040L
//IH_INT_FLOOD_CNTL
#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0
#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3
#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4
#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L
#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L
#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L
//IH_RB0_INT_FLOOD_STATUS
#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
//IH_RB1_INT_FLOOD_STATUS
#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0
#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f
#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL
#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L
//IH_INT_FLOOD_STATUS
#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d
#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e
#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L
#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L
#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L
//IH_STORM_CLIENT_LIST_CNTL
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L
#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L
//IH_CLK_CTRL
#define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x17
#define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT 0x18
#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19
#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a
#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b
#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c
#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e
#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f
#define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK 0x00800000L
#define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK 0x01000000L
#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L
#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L
#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L
#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L
#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L
#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L
#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L
//IH_INT_FLAGS
#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0
#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1
#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2
#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3
#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4
#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5
#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6
#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7
#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8
#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9
#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa
#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb
#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc
#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd
#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe
#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf
#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10
#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11
#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12
#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13
#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14
#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15
#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16
#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17
#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18
#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19
#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a
#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b
#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c
#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d
#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e
#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f
#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L
#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L
#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L
#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L
#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L
#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L
#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L
#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L
#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L
#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L
#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L
#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L
#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L
#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L
#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L
#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L
#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L
#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L
#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L
#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L
#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L
#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L
#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L
#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L
#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L
#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L
#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L
#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L
#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L
#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L
#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L
#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L
//IH_LAST_INT_INFO0
#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0
#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8
#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10
#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18
#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f
#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL
#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L
#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L
#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L
#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L
//IH_LAST_INT_INFO1
#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0
#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL
//IH_LAST_INT_INFO2
#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0
#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10
#define IH_LAST_INT_INFO2__VF__SHIFT 0x17
#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL
#define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L
#define IH_LAST_INT_INFO2__VF_MASK 0x00800000L
//IH_SCRATCH
#define IH_SCRATCH__DATA__SHIFT 0x0
#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL
//IH_CLIENT_CREDIT_ERROR
#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0
#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1
#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2
#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3
#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4
#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5
#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6
#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7
#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8
#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9
#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa
#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb
#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc
#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd
#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe
#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf
#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10
#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11
#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12
#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13
#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14
#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15
#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16
#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17
#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18
#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19
#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a
#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b
#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c
#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d
#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e
#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f
#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L
#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L
//IH_COOKIE_REC_VIOLATION_LOG
#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0
#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8
#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10
#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L
#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L
#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L
//IH_CREDIT_STATUS
#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1
#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2
#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3
#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4
#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5
#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6
#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7
#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8
#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9
#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa
#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb
#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc
#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd
#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe
#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf
#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10
#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11
#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12
#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13
#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14
#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15
#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16
#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17
#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18
#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19
#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a
#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b
#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c
#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d
#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e
#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f
#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L
#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L
#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L
#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L
#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L
#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L
#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L
#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L
#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L
#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L
#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L
#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L
#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L
#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L
#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L
#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L
#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L
#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L
#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L
#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L
#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L
#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L
#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L
#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L
#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L
#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L
#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L
#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L
#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L
#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L
#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L
//IH_MMHUB_ERROR
#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1
#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2
#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3
#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5
#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6
#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7
#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L
#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L
#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L
#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L
#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L
#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L
//IH_MEM_POWER_CTRL
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT 0x10
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT 0x11
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT 0x12
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT 0x13
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT 0x14
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x18
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK 0x00010000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK 0x00020000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK 0x00040000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK 0x00080000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK 0x00700000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F000000L
#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L
//IH_VF_RB_STATUS3
#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0
#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x0000FFFFL
//IH_VF_RB_STATUS4
#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0
#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x0000FFFFL
//IH_VF_RB1_STATUS3
#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0
#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x0000FFFFL
//IH_RETRY_INT_CAM_CNTL
#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0
#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8
#define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10
#define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE__SHIFT 0x11
#define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE__SHIFT 0x12
#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14
#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL
#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L
#define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L
#define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE_MASK 0x00020000L
#define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE_MASK 0x00040000L
#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L
//IH_MEM_POWER_CTRL2
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT 0x0
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT 0x1
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT 0x2
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT 0x3
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT 0x4
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x8
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK 0x00000001L
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK 0x00000002L
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK 0x00000004L
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK 0x00000008L
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK 0x00000070L
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F00L
#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L
//IH_MSI_STORM_CTRL
#define IH_MSI_STORM_CTRL__DELAY__SHIFT 0x0
#define IH_MSI_STORM_CTRL__DELAY_MASK 0x00000FFFL
//IH_MSI_STORM_CLIENT_INDEX
#define IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT 0x0
#define IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK 0x00000007L
//IH_MSI_STORM_CLIENT_DATA
#define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT 0x0
#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT 0x8
#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10
#define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE__SHIFT 0x11
#define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT 0x1f
#define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK 0x000000FFL
#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK 0x0000FF00L
#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L
#define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_MATCH_ENABLE_MASK 0x00020000L
#define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK 0x80000000L
//IH_REGISTER_LAST_PART2
#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
//SEM_MAILBOX
#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0
#define SEM_MAILBOX__RESERVED__SHIFT 0x10
#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL
#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L
//SEM_MAILBOX_CLEAR
#define SEM_MAILBOX_CLEAR__CLEAR__SHIFT 0x0
#define SEM_MAILBOX_CLEAR__RESERVED__SHIFT 0x10
#define SEM_MAILBOX_CLEAR__CLEAR_MASK 0x0000FFFFL
#define SEM_MAILBOX_CLEAR__RESERVED_MASK 0xFFFF0000L
//SEM_REGISTER_LAST_PART2
#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0
#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL
//IH_CLIENT_CFG
#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0
#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000003FL
//IH_RING1_CLIENT_CFG_INDEX
#define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0
#define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK 0x00000007L
//IH_RING1_CLIENT_CFG_DATA
#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT 0x0
#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT 0x8
#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10
#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK 0x000000FFL
#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK 0x0000FF00L
#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L
//IH_CLIENT_CFG_INDEX
#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0
#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL
//IH_CLIENT_CFG_DATA
#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12
#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16
#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19
#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L
#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L
#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L
//IH_CID_REMAP_INDEX
#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0
#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L
//IH_CID_REMAP_DATA
#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0
#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8
#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18
#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL
#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L
#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L
//IH_CHICKEN
#define IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT 0x2
#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3
#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4
#define IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK 0x00000004L
#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L
#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L
//IH_INT_DROP_CNTL
#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0
#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1
#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2
#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3
#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4
#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5
#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6
#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8
#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10
#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L
#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L
#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L
#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L
#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L
#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L
#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L
#define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L
#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L
//IH_INT_DROP_MATCH_VALUE0
#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0
#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8
#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10
#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17
#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18
#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL
#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L
#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L
#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L
#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L
//IH_INT_DROP_MATCH_VALUE1
#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0
#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL
//IH_INT_DROP_MATCH_MASK0
#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0
#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8
#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10
#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17
#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18
#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL
#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L
#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L
#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L
#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L
//IH_INT_DROP_MATCH_MASK1
#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0
#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL
//IH_REGISTER_LAST_PART1
#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0
#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL
#endif
extra/amdpci/headers/psp_gfx_if.h
+471
View File
@@ -0,0 +1,471 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _PSP_TEE_GFX_IF_H_
#define _PSP_TEE_GFX_IF_H_
#define PSP_GFX_CMD_BUF_VERSION 0x00000001
#define GFX_CMD_STATUS_MASK 0x0000FFFF
#define GFX_CMD_ID_MASK 0x000F0000
#define GFX_CMD_RESERVED_MASK 0x7FF00000
#define GFX_CMD_RESPONSE_MASK 0x80000000
/* USBC PD FW version retrieval command */
#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
/* TEE Gfx Command IDs for the register interface.
* Command ID must be between 0x00010000 and 0x000F0000.
*/
enum psp_gfx_crtl_cmd_id
{
GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */
GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
};
/*-----------------------------------------------------------------------------
NOTE: All physical addresses used in this interface are actually
GPU Virtual Addresses.
*/
/* Control registers of the TEE Gfx interface. These are located in
* SRBM-to-PSP mailbox registers (total 8 registers).
*/
struct psp_gfx_ctrl
{
volatile unsigned int cmd_resp; /* +0 Command/Response register for Gfx commands */
volatile unsigned int rbi_wptr; /* +4 Write pointer (index) of RBI ring */
volatile unsigned int rbi_rptr; /* +8 Read pointer (index) of RBI ring */
volatile unsigned int gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
volatile unsigned int gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
volatile unsigned int ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
volatile unsigned int ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
volatile unsigned int ring_buf_size; /* +28 Ring buffer size (in bytes) */
};
/* Response flag is set in the command when command is completed by PSP.
* Used in the GFX_CTRL.CmdResp.
* When PSP GFX I/F is initialized, the flag is set.
*/
#define GFX_FLAG_RESPONSE 0x80000000
/* TEE Gfx Command IDs for the ring buffer interface. */
enum psp_gfx_cmd_id
{
GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */
GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */
GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */
GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */
GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */
GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */
GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */
GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F, /* Query GPUVA of the Fw Attestation DB */
/* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */
GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */
GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */
GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027, /* Configure spatial partitioning mode */
};
/* PSP boot config sub-commands */
enum psp_gfx_boot_config_cmd
{
BOOTCFG_CMD_SET = 1, /* Set boot configuration settings */
BOOTCFG_CMD_GET = 2, /* Get boot configuration settings */
BOOTCFG_CMD_INVALIDATE = 3 /* Reset current boot configuration settings to VBIOS defaults */
};
/* PSP boot config bitmask values */
enum psp_gfx_boot_config
{
BOOT_CONFIG_GECC = 0x1,
};
/* Command to load Trusted Application binary into PSP OS. */
struct psp_gfx_cmd_load_ta
{
unsigned int app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
unsigned int app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */
unsigned int app_len; /* length of the TA binary in bytes */
unsigned int cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
unsigned int cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
unsigned int cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
/* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
* for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
* of using global persistent buffer.
*/
};
/* Command to Unload Trusted Application binary from PSP OS. */
struct psp_gfx_cmd_unload_ta
{
unsigned int session_id; /* Session ID of the loaded TA to be unloaded */
};
/* Shared buffers for InvokeCommand.
*/
struct psp_gfx_buf_desc
{
unsigned int buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
unsigned int buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
unsigned int buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
};
/* Max number of descriptors for one shared buffer (in how many different
* physical locations one shared buffer can be stored). If buffer is too much
* fragmented, error will be returned.
*/
#define GFX_BUF_MAX_DESC 64
struct psp_gfx_buf_list
{
unsigned int num_desc; /* number of buffer descriptors in the list */
unsigned int total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
/* total 776 bytes */
};
/* Command to execute InvokeCommand entry point of the TA. */
struct psp_gfx_cmd_invoke_cmd
{
unsigned int session_id; /* Session ID of the TA to be executed */
unsigned int ta_cmd_id; /* Command ID to be sent to TA */
struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
};
/* Command to setup TMR region. */
struct psp_gfx_cmd_setup_tmr
{
unsigned int buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
unsigned int buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
unsigned int buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
union {
struct {
unsigned int sriov_enabled:1; /* whether the device runs under SR-IOV*/
unsigned int virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/
unsigned int reserved:30;
} bitfield;
unsigned int tmr_flags;
};
unsigned int system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
unsigned int system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffer */
};
/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
enum psp_gfx_fw_type {
GFX_FW_TYPE_NONE = 0, /* */
GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */
GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */
GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
GFX_FW_TYPE_VCN = 13, /* VCN RV */
GFX_FW_TYPE_UVD = 14, /* UVD VG */
GFX_FW_TYPE_VCE = 15, /* VCE VG */
GFX_FW_TYPE_ISP = 16, /* ISP RV */
GFX_FW_TYPE_ACP = 17, /* ACP RV */
GFX_FW_TYPE_SMU = 18, /* SMU VG */
GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */
GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */
GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */
GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */
GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */
GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */
GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */
GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */
GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */
GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */
GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */
GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */
GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */
GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */
GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */
GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */
GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */
GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */
GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */
GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */
GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */
GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */
GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */
GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */
GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */
GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */
GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */
GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */
GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */
GFX_FW_TYPE_DMUB = 51, /* DMUB RN */
GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */
GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */
GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */
GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */
GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */
GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */
GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */
GFX_FW_TYPE_CAP = 62, /* CAP_FW */
GFX_FW_TYPE_SE2_TAP_DELAYS = 65, /* SE2 TAP DELAYS NV */
GFX_FW_TYPE_SE3_TAP_DELAYS = 66, /* SE3 TAP DELAYS NV */
GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */
GFX_FW_TYPE_IMU_I = 68, /* IMU Instruction FW SOC21 */
GFX_FW_TYPE_IMU_D = 69, /* IMU Data FW SOC21 */
GFX_FW_TYPE_LSDMA = 70, /* LSDMA FW SOC21 */
GFX_FW_TYPE_SDMA_UCODE_TH0 = 71, /* SDMA Thread 0/CTX SOC21 */
GFX_FW_TYPE_SDMA_UCODE_TH1 = 72, /* SDMA Thread 1/CTL SOC21 */
GFX_FW_TYPE_PPTABLE = 73, /* PPTABLE SOC21 */
GFX_FW_TYPE_DISCRETE_USB4 = 74, /* dUSB4 FW SOC21 */
GFX_FW_TYPE_TA = 75, /* SRIOV TA FW UUID SOC21 */
GFX_FW_TYPE_RS64_MES = 76, /* RS64 MES ucode SOC21 */
GFX_FW_TYPE_RS64_MES_STACK = 77, /* RS64 MES stack ucode SOC21 */
GFX_FW_TYPE_RS64_KIQ = 78, /* RS64 KIQ ucode SOC21 */
GFX_FW_TYPE_RS64_KIQ_STACK = 79, /* RS64 KIQ Heap stack SOC21 */
GFX_FW_TYPE_ISP_DATA = 80, /* ISP DATA SOC21 */
GFX_FW_TYPE_CP_MES_KIQ = 81, /* MES KIQ ucode SOC21 */
GFX_FW_TYPE_MES_KIQ_STACK = 82, /* MES KIQ stack SOC21 */
GFX_FW_TYPE_UMSCH_DATA = 83, /* User Mode Scheduler Data SOC21 */
GFX_FW_TYPE_UMSCH_UCODE = 84, /* User Mode Scheduler Ucode SOC21 */
GFX_FW_TYPE_UMSCH_CMD_BUFFER = 85, /* User Mode Scheduler Command Buffer SOC21 */
GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */
GFX_FW_TYPE_RS64_PFP = 87, /* RS64 PFP SOC21 */
GFX_FW_TYPE_RS64_ME = 88, /* RS64 ME SOC21 */
GFX_FW_TYPE_RS64_MEC = 89, /* RS64 MEC SOC21 */
GFX_FW_TYPE_RS64_PFP_P0_STACK = 90, /* RS64 PFP stack P0 SOC21 */
GFX_FW_TYPE_RS64_PFP_P1_STACK = 91, /* RS64 PFP stack P1 SOC21 */
GFX_FW_TYPE_RS64_ME_P0_STACK = 92, /* RS64 ME stack P0 SOC21 */
GFX_FW_TYPE_RS64_ME_P1_STACK = 93, /* RS64 ME stack P1 SOC21 */
GFX_FW_TYPE_RS64_MEC_P0_STACK = 94, /* RS64 MEC stack P0 SOC21 */
GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */
GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */
GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */
GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */
GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */
GFX_FW_TYPE_VPE = 102,
GFX_FW_TYPE_JPEG_RAM = 128, /**< JPEG Command buffer */
GFX_FW_TYPE_P2S_TABLE = 129,
GFX_FW_TYPE_MAX
};
/* Command to load HW IP FW. */
struct psp_gfx_cmd_load_ip_fw
{
unsigned int fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
unsigned int fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
unsigned int fw_size; /* FW buffer size in bytes */
enum psp_gfx_fw_type fw_type; /* FW type */
};
/* Command to save/restore HW IP FW. */
struct psp_gfx_cmd_save_restore_ip_fw
{
unsigned int save_fw; /* if set, command is used for saving fw otherwise for resetoring*/
unsigned int save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
unsigned int save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
unsigned int buf_size; /* Size of the save/restore buffer in bytes */
enum psp_gfx_fw_type fw_type; /* FW type */
};
/* Command to setup register program */
struct psp_gfx_cmd_reg_prog {
unsigned int reg_value;
unsigned int reg_id;
};
/* Command to load TOC */
struct psp_gfx_cmd_load_toc
{
unsigned int toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
unsigned int toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
unsigned int toc_size; /* FW buffer size in bytes */
};
/* Dynamic boot configuration */
struct psp_gfx_cmd_boot_cfg
{
unsigned int timestamp; /* calendar time as number of seconds */
enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process command data */
unsigned int boot_config; /* dynamic boot configuration bitmask */
unsigned int boot_config_valid; /* dynamic boot configuration valid bits bitmask */
};
struct psp_gfx_cmd_sriov_spatial_part {
unsigned int mode;
unsigned int override_ips;
unsigned int override_xcds_avail;
unsigned int override_this_aid;
};
/* All GFX ring buffer commands. */
union psp_gfx_commands
{
struct psp_gfx_cmd_load_ta cmd_load_ta;
struct psp_gfx_cmd_unload_ta cmd_unload_ta;
struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog;
struct psp_gfx_cmd_setup_tmr cmd_setup_vmr;
struct psp_gfx_cmd_load_toc cmd_load_toc;
struct psp_gfx_cmd_boot_cfg boot_cfg;
struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part;
};
struct psp_gfx_uresp_reserved
{
unsigned int reserved[8];
};
/* Command-specific response for Fw Attestation Db */
struct psp_gfx_uresp_fwar_db_info
{
unsigned int fwar_db_addr_lo;
unsigned int fwar_db_addr_hi;
};
/* Command-specific response for boot config. */
struct psp_gfx_uresp_bootcfg {
unsigned int boot_cfg; /* boot config data */
};
/* Union of command-specific responses for GPCOM ring. */
union psp_gfx_uresp {
struct psp_gfx_uresp_reserved reserved;
struct psp_gfx_uresp_bootcfg boot_cfg;
struct psp_gfx_uresp_fwar_db_info fwar_db_info;
};
/* Structure of GFX Response buffer.
* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
* it is separate buffer.
*/
struct psp_gfx_resp
{
unsigned int status; /* +0 status of command execution */
unsigned int session_id; /* +4 session ID in response to LoadTa command */
unsigned int fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
unsigned int fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
unsigned int tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
unsigned int reserved[11];
union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */
/* total 96 bytes */
};
/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
* and psp_gfx_rb_frame.cmd_buf_addr_lo.
*/
struct psp_gfx_cmd_resp
{
unsigned int buf_size; /* +0 total size of the buffer in bytes */
unsigned int buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
unsigned int cmd_id; /* +8 command ID */
/* These fields are used for RBI only. They are all 0 in GPCOM commands
*/
unsigned int resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
unsigned int resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */
unsigned int resp_offset; /* +20 offset within response buffer */
unsigned int resp_buf_size; /* +24 total size of the response buffer in bytes */
union psp_gfx_commands cmd; /* +28 command specific structures */
unsigned char reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
/* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
* is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
*/
struct psp_gfx_resp resp; /* +864 response */
unsigned char reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
/* total size 1024 bytes */
};
#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
/* Structure of the Ring Buffer Frame */
struct psp_gfx_rb_frame
{
unsigned int cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
unsigned int cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
unsigned int cmd_buf_size; /* +8 command buffer size in bytes */
unsigned int fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
unsigned int fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
unsigned int fence_value; /* +20 Fence value */
unsigned int sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
unsigned int sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
unsigned char vmid; /* +32 VMID value used for mapping of all addresses for this frame */
unsigned char frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
unsigned char reserved1[2]; /* +34 reserved, must be 0 */
unsigned int reserved2[7]; /* +36 reserved, must be 0 */
/* total 64 bytes */
};
#define PSP_ERR_UNKNOWN_COMMAND 0x00000100
enum tee_error_code {
TEE_SUCCESS = 0x00000000,
TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A,
};
#endif /* _PSP_TEE_GFX_IF_H_ */
extra/amdpci/headers/smu13_driver_if_v13_0_0.h
+1641
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extra/amdpci/headers/smu_v13_0_0_ppsmc.h
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/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU_V13_0_0_PPSMC_H
#define SMU_V13_0_0_PPSMC_H
#define PPSMC_VERSION 0x1
#define DEBUGSMC_VERSION 0x1
// SMU Response Codes:
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
// Message Definitions:
// BASIC
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
#define PPSMC_MSG_EnableAllSmuFeatures 0x6
#define PPSMC_MSG_DisableAllSmuFeatures 0x7
#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
#define PPSMC_MSG_GetRunningSmuFeaturesLow 0xC
#define PPSMC_MSG_GetRunningSmuFeaturesHigh 0xD
#define PPSMC_MSG_SetDriverDramAddrHigh 0xE
#define PPSMC_MSG_SetDriverDramAddrLow 0xF
#define PPSMC_MSG_SetToolsDramAddrHigh 0x10
#define PPSMC_MSG_SetToolsDramAddrLow 0x11
#define PPSMC_MSG_TransferTableSmu2Dram 0x12
#define PPSMC_MSG_TransferTableDram2Smu 0x13
#define PPSMC_MSG_UseDefaultPPTable 0x14
//BACO/BAMACO/BOMACO
#define PPSMC_MSG_EnterBaco 0x15
#define PPSMC_MSG_ExitBaco 0x16
#define PPSMC_MSG_ArmD3 0x17
#define PPSMC_MSG_BacoAudioD3PME 0x18
//DPM
#define PPSMC_MSG_SetSoftMinByFreq 0x19
#define PPSMC_MSG_SetSoftMaxByFreq 0x1A
#define PPSMC_MSG_SetHardMinByFreq 0x1B
#define PPSMC_MSG_SetHardMaxByFreq 0x1C
#define PPSMC_MSG_GetMinDpmFreq 0x1D
#define PPSMC_MSG_GetMaxDpmFreq 0x1E
#define PPSMC_MSG_GetDpmFreqByIndex 0x1F
#define PPSMC_MSG_OverridePcieParameters 0x20
//DramLog Set DramAddr
#define PPSMC_MSG_DramLogSetDramAddrHigh 0x21
#define PPSMC_MSG_DramLogSetDramAddrLow 0x22
#define PPSMC_MSG_DramLogSetDramSize 0x23
#define PPSMC_MSG_SetWorkloadMask 0x24
#define PPSMC_MSG_GetVoltageByDpm 0x25
#define PPSMC_MSG_SetVideoFps 0x26
#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x27
//Power Gating
#define PPSMC_MSG_AllowGfxOff 0x28
#define PPSMC_MSG_DisallowGfxOff 0x29
#define PPSMC_MSG_PowerUpVcn 0x2A
#define PPSMC_MSG_PowerDownVcn 0x2B
#define PPSMC_MSG_PowerUpJpeg 0x2C
#define PPSMC_MSG_PowerDownJpeg 0x2D
//Resets
#define PPSMC_MSG_PrepareMp1ForUnload 0x2E
#define PPSMC_MSG_Mode1Reset 0x2F
#define PPSMC_MSG_Mode2Reset 0x4F
//Set SystemVirtual DramAddrHigh
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x30
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x31
//ACDC Power Source
#define PPSMC_MSG_SetPptLimit 0x32
#define PPSMC_MSG_GetPptLimit 0x33
#define PPSMC_MSG_ReenableAcDcInterrupt 0x34
#define PPSMC_MSG_NotifyPowerSource 0x35
//BTC
#define PPSMC_MSG_RunDcBtc 0x36
//Debug
#define PPSMC_MSG_GetDebugData 0x37
//Others
#define PPSMC_MSG_SetTemperatureInputSelect 0x38
#define PPSMC_MSG_SetFwDstatesMask 0x39
#define PPSMC_MSG_SetThrottlerMask 0x3A
#define PPSMC_MSG_SetExternalClientDfCstateAllow 0x3B
#define PPSMC_MSG_SetMGpuFanBoostLimitRpm 0x3C
//STB to dram log
#define PPSMC_MSG_DumpSTBtoDram 0x3D
#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3E
#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3F
#define PPSMC_MSG_STBtoDramLogSetDramSize 0x40
#define PPSMC_MSG_SetGpoAllow 0x41
#define PPSMC_MSG_AllowGfxDcs 0x42
#define PPSMC_MSG_DisallowGfxDcs 0x43
#define PPSMC_MSG_EnableAudioStutterWA 0x44
#define PPSMC_MSG_PowerUpUmsch 0x45
#define PPSMC_MSG_PowerDownUmsch 0x46
#define PPSMC_MSG_SetDcsArch 0x47
#define PPSMC_MSG_TriggerVFFLR 0x48
#define PPSMC_MSG_SetNumBadMemoryPagesRetired 0x49
#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A
#define PPSMC_MSG_SetPriorityDeltaGain 0x4B
#define PPSMC_MSG_AllowIHHostInterrupt 0x4C
#define PPSMC_MSG_DALNotPresent 0x4E
#define PPSMC_MSG_EnableUCLKShadow 0x51
#define PPSMC_Message_Count 0x52
//Debug Dump Message
#define DEBUGSMC_MSG_TestMessage 0x1
#define DEBUGSMC_MSG_GetDebugData 0x2
#define DEBUGSMC_MSG_DebugDumpExit 0x3
#define DEBUGSMC_Message_Count 0x4
#endif
extra/amdpci/headers/soc15_ih_clientid.h
+113
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/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SOC15_IH_CLIENTID_H__
#define __SOC15_IH_CLIENTID_H__
/*
* Vega10+ IH clients
* Whenever this structure is updated, which should not happen, make sure
* soc15_ih_clientid_name in the below is also updated accordingly.
*/
enum soc15_ih_clientid {
SOC15_IH_CLIENTID_IH = 0x00,
SOC15_IH_CLIENTID_ACP = 0x01,
SOC15_IH_CLIENTID_ATHUB = 0x02,
SOC15_IH_CLIENTID_BIF = 0x03,
SOC15_IH_CLIENTID_DCE = 0x04,
SOC15_IH_CLIENTID_ISP = 0x05,
SOC15_IH_CLIENTID_PCIE0 = 0x06,
SOC15_IH_CLIENTID_RLC = 0x07,
SOC15_IH_CLIENTID_SDMA0 = 0x08,
SOC15_IH_CLIENTID_SDMA1 = 0x09,
SOC15_IH_CLIENTID_SE0SH = 0x0a,
SOC15_IH_CLIENTID_SE1SH = 0x0b,
SOC15_IH_CLIENTID_SE2SH = 0x0c,
SOC15_IH_CLIENTID_SE3SH = 0x0d,
SOC15_IH_CLIENTID_UVD1 = 0x0e,
SOC15_IH_CLIENTID_THM = 0x0f,
SOC15_IH_CLIENTID_UVD = 0x10,
SOC15_IH_CLIENTID_VCE0 = 0x11,
SOC15_IH_CLIENTID_VMC = 0x12,
SOC15_IH_CLIENTID_XDMA = 0x13,
SOC15_IH_CLIENTID_GRBM_CP = 0x14,
SOC15_IH_CLIENTID_ATS = 0x15,
SOC15_IH_CLIENTID_ROM_SMUIO = 0x16,
SOC15_IH_CLIENTID_DF = 0x17,
SOC15_IH_CLIENTID_VCE1 = 0x18,
SOC15_IH_CLIENTID_PWR = 0x19,
SOC15_IH_CLIENTID_RESERVED = 0x1a,
SOC15_IH_CLIENTID_UTCL2 = 0x1b,
SOC15_IH_CLIENTID_EA = 0x1c,
SOC15_IH_CLIENTID_UTCL2LOG = 0x1d,
SOC15_IH_CLIENTID_MP0 = 0x1e,
SOC15_IH_CLIENTID_MP1 = 0x1f,
SOC15_IH_CLIENTID_MAX,
SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD,
SOC15_IH_CLIENTID_VCN1 = SOC15_IH_CLIENTID_UVD1,
SOC15_IH_CLIENTID_SDMA2 = SOC15_IH_CLIENTID_ACP,
SOC15_IH_CLIENTID_SDMA3 = SOC15_IH_CLIENTID_DCE,
SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid = SOC15_IH_CLIENTID_ISP,
SOC15_IH_CLIENTID_SDMA4 = SOC15_IH_CLIENTID_ISP,
SOC15_IH_CLIENTID_SDMA5 = SOC15_IH_CLIENTID_VCE0,
SOC15_IH_CLIENTID_SDMA6 = SOC15_IH_CLIENTID_XDMA,
SOC15_IH_CLIENTID_SDMA7 = SOC15_IH_CLIENTID_VCE1,
SOC15_IH_CLIENTID_VMC1 = SOC15_IH_CLIENTID_PCIE0,
};
extern const char *soc15_ih_clientid_name[];
/*
* soc21 IH clients
*/
enum soc21_ih_clientid {
SOC21_IH_CLIENTID_IH = 0x00,
SOC21_IH_CLIENTID_ATHUB = 0x02,
SOC21_IH_CLIENTID_BIF = 0x03,
SOC21_IH_CLIENTID_DCN = 0x04,
SOC21_IH_CLIENTID_ISP = 0x05,
SOC21_IH_CLIENTID_MP3 = 0x06,
SOC21_IH_CLIENTID_RLC = 0x07,
SOC21_IH_CLIENTID_GFX = 0x0a,
SOC21_IH_CLIENTID_IMU = 0x0b,
SOC21_IH_CLIENTID_VCN1 = 0x0e,
SOC21_IH_CLIENTID_THM = 0x0f,
SOC21_IH_CLIENTID_VCN = 0x10,
SOC21_IH_CLIENTID_VPE1 = 0x11,
SOC21_IH_CLIENTID_VMC = 0x12,
SOC21_IH_CLIENTID_GRBM_CP = 0x14,
SOC21_IH_CLIENTID_ROM_SMUIO = 0x16,
SOC21_IH_CLIENTID_DF = 0x17,
SOC21_IH_CLIENTID_VPE = 0x18,
SOC21_IH_CLIENTID_PWR = 0x19,
SOC21_IH_CLIENTID_LSDMA = 0x1a,
SOC21_IH_CLIENTID_MP0 = 0x1e,
SOC21_IH_CLIENTID_MP1 = 0x1f,
SOC21_IH_CLIENTID_MAX,
};
#endif
extra/amdpci/headers/soc21_enum.h
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extra/amdpci/headers/v11_structs.h
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extra/amdpci/proclogs.py
+56
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import re, ctypes, sys
from tinygrad.runtime.autogen import libpciaccess
from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0
def parse_amdgpu_logs(log_content, register_names=None):
register_map = register_names or REGISTER_NAMES
final = ""
def replace_register(match):
register = match.group(1)
return f"Reading register {register_map.get(int(register, base=16), register)}"
pattern = r'Reading register (0x[0-9a-fA-F]+)'
processed_log = re.sub(pattern, replace_register, log_content)
def replace_register_2(match):
register = match.group(1)
return f"Writing register {register_map.get(int(register, base=16), register)}"
pattern = r'Writing register (0x[0-9a-fA-F]+)'
processed_log = re.sub(pattern, replace_register_2, processed_log)
lines = processed_log.split('\n')
in_trace = False
cleaned_lines = []
return '\n'.join(cleaned_lines)
def main():
regs_offset = {13: {0: [3072, 37784576]}, 28: {0: [93184, 37754880], 1: [201327616, 201461760], 2: [209716224, 209850368], 3: [218104832, 218238976], 4: [226493440, 226627584], 5: [234882048, 235016192], 6: [243270656, 243404800]}, 21: {0: [28672, 12582912, 37795840, 130023424, 306184192], 1: [201326592, 201463808, 201465856, 204210176, 204472320], 2: [209715200, 209852416, 209854464, 212598784, 212860928], 3: [218103808, 218241024, 218243072, 220987392, 221249536], 4: [226492416, 226629632, 226631680, 229376000, 229638144], 5: [234881024, 235018240, 235020288, 237764608, 238026752], 6: [243269632, 243406848, 243408896, 246153216, 246415360]}, 22: {0: [18, 192, 13504, 36864, 37764096]}, 1: {0: [4704, 40960, 114688, 37760000]}, 2: {0: [3872, 37790720]}, 11: {0: [70656, 38103040]}, 12: {0: [106496, 37783552]}, 15: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 16: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 14: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 26: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 23: {0: [4256, 37789696]}, 33: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 25: {0: []}, 3: {0: [4704, 40960, 114688, 37760000]}, 4: {0: [4704, 40960, 114688, 37760000]}, 24: {0: [92160, 92672, 37752832, 54788096]}, 27: {0: [91648, 37751808], 1: [201339904, 201458176], 2: [209728512, 209846784], 3: [218117120, 218235392], 4: [226505728, 226624000], 5: [234894336, 235012608], 6: [243282944, 243401216]}, 29: {0: [201342976, 201344000, 205520896, 205537280], 1: [209731584, 209732608, 213909504, 213925888], 2: [218120192, 218121216, 222298112, 222314496], 3: [226508800, 226509824, 230686720, 230703104], 4: [234897408, 234898432, 239075328, 239091712], 5: [243286016, 243287040, 247463936, 247480320]}, 17: {0: [30720, 32256], 1: [31488, 73728]}}
def _prepare_registers(modules):
for base, m in modules:
for k, regval in m.__dict__.items():
if k.startswith("reg") and not k.endswith("_BASE_IDX") and (base_idx:=getattr(m, f"{k}_BASE_IDX", None)) is not None:
REGISTER_NAMES[regs_offset[am.__dict__.get(f"{base}_HWIP")][0][base_idx] + regval] = k
_prepare_registers([("MP0", mp_13_0_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)])
with open(sys.argv[1], 'r') as f:
log_content = log_content_them = f.read()
processed_log = parse_amdgpu_logs(log_content)
with open(sys.argv[2], 'w') as f:
f.write(processed_log)
if __name__ == '__main__':
if len(sys.argv) != 3:
print("Usage: <input_file_path> <output_file_path>")
sys.exit(1)
main()
setup.py
+1 -1
View File
@@ -15,7 +15,7 @@ setup(name='tinygrad',
long_description=long_description,
long_description_content_type='text/markdown',
packages = ['tinygrad', 'tinygrad.runtime.autogen', 'tinygrad.codegen', 'tinygrad.nn', 'tinygrad.renderer', 'tinygrad.engine',
'tinygrad.runtime', 'tinygrad.runtime.support', 'tinygrad.runtime.graph', 'tinygrad.shape'],
'tinygrad.runtime', 'tinygrad.runtime.support', 'tinygrad.runtime.support.am', 'tinygrad.runtime.graph', 'tinygrad.shape'],
package_data = {'tinygrad': ['py.typed']},
classifiers=[
"Programming Language :: Python :: 3",
test/external/external_fuzz_ampt.py
Vendored
+104
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@@ -0,0 +1,104 @@
import random
from tinygrad.helpers import round_up
from tinygrad.runtime.support.am.amdev import AMMemoryManager
from test.external.external_test_am import helper_read_entry_components, FakeAM
class AMPTFuzzer:
def __init__(self, total_size):
self.total_size = total_size
self.alloc_payload = 0
self.d = FakeAM()
self.allocations: dict[int, tuple[int, int]] = {} # ptr -> (size, pattern)
self.min_alloc_size = 0x1000
self.max_alloc_size = int(total_size * 0.1)
self.alloc_probability = 0.7
def generate_pattern(self, ptr: int, size: int) -> int: return random.randint(0, 0xff)
def fill_memory(self, va, size: int, pattern: int):
internal_va = va.va_addr - AMMemoryManager.va_allocator.base
pages = list(self.d.mm.page_table_walker(self.d.mm.root_page_table, vaddr=internal_va, size=size))
for _vaddr, _offset, _pte_idx, _n_ptes, _pte_covers, _pt in pages:
for i in range(_n_ptes):
pte = helper_read_entry_components(_pt.get_entry(_pte_idx + i))
self.d.vram[pte['paddr']] = pattern # Mark this page
assert pte['valid'] == 1
# If page has contigous fragment, all range should be this valid memory
frags_cnt = pte['fragment']
contig_range = (1 << (frags_cnt + 12))
start_vaddr = _vaddr & ~(contig_range - 1)
start_paddr = pte['paddr'] - (_vaddr - start_vaddr)
contig_ptes = contig_range // _pte_covers
assert contig_ptes > 0
frags_l = list(self.d.mm.page_table_walker(self.d.mm.root_page_table, vaddr=start_vaddr, size=contig_range))
for f_vaddr, f_offset, f_pte_idx, f_n_ptes, f_pte_covers, f_pt in frags_l:
for j in range(f_n_ptes):
f_pte = helper_read_entry_components(f_pt.get_entry(f_pte_idx + j))
assert f_pte['valid'] == 1
assert f_pte['paddr'] == start_paddr+f_offset+j*f_pte_covers, f"paddr {f_pte['paddr']:#x} not {start_paddr+f_offset+j*f_pte_covers:#x}"
_vaddr += _pte_covers
_offset += _pte_covers
return pages
def verify_memory(self, pages, pattern: int) -> bool:
for _vaddr, _offset, _pte_idx, _n_ptes, _pte_covers, _pt in pages:
for i in range(_n_ptes):
pte = helper_read_entry_components(_pt.get_entry(_pte_idx + i))
if self.d.vram[pte['paddr']] != pattern: return False
if pte['valid'] == 0: return False
return True
def random_alloc(self):
if self.total_size - self.alloc_payload < self.min_alloc_size: return None
size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload))
size = round_up(size, (2 << 20) if size > (4 << 20) else (4 << 10))
try: ptr = self.d.mm.valloc(size)
except MemoryError:
print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%")
return None
pattern = self.generate_pattern(ptr, size)
pages = self.fill_memory(ptr, size, pattern)
self.allocations[ptr] = (size, pattern, pages)
self.alloc_payload += size
print(f"Allocated {size} bytes at {ptr.va_addr:x}, pattern: {pattern:02x}")
return ptr
def random_free(self) -> bool:
if not self.allocations: return False
ptr = random.choice(list(self.allocations.keys()))
size, pattern, pages = self.allocations[ptr]
# Verify pattern before freeing
if not self.verify_memory(pages, pattern):
raise RuntimeError(f"Memory corruption detected at {ptr.va_addr:x}!")
print(f"Freeing {size} bytes at {ptr.va_addr:x}, pattern verified: {pattern:02x}")
self.alloc_payload -= size
self.d.mm.vfree(ptr)
del self.allocations[ptr]
return True
def run(self):
for i in range(10000000):
if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc()
else: self.random_free()
print("\nCleaning up remaining allocations...")
while self.allocations: self.random_free()
print("Fuzzing completed successfully!")
if __name__ == "__main__":
fuzzer = AMPTFuzzer(1 << 30)
fuzzer.run()
test/external/external_fuzz_tlsf.py
Vendored
+76
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@@ -0,0 +1,76 @@
import random
from typing import Dict, Optional
from tinygrad.runtime.support.allocator import TLSFAllocator
class AllocatorFuzzer:
def __init__(self, total_size):
self.total_size = total_size
self.alloc_payload = 0
self.mv = memoryview(bytearray(total_size))
self.alloctor = TLSFAllocator(total_size, block_size=16)
self.allocations: Dict[int, tuple[int, int]] = {} # ptr -> (size, pattern)
self.min_alloc_size = 16
self.max_alloc_size = int(total_size * 0.3)
self.alloc_probability = 0.7
def generate_pattern(self, ptr: int, size: int) -> int: return (ptr * 31 + size * 17) & 0xFF
def fill_memory(self, ptr: int, size: int, pattern: int):
for i in range(min(size, 32)):
self.mv[ptr + i] = pattern
self.mv[ptr + (size - 1 - i)] = pattern
def verify_memory(self, ptr: int, size: int, pattern: int) -> bool:
for i in range(min(size, 32)):
assert self.mv[ptr + i] == pattern
assert self.mv[ptr + (size - 1 - i)] == pattern
return True
def random_alloc(self) -> Optional[int]:
size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload))
try:
ptr = self.alloctor.alloc(size)
except MemoryError:
print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%")
return None
pattern = self.generate_pattern(ptr, size)
self.fill_memory(ptr, size, pattern)
self.allocations[ptr] = (size, pattern)
self.alloc_payload += size
print(f"Allocated {size} bytes at {ptr:x}, pattern: {pattern:02x}")
return ptr
def random_free(self) -> bool:
if not self.allocations: return False
ptr = random.choice(list(self.allocations.keys()))
size, pattern = self.allocations[ptr]
# Verify pattern before freeing
if not self.verify_memory(ptr, size, pattern):
raise RuntimeError(f"Memory corruption detected at {ptr:x}!")
print(f"Freeing {size} bytes at {ptr:x}, pattern verified: {pattern:02x}")
self.alloc_payload -= size
self.alloctor.free(ptr)
del self.allocations[ptr]
return True
def run(self):
for i in range(10000000):
if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc()
else: self.random_free()
print("\nCleaning up remaining allocations...")
while self.allocations: self.random_free()
print("Fuzzing completed successfully!")
if __name__ == "__main__":
fuzzer = AllocatorFuzzer(1 << 30)
fuzzer.run()
test/external/external_test_am.py
Vendored
+162
View File
@@ -0,0 +1,162 @@
import unittest
from tinygrad.runtime.support.am.amdev import AMMemoryManager
class FakeGMC:
def flush_tlb(self, *args, **kwargs): pass
class FakePCIRegion:
def __init__(self): self.base_addr = 0xc12300000000
class FakePCIDev:
def __init__(self): self.regions = [FakePCIRegion()]
class FakeAM:
def __init__(self):
self.pcidev = FakePCIDev()
self.vram = memoryview(bytearray(4 << 30))
self.gmc = FakeGMC()
self.mm = AMMemoryManager(self, vram_size=4 << 30)
# * PTE format:
# * 63:59 reserved
# * 58:57 reserved
# * 56 F
# * 55 L
# * 54 reserved
# * 53:52 SW
# * 51 T
# * 50:48 mtype
# * 47:12 4k physical page base address
# * 11:7 fragment
# * 6 write
# * 5 read
# * 4 exe
# * 3 Z
# * 2 snooped
# * 1 system
# * 0 valid
def helper_read_entry_components(entry_val):
return {"paddr": entry_val & 0x0000FFFFFFFFF000, "fragment":(entry_val >> 7) & 0x1f, "valid": entry_val & 0x1,
"read": (entry_val >> 5) & 0x1, "write": (entry_val >> 6) & 0x1, "exec": (entry_val >> 4) & 0x1,
"mtype": (entry_val >> 48) & 0x7, "T": (entry_val >> 51) & 0x1, "L": (entry_val >> 55) & 0x1, "F": (entry_val >> 56) & 0x1}
class TestAMPageTable(unittest.TestCase):
@classmethod
def setUpClass(cls):
cls.d = [FakeAM() for _ in range(2)]
def test_page_table_walkers(self):
mm = self.d[0].mm
for va,sz in [(0x10000, 0x3000), (0x11000, 0x300000), (0x10000, 0x2000), (0x11000, 0x5000),
(0x2000000, 0x2000), (0x4000000, 0x4000000), (0x38000, 0x303000), (0x8000, 0x1000)]:
exteranl_va = va + AMMemoryManager.va_allocator.base
mm.map_range(vaddr=exteranl_va, size=sz, paddr=va)
results = list(mm.page_table_walker(mm.root_page_table, vaddr=va, size=sz))
total_covered = 0
for tup in results:
_vaddr, _offset, _pte_idx, _n_ptes, _pte_covers, _pt = tup
total_covered += _n_ptes * _pte_covers
assert total_covered == sz, f"Expected total coverage {total_covered} to be {sz}"
for tup in results:
_vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup
for i in range(n_ptes):
pte = helper_read_entry_components(pt.get_entry(pte_idx + i))
assert pte['paddr'] == va + _offset + i * pte_covers, f"Expected paddr {pte['paddr']:#x} to be {va + _offset + i * pte_covers:#x}"
assert pte['valid'] == 1
mm.unmap_range(va, sz, free_paddrs=False)
for tup in results:
_vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup
for i in range(n_ptes):
pte = helper_read_entry_components(pt.get_entry(pte_idx + i))
assert pte['paddr'] == 0
assert pte['valid'] == 0
def test_double_map(self):
mm0 = self.d[0].mm
for va,sz in [(0x10000, 0x3000), (0x1000000, 0x1000000), (0x12000, 0x4000)]:
exteranl_va = va + AMMemoryManager.va_allocator.base
mm0.map_range(vaddr=exteranl_va, size=sz, paddr=va)
with self.assertRaises(AssertionError):
mm0.map_range(vaddr=exteranl_va, size=0x1000, paddr=va)
with self.assertRaises(AssertionError):
mm0.map_range(vaddr=exteranl_va, size=0x100000, paddr=va)
with self.assertRaises(AssertionError):
mm0.map_range(vaddr=exteranl_va + 0x1000, size=0x1000, paddr=va)
with self.assertRaises(AssertionError):
mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddr=va)
mm0.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False)
# Finally can map and check paddrs
mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddr=0xdead0000)
for tup in mm0.page_table_walker(mm0.root_page_table, vaddr=va + 0x2000, size=0x100000):
_vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup
for i in range(n_ptes):
pte = helper_read_entry_components(pt.get_entry(pte_idx + i))
assert pte['paddr'] == 0xdead0000 + _offset + i * pte_covers, f"paddr {pte['paddr']:#x} not {0xdead0000 + _offset + i * pte_covers:#x}"
assert pte['valid'] == 1
mm0.unmap_range(vaddr=exteranl_va + 0x2000, size=0x100000, free_paddrs=False)
def test_map_from(self):
mm0 = self.d[0].mm
mm1 = self.d[1].mm
for va,sz in [(0x10000, 0x3000), (0x11000, 0x300000), (0x10000, 0x2000), (0x11000, 0x5000),
(0x2000000, 0x2000), (0x4000000, 0x4000000), (0x38000, 0x303000), (0x8000, 0x1000)]:
exteranl_va = va + AMMemoryManager.va_allocator.base
mm0.map_range(vaddr=exteranl_va, size=sz, paddr=va)
mm1.map_range(vaddr=exteranl_va, size=sz, paddr=va)
with self.assertRaises(AssertionError):
mm0.map_from(vaddr=exteranl_va, size=sz, from_adev=mm0.adev) # self mapping -- bad
with self.assertRaises(AssertionError):
mm0.map_from(vaddr=exteranl_va, size=sz, from_adev=mm1.adev) # mapping from mm1 to same addrs -- bad
mm0.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False) # unmap from mm0
mm0.map_from(vaddr=exteranl_va, size=sz, from_adev=mm1.adev) # mapping from mm1 to same addrs -- ok
d1_pci_base = self.d[1].pcidev.regions[0].base_addr
for tup in mm0.page_table_walker(mm0.root_page_table, vaddr=va, size=sz):
_vaddr, _offset, pte_idx, n_ptes, pte_covers, pt = tup
for i in range(n_ptes):
pte = helper_read_entry_components(pt.get_entry(pte_idx + i))
assert pte['paddr'] == d1_pci_base + va + _offset + i * pte_covers, f"paddr {pte['paddr']:#x} not {d1_pci_base+va+_offset+i*pte_covers:#x}"
assert pte['valid'] == 1
mm0.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False)
mm1.unmap_range(vaddr=exteranl_va, size=sz, free_paddrs=False)
def test_try_bad_unmap(self):
mm0 = self.d[0].mm
with self.assertRaises(AssertionError):
mm0.unmap_range(0x10000, 0x3000, free_paddrs=False)
mm0.map_range(0x10000, 0x3000, 0x10000)
mm0.unmap_range(0x10000, 0x3000, free_paddrs=False)
with self.assertRaises(AssertionError):
mm0.unmap_range(0x10000, 0x3000, free_paddrs=False)
mm0.map_range(0x10000, 0x3000, 0x10000)
mm0.unmap_range(0x10000, 0x3000, free_paddrs=False)
with self.assertRaises(AssertionError):
mm0.unmap_range(0x10000, 0x3000, free_paddrs=False)
if __name__ == "__main__":
unittest.main()
test/external/external_test_tlsf.py
Vendored
+78
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@@ -0,0 +1,78 @@
import unittest
from tinygrad.runtime.support.allocator import TLSFAllocator
class TestTLSFAllocator(unittest.TestCase):
def setUp(self):
self.allocator = TLSFAllocator(1024, block_size=16)
def test_basic_alloc_free(self):
addr1 = self.allocator.alloc(32)
self.assertEqual(addr1, 0)
addr2 = self.allocator.alloc(64)
self.assertEqual(addr2, 32)
self.allocator.free(addr1)
addr3 = self.allocator.alloc(32)
self.assertEqual(addr3, 0)
def test_block_size_alignment(self):
addr1 = self.allocator.alloc(20)
addr2 = self.allocator.alloc(35)
self.assertEqual(addr1 % 16, 0)
self.assertEqual(addr2 % 16, 0)
def test_merge_blocks(self):
addr1 = self.allocator.alloc(32)
addr2 = self.allocator.alloc(32)
self.allocator.alloc(32)
self.allocator.free(addr1)
self.allocator.free(addr2)
addr4 = self.allocator.alloc(64)
self.assertEqual(addr4, addr1)
def test_split_blocks(self):
addr1 = self.allocator.alloc(128)
self.allocator.free(addr1)
addr2 = self.allocator.alloc(32)
self.assertEqual(addr2, addr1)
addr3 = self.allocator.alloc(32)
self.assertEqual(addr3, addr1 + 32)
def test_out_of_memory(self):
with self.assertRaises(MemoryError):
self.allocator.alloc(2048)
def test_fragmentation_handling(self):
addrs = []
for _ in range(5):
addrs.append(self.allocator.alloc(32))
# Free alternate blocks
for i in range(0, len(addrs), 2):
self.allocator.free(addrs[i])
def test_custom_start_address(self):
allocator = TLSFAllocator(1024, start_addr=1000)
addr1 = allocator.alloc(32)
self.assertEqual(addr1, 1000)
addr2 = allocator.alloc(64)
self.assertEqual(addr2, 1032)
def test_block_tracking(self):
addr1 = self.allocator.alloc(32)
addr2 = self.allocator.alloc(64)
self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks])
self.assertTrue(addr2 in [addr - self.allocator.start_addr for addr in self.allocator.blocks])
self.allocator.free(addr1)
self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks])
if __name__ == '__main__':
unittest.main()
test/mockgpu/amd/amddriver.py
+1
View File
@@ -76,6 +76,7 @@ class AMDDriver(VirtDriver):
self.doorbells[gpu_id] = memoryview(bytearray(0x2000))
self.gpus[gpu_id] = AMDGPU(gpu_id)
self.tracked_files += [
VirtFile('/sys/module/amdgpu', functools.partial(TextFileDesc, text="1")),
VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}', functools.partial(DirFileDesc, child_names=['gpu_id', 'properties'])),
VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/gpu_id', functools.partial(TextFileDesc, text=f"{gpu_id}")),
VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/properties',
tinygrad/helpers.py
+2
View File
@@ -43,6 +43,8 @@ def fromimport(mod, frm): return getattr(__import__(mod, fromlist=[frm]), frm)
def strip_parens(fst:str): return fst[1:-1] if fst[0] == '(' and fst[-1] == ')' and fst[1:-1].find('(') <= fst[1:-1].find(')') else fst
def ceildiv(num, amt): return int(ret) if isinstance((ret:=-(num//-amt)), float) else ret
def round_up(num:int, amt:int) -> int: return (num+amt-1)//amt * amt
def lo32(x:Any) -> Any: return x & 0xFFFFFFFF # Any is sint
def hi32(x:Any) -> Any: return x >> 32 # Any is sint
def data64(data:Any) -> tuple[Any, Any]: return (data >> 32, data & 0xFFFFFFFF) # Any is sint
def data64_le(data:Any) -> tuple[Any, Any]: return (data & 0xFFFFFFFF, data >> 32) # Any is sint
def merge_dicts(ds:Iterable[dict[T,U]]) -> dict[T,U]:
tinygrad/runtime/autogen/am/am.py
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tinygrad/runtime/autogen/am/gc_11_0_0.py
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tinygrad/runtime/autogen/am/mmhub_3_0_0.py
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tinygrad/runtime/autogen/am/mp_11_0.py
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tinygrad/runtime/autogen/libpciaccess.py
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tinygrad/runtime/autogen/vfio.py
+891
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@@ -0,0 +1,891 @@
# mypy: ignore-errors
# -*- coding: utf-8 -*-
#
# TARGET arch is: []
# WORD_SIZE is: 8
# POINTER_SIZE is: 8
# LONGDOUBLE_SIZE is: 16
#
import ctypes
import fcntl, functools
def _do_ioctl_io(__idir, __base, __nr, __fd, val=0, __len=0):
return fcntl.ioctl(__fd, (__idir<<30) | (__len<<16) | (__base<<8) | __nr, val)
def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, __val=None, **kwargs):
ret = fcntl.ioctl(__fd, (__idir<<30) | (ctypes.sizeof(made := (__made or __user_struct(**kwargs)))<<16) | (__base<<8) | __nr, made)
if ret != 0: raise RuntimeError(f"ioctl returned {ret}")
return made
def _IO(base, nr): return functools.partial(_do_ioctl_io, 0, ord(base) if isinstance(base, str) else base, nr)
def _IOW(base, nr, type): return functools.partial(_do_ioctl, 1, ord(base) if isinstance(base, str) else base, nr, type)
def _IOR(base, nr, type): return functools.partial(_do_ioctl, 2, ord(base) if isinstance(base, str) else base, nr, type)
def _IOWR(base, nr, type): return functools.partial(_do_ioctl, 3, ord(base) if isinstance(base, str) else base, nr, type)
class AsDictMixin:
@classmethod
def as_dict(cls, self):
result = {}
if not isinstance(self, AsDictMixin):
# not a structure, assume it's already a python object
return self
if not hasattr(cls, "_fields_"):
return result
# sys.version_info >= (3, 5)
# for (field, *_) in cls._fields_: # noqa
for field_tuple in cls._fields_: # noqa
field = field_tuple[0]
if field.startswith('PADDING_'):
continue
value = getattr(self, field)
type_ = type(value)
if hasattr(value, "_length_") and hasattr(value, "_type_"):
# array
if not hasattr(type_, "as_dict"):
value = [v for v in value]
else:
type_ = type_._type_
value = [type_.as_dict(v) for v in value]
elif hasattr(value, "contents") and hasattr(value, "_type_"):
# pointer
try:
if not hasattr(type_, "as_dict"):
value = value.contents
else:
type_ = type_._type_
value = type_.as_dict(value.contents)
except ValueError:
# nullptr
value = None
elif isinstance(value, AsDictMixin):
# other structure
value = type_.as_dict(value)
result[field] = value
return result
class Structure(ctypes.Structure, AsDictMixin):
def __init__(self, *args, **kwds):
# We don't want to use positional arguments fill PADDING_* fields
args = dict(zip(self.__class__._field_names_(), args))
args.update(kwds)
super(Structure, self).__init__(**args)
@classmethod
def _field_names_(cls):
if hasattr(cls, '_fields_'):
return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING'))
else:
return ()
@classmethod
def get_type(cls, field):
for f in cls._fields_:
if f[0] == field:
return f[1]
return None
@classmethod
def bind(cls, bound_fields):
fields = {}
for name, type_ in cls._fields_:
if hasattr(type_, "restype"):
if name in bound_fields:
if bound_fields[name] is None:
fields[name] = type_()
else:
# use a closure to capture the callback from the loop scope
fields[name] = (
type_((lambda callback: lambda *args: callback(*args))(
bound_fields[name]))
)
del bound_fields[name]
else:
# default callback implementation (does nothing)
try:
default_ = type_(0).restype().value
except TypeError:
default_ = None
fields[name] = type_((
lambda default_: lambda *args: default_)(default_))
else:
# not a callback function, use default initialization
if name in bound_fields:
fields[name] = bound_fields[name]
del bound_fields[name]
else:
fields[name] = type_()
if len(bound_fields) != 0:
raise ValueError(
"Cannot bind the following unknown callback(s) {}.{}".format(
cls.__name__, bound_fields.keys()
))
return cls(**fields)
class Union(ctypes.Union, AsDictMixin):
pass
VFIO_H = True # macro
VFIO_API_VERSION = 0 # macro
VFIO_TYPE1_IOMMU = 1 # macro
VFIO_SPAPR_TCE_IOMMU = 2 # macro
VFIO_TYPE1v2_IOMMU = 3 # macro
VFIO_DMA_CC_IOMMU = 4 # macro
VFIO_EEH = 5 # macro
VFIO_TYPE1_NESTING_IOMMU = 6 # macro
VFIO_SPAPR_TCE_v2_IOMMU = 7 # macro
VFIO_NOIOMMU_IOMMU = 8 # macro
VFIO_UNMAP_ALL = 9 # macro
VFIO_UPDATE_VADDR = 10 # macro
VFIO_TYPE = (';') # macro
VFIO_BASE = 100 # macro
VFIO_GET_API_VERSION = _IO ( ( ';' ) , 100 + 0 ) # macro (from list)
VFIO_CHECK_EXTENSION = _IO ( ( ';' ) , 100 + 1 ) # macro (from list)
VFIO_SET_IOMMU = _IO ( ( ';' ) , 100 + 2 ) # macro (from list)
VFIO_GROUP_FLAGS_VIABLE = (1<<0) # macro
VFIO_GROUP_FLAGS_CONTAINER_SET = (1<<1) # macro
VFIO_GROUP_GET_STATUS = _IO ( ( ';' ) , 100 + 3 ) # macro (from list)
VFIO_GROUP_SET_CONTAINER = _IO ( ( ';' ) , 100 + 4 ) # macro (from list)
VFIO_GROUP_UNSET_CONTAINER = _IO ( ( ';' ) , 100 + 5 ) # macro (from list)
VFIO_GROUP_GET_DEVICE_FD = _IO ( ( ';' ) , 100 + 6 ) # macro (from list)
VFIO_DEVICE_FLAGS_RESET = (1<<0) # macro
VFIO_DEVICE_FLAGS_PCI = (1<<1) # macro
VFIO_DEVICE_FLAGS_PLATFORM = (1<<2) # macro
VFIO_DEVICE_FLAGS_AMBA = (1<<3) # macro
VFIO_DEVICE_FLAGS_CCW = (1<<4) # macro
VFIO_DEVICE_FLAGS_AP = (1<<5) # macro
VFIO_DEVICE_FLAGS_FSL_MC = (1<<6) # macro
VFIO_DEVICE_FLAGS_CAPS = (1<<7) # macro
VFIO_DEVICE_GET_INFO = _IO ( ( ';' ) , 100 + 7 ) # macro (from list)
VFIO_DEVICE_API_PCI_STRING = "vfio-pci" # macro
VFIO_DEVICE_API_PLATFORM_STRING = "vfio-platform" # macro
VFIO_DEVICE_API_AMBA_STRING = "vfio-amba" # macro
VFIO_DEVICE_API_CCW_STRING = "vfio-ccw" # macro
VFIO_DEVICE_API_AP_STRING = "vfio-ap" # macro
VFIO_DEVICE_INFO_CAP_ZPCI_BASE = 1 # macro
VFIO_DEVICE_INFO_CAP_ZPCI_GROUP = 2 # macro
VFIO_DEVICE_INFO_CAP_ZPCI_UTIL = 3 # macro
VFIO_DEVICE_INFO_CAP_ZPCI_PFIP = 4 # macro
VFIO_REGION_INFO_FLAG_READ = (1<<0) # macro
VFIO_REGION_INFO_FLAG_WRITE = (1<<1) # macro
VFIO_REGION_INFO_FLAG_MMAP = (1<<2) # macro
VFIO_REGION_INFO_FLAG_CAPS = (1<<3) # macro
VFIO_DEVICE_GET_REGION_INFO = _IO ( ( ';' ) , 100 + 8 ) # macro (from list)
VFIO_REGION_INFO_CAP_SPARSE_MMAP = 1 # macro
VFIO_REGION_INFO_CAP_TYPE = 2 # macro
VFIO_REGION_TYPE_PCI_VENDOR_TYPE = (1<<31) # macro
VFIO_REGION_TYPE_PCI_VENDOR_MASK = (0xffff) # macro
VFIO_REGION_TYPE_GFX = (1) # macro
VFIO_REGION_TYPE_CCW = (2) # macro
VFIO_REGION_TYPE_MIGRATION = (3) # macro
VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION = (1) # macro
VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG = (2) # macro
VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG = (3) # macro
VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM = (1) # macro
VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD = (1) # macro
VFIO_REGION_SUBTYPE_GFX_EDID = (1) # macro
VFIO_DEVICE_GFX_LINK_STATE_UP = 1 # macro
VFIO_DEVICE_GFX_LINK_STATE_DOWN = 2 # macro
VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD = (1) # macro
VFIO_REGION_SUBTYPE_CCW_SCHIB = (2) # macro
VFIO_REGION_SUBTYPE_CCW_CRW = (3) # macro
VFIO_REGION_SUBTYPE_MIGRATION = (1) # macro
VFIO_DEVICE_STATE_STOP = (0) # macro
VFIO_DEVICE_STATE_RUNNING = (1<<0) # macro
VFIO_DEVICE_STATE_SAVING = (1<<1) # macro
VFIO_DEVICE_STATE_RESUMING = (1<<2) # macro
VFIO_DEVICE_STATE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro
# def VFIO_DEVICE_STATE_VALID(state): # macro
# return (state&(1<<2)?(state&((1<<0)|(1<<1)|(1<<2)))==(1<<2):1)
def VFIO_DEVICE_STATE_IS_ERROR(state): # macro
return ((state&((1<<0)|(1<<1)|(1<<2)))==((1<<1)|(1<<2)))
# def VFIO_DEVICE_STATE_SET_ERROR(state): # macro
# return ((state&~((1<<0)|(1<<1)|(1<<2)))|VFIO_DEVICE_SATE_SAVING|(1<<2))
VFIO_REGION_INFO_CAP_MSIX_MAPPABLE = 3 # macro
VFIO_REGION_INFO_CAP_NVLINK2_SSATGT = 4 # macro
VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD = 5 # macro
VFIO_IRQ_INFO_EVENTFD = (1<<0) # macro
VFIO_IRQ_INFO_MASKABLE = (1<<1) # macro
VFIO_IRQ_INFO_AUTOMASKED = (1<<2) # macro
VFIO_IRQ_INFO_NORESIZE = (1<<3) # macro
VFIO_DEVICE_GET_IRQ_INFO = _IO ( ( ';' ) , 100 + 9 ) # macro (from list)
VFIO_IRQ_SET_DATA_NONE = (1<<0) # macro
VFIO_IRQ_SET_DATA_BOOL = (1<<1) # macro
VFIO_IRQ_SET_DATA_EVENTFD = (1<<2) # macro
VFIO_IRQ_SET_ACTION_MASK = (1<<3) # macro
VFIO_IRQ_SET_ACTION_UNMASK = (1<<4) # macro
VFIO_IRQ_SET_ACTION_TRIGGER = (1<<5) # macro
VFIO_DEVICE_SET_IRQS = _IO ( ( ';' ) , 100 + 10 ) # macro (from list)
VFIO_IRQ_SET_DATA_TYPE_MASK = ((1<<0)|(1<<1)|(1<<2)) # macro
VFIO_IRQ_SET_ACTION_TYPE_MASK = ((1<<3)|(1<<4)|(1<<5)) # macro
VFIO_DEVICE_RESET = _IO ( ( ';' ) , 100 + 11 ) # macro (from list)
VFIO_DEVICE_GET_PCI_HOT_RESET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list)
VFIO_DEVICE_PCI_HOT_RESET = _IO ( ( ';' ) , 100 + 13 ) # macro (from list)
VFIO_GFX_PLANE_TYPE_PROBE = (1<<0) # macro
VFIO_GFX_PLANE_TYPE_DMABUF = (1<<1) # macro
VFIO_GFX_PLANE_TYPE_REGION = (1<<2) # macro
VFIO_DEVICE_QUERY_GFX_PLANE = _IO ( ( ';' ) , 100 + 14 ) # macro (from list)
VFIO_DEVICE_GET_GFX_DMABUF = _IO ( ( ';' ) , 100 + 15 ) # macro (from list)
VFIO_DEVICE_IOEVENTFD_8 = (1<<0) # macro
VFIO_DEVICE_IOEVENTFD_16 = (1<<1) # macro
VFIO_DEVICE_IOEVENTFD_32 = (1<<2) # macro
VFIO_DEVICE_IOEVENTFD_64 = (1<<3) # macro
VFIO_DEVICE_IOEVENTFD_SIZE_MASK = (0xf) # macro
VFIO_DEVICE_IOEVENTFD = _IO ( ( ';' ) , 100 + 16 ) # macro (from list)
VFIO_DEVICE_FEATURE_MASK = (0xffff) # macro
VFIO_DEVICE_FEATURE_GET = (1<<16) # macro
VFIO_DEVICE_FEATURE_SET = (1<<17) # macro
VFIO_DEVICE_FEATURE_PROBE = (1<<18) # macro
VFIO_DEVICE_FEATURE = _IO ( ( ';' ) , 100 + 17 ) # macro (from list)
VFIO_DEVICE_FEATURE_PCI_VF_TOKEN = (0) # macro
VFIO_IOMMU_INFO_PGSIZES = (1<<0) # macro
VFIO_IOMMU_INFO_CAPS = (1<<1) # macro
VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE = 1 # macro
VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION = 2 # macro
VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL = 3 # macro
VFIO_IOMMU_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list)
VFIO_DMA_MAP_FLAG_READ = (1<<0) # macro
VFIO_DMA_MAP_FLAG_WRITE = (1<<1) # macro
VFIO_DMA_MAP_FLAG_VADDR = (1<<2) # macro
VFIO_IOMMU_MAP_DMA = _IO ( ( ';' ) , 100 + 13 ) # macro (from list)
VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP = (1<<0) # macro
VFIO_DMA_UNMAP_FLAG_ALL = (1<<1) # macro
VFIO_DMA_UNMAP_FLAG_VADDR = (1<<2) # macro
VFIO_IOMMU_UNMAP_DMA = _IO ( ( ';' ) , 100 + 14 ) # macro (from list)
VFIO_IOMMU_ENABLE = _IO ( ( ';' ) , 100 + 15 ) # macro (from list)
VFIO_IOMMU_DISABLE = _IO ( ( ';' ) , 100 + 16 ) # macro (from list)
VFIO_IOMMU_DIRTY_PAGES_FLAG_START = (1<<0) # macro
VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP = (1<<1) # macro
VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP = (1<<2) # macro
VFIO_IOMMU_DIRTY_PAGES = _IO ( ( ';' ) , 100 + 17 ) # macro (from list)
VFIO_IOMMU_SPAPR_INFO_DDW = (1<<0) # macro
VFIO_IOMMU_SPAPR_TCE_GET_INFO = _IO ( ( ';' ) , 100 + 12 ) # macro (from list)
VFIO_EEH_PE_DISABLE = 0 # macro
VFIO_EEH_PE_ENABLE = 1 # macro
VFIO_EEH_PE_UNFREEZE_IO = 2 # macro
VFIO_EEH_PE_UNFREEZE_DMA = 3 # macro
VFIO_EEH_PE_GET_STATE = 4 # macro
VFIO_EEH_PE_STATE_NORMAL = 0 # macro
VFIO_EEH_PE_STATE_RESET = 1 # macro
VFIO_EEH_PE_STATE_STOPPED = 2 # macro
VFIO_EEH_PE_STATE_STOPPED_DMA = 4 # macro
VFIO_EEH_PE_STATE_UNAVAIL = 5 # macro
VFIO_EEH_PE_RESET_DEACTIVATE = 5 # macro
VFIO_EEH_PE_RESET_HOT = 6 # macro
VFIO_EEH_PE_RESET_FUNDAMENTAL = 7 # macro
VFIO_EEH_PE_CONFIGURE = 8 # macro
VFIO_EEH_PE_INJECT_ERR = 9 # macro
VFIO_EEH_PE_OP = _IO ( ( ';' ) , 100 + 21 ) # macro (from list)
VFIO_IOMMU_SPAPR_REGISTER_MEMORY = _IO ( ( ';' ) , 100 + 17 ) # macro (from list)
VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY = _IO ( ( ';' ) , 100 + 18 ) # macro (from list)
VFIO_IOMMU_SPAPR_TCE_CREATE = _IO ( ( ';' ) , 100 + 19 ) # macro (from list)
VFIO_IOMMU_SPAPR_TCE_REMOVE = _IO ( ( ';' ) , 100 + 20 ) # macro (from list)
class struct_vfio_info_cap_header(Structure):
pass
struct_vfio_info_cap_header._pack_ = 1 # source:False
struct_vfio_info_cap_header._fields_ = [
('id', ctypes.c_uint16),
('version', ctypes.c_uint16),
('next', ctypes.c_uint32),
]
class struct_vfio_group_status(Structure):
pass
struct_vfio_group_status._pack_ = 1 # source:False
struct_vfio_group_status._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
]
class struct_vfio_device_info(Structure):
pass
struct_vfio_device_info._pack_ = 1 # source:False
struct_vfio_device_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('num_regions', ctypes.c_uint32),
('num_irqs', ctypes.c_uint32),
('cap_offset', ctypes.c_uint32),
]
class struct_vfio_region_info(Structure):
pass
struct_vfio_region_info._pack_ = 1 # source:False
struct_vfio_region_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('index', ctypes.c_uint32),
('cap_offset', ctypes.c_uint32),
('size', ctypes.c_uint64),
('offset', ctypes.c_uint64),
]
class struct_vfio_region_sparse_mmap_area(Structure):
pass
struct_vfio_region_sparse_mmap_area._pack_ = 1 # source:False
struct_vfio_region_sparse_mmap_area._fields_ = [
('offset', ctypes.c_uint64),
('size', ctypes.c_uint64),
]
class struct_vfio_region_info_cap_sparse_mmap(Structure):
pass
struct_vfio_region_info_cap_sparse_mmap._pack_ = 1 # source:False
struct_vfio_region_info_cap_sparse_mmap._fields_ = [
('header', struct_vfio_info_cap_header),
('nr_areas', ctypes.c_uint32),
('reserved', ctypes.c_uint32),
('areas', struct_vfio_region_sparse_mmap_area * 0),
]
class struct_vfio_region_info_cap_type(Structure):
pass
struct_vfio_region_info_cap_type._pack_ = 1 # source:False
struct_vfio_region_info_cap_type._fields_ = [
('header', struct_vfio_info_cap_header),
('type', ctypes.c_uint32),
('subtype', ctypes.c_uint32),
]
class struct_vfio_region_gfx_edid(Structure):
pass
struct_vfio_region_gfx_edid._pack_ = 1 # source:False
struct_vfio_region_gfx_edid._fields_ = [
('edid_offset', ctypes.c_uint32),
('edid_max_size', ctypes.c_uint32),
('edid_size', ctypes.c_uint32),
('max_xres', ctypes.c_uint32),
('max_yres', ctypes.c_uint32),
('link_state', ctypes.c_uint32),
]
class struct_vfio_device_migration_info(Structure):
pass
struct_vfio_device_migration_info._pack_ = 1 # source:False
struct_vfio_device_migration_info._fields_ = [
('device_state', ctypes.c_uint32),
('reserved', ctypes.c_uint32),
('pending_bytes', ctypes.c_uint64),
('data_offset', ctypes.c_uint64),
('data_size', ctypes.c_uint64),
]
class struct_vfio_region_info_cap_nvlink2_ssatgt(Structure):
pass
struct_vfio_region_info_cap_nvlink2_ssatgt._pack_ = 1 # source:False
struct_vfio_region_info_cap_nvlink2_ssatgt._fields_ = [
('header', struct_vfio_info_cap_header),
('tgt', ctypes.c_uint64),
]
class struct_vfio_region_info_cap_nvlink2_lnkspd(Structure):
pass
struct_vfio_region_info_cap_nvlink2_lnkspd._pack_ = 1 # source:False
struct_vfio_region_info_cap_nvlink2_lnkspd._fields_ = [
('header', struct_vfio_info_cap_header),
('link_speed', ctypes.c_uint32),
('__pad', ctypes.c_uint32),
]
class struct_vfio_irq_info(Structure):
pass
struct_vfio_irq_info._pack_ = 1 # source:False
struct_vfio_irq_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('index', ctypes.c_uint32),
('count', ctypes.c_uint32),
]
class struct_vfio_irq_set(Structure):
pass
struct_vfio_irq_set._pack_ = 1 # source:False
struct_vfio_irq_set._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('index', ctypes.c_uint32),
('start', ctypes.c_uint32),
('count', ctypes.c_uint32),
('data', ctypes.c_int * 1),
]
# values for enumeration 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX'
c__Ea_VFIO_PCI_BAR0_REGION_INDEX__enumvalues = {
0: 'VFIO_PCI_BAR0_REGION_INDEX',
1: 'VFIO_PCI_BAR1_REGION_INDEX',
2: 'VFIO_PCI_BAR2_REGION_INDEX',
3: 'VFIO_PCI_BAR3_REGION_INDEX',
4: 'VFIO_PCI_BAR4_REGION_INDEX',
5: 'VFIO_PCI_BAR5_REGION_INDEX',
6: 'VFIO_PCI_ROM_REGION_INDEX',
7: 'VFIO_PCI_CONFIG_REGION_INDEX',
8: 'VFIO_PCI_VGA_REGION_INDEX',
9: 'VFIO_PCI_NUM_REGIONS',
}
VFIO_PCI_BAR0_REGION_INDEX = 0
VFIO_PCI_BAR1_REGION_INDEX = 1
VFIO_PCI_BAR2_REGION_INDEX = 2
VFIO_PCI_BAR3_REGION_INDEX = 3
VFIO_PCI_BAR4_REGION_INDEX = 4
VFIO_PCI_BAR5_REGION_INDEX = 5
VFIO_PCI_ROM_REGION_INDEX = 6
VFIO_PCI_CONFIG_REGION_INDEX = 7
VFIO_PCI_VGA_REGION_INDEX = 8
VFIO_PCI_NUM_REGIONS = 9
c__Ea_VFIO_PCI_BAR0_REGION_INDEX = ctypes.c_uint32 # enum
# values for enumeration 'c__Ea_VFIO_PCI_INTX_IRQ_INDEX'
c__Ea_VFIO_PCI_INTX_IRQ_INDEX__enumvalues = {
0: 'VFIO_PCI_INTX_IRQ_INDEX',
1: 'VFIO_PCI_MSI_IRQ_INDEX',
2: 'VFIO_PCI_MSIX_IRQ_INDEX',
3: 'VFIO_PCI_ERR_IRQ_INDEX',
4: 'VFIO_PCI_REQ_IRQ_INDEX',
5: 'VFIO_PCI_NUM_IRQS',
}
VFIO_PCI_INTX_IRQ_INDEX = 0
VFIO_PCI_MSI_IRQ_INDEX = 1
VFIO_PCI_MSIX_IRQ_INDEX = 2
VFIO_PCI_ERR_IRQ_INDEX = 3
VFIO_PCI_REQ_IRQ_INDEX = 4
VFIO_PCI_NUM_IRQS = 5
c__Ea_VFIO_PCI_INTX_IRQ_INDEX = ctypes.c_uint32 # enum
# values for enumeration 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX'
c__Ea_VFIO_CCW_CONFIG_REGION_INDEX__enumvalues = {
0: 'VFIO_CCW_CONFIG_REGION_INDEX',
1: 'VFIO_CCW_NUM_REGIONS',
}
VFIO_CCW_CONFIG_REGION_INDEX = 0
VFIO_CCW_NUM_REGIONS = 1
c__Ea_VFIO_CCW_CONFIG_REGION_INDEX = ctypes.c_uint32 # enum
# values for enumeration 'c__Ea_VFIO_CCW_IO_IRQ_INDEX'
c__Ea_VFIO_CCW_IO_IRQ_INDEX__enumvalues = {
0: 'VFIO_CCW_IO_IRQ_INDEX',
1: 'VFIO_CCW_CRW_IRQ_INDEX',
2: 'VFIO_CCW_REQ_IRQ_INDEX',
3: 'VFIO_CCW_NUM_IRQS',
}
VFIO_CCW_IO_IRQ_INDEX = 0
VFIO_CCW_CRW_IRQ_INDEX = 1
VFIO_CCW_REQ_IRQ_INDEX = 2
VFIO_CCW_NUM_IRQS = 3
c__Ea_VFIO_CCW_IO_IRQ_INDEX = ctypes.c_uint32 # enum
class struct_vfio_pci_dependent_device(Structure):
pass
struct_vfio_pci_dependent_device._pack_ = 1 # source:False
struct_vfio_pci_dependent_device._fields_ = [
('group_id', ctypes.c_uint32),
('segment', ctypes.c_uint16),
('bus', ctypes.c_ubyte),
('devfn', ctypes.c_ubyte),
]
class struct_vfio_pci_hot_reset_info(Structure):
pass
struct_vfio_pci_hot_reset_info._pack_ = 1 # source:False
struct_vfio_pci_hot_reset_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('count', ctypes.c_uint32),
('devices', struct_vfio_pci_dependent_device * 0),
]
class struct_vfio_pci_hot_reset(Structure):
pass
struct_vfio_pci_hot_reset._pack_ = 1 # source:False
struct_vfio_pci_hot_reset._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('count', ctypes.c_uint32),
('group_fds', ctypes.c_int32 * 0),
]
class struct_vfio_device_gfx_plane_info(Structure):
pass
class union_vfio_device_gfx_plane_info_0(Union):
pass
union_vfio_device_gfx_plane_info_0._pack_ = 1 # source:False
union_vfio_device_gfx_plane_info_0._fields_ = [
('region_index', ctypes.c_uint32),
('dmabuf_id', ctypes.c_uint32),
]
struct_vfio_device_gfx_plane_info._pack_ = 1 # source:False
struct_vfio_device_gfx_plane_info._anonymous_ = ('_0',)
struct_vfio_device_gfx_plane_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('drm_plane_type', ctypes.c_uint32),
('drm_format', ctypes.c_uint32),
('drm_format_mod', ctypes.c_uint64),
('width', ctypes.c_uint32),
('height', ctypes.c_uint32),
('stride', ctypes.c_uint32),
('size', ctypes.c_uint32),
('x_pos', ctypes.c_uint32),
('y_pos', ctypes.c_uint32),
('x_hot', ctypes.c_uint32),
('y_hot', ctypes.c_uint32),
('_0', union_vfio_device_gfx_plane_info_0),
('PADDING_0', ctypes.c_ubyte * 4),
]
class struct_vfio_device_ioeventfd(Structure):
pass
struct_vfio_device_ioeventfd._pack_ = 1 # source:False
struct_vfio_device_ioeventfd._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('offset', ctypes.c_uint64),
('data', ctypes.c_uint64),
('fd', ctypes.c_int32),
('PADDING_0', ctypes.c_ubyte * 4),
]
class struct_vfio_device_feature(Structure):
pass
struct_vfio_device_feature._pack_ = 1 # source:False
struct_vfio_device_feature._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('data', ctypes.c_ubyte * 0),
]
class struct_vfio_iommu_type1_info(Structure):
pass
struct_vfio_iommu_type1_info._pack_ = 1 # source:False
struct_vfio_iommu_type1_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('iova_pgsizes', ctypes.c_uint64),
('cap_offset', ctypes.c_uint32),
('PADDING_0', ctypes.c_ubyte * 4),
]
class struct_vfio_iova_range(Structure):
pass
struct_vfio_iova_range._pack_ = 1 # source:False
struct_vfio_iova_range._fields_ = [
('start', ctypes.c_uint64),
('end', ctypes.c_uint64),
]
class struct_vfio_iommu_type1_info_cap_iova_range(Structure):
pass
struct_vfio_iommu_type1_info_cap_iova_range._pack_ = 1 # source:False
struct_vfio_iommu_type1_info_cap_iova_range._fields_ = [
('header', struct_vfio_info_cap_header),
('nr_iovas', ctypes.c_uint32),
('reserved', ctypes.c_uint32),
('iova_ranges', struct_vfio_iova_range * 0),
]
class struct_vfio_iommu_type1_info_cap_migration(Structure):
pass
struct_vfio_iommu_type1_info_cap_migration._pack_ = 1 # source:False
struct_vfio_iommu_type1_info_cap_migration._fields_ = [
('header', struct_vfio_info_cap_header),
('flags', ctypes.c_uint32),
('PADDING_0', ctypes.c_ubyte * 4),
('pgsize_bitmap', ctypes.c_uint64),
('max_dirty_bitmap_size', ctypes.c_uint64),
]
class struct_vfio_iommu_type1_info_dma_avail(Structure):
pass
struct_vfio_iommu_type1_info_dma_avail._pack_ = 1 # source:False
struct_vfio_iommu_type1_info_dma_avail._fields_ = [
('header', struct_vfio_info_cap_header),
('avail', ctypes.c_uint32),
]
class struct_vfio_iommu_type1_dma_map(Structure):
pass
struct_vfio_iommu_type1_dma_map._pack_ = 1 # source:False
struct_vfio_iommu_type1_dma_map._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('vaddr', ctypes.c_uint64),
('iova', ctypes.c_uint64),
('size', ctypes.c_uint64),
]
class struct_vfio_bitmap(Structure):
pass
struct_vfio_bitmap._pack_ = 1 # source:False
struct_vfio_bitmap._fields_ = [
('pgsize', ctypes.c_uint64),
('size', ctypes.c_uint64),
('data', ctypes.POINTER(ctypes.c_uint64)),
]
class struct_vfio_iommu_type1_dma_unmap(Structure):
pass
struct_vfio_iommu_type1_dma_unmap._pack_ = 1 # source:False
struct_vfio_iommu_type1_dma_unmap._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('iova', ctypes.c_uint64),
('size', ctypes.c_uint64),
('data', ctypes.c_ubyte * 0),
]
class struct_vfio_iommu_type1_dirty_bitmap(Structure):
pass
struct_vfio_iommu_type1_dirty_bitmap._pack_ = 1 # source:False
struct_vfio_iommu_type1_dirty_bitmap._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('data', ctypes.c_ubyte * 0),
]
class struct_vfio_iommu_type1_dirty_bitmap_get(Structure):
pass
struct_vfio_iommu_type1_dirty_bitmap_get._pack_ = 1 # source:False
struct_vfio_iommu_type1_dirty_bitmap_get._fields_ = [
('iova', ctypes.c_uint64),
('size', ctypes.c_uint64),
('bitmap', struct_vfio_bitmap),
]
class struct_vfio_iommu_spapr_tce_ddw_info(Structure):
pass
struct_vfio_iommu_spapr_tce_ddw_info._pack_ = 1 # source:False
struct_vfio_iommu_spapr_tce_ddw_info._fields_ = [
('pgsizes', ctypes.c_uint64),
('max_dynamic_windows_supported', ctypes.c_uint32),
('levels', ctypes.c_uint32),
]
class struct_vfio_iommu_spapr_tce_info(Structure):
pass
struct_vfio_iommu_spapr_tce_info._pack_ = 1 # source:False
struct_vfio_iommu_spapr_tce_info._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('dma32_window_start', ctypes.c_uint32),
('dma32_window_size', ctypes.c_uint32),
('ddw', struct_vfio_iommu_spapr_tce_ddw_info),
]
class struct_vfio_eeh_pe_err(Structure):
pass
struct_vfio_eeh_pe_err._pack_ = 1 # source:False
struct_vfio_eeh_pe_err._fields_ = [
('type', ctypes.c_uint32),
('func', ctypes.c_uint32),
('addr', ctypes.c_uint64),
('mask', ctypes.c_uint64),
]
class struct_vfio_eeh_pe_op(Structure):
pass
class union_vfio_eeh_pe_op_0(Union):
_pack_ = 1 # source:False
_fields_ = [
('err', struct_vfio_eeh_pe_err),
]
struct_vfio_eeh_pe_op._pack_ = 1 # source:False
struct_vfio_eeh_pe_op._anonymous_ = ('_0',)
struct_vfio_eeh_pe_op._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('op', ctypes.c_uint32),
('PADDING_0', ctypes.c_ubyte * 4),
('_0', union_vfio_eeh_pe_op_0),
]
class struct_vfio_iommu_spapr_register_memory(Structure):
pass
struct_vfio_iommu_spapr_register_memory._pack_ = 1 # source:False
struct_vfio_iommu_spapr_register_memory._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('vaddr', ctypes.c_uint64),
('size', ctypes.c_uint64),
]
class struct_vfio_iommu_spapr_tce_create(Structure):
pass
struct_vfio_iommu_spapr_tce_create._pack_ = 1 # source:False
struct_vfio_iommu_spapr_tce_create._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('page_shift', ctypes.c_uint32),
('__resv1', ctypes.c_uint32),
('window_size', ctypes.c_uint64),
('levels', ctypes.c_uint32),
('__resv2', ctypes.c_uint32),
('start_addr', ctypes.c_uint64),
]
class struct_vfio_iommu_spapr_tce_remove(Structure):
pass
struct_vfio_iommu_spapr_tce_remove._pack_ = 1 # source:False
struct_vfio_iommu_spapr_tce_remove._fields_ = [
('argsz', ctypes.c_uint32),
('flags', ctypes.c_uint32),
('start_addr', ctypes.c_uint64),
]
__all__ = \
['VFIO_API_VERSION', 'VFIO_BASE', 'VFIO_CCW_CONFIG_REGION_INDEX',
'VFIO_CCW_CRW_IRQ_INDEX', 'VFIO_CCW_IO_IRQ_INDEX',
'VFIO_CCW_NUM_IRQS', 'VFIO_CCW_NUM_REGIONS',
'VFIO_CCW_REQ_IRQ_INDEX', 'VFIO_DEVICE_API_AMBA_STRING',
'VFIO_DEVICE_API_AP_STRING', 'VFIO_DEVICE_API_CCW_STRING',
'VFIO_DEVICE_API_PCI_STRING', 'VFIO_DEVICE_API_PLATFORM_STRING',
'VFIO_DEVICE_FEATURE_GET', 'VFIO_DEVICE_FEATURE_MASK',
'VFIO_DEVICE_FEATURE_PCI_VF_TOKEN', 'VFIO_DEVICE_FEATURE_PROBE',
'VFIO_DEVICE_FEATURE_SET', 'VFIO_DEVICE_FLAGS_AMBA',
'VFIO_DEVICE_FLAGS_AP', 'VFIO_DEVICE_FLAGS_CAPS',
'VFIO_DEVICE_FLAGS_CCW', 'VFIO_DEVICE_FLAGS_FSL_MC',
'VFIO_DEVICE_FLAGS_PCI', 'VFIO_DEVICE_FLAGS_PLATFORM',
'VFIO_DEVICE_FLAGS_RESET', 'VFIO_DEVICE_GFX_LINK_STATE_DOWN',
'VFIO_DEVICE_GFX_LINK_STATE_UP', 'VFIO_DEVICE_INFO_CAP_ZPCI_BASE',
'VFIO_DEVICE_INFO_CAP_ZPCI_GROUP',
'VFIO_DEVICE_INFO_CAP_ZPCI_PFIP',
'VFIO_DEVICE_INFO_CAP_ZPCI_UTIL', 'VFIO_DEVICE_IOEVENTFD_16',
'VFIO_DEVICE_IOEVENTFD_32', 'VFIO_DEVICE_IOEVENTFD_64',
'VFIO_DEVICE_IOEVENTFD_8', 'VFIO_DEVICE_IOEVENTFD_SIZE_MASK',
'VFIO_DEVICE_STATE_MASK', 'VFIO_DEVICE_STATE_RESUMING',
'VFIO_DEVICE_STATE_RUNNING', 'VFIO_DEVICE_STATE_SAVING',
'VFIO_DEVICE_STATE_STOP', 'VFIO_DMA_CC_IOMMU',
'VFIO_DMA_MAP_FLAG_READ', 'VFIO_DMA_MAP_FLAG_VADDR',
'VFIO_DMA_MAP_FLAG_WRITE', 'VFIO_DMA_UNMAP_FLAG_ALL',
'VFIO_DMA_UNMAP_FLAG_GET_DIRTY_BITMAP',
'VFIO_DMA_UNMAP_FLAG_VADDR', 'VFIO_EEH', 'VFIO_EEH_PE_CONFIGURE',
'VFIO_EEH_PE_DISABLE', 'VFIO_EEH_PE_ENABLE',
'VFIO_EEH_PE_GET_STATE', 'VFIO_EEH_PE_INJECT_ERR',
'VFIO_EEH_PE_RESET_DEACTIVATE', 'VFIO_EEH_PE_RESET_FUNDAMENTAL',
'VFIO_EEH_PE_RESET_HOT', 'VFIO_EEH_PE_STATE_NORMAL',
'VFIO_EEH_PE_STATE_RESET', 'VFIO_EEH_PE_STATE_STOPPED',
'VFIO_EEH_PE_STATE_STOPPED_DMA', 'VFIO_EEH_PE_STATE_UNAVAIL',
'VFIO_EEH_PE_UNFREEZE_DMA', 'VFIO_EEH_PE_UNFREEZE_IO',
'VFIO_GFX_PLANE_TYPE_DMABUF', 'VFIO_GFX_PLANE_TYPE_PROBE',
'VFIO_GFX_PLANE_TYPE_REGION', 'VFIO_GROUP_FLAGS_CONTAINER_SET',
'VFIO_GROUP_FLAGS_VIABLE', 'VFIO_H',
'VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP',
'VFIO_IOMMU_DIRTY_PAGES_FLAG_START',
'VFIO_IOMMU_DIRTY_PAGES_FLAG_STOP', 'VFIO_IOMMU_INFO_CAPS',
'VFIO_IOMMU_INFO_PGSIZES', 'VFIO_IOMMU_SPAPR_INFO_DDW',
'VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE',
'VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION',
'VFIO_IOMMU_TYPE1_INFO_DMA_AVAIL', 'VFIO_IRQ_INFO_AUTOMASKED',
'VFIO_IRQ_INFO_EVENTFD', 'VFIO_IRQ_INFO_MASKABLE',
'VFIO_IRQ_INFO_NORESIZE', 'VFIO_IRQ_SET_ACTION_MASK',
'VFIO_IRQ_SET_ACTION_TRIGGER', 'VFIO_IRQ_SET_ACTION_TYPE_MASK',
'VFIO_IRQ_SET_ACTION_UNMASK', 'VFIO_IRQ_SET_DATA_BOOL',
'VFIO_IRQ_SET_DATA_EVENTFD', 'VFIO_IRQ_SET_DATA_NONE',
'VFIO_IRQ_SET_DATA_TYPE_MASK', 'VFIO_NOIOMMU_IOMMU',
'VFIO_PCI_BAR0_REGION_INDEX', 'VFIO_PCI_BAR1_REGION_INDEX',
'VFIO_PCI_BAR2_REGION_INDEX', 'VFIO_PCI_BAR3_REGION_INDEX',
'VFIO_PCI_BAR4_REGION_INDEX', 'VFIO_PCI_BAR5_REGION_INDEX',
'VFIO_PCI_CONFIG_REGION_INDEX', 'VFIO_PCI_ERR_IRQ_INDEX',
'VFIO_PCI_INTX_IRQ_INDEX', 'VFIO_PCI_MSIX_IRQ_INDEX',
'VFIO_PCI_MSI_IRQ_INDEX', 'VFIO_PCI_NUM_IRQS',
'VFIO_PCI_NUM_REGIONS', 'VFIO_PCI_REQ_IRQ_INDEX',
'VFIO_PCI_ROM_REGION_INDEX', 'VFIO_PCI_VGA_REGION_INDEX',
'VFIO_REGION_INFO_CAP_MSIX_MAPPABLE',
'VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD',
'VFIO_REGION_INFO_CAP_NVLINK2_SSATGT',
'VFIO_REGION_INFO_CAP_SPARSE_MMAP', 'VFIO_REGION_INFO_CAP_TYPE',
'VFIO_REGION_INFO_FLAG_CAPS', 'VFIO_REGION_INFO_FLAG_MMAP',
'VFIO_REGION_INFO_FLAG_READ', 'VFIO_REGION_INFO_FLAG_WRITE',
'VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD',
'VFIO_REGION_SUBTYPE_CCW_CRW', 'VFIO_REGION_SUBTYPE_CCW_SCHIB',
'VFIO_REGION_SUBTYPE_GFX_EDID',
'VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD',
'VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG',
'VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG',
'VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION',
'VFIO_REGION_SUBTYPE_MIGRATION',
'VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM', 'VFIO_REGION_TYPE_CCW',
'VFIO_REGION_TYPE_GFX', 'VFIO_REGION_TYPE_MIGRATION',
'VFIO_REGION_TYPE_PCI_VENDOR_MASK',
'VFIO_REGION_TYPE_PCI_VENDOR_TYPE', 'VFIO_SPAPR_TCE_IOMMU',
'VFIO_SPAPR_TCE_v2_IOMMU', 'VFIO_TYPE', 'VFIO_TYPE1_IOMMU',
'VFIO_TYPE1_NESTING_IOMMU', 'VFIO_TYPE1v2_IOMMU',
'VFIO_UNMAP_ALL', 'VFIO_UPDATE_VADDR', '_IO', '_IOR', '_IOW',
'_IOWR', 'c__Ea_VFIO_CCW_CONFIG_REGION_INDEX',
'c__Ea_VFIO_CCW_IO_IRQ_INDEX', 'c__Ea_VFIO_PCI_BAR0_REGION_INDEX',
'c__Ea_VFIO_PCI_INTX_IRQ_INDEX', 'struct_vfio_bitmap',
'struct_vfio_device_feature', 'struct_vfio_device_gfx_plane_info',
'struct_vfio_device_info', 'struct_vfio_device_ioeventfd',
'struct_vfio_device_migration_info', 'struct_vfio_eeh_pe_err',
'struct_vfio_eeh_pe_op', 'struct_vfio_group_status',
'struct_vfio_info_cap_header',
'struct_vfio_iommu_spapr_register_memory',
'struct_vfio_iommu_spapr_tce_create',
'struct_vfio_iommu_spapr_tce_ddw_info',
'struct_vfio_iommu_spapr_tce_info',
'struct_vfio_iommu_spapr_tce_remove',
'struct_vfio_iommu_type1_dirty_bitmap',
'struct_vfio_iommu_type1_dirty_bitmap_get',
'struct_vfio_iommu_type1_dma_map',
'struct_vfio_iommu_type1_dma_unmap',
'struct_vfio_iommu_type1_info',
'struct_vfio_iommu_type1_info_cap_iova_range',
'struct_vfio_iommu_type1_info_cap_migration',
'struct_vfio_iommu_type1_info_dma_avail',
'struct_vfio_iova_range', 'struct_vfio_irq_info',
'struct_vfio_irq_set', 'struct_vfio_pci_dependent_device',
'struct_vfio_pci_hot_reset', 'struct_vfio_pci_hot_reset_info',
'struct_vfio_region_gfx_edid', 'struct_vfio_region_info',
'struct_vfio_region_info_cap_nvlink2_lnkspd',
'struct_vfio_region_info_cap_nvlink2_ssatgt',
'struct_vfio_region_info_cap_sparse_mmap',
'struct_vfio_region_info_cap_type',
'struct_vfio_region_sparse_mmap_area',
'union_vfio_device_gfx_plane_info_0', 'union_vfio_eeh_pe_op_0']
tinygrad/runtime/ops_amd.py
+131 -7
View File
@@ -1,6 +1,6 @@
from __future__ import annotations
from typing import Any, Optional
import os, ctypes, ctypes.util, functools, pathlib, mmap, errno, array, contextlib, sys
import os, ctypes, ctypes.util, functools, pathlib, mmap, errno, array, contextlib, sys, select, struct
assert sys.platform != 'win32'
from dataclasses import dataclass
from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQSignal, HCQProgram
@@ -8,9 +8,11 @@ from tinygrad.ops import sint
from tinygrad.device import BufferSpec
from tinygrad.helpers import getenv, to_mv, round_up, data64_le, mv_address
from tinygrad.renderer.cstyle import AMDRenderer
from tinygrad.runtime.autogen import kfd, hsa, amd_gpu, libc
from tinygrad.runtime.autogen import kfd, hsa, amd_gpu, libc, libpciaccess, vfio
from tinygrad.runtime.autogen.am import am
from tinygrad.runtime.support.compiler_hip import AMDCompiler
from tinygrad.runtime.support.elf import elf_loader
from tinygrad.runtime.support.am.amdev import AMDev
if getenv("IOCTL"): import extra.hip_gpu_driver.hip_ioctl # noqa: F401 # pylint: disable=unused-import
if getenv("MOCKGPU"): import test.mockgpu.mockgpu # noqa: F401 # pylint: disable=unused-import
@@ -128,7 +130,7 @@ class AMDComputeQueue(HWQueue):
self.release_mem(signal.value_addr, value, amd_gpu.data_sel__mec_release_mem__send_32_bit_low,
amd_gpu.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True)
if (dev:=signal.timeline_for_device) is not None:
if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None:
self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, amd_gpu.data_sel__mec_release_mem__send_32_bit_low,
amd_gpu.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id)
return self
@@ -178,7 +180,7 @@ class AMDCopyQueue(HWQueue):
def signal(self, signal:AMDSignal, value:sint=0):
self.q(amd_gpu.SDMA_OP_FENCE | amd_gpu.SDMA_PKT_FENCE_HEADER_MTYPE(3), *data64_le(signal.value_addr), value)
if (dev:=signal.timeline_for_device) is not None:
if not AMDDevice.driverless and (dev:=signal.timeline_for_device) is not None:
self.q(amd_gpu.SDMA_OP_FENCE | amd_gpu.SDMA_PKT_FENCE_HEADER_MTYPE(3), *data64_le(dev.queue_event_mailbox_ptr), dev.queue_event.event_id)
self.q(amd_gpu.SDMA_OP_TRAP, amd_gpu.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(dev.queue_event.event_id))
@@ -267,7 +269,7 @@ class AMDAllocator(HCQAllocator['AMDDevice']):
def map(self, buf:HCQBuffer): self.dev.dev_iface.map(buf._base if buf._base is not None else buf)
MAP_FIXED, MAP_NORESERVE = 0x10, 0x400
MAP_FIXED, MAP_NORESERVE, MAP_LOCKED = 0x10, 0x400, 0x2000
@dataclass
class AMDQueueDesc:
@@ -394,20 +396,142 @@ class KFDIface:
raise RuntimeError("\n".join(report))
class PCIIface:
vfio:bool = getenv("VFIO", 1) and os.path.exists("/dev/vfio/vfio")
vfio_fd:int = -1
gpus:list[Any] = []
def __init__(self, dev, dev_id):
self.dev = dev
if first_dev:=len(PCIIface.gpus) == 0:
libpciaccess.pci_system_init()
pci_iter = libpciaccess.pci_id_match_iterator_create(None)
while pcidev:=libpciaccess.pci_device_next(pci_iter):
if pcidev.contents.vendor_id == 0x1002 and pcidev.contents.device_id == 0x744c: PCIIface.gpus.append(pcidev.contents)
# TODO: visible_devices should be handled layer above this?
visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', getenv('HIP_VISIBLE_DEVICES', ''))).split(',') if x.strip()]
PCIIface.gpus = [PCIIface.gpus[x] for x in visible_devices] if visible_devices else PCIIface.gpus
self.pcidev = PCIIface.gpus[dev_id]
self.pcibus = f"{self.pcidev.domain_16:04x}:{self.pcidev.bus:02x}:{self.pcidev.dev:02x}.{self.pcidev.func:d}"
# Unbind the device from the kernel driver
if os.path.exists(f"/sys/bus/pci/devices/{self.pcibus}/driver"):
pathlib.Path(f"/sys/bus/pci/devices/{self.pcibus}/driver/unbind").write_text(self.pcibus)
pathlib.Path(f"/sys/bus/pci/devices/{self.pcibus}/resource0_resize").write_text("15")
# Probe device
libpciaccess.pci_device_probe(ctypes.byref(self.pcidev))
# Try to init vfio. Use it if success.
if PCIIface.vfio and PCIIface.vfio_fd == -1:
try:
pathlib.Path("/sys/module/vfio/parameters/enable_unsafe_noiommu_mode").write_text("1")
PCIIface.vfio_fd = os.open("/dev/vfio/vfio", os.O_RDWR)
vfio.VFIO_CHECK_EXTENSION(PCIIface.vfio_fd, vfio.VFIO_NOIOMMU_IOMMU)
except OSError: PCIIface.vfio = False
# Init vfio for the device
if PCIIface.vfio:
pathlib.Path(f"/sys/bus/pci/devices/{self.pcibus}/driver_override").write_text("vfio-pci")
pathlib.Path("/sys/bus/pci/drivers_probe").write_text(self.pcibus)
iommu_group = os.readlink(f"/sys/bus/pci/devices/{self.pcibus}/iommu_group").split('/')[-1]
self.vfio_group = os.open(f"/dev/vfio/noiommu-{iommu_group}", os.O_RDWR)
vfio.VFIO_GROUP_SET_CONTAINER(self.vfio_group, ctypes.c_int(PCIIface.vfio_fd))
if first_dev: vfio.VFIO_SET_IOMMU(PCIIface.vfio_fd, vfio.VFIO_NOIOMMU_IOMMU)
self.vfio_dev = vfio.VFIO_GROUP_GET_DEVICE_FD(self.vfio_group, ctypes.create_string_buffer(self.pcibus.encode()))
self.irq_fd = os.eventfd(0, 0)
self.irq_poller = select.poll()
self.irq_poller.register(self.irq_fd, select.POLLIN)
irqs = vfio.struct_vfio_irq_set(index=vfio.VFIO_PCI_MSI_IRQ_INDEX, flags=vfio.VFIO_IRQ_SET_DATA_EVENTFD|vfio.VFIO_IRQ_SET_ACTION_TRIGGER,
argsz=ctypes.sizeof(vfio.struct_vfio_irq_set), count=1, data=(ctypes.c_int * 1)(self.irq_fd))
vfio.VFIO_DEVICE_SET_IRQS(self.vfio_dev, irqs)
else: libpciaccess.pci_device_enable(ctypes.byref(self.pcidev))
self.bar_fds = {bar: os.open(f"/sys/bus/pci/devices/{self.pcibus}/resource{bar}", os.O_RDWR | os.O_SYNC) for bar in [0, 2, 5]}
self.adev = AMDev(self.pcidev, self._map_pci_range(0), dbell:=self._map_pci_range(2).cast('Q'), self._map_pci_range(5).cast('I'))
self.doorbell_cpu_addr = mv_address(dbell)
# TODO: this is for 7900xtx, the only tested card.
self.props = {'simd_count': 192, 'simd_per_cu': 2, 'max_waves_per_simd': 16, 'gfx_target_version': 110000, 'max_slots_scratch_cu': 32,
'array_count': 12, 'simd_arrays_per_engine': 2, 'lds_size_in_kb': 64}
def _map_pci_range(self, bar, off=0, addr=0, size=None):
if PCIIface.vfio:
vfio.VFIO_DEVICE_GET_REGION_INFO(self.vfio_dev, reg:=vfio.struct_vfio_region_info(argsz=ctypes.sizeof(vfio.struct_vfio_region_info), index=bar))
fd, sz, off = self.vfio_dev, size or reg.size, reg.offset + off
else: fd, sz = self.bar_fds[bar], size or self.pcidev.regions[bar].size
return to_mv(libc.mmap(addr, sz, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | (MAP_FIXED if addr else 0), fd, off), sz)
def alloc(self, size:int, host=False, uncached=False, cpu_access=False):
if host:
vaddr = self.adev.mm.alloc_vaddr(size, align=mmap.PAGESIZE)
va = libc.mmap(vaddr, size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | mmap.MAP_ANONYMOUS | MAP_LOCKED | MAP_FIXED, -1, 0)
# Read pagemap to get the physical address of each page. The pages are locked.
with open("/proc/self/pagemap", "rb") as f:
for off in range(0, size, mmap.PAGESIZE):
f.seek(((va + off) // mmap.PAGESIZE) * 8)
pt_entry = struct.unpack("Q", f.read(8))[0] & ((1 << 55) - 1)
self.adev.mm.map_range(vaddr=vaddr + off, size=mmap.PAGESIZE, paddr=pt_entry * mmap.PAGESIZE, system=True, snooped=True, uncached=True)
return HCQBuffer(vaddr, size, meta=(self.dev, [self.dev], None))
vm = self.adev.mm.valloc(size:=round_up(size, 4 << 10), uncached=uncached, contigous=cpu_access)
if cpu_access: self._map_pci_range(bar=0, off=vm.paddr, addr=vm.va_addr, size=vm.size)
return HCQBuffer(vm.va_addr, size, meta=(self.dev, [self.dev], vm))
def free(self, mem):
if mem.meta[2] is not None:
for dev in mem.meta[1][1:]: dev.dev_iface.adev.mm.unmap_range(mem.va_addr, mem.size, free_paddrs=False)
self.adev.mm.vfree(mem.meta[2])
def map(self, mem):
if mem.meta[0] == self.dev or self.dev in mem.meta[1]: return
mem.meta[1].append(self.dev)
self.adev.mm.map_from(mem.va_addr, mem.size, mem.meta[0].dev_iface.adev)
def create_queue(self, queue_type, ring, gart, eop_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, debug_memory_size=0):
if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA:
self.adev.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10,
doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0)
else:
self.adev.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10,
eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0)
return AMDQueueDesc(ring=to_mv(ring.va_addr, ring.size).cast("I"), doorbell=to_mv(self.doorbell_cpu_addr + doorbell_index * 8, 8).cast("Q"),
read_ptr=to_mv(gart.va_addr, 8).cast("Q"), write_ptr=to_mv(gart.va_addr+0x10, 8).cast("Q"))
def sleep(self, timeout):
if PCIIface.vfio and len(self.irq_poller.poll(timeout)):
os.read(self.irq_fd, 1024)
self.adev.ih.interrupt_handler()
def on_device_hang(self):
for d in self.dev.devices: d.dev_iface.adev.gmc.on_interrupt()
raise RuntimeError("Device hang detected")
class AMDDevice(HCQCompiled):
driverless:bool = not os.path.exists('/sys/module/amdgpu') or bool(getenv("AMD_DRIVERLESS", 0))
signals_page:Any = None
signals_pool:list[int] = []
def __init__(self, device:str=""):
self.device_id = int(device.split(":")[1]) if ":" in device else 0
self.dev_iface = KFDIface(self, self.device_id)
self.dev_iface = PCIIface(self, self.device_id) if AMDDevice.driverless else KFDIface(self, self.device_id)
self.target = int(self.dev_iface.props['gfx_target_version'])
self.arch = "gfx%d%x%x" % (self.target // 10000, (self.target // 100) % 100, self.target % 100)
if self.target < 100300 or self.target >= 120000: raise RuntimeError(f"Unsupported arch: {self.arch}")
if AMDDevice.signals_page is None:
AMDDevice.signals_page = self.dev_iface.alloc(16 * 65536, uncached=True, cpu_access=True)
AMDDevice.signals_page = self.dev_iface.alloc(16 * 65536, host=AMDDevice.driverless, uncached=True, cpu_access=True)
AMDDevice.signals_pool = [AMDDevice.signals_page.va_addr + off for off in range(0, AMDDevice.signals_page.size, 16)]
else: self.dev_iface.map(AMDDevice.signals_page)
tinygrad/runtime/support/allocator.py
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import collections
from typing import Optional
from tinygrad.helpers import round_up
class TLSFAllocator:
"""
The allocator is based on the Two-Level Segregated Fit (TLSF) algorithm. The allocator maintains 2 level of buckets:
* 1st level is determined by the most significant bit of the size.
* 2nd level splits the covered memory of 1st level into @lv2_cnt entries.
For each allocation request, the allocator searches for the smallest block that can fit the requested size.
For each deallocation request, the allocator merges the block with its neighbors if they are free.
"""
def __init__(self, size:int, base:int=0, block_size:int=16, lv2_cnt:int=16):
self.size, self.base, self.block_size, self.l2_cnt = size, base, block_size, lv2_cnt.bit_length()
self.storage:list = [collections.defaultdict(list) for _ in range(size.bit_length() + 1)]
# self.blocks is more like a linked list, where each entry is a contigous block.
self.blocks:dict[int, tuple[int, Optional[int], Optional[int], bool]] = {0: (size, None, None, True)} # size, next, prev, is_free
self._insert_block(0, size)
def lv1(self, size): return size.bit_length()
def lv2(self, size): return (size - (1 << (size.bit_length() - 1))) // (1 << max(0, size.bit_length() - self.l2_cnt))
def _insert_block(self, start:int, size:int, prev:Optional[int]=None):
if prev is None: prev = self.blocks[start][2]
self.storage[self.lv1(size)][self.lv2(size)].append(start)
self.blocks[start] = (size, start + size, prev, True)
return self
def _remove_block(self, start:int, size:int, prev:Optional[int]=None):
if prev is None: prev = self.blocks[start][2]
self.storage[self.lv1(size)][self.lv2(size)].remove(start)
self.blocks[start] = (size, start + size, prev, False)
return self
def _split_block(self, start:int, size:int, new_size:int):
nxt = self.blocks[start][1]
assert self.blocks[start][3], "block must be free"
self._remove_block(start, size)._insert_block(start, new_size)._insert_block(start + new_size, size - new_size, prev=start)
if nxt in self.blocks: self.blocks[nxt] = (self.blocks[nxt][0], self.blocks[nxt][1], start + new_size, self.blocks[nxt][3])
return self
def _merge_right(self, start:int):
size, nxt, _, is_free = self.blocks[start]
assert is_free, "block must be free"
while is_free and nxt in self.blocks:
if (blk:=self.blocks[nxt])[3] is False: break
self._remove_block(start, size)._remove_block(nxt, blk[0])._insert_block(start, size:=size + blk[0])
assert self.blocks[start][1] == blk[1]
_, nxt, _, _ = self.blocks.pop(nxt)
if nxt in self.blocks: self.blocks[nxt] = (self.blocks[nxt][0], self.blocks[nxt][1], start, self.blocks[nxt][3])
def _merge_block(self, start:int):
# Go left while blocks are free. Then merge all them right.
while (x:=self.blocks[start][2]) is not None and self.blocks[x][3] is True: start = x
self._merge_right(start)
def alloc(self, req_size:int, align:int=1) -> int:
req_size = max(self.block_size, req_size) # at least block size.
size = max(self.block_size, req_size + align - 1)
# Round up the allocation size to the next bucket, so any entry there can fit the requested size.
size = round_up(size, (1 << size.bit_length() - self.l2_cnt))
# Search for the smallest block that can fit the requested size. Start with the it's bucket and go up until any block is found.
for l1 in range(self.lv1(size), len(self.storage)):
for l2 in range(self.lv2(size) if l1 == size.bit_length() else 0, (1 << self.l2_cnt)):
if len(self.storage[l1][l2]) > 0:
nsize = self.blocks[self.storage[l1][l2][0]][0]
assert nsize >= size, "block must be larger"
# Block start address.
start = self.storage[l1][l2][0]
# If request contains alignment, split the block into two parts.
if (new_start:=round_up(start, align)) != start:
self._split_block(start, nsize, new_start - start)
start, nsize = new_start, self.blocks[new_start][0]
# If the block is larger than the requested size, split it into two parts.
if nsize > req_size: self._split_block(start, nsize, req_size)
self._remove_block(start, req_size) # Mark the block as allocated.
return start + self.base
raise MemoryError(f"Can't allocate {req_size} bytes")
def free(self, start:int):
self._insert_block(start - self.base, self.blocks[start - self.base][0])._merge_block(start - self.base)
tinygrad/runtime/support/am/__init__.py
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tinygrad/runtime/support/am/amdev.py
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from __future__ import annotations
import ctypes, collections, time, dataclasses, pathlib
from typing import Optional
from tinygrad.helpers import to_mv, mv_address, getenv, round_up
from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0
from tinygrad.runtime.support.allocator import TLSFAllocator
from tinygrad.runtime.support.am.ip import AM_SOC21, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA
AM_DEBUG = getenv("AM_DEBUG", 0)
@dataclasses.dataclass(frozen=True)
class AMRegister:
adev:AMDev; reg_off:int; reg_fields:dict[str, tuple[int, int]] # noqa: E702
def _parse_kwargs(self, **kwargs):
mask, values = 0xffffffff, 0
for k, v in kwargs.items():
if k not in self.reg_fields: raise ValueError(f"Unknown register field: {k}. {self.reg_fields.keys()}")
m, s = self.reg_fields[k]
if v & (m>>s) != v: raise ValueError(f"Value {v} for {k} is out of range {m=} {s=}")
mask &= ~m
values |= v << s
return mask, values
def build(self, **kwargs) -> int: return self._parse_kwargs(**kwargs)[1]
def update(self, **kwargs): self.write(value=self.read(), **kwargs)
def write(self, value=0, **kwargs):
mask, values = self._parse_kwargs(**kwargs)
self.adev.wreg(self.reg_off, (value & mask) | values)
def read(self, **kwargs): return self.adev.rreg(self.reg_off) & self._parse_kwargs(**kwargs)[0]
class AMFirmware:
def __init__(self):
# Load SOS firmware
self.sos_fw = {}
blob, sos_hdr = self.load_fw("psp_13_0_0_sos.bin", am.struct_psp_firmware_header_v2_0)
fw_bin = sos_hdr.psp_fw_bin
for fw_i in range(sos_hdr.psp_fw_bin_count):
fw_bin_desc = am.struct_psp_fw_bin_desc.from_address(ctypes.addressof(fw_bin) + fw_i * ctypes.sizeof(am.struct_psp_fw_bin_desc))
ucode_start_offset = fw_bin_desc.offset_bytes + sos_hdr.header.ucode_array_offset_bytes
self.sos_fw[fw_bin_desc.fw_type] = blob[ucode_start_offset:ucode_start_offset+fw_bin_desc.size_bytes]
# Load other fw
self.ucode_start: dict[str, int] = {}
self.descs: list[tuple[int, memoryview]] = []
blob, hdr = self.load_fw("smu_13_0_0.bin", am.struct_smc_firmware_header_v1_0)
self.smu_psp_desc = self.desc(am.GFX_FW_TYPE_SMU, blob, hdr.header.ucode_array_offset_bytes, hdr.header.ucode_size_bytes)
# SDMA firmware
blob, hdr = self.load_fw("sdma_6_0_0.bin", am.struct_sdma_firmware_header_v2_0)
self.descs += [self.desc(am.GFX_FW_TYPE_SDMA_UCODE_TH0, blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes)]
self.descs += [self.desc(am.GFX_FW_TYPE_SDMA_UCODE_TH1, blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes)]
# PFP, ME, MEC firmware
for (fw_name, fw_cnt) in [('PFP', 2), ('ME', 2), ('MEC', 4)]:
blob, hdr = self.load_fw(f"gc_11_0_0_{fw_name.lower()}.bin", am.struct_gfx_firmware_header_v2_0)
# Code part
self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}'), blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes)]
# Stack
fw_types = [getattr(am, f'GFX_FW_TYPE_RS64_{fw_name}_P{fwnun}_STACK') for fwnun in range(fw_cnt)]
self.descs += [self.desc(typ, blob, hdr.data_offset_bytes, hdr.data_size_bytes) for typ in fw_types]
self.ucode_start[fw_name] = hdr.ucode_start_addr_lo | (hdr.ucode_start_addr_hi << 32)
# IMU firmware
blob, hdr = self.load_fw("gc_11_0_0_imu.bin", am.struct_imu_firmware_header_v1_0)
imu_i_off, imu_i_sz, imu_d_sz = hdr.header.ucode_array_offset_bytes, hdr.imu_iram_ucode_size_bytes, hdr.imu_dram_ucode_size_bytes
self.descs += [self.desc(am.GFX_FW_TYPE_IMU_I, blob, imu_i_off, imu_i_sz), self.desc(am.GFX_FW_TYPE_IMU_D, blob, imu_i_off + imu_i_sz, imu_d_sz)]
# RLC firmware
blob, hdr0, hdr1, hdr2, hdr3 = self.load_fw("gc_11_0_0_rlc.bin", am.struct_rlc_firmware_header_v2_0,
am.struct_rlc_firmware_header_v2_1, am.struct_rlc_firmware_header_v2_2, am.struct_rlc_firmware_header_v2_3)
for mem in ['GPM', 'SRM']:
off, sz = getattr(hdr1, f'save_restore_list_{mem.lower()}_offset_bytes'), getattr(hdr1, f'save_restore_list_{mem.lower()}_size_bytes')
self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RLC_RESTORE_LIST_{mem}_MEM'), blob, off, sz)]
for mem,fmem in [('IRAM', 'iram'), ('DRAM_BOOT', 'dram')]:
off, sz = getattr(hdr2, f'rlc_{fmem}_ucode_offset_bytes'), getattr(hdr2, f'rlc_{fmem}_ucode_size_bytes')
self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RLC_{mem}'), blob, off, sz)]
for mem in ['P', 'V']:
off, sz = getattr(hdr3, f'rlc{mem.lower()}_ucode_offset_bytes'), getattr(hdr3, f'rlc{mem.lower()}_ucode_size_bytes')
self.descs += [self.desc(getattr(am, f'GFX_FW_TYPE_RLC_{mem}'), blob, off, sz)]
self.descs += [self.desc(am.GFX_FW_TYPE_RLC_G, blob, hdr0.header.ucode_array_offset_bytes, hdr0.header.ucode_size_bytes)]
def load_fw(self, fname:str, *headers):
fpath = next(f for loc in ["/lib/firmware/updates/amdgpu/", "/lib/firmware/amdgpu/"] if (f:=pathlib.Path(loc + fname)).exists())
blob = memoryview(bytearray(fpath.read_bytes()))
return tuple([blob] + [hdr.from_address(mv_address(blob)) for hdr in headers])
def desc(self, typ:int, blob:memoryview, offset:int, size:int) -> tuple[int, memoryview]: return (typ, blob[offset:offset+size])
class AMPhysicalMemoryBlock:
def __init__(self, adev:AMDev, paddr:int, size:int): self.adev, self.paddr, self.size = adev, paddr, size
def mc_addr(self): return self.adev.gmc.mc_base + self.paddr
def cpu_addr(self): return mv_address(self.adev.vram) + self.paddr
def cpu_view(self): return to_mv(self.cpu_addr(), self.size)
@dataclasses.dataclass(frozen=True)
class AMVirtualMapping: va_addr:int; size:int; cpu_addr:Optional[int]=None; paddr:Optional[int]=None # noqa: E702
class AMPageTableEntry:
def __init__(self, pm, lv): self.pm, self.view, self.lv = pm, pm.cpu_view().cast('Q'), lv
def set_table(self, entry_id, pte:AMPageTableEntry, valid=True):
self.view[entry_id] = (pte.pm.paddr & 0x0000FFFFFFFFF000) | (am.AMDGPU_PTE_VALID if valid else 0)
def set_page(self, entry_id, paddr, uncached=False, system=False, snooped=False, frag=0, valid=True):
f = (am.AMDGPU_PTE_VALID if valid else 0) | am.AMDGPU_PTE_WRITEABLE | am.AMDGPU_PTE_READABLE | am.AMDGPU_PTE_EXECUTABLE \
| am.AMDGPU_PTE_FRAG(frag) | (am.AMDGPU_PDE_PTE if self.lv != am.AMDGPU_VM_PTB else 0) \
| ((am.AMDGPU_PTE_SYSTEM) if system else 0) | ((am.AMDGPU_PTE_SNOOPED) if snooped else 0) \
| (am.AMDGPU_PTE_MTYPE_NV10(0, am.MTYPE_UC) if uncached else 0)
self.view[entry_id] = (paddr & 0x0000FFFFFFFFF000) | f
def get_entry(self, entry_id): return self.view[entry_id]
class AMMemoryManager:
va_allocator = TLSFAllocator(512 * (1 << 30), base=0x7F0000000000) # global for all devices.
def __init__(self, adev, vram_size:int):
self.adev, self.vram_size = adev, vram_size
self.pa_allocator = TLSFAllocator(vram_size - (64 << 20)) # per device
self.root_page_table = AMPageTableEntry(self.palloc(0x1000, zero=True), lv=am.AMDGPU_VM_PDB1)
def page_table_walker(self, page_table, vaddr, size, offset=0, free_pt=False, creat_pt=True):
"""
The function traverses the page table structure, yielding the largest entries that cover the requested virtual address range.
"""
pte_covers = 1 << ((9 * (3-page_table.lv)) + 12)
assert size // pte_covers < 512, "Size must be less than 512 ptes"
def _move_cursor(sz):
nonlocal vaddr, offset, size
vaddr, offset, size = vaddr + sz, offset + sz, size - sz
def _level_down(va, sz):
entry = page_table.get_entry(pte_idx:=(va // pte_covers) % 512)
if entry & am.AMDGPU_PTE_VALID:
assert entry & am.AMDGPU_PDE_PTE == 0, f"Must be table pt={page_table.pm.paddr:#x}, {pte_idx=} {entry=:#x}"
child_page_table = AMPageTableEntry(AMPhysicalMemoryBlock(page_table.pm.adev, entry & 0x0000FFFFFFFFF000, 0x1000), lv=page_table.lv+1)
else:
assert creat_pt, "Not allowed to create new page table"
child_page_table = AMPageTableEntry(self.palloc(0x1000, zero=True), lv=page_table.lv+1)
page_table.set_table(pte_idx, child_page_table)
yield from self.page_table_walker(child_page_table, va, sz, offset=offset, free_pt=free_pt, creat_pt=creat_pt)
if free_pt and all(child_page_table.get_entry(i) & am.AMDGPU_PTE_VALID == 0 for i in range(512)):
self.pfree(child_page_table.pm)
page_table.set_page(pte_idx, paddr=0x0, valid=False)
# First pte is not full covered
if vaddr % pte_covers != 0:
yield from _level_down(vaddr, min(pte_covers - (vaddr % pte_covers), size))
_move_cursor(min(pte_covers - (vaddr % pte_covers), size))
n_ptes = size // pte_covers
if n_ptes > 0: yield (vaddr, offset, (vaddr // pte_covers) % 512, n_ptes, pte_covers, page_table)
_move_cursor(n_ptes * pte_covers)
# Last pte is not full covered
if size > 0: yield from _level_down(vaddr, size)
def frags_walker(self, page_table, vaddr, size, from_entry=False, free_pt=False, creat_pt=True):
"""
The TLB hardware has a feature to optimize the number of entries when mapping contiguous regions.
The function yields the largest possible fragments to cover the requested area.
"""
for va, off, pte_st_idx, n_ptes, pte_covers, pt in self.page_table_walker(page_table, vaddr, size, free_pt=free_pt, creat_pt=creat_pt):
inner_off = 0
while n_ptes > 0:
if from_entry: frags_cnt = (pt.get_entry(pte_st_idx) >> 7) & 0x1f
else: frags_cnt = pte_covers.bit_length() - 13 # TODO: optimize for other frag sizes
update_ptes = (1 << (frags_cnt + 12)) // pte_covers
assert update_ptes > 0, f"Invalid update_ptes {update_ptes} {frags_cnt} {pte_covers}"
yield va + inner_off, off + inner_off, pte_st_idx, update_ptes, pte_covers, pt, frags_cnt
pte_st_idx, n_ptes, inner_off = pte_st_idx + update_ptes, n_ptes - update_ptes, inner_off + pte_covers * update_ptes
def _try_alloc(self, pte_cnt, pte_cvrs, frags_cnt):
# Try to allocate contiguous physical memory.
try: return self.pa_allocator.alloc(pte_cnt * pte_cvrs), pte_cnt, frags_cnt
except MemoryError:
if pte_cnt > 1: return self._try_alloc(pte_cnt // 2, pte_cvrs, frags_cnt - 1)
raise
def map_range(self, vaddr, size, paddr=None, uncached=False, system=False, snooped=False):
if AM_DEBUG >= 2: print(f"Mapping {vaddr=:#x} -> {paddr} ({size=:#x})")
vaddr = vaddr - AMMemoryManager.va_allocator.base
for _, off, pte_st_idx, n_ptes, pte_covers, pt, frags_cnt in self.frags_walker(self.root_page_table, vaddr, size):
while n_ptes > 0:
# Trying to alloc the contigous frags when possible.
(lpaddr, upd_pte, f_cnt), off = (self._try_alloc(n_ptes, pte_covers, frags_cnt), 0) if paddr is None else ((paddr, n_ptes, frags_cnt), off)
for pte_idx in range(upd_pte):
assert (pe:=pt.get_entry(pte_st_idx + pte_idx)) & am.AMDGPU_PTE_VALID == 0, f"Entry already set {pe:#x}"
pt.set_page(pte_st_idx + pte_idx, paddr=lpaddr + off, uncached=uncached, system=system, snooped=snooped, frag=f_cnt, valid=True)
off += pte_covers
if AM_DEBUG >= 3: print(f"\tnptes={upd_pte:#x} incr={pte_covers:#x} upd_flags={pt.get_entry(pte_st_idx):#x} frags={f_cnt:#x}")
n_ptes, pte_st_idx = n_ptes - upd_pte, pte_st_idx + upd_pte
# Invalidate TLB after mappings.
self.adev.gmc.flush_tlb(ip="GC", vmid=0, flush_type=2)
self.adev.gmc.flush_tlb(ip="GC", vmid=0)
self.adev.gmc.flush_tlb(ip="MM", vmid=0, flush_type=2)
self.adev.gmc.flush_tlb(ip="MM", vmid=0)
def unmap_range(self, vaddr:int, size:int, free_paddrs=True):
if AM_DEBUG >= 2: print(f"Unmapping {vaddr=:#x} ({size=:#x})")
vaddr = vaddr - AMMemoryManager.va_allocator.base
for _, _, pte_st_idx, n_ptes, _, pt, _ in self.frags_walker(self.root_page_table, vaddr, size, from_entry=True, free_pt=True):
entry = pt.get_entry(pte_st_idx)
if not (entry & am.AMDGPU_PTE_SYSTEM) and free_paddrs: self.pa_allocator.free(entry & 0x0000FFFFFFFFF000)
for pte_idx in range(n_ptes):
assert pt.get_entry(pte_st_idx + pte_idx) & am.AMDGPU_PTE_VALID == am.AMDGPU_PTE_VALID, "Entry must be set"
pt.set_page(pte_st_idx + pte_idx, paddr=0x0, valid=False)
def map_from(self, vaddr:int, size:int, from_adev):
if AM_DEBUG >= 2: print(f"Mapping from {vaddr=:#x} {size=:#x} from {from_adev.pcidev}")
vaddr = vaddr - AMMemoryManager.va_allocator.base
for va, _, pte_st_idx, n_ptes, pte_covers, pt, _ in self.frags_walker(from_adev.mm.root_page_table, vaddr, size, from_entry=True, creat_pt=False):
entry = pt.get_entry(pte_st_idx)
paddr = (entry & 0x0000FFFFFFFFF000) if entry & am.AMDGPU_PTE_SYSTEM else (entry & 0x0000FFFFFFFFF000) + from_adev.pcidev.regions[0].base_addr
self.map_range(va + AMMemoryManager.va_allocator.base, n_ptes * pte_covers, paddr=paddr, system=True,
uncached=bool(entry & am.AMDGPU_PTE_MTYPE_NV10(0, am.MTYPE_UC)), snooped=bool(entry & am.AMDGPU_PTE_SNOOPED))
@staticmethod
def alloc_vaddr(size:int, align=0x1000) -> int: return AMMemoryManager.va_allocator.alloc(size, max((1 << (size.bit_length() - 1)), align))
def valloc(self, size:int, align=0x1000, uncached=False, contigous=False) -> AMVirtualMapping:
pm = self.palloc(round_up(size, 0x1000), zero=True) if contigous else None
self.map_range(va:=self.alloc_vaddr(size, align), size, paddr=pm.paddr if pm else None, uncached=uncached)
return AMVirtualMapping(va, size, pm.cpu_addr() if pm is not None else None, pm.paddr if pm is not None else None)
def vfree(self, vm:AMVirtualMapping):
self.unmap_range(vm.va_addr, vm.size, free_paddrs=(vm.paddr is None))
self.va_allocator.free(vm.va_addr)
if vm.paddr is not None: self.pa_allocator.free(vm.paddr)
def palloc(self, size, align=0x1000, zero=True) -> AMPhysicalMemoryBlock:
pm = AMPhysicalMemoryBlock(self.adev, self.pa_allocator.alloc(round_up(size, 0x1000), align), size)
if zero: ctypes.memset(pm.cpu_addr(), 0, pm.size)
return pm
def pfree(self, pm:AMPhysicalMemoryBlock): self.pa_allocator.free(pm.paddr)
class AMDev:
def __init__(self, pcidev, vram_bar:memoryview, doorbell_bar:memoryview, mmio_bar:memoryview):
self.pcidev = pcidev
self.vram, self.doorbell64, self.mmio = vram_bar, doorbell_bar, mmio_bar
self._run_discovery()
self._build_regs()
# Memory manager & firmware
self.mm = AMMemoryManager(self, self.vram_size)
self.fw = AMFirmware()
# Initialize IP blocks
self.soc21:AM_SOC21 = AM_SOC21(self)
self.gmc:AM_GMC = AM_GMC(self)
self.ih:AM_IH = AM_IH(self)
self.psp:AM_PSP = AM_PSP(self)
self.smu:AM_SMU = AM_SMU(self)
self.gfx:AM_GFX = AM_GFX(self)
self.sdma:AM_SDMA = AM_SDMA(self)
if self.psp.is_sos_alive(): self.smu.mode1_reset()
# Initialize all blocks
for ip in [self.soc21, self.gmc, self.ih, self.psp, self.smu, self.gfx, self.sdma]: ip.init()
self.gfx.set_clockgating_state()
def ip_base(self, ip:str, inst:int, seg:int) -> int: return self.regs_offset[am.__dict__[f"{ip}_HWIP"]][inst][seg]
def reg(self, reg:str) -> AMRegister: return self.__dict__[reg]
def rreg(self, reg:int) -> int:
val = self.indirect_rreg(reg * 4) if reg > len(self.mmio) else self.mmio[reg]
if AM_DEBUG >= 4 and getattr(self, '_prev_rreg', None) != (reg, val): print(f"Reading register {reg:#x} with value {val:#x}")
self._prev_rreg = (reg, val)
return val
def wreg(self, reg:int, val:int):
if AM_DEBUG >= 4: print(f"Writing register {reg:#x} with value {val:#x}")
if reg > len(self.mmio): self.indirect_wreg(reg * 4, val)
else: self.mmio[reg] = val
def wreg_pair(self, reg_base:str, lo_suffix:str, hi_suffix:str, val:int):
self.reg(f"{reg_base}{lo_suffix}").write(val & 0xffffffff)
self.reg(f"{reg_base}{hi_suffix}").write(val >> 32)
def indirect_rreg(self, reg:int) -> int:
self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg)
return self.reg("regBIF_BX_PF0_RSMU_DATA").read()
def indirect_wreg(self, reg:int, val:int):
self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg)
self.reg("regBIF_BX_PF0_RSMU_DATA").write(val)
def wait_reg(self, reg:AMRegister, value:int, mask=0xffffffff) -> int:
for _ in range(10000):
if ((rval:=reg.read()) & mask) == value: return rval
time.sleep(0.001)
raise RuntimeError(f'wait_reg timeout reg=0x{reg.reg_off:X} mask=0x{mask:X} value=0x{value:X} last_val=0x{rval}')
def _run_discovery(self):
# NOTE: Fixed register to query memory size without known ip bases to find the discovery table.
# The table is located at the end of VRAM - 64KB and is 10KB in size.
mmRCC_CONFIG_MEMSIZE = 0xde3
self.vram_size = self.rreg(mmRCC_CONFIG_MEMSIZE) << 20
self.discovery_pm = AMPhysicalMemoryBlock(self, self.vram_size - (64 << 10), 10 << 10)
bhdr = am.struct_binary_header.from_address(self.discovery_pm.cpu_addr())
ihdr = am.struct_ip_discovery_header.from_address(ctypes.addressof(bhdr) + bhdr.table_list[am.IP_DISCOVERY].offset)
assert ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE and not ihdr.base_addr_64_bit
# Mapping of HW IP to Discovery HW IP
hw_id_map = {am.__dict__[x]: int(y) for x,y in am.hw_id_map}
self.regs_offset:dict[int, dict[int, list]] = collections.defaultdict(dict)
for num_die in range(ihdr.num_dies):
dhdr = am.struct_die_header.from_address(ctypes.addressof(bhdr) + ihdr.die_info[num_die].die_offset)
ip_offset = ctypes.addressof(bhdr) + ctypes.sizeof(dhdr) + ihdr.die_info[num_die].die_offset
for _ in range(dhdr.num_ips):
ip = am.struct_ip_v4.from_address(ip_offset)
ba = (ctypes.c_uint32 * ip.num_base_address).from_address(ip_offset + 8)
for hw_ip in range(1, am.MAX_HWIP):
if hw_ip in hw_id_map and hw_id_map[hw_ip] == ip.hw_id: self.regs_offset[hw_ip][ip.instance_number] = list(ba)
ip_offset += 8 + (8 if ihdr.base_addr_64_bit else 4) * ip.num_base_address
def _build_regs(self):
mods = [("MP0", mp_13_0_0), ("MP1", mp_11_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)]
for base, module in mods:
rpref = "mm" if base == "MP1" else "reg" # MP1 regs starts with mm
reg_names: set[str] = set(k[len(rpref):] for k in module.__dict__.keys() if k.startswith(rpref) and not k.endswith("_BASE_IDX"))
reg_fields: dict[str, dict[str, tuple]] = collections.defaultdict(dict)
for k, val in module.__dict__.items():
if k.endswith("_MASK") and ((rname:=k.split("__")[0]) in reg_names):
reg_fields[rname][k[2+len(rname):-5].lower()] = (val, module.__dict__.get(f"{k[:-5]}__SHIFT", val.bit_length() - 1))
for k, regval in module.__dict__.items():
if k.startswith(rpref) and not k.endswith("_BASE_IDX") and (base_idx:=getattr(module, f"{k}_BASE_IDX", None)) is not None:
setattr(self, k, AMRegister(self, self.ip_base(base, 0, base_idx) + regval, reg_fields.get(k[len(rpref):], {})))
tinygrad/runtime/support/am/ip.py
+412
View File
@@ -0,0 +1,412 @@
from __future__ import annotations
import ctypes, time
from typing import Literal
from tinygrad.runtime.autogen import libpciaccess
from tinygrad.runtime.autogen.am import am, gc_11_0_0, smu_v13_0_0
from tinygrad.helpers import to_mv, data64, lo32, hi32
class AM_IP:
def __init__(self, adev): self.adev = adev
def init(self): raise NotImplementedError("IP block init must be implemeted")
class AM_SOC21(AM_IP):
def init(self):
self.adev.regRCC_DEV0_EPF2_STRAP2.update(strap_no_soft_reset_dev0_f2=0x0)
self.adev.regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN.write(0x1)
class AM_GMC(AM_IP):
def __init__(self, adev):
super().__init__(adev)
# Memory controller aperture
self.mc_base = self.adev.regMMMC_VM_FB_LOCATION_BASE.read() << 24
self.mc_end = self.mc_base + self.adev.mm.vram_size - 1
# VM aperture
self.vm_base = self.adev.mm.va_allocator.base
self.vm_end = self.vm_base + self.adev.mm.va_allocator.size - 1
self.memscratch_pm = self.adev.mm.palloc(0x1000)
self.dummy_page_pm = self.adev.mm.palloc(0x1000)
self.hub_initted = {"MM": False, "GC": False}
def init(self): self.init_hub("MM")
def flush_hdp(self): self.adev.regBIF_BX_PF0_GPU_HDP_FLUSH_REQ.write(0xffffffff)
def flush_tlb(self, ip:Literal["MM", "GC"], vmid, flush_type=0):
self.flush_hdp()
# Can't issue TLB invalidation if the hub isn't initialized.
if not self.hub_initted[ip]: return
if ip == "MM": self.adev.wait_reg(self.adev.regMMVM_INVALIDATE_ENG17_SEM, mask=0x1, value=0x1)
self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_REQ").write(flush_type=flush_type, per_vmid_invalidate_req=(1 << vmid), invalidate_l2_ptes=1,
invalidate_l2_pde0=1, invalidate_l2_pde1=1, invalidate_l2_pde2=1, invalidate_l1_ptes=1, clear_protection_fault_status_addr=0)
self.adev.wait_reg(self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_ACK"), mask=(1 << vmid), value=(1 << vmid))
if ip == "MM":
self.adev.regMMVM_INVALIDATE_ENG17_SEM.write(0x0)
self.adev.regMMVM_L2_BANK_SELECT_RESERVED_CID2.update(reserved_cache_private_invalidation=1)
# Read back the register to ensure the invalidation is complete
self.adev.regMMVM_L2_BANK_SELECT_RESERVED_CID2.read()
def enable_vm_addressing(self, page_table, ip:Literal["MM", "GC"], vmid):
self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_START_ADDR", "_LO32", "_HI32", self.vm_base >> 12)
self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_END_ADDR", "_LO32", "_HI32", self.vm_end >> 12)
self.adev.wreg_pair(f"reg{ip}VM_CONTEXT{vmid}_PAGE_TABLE_BASE_ADDR", "_LO32", "_HI32", page_table.pm.paddr | 1)
self.adev.reg(f"reg{ip}VM_CONTEXT{vmid}_CNTL").write(0x1fffe00, enable_context=1, page_table_depth=(3 - page_table.lv))
def init_hub(self, ip:Literal["MM", "GC"]):
# Init system apertures
self.adev.reg(f"reg{ip}MC_VM_AGP_BASE").write(0)
self.adev.reg(f"reg{ip}MC_VM_AGP_BOT").write(0xffffffffffff >> 24) # disable AGP
self.adev.reg(f"reg{ip}MC_VM_AGP_TOP").write(0)
self.adev.reg(f"reg{ip}MC_VM_SYSTEM_APERTURE_LOW_ADDR").write(self.mc_base >> 18)
self.adev.reg(f"reg{ip}MC_VM_SYSTEM_APERTURE_HIGH_ADDR").write(self.mc_end >> 18)
self.adev.wreg_pair(f"reg{ip}MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", "_LSB", "_MSB", self.memscratch_pm.paddr >> 12)
self.adev.wreg_pair(f"reg{ip}VM_L2_PROTECTION_FAULT_DEFAULT_ADDR", "_LO32", "_HI32", self.dummy_page_pm.paddr >> 12)
self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_CNTL2").update(active_page_migration_pte_read_retry=1)
# Init TLB and cache
self.adev.reg(f"reg{ip}MC_VM_MX_L1_TLB_CNTL").update(enable_l1_tlb=1, system_access_mode=3, enable_advanced_driver_model=1,
system_aperture_unmapped_access=0, eco_bits=0, mtype=am.MTYPE_UC)
self.adev.reg(f"reg{ip}VM_L2_CNTL").update(enable_l2_cache=1, enable_l2_fragment_processing=0, enable_default_page_out_to_system_memory=1,
l2_pde0_cache_tag_generation_mode=0, pde_fault_classification=0, context1_identity_access_mode=1, identity_mode_fragment_size=0)
self.adev.reg(f"reg{ip}VM_L2_CNTL2").update(invalidate_all_l1_tlbs=1, invalidate_l2_cache=1)
self.adev.reg(f"reg{ip}VM_L2_CNTL3").write(bank_select=9, l2_cache_bigk_fragment_size=6,l2_cache_4k_associativity=1,l2_cache_bigk_associativity=1)
self.adev.reg(f"reg{ip}VM_L2_CNTL4").write(l2_cache_4k_partition_count=1)
self.adev.reg(f"reg{ip}VM_L2_CNTL5").write(walker_priority_client_id=0x1ff)
self.enable_vm_addressing(self.adev.mm.root_page_table, ip, vmid=0)
# Disable identity aperture
self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", "_LO32", "_HI32", 0xfffffffff)
self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", "_LO32", "_HI32", 0x0)
self.adev.wreg_pair(f"reg{ip}VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", "_LO32", "_HI32", 0x0)
for eng_i in range(18): self.adev.wreg_pair(f"reg{ip}VM_INVALIDATE_ENG{eng_i}_ADDR_RANGE", "_LO32", "_HI32", 0x1fffffffff)
self.hub_initted[ip] = True
def on_interrupt(self):
for ip in ["MM", "GC"]:
st, va = self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_STATUS').read(), self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_LO32').read()
va = (va | (self.adev.reg(f'reg{ip}VM_L2_PROTECTION_FAULT_ADDR_HI32').read()) << 32) << 12
if self.adev.reg(f"reg{ip}VM_L2_PROTECTION_FAULT_STATUS").read(): raise RuntimeError(f"{ip}VM_L2_PROTECTION_FAULT_STATUS: {st:#x} {va:#x}")
class AM_SMU(AM_IP):
def init(self):
self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_EnableAllSmuFeatures, 0, poll=True)
for clck in [0x00000C94, 0x000204E1, 0x000105DC, 0x00050B76, 0x00070B76, 0x00040898, 0x00060898, 0x000308FD]:
self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_SetSoftMinByFreq, clck, poll=True)
self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_SetSoftMaxByFreq, clck, poll=True)
def mode1_reset(self):
self._smu_cmn_send_smc_msg_with_param(smu_v13_0_0.PPSMC_MSG_Mode1Reset, 0, poll=True)
time.sleep(0.5)
def _smu_cmn_poll_stat(self): self.adev.wait_reg(self.adev.mmMP1_SMN_C2PMSG_90, mask=0xFFFFFFFF, value=1)
def _smu_cmn_send_msg(self, msg, param=0):
self.adev.mmMP1_SMN_C2PMSG_90.write(0) # resp reg
self.adev.mmMP1_SMN_C2PMSG_82.write(param)
self.adev.mmMP1_SMN_C2PMSG_66.write(msg)
def _smu_cmn_send_smc_msg_with_param(self, msg, param, poll=True, read_back_arg=False):
if poll: self._smu_cmn_poll_stat()
self._smu_cmn_send_msg(msg, param)
self._smu_cmn_poll_stat()
return self.adev.rreg(self.adev.mmMP1_SMN_C2PMSG_82) if read_back_arg else None
class AM_GFX(AM_IP):
def init(self):
self._wait_for_rlc_autoload()
self._config_gfx_rs64()
self.adev.gmc.init_hub("GC")
# NOTE: Golden reg for gfx11. No values for this reg provided. The kernel just ors 0x20000000 to this reg.
self.adev.regTCP_CNTL.write(self.adev.regTCP_CNTL.read() | 0x20000000)
self.adev.regRLC_SRM_CNTL.update(srm_enable=1, auto_incr_addr=1)
self.adev.regGRBM_CNTL.update(read_timeout=0xff)
for i in range(0, 16):
self._grbm_select(vmid=i)
self.adev.regSH_MEM_CONFIG.write(address_mode=am.SH_MEM_ADDRESS_MODE_64, alignment_mode=am.SH_MEM_ALIGNMENT_MODE_UNALIGNED,
initial_inst_prefetch=3)
# Configure apertures:
# LDS: 0x10000000'00000000 - 0x10000001'00000000 (4GB)
# Scratch: 0x20000000'00000000 - 0x20000001'00000000 (4GB)
self.adev.regSH_MEM_BASES.write(shared_base=0x1, private_base=0x2)
self._grbm_select()
# Configure MEC doorbell range
self.adev.regCP_MEC_DOORBELL_RANGE_LOWER.write(0x0)
self.adev.regCP_MEC_DOORBELL_RANGE_UPPER.write(0x450)
# Enable MEC
self.adev.regCP_MEC_RS64_CNTL.update(mec_invalidate_icache=0, mec_pipe0_reset=0, mec_pipe1_reset=0, mec_pipe2_reset=0, mec_pipe3_reset=0,
mec_pipe0_active=1, mec_pipe1_active=1, mec_pipe2_active=1, mec_pipe3_active=1, mec_halt=0)
# NOTE: Wait for MEC to be ready. The kernel does udelay here as well.
time.sleep(0.5)
def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, eop_addr:int, eop_size:int, doorbell:int, pipe:int, queue:int):
mqd = self.adev.mm.valloc(0x1000, uncached=True, contigous=True)
mqd_struct = am.struct_v11_compute_mqd(header=0xC0310800, cp_mqd_base_addr_lo=lo32(mqd.va_addr), cp_mqd_base_addr_hi=hi32(mqd.va_addr),
cp_hqd_persistent_state=self.adev.regCP_HQD_PERSISTENT_STATE.build(preload_size=0x55, preload_req=1),
cp_hqd_pipe_priority=0x2, cp_hqd_queue_priority=0xf, cp_hqd_quantum=0x111,
cp_hqd_pq_base_lo=lo32(ring_addr>>8), cp_hqd_pq_base_hi=hi32(ring_addr>>8),
cp_hqd_pq_rptr_report_addr_lo=lo32(rptr_addr), cp_hqd_pq_rptr_report_addr_hi=hi32(rptr_addr),
cp_hqd_pq_wptr_poll_addr_lo=lo32(wptr_addr), cp_hqd_pq_wptr_poll_addr_hi=hi32(wptr_addr),
cp_hqd_pq_doorbell_control=self.adev.regCP_HQD_PQ_DOORBELL_CONTROL.build(doorbell_offset=doorbell*2, doorbell_en=1),
cp_hqd_pq_control=self.adev.regCP_HQD_PQ_CONTROL.build(rptr_block_size=5, unord_dispatch=1, queue_size=(ring_size//4).bit_length()-2),
cp_hqd_ib_control=self.adev.regCP_HQD_IB_CONTROL.build(min_ib_avail_size=0x3), cp_hqd_hq_status0=0x20004000,
cp_mqd_control=self.adev.regCP_MQD_CONTROL.build(priv_state=1), cp_hqd_vmid=0,
cp_hqd_eop_base_addr_lo=lo32(eop_addr>>8), cp_hqd_eop_base_addr_hi=hi32(eop_addr>>8),
cp_hqd_eop_control=self.adev.regCP_HQD_EOP_CONTROL.build(eop_size=(eop_size//4).bit_length()-2))
# Copy mqd into memory
ctypes.memmove(mqd.cpu_addr, ctypes.addressof(mqd_struct), ctypes.sizeof(mqd_struct))
self.adev.gmc.flush_hdp()
self._grbm_select(me=1, pipe=pipe, queue=queue)
mqd_st_mv = to_mv(ctypes.addressof(mqd_struct), ctypes.sizeof(mqd_struct)).cast('I')
for i, reg in enumerate(range(self.adev.regCP_MQD_BASE_ADDR.reg_off, self.adev.regCP_HQD_PQ_WPTR_HI.reg_off + 1)):
self.adev.wreg(reg, mqd_st_mv[0x80 + i])
self.adev.regCP_HQD_ACTIVE.write(0x1)
self._grbm_select()
self.adev.reg(f"regCP_ME1_PIPE{pipe}_INT_CNTL").update(time_stamp_int_enable=1, generic0_int_enable=1)
def set_clockgating_state(self):
self.adev.regRLC_SAFE_MODE.write(message=1, cmd=1)
self.adev.wait_reg(self.adev.regRLC_SAFE_MODE, mask=0x1, value=0x0)
self.adev.regRLC_CGCG_CGLS_CTRL.update(cgcg_gfx_idle_threshold=0x36, cgcg_en=1, cgls_rep_compansat_delay=0xf, cgls_en=1)
self.adev.regCP_RB_WPTR_POLL_CNTL.update(poll_frequency=0x100, idle_poll_count=0x90)
self.adev.regCP_INT_CNTL.update(cntx_busy_int_enable=1, cntx_empty_int_enable=1, cmp_busy_int_enable=1, gfx_idle_int_enable=1)
self.adev.regSDMA0_RLC_CGCG_CTRL.update(cgcg_int_enable=1)
self.adev.regRLC_CGTT_MGCG_OVERRIDE.update(perfmon_clock_state=0, gfxip_fgcg_override=0, gfxip_repeater_fgcg_override=0,
grbm_cgtt_sclk_override=0, rlc_cgtt_sclk_override=0, gfxip_mgcg_override=0, gfxip_cgls_override=0)
self.adev.regRLC_SAFE_MODE.write(message=0, cmd=1)
def _grbm_select(self, me=0, pipe=0, queue=0, vmid=0): self.adev.regGRBM_GFX_CNTL.write(meid=me, pipeid=pipe, vmid=vmid, queueid=queue)
def _wait_for_rlc_autoload(self):
while True:
bootload_ready = (self.adev.regRLC_RLCS_BOOTLOAD_STATUS.read() & gc_11_0_0.RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK) != 0
if self.adev.regCP_STAT.read() == 0 and bootload_ready: break
def _config_gfx_rs64(self):
def _config_helper(eng_name, cntl_reg, eng_reg, pipe_cnt, me=0):
for pipe in range(pipe_cnt):
self._grbm_select(me=me, pipe=pipe)
self.adev.wreg_pair(f"regCP_{eng_reg}_PRGRM_CNTR_START", "", "_HI", self.adev.fw.ucode_start[eng_name] >> 2)
self._grbm_select()
self.adev.reg(f"regCP_{cntl_reg}_CNTL").update(**{f"{eng_name.lower()}_pipe{pipe}_reset": 1 for pipe in range(pipe_cnt)})
self.adev.reg(f"regCP_{cntl_reg}_CNTL").update(**{f"{eng_name.lower()}_pipe{pipe}_reset": 0 for pipe in range(pipe_cnt)})
_config_helper(eng_name="PFP", cntl_reg="ME", eng_reg="PFP", pipe_cnt=2)
_config_helper(eng_name="ME", cntl_reg="ME", eng_reg="ME", pipe_cnt=2)
_config_helper(eng_name="MEC", cntl_reg="MEC_RS64", eng_reg="MEC_RS64", pipe_cnt=4, me=1)
class AM_IH(AM_IP):
def interrupt_handler(self):
ring_vm, rwptr_vm, suf, _ = self.rings[0]
wptr = to_mv(rwptr_vm.cpu_addr, 8).cast('Q')[0]
if self.adev.reg(f"regIH_RB_WPTR{suf}").read(rb_overflow=1):
self.adev.reg(f"regIH_RB_WPTR{suf}").update(rb_overflow=0)
self.adev.reg(f"regIH_RB_CNTL{suf}").update(wptr_overflow_clear=1)
self.adev.reg(f"regIH_RB_CNTL{suf}").update(wptr_overflow_clear=0)
self.adev.regIH_RB_RPTR.write(wptr % ring_vm.size)
def init(self):
self.rings = [(self.adev.mm.valloc(1 << 20, uncached=True, contigous=True), self.adev.mm.valloc(0x1000, uncached=True, contigous=True), "", 0),
(self.adev.mm.valloc(1 << 20, uncached=True, contigous=True), self.adev.mm.valloc(0x1000, uncached=True, contigous=True), "_RING1", 1)]
for ring_vm, rwptr_vm, suf, ring_id in self.rings:
self.adev.wreg_pair("regIH_RB_BASE", suf, f"_HI{suf}", ring_vm.va_addr >> 8)
self.adev.reg(f"regIH_RB_CNTL{suf}").write(mc_space=4, wptr_overflow_clear=1, rb_size=(ring_vm.size//4).bit_length(),
mc_snoop=1, mc_ro=0, mc_vmid=0, **({'wptr_overflow_enable': 1, 'rptr_rearm': 1} if ring_id == 0 else {'rb_full_drain_enable': 1}))
if ring_id == 0: self.adev.wreg_pair("regIH_RB_WPTR_ADDR", "_LO", "_HI", rwptr_vm.va_addr)
self.adev.reg(f"regIH_RB_WPTR{suf}").write(0)
self.adev.reg(f"regIH_RB_RPTR{suf}").write(0)
self.adev.reg(f"regIH_DOORBELL_RPTR{suf}").write(((am.AMDGPU_NAVI10_DOORBELL_IH + ring_id) * 2), enable=1)
self.adev.regIH_STORM_CLIENT_LIST_CNTL.update(client18_is_storm_client=1)
self.adev.regIH_INT_FLOOD_CNTL.update(flood_cntl_enable=1)
self.adev.regIH_MSI_STORM_CTRL.update(delay=3)
libpciaccess.pci_device_cfg_read_u16(self.adev.pcidev, ctypes.byref(val:=ctypes.c_uint16()), libpciaccess.PCI_COMMAND)
libpciaccess.pci_device_cfg_write_u16(self.adev.pcidev, val.value | libpciaccess.PCI_COMMAND_MASTER, libpciaccess.PCI_COMMAND)
# toggle interrupts
for _, rwptr_vm, suf, ring_id in self.rings:
self.adev.reg(f"regIH_RB_CNTL{suf}").update(rb_enable=1, **({'enable_intr': 1} if ring_id == 0 else {}))
class AM_SDMA(AM_IP):
def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, doorbell:int, pipe:int, queue:int):
# Stop if something is running...
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_RB_CNTL").update(rb_enable=0)
while not self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_CONTEXT_STATUS").read(idle=1): pass
# Setup the ring
self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_RPTR", "", "_HI", 0)
self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_WPTR", "", "_HI", 0)
self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_BASE", "", "_HI", ring_addr >> 8)
self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_RPTR_ADDR", "_LO", "_HI", rptr_addr)
self.adev.wreg_pair(f"regSDMA{pipe}_QUEUE{queue}_RB_WPTR_POLL_ADDR", "_LO", "_HI", wptr_addr)
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL_OFFSET").update(offset=doorbell * 2)
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_DOORBELL").update(enable=1)
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_RB_CNTL").write(rb_vmid=0, rptr_writeback_enable=1, rptr_writeback_timer=4,
f32_wptr_poll_enable=1, rb_size=(ring_size//4).bit_length()-1, rb_enable=1, rb_priv=1)
self.adev.reg(f"regSDMA{pipe}_QUEUE{queue}_IB_CNTL").update(ib_enable=1)
def init(self):
self.adev.regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL.write(0x0)
self.adev.regSDMA0_WATCHDOG_CNTL.update(queue_hang_count=100) # 10s, 100ms per unit
self.adev.regSDMA0_UTCL1_CNTL.update(resp_mode=3, redo_delay=9)
self.adev.regSDMA0_UTCL1_PAGE.update(rd_l2_policy=0x2, wr_l2_policy=0x3, llc_noalloc=1) # rd=noa, wr=bypass
self.adev.regSDMA0_F32_CNTL.update(halt=0, th1_reset=0)
self.adev.regSDMA0_CNTL.update(ctxempty_int_enable=1, trap_enable=1)
class AM_PSP(AM_IP):
def __init__(self, adev):
super().__init__(adev)
self.msg1_pm = self.adev.mm.palloc(am.PSP_1_MEG, align=am.PSP_1_MEG)
self.cmd_pm = self.adev.mm.palloc(am.PSP_CMD_BUFFER_SIZE)
self.fence_pm = self.adev.mm.palloc(am.PSP_FENCE_BUFFER_SIZE)
self.ring_pm = self.adev.mm.palloc(0x10000)
def is_sos_alive(self): return self.adev.regMP0_SMN_C2PMSG_81.read() != 0x0
def init(self):
sos_components_load_order = [
(am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_KEY_DATABASE), (am.PSP_FW_TYPE_PSP_KDB, am.PSP_BL__LOAD_TOS_SPL_TABLE),
(am.PSP_FW_TYPE_PSP_SYS_DRV, am.PSP_BL__LOAD_SYSDRV), (am.PSP_FW_TYPE_PSP_SOC_DRV, am.PSP_BL__LOAD_SOCDRV),
(am.PSP_FW_TYPE_PSP_INTF_DRV, am.PSP_BL__LOAD_INTFDRV), (am.PSP_FW_TYPE_PSP_DBG_DRV, am.PSP_BL__LOAD_DBGDRV),
(am.PSP_FW_TYPE_PSP_RAS_DRV, am.PSP_BL__LOAD_RASDRV), (am.PSP_FW_TYPE_PSP_SOS, am.PSP_BL__LOAD_SOSDRV)]
for fw, compid in sos_components_load_order: self._bootloader_load_component(fw, compid)
while not self.is_sos_alive(): time.sleep(0.01)
self._ring_create()
self._tmr_init()
# SMU fw should be loaded before TMR.
self._load_ip_fw_cmd(self.adev.fw.smu_psp_desc)
self._tmr_load_cmd()
for psp_desc in self.adev.fw.descs: self._load_ip_fw_cmd(psp_desc)
self._rlc_autoload_cmd()
def _wait_for_bootloader(self): self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_35, mask=0xFFFFFFFF, value=0x80000000)
def _prep_msg1(self, data):
ctypes.memset(self.msg1_pm.cpu_addr(), 0, self.msg1_pm.size)
self.msg1_pm.cpu_view()[:len(data)] = data
self.adev.gmc.flush_hdp()
def _bootloader_load_component(self, fw, compid):
if fw not in self.adev.fw.sos_fw: return 0
self._wait_for_bootloader()
self._prep_msg1(self.adev.fw.sos_fw[fw])
self.adev.regMP0_SMN_C2PMSG_36.write(self.msg1_pm.mc_addr() >> 20)
self.adev.regMP0_SMN_C2PMSG_35.write(compid)
return self._wait_for_bootloader()
def _tmr_init(self):
# Load TOC and calculate TMR size
self._prep_msg1(fwm:=self.adev.fw.sos_fw[am.PSP_FW_TYPE_PSP_TOC])
resp = self._load_toc_cmd(len(fwm))
self.tmr_pm = self.adev.mm.palloc(resp.resp.tmr_size, align=am.PSP_TMR_ALIGNMENT)
def _ring_create(self):
# Wait until the sOS is ready
self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_64, mask=0x80000000, value=0x80000000)
self.adev.wreg_pair("regMP0_SMN_C2PMSG", "_69", "_70", self.ring_pm.mc_addr())
self.adev.regMP0_SMN_C2PMSG_71.write(self.ring_pm.size)
self.adev.regMP0_SMN_C2PMSG_64.write(am.PSP_RING_TYPE__KM << 16)
# There might be handshake issue with hardware which needs delay
time.sleep(0.1)
self.adev.wait_reg(self.adev.regMP0_SMN_C2PMSG_64, mask=0x8000FFFF, value=0x80000000)
def _ring_submit(self):
prev_wptr = self.adev.regMP0_SMN_C2PMSG_67.read()
ring_entry_addr = self.ring_pm.cpu_addr() + prev_wptr * 4
ctypes.memset(ring_entry_addr, 0, ctypes.sizeof(am.struct_psp_gfx_rb_frame))
write_loc = am.struct_psp_gfx_rb_frame.from_address(ring_entry_addr)
write_loc.cmd_buf_addr_hi, write_loc.cmd_buf_addr_lo = data64(self.cmd_pm.mc_addr())
write_loc.fence_addr_hi, write_loc.fence_addr_lo = data64(self.fence_pm.mc_addr())
write_loc.fence_value = prev_wptr
# Move the wptr
self.adev.regMP0_SMN_C2PMSG_67.write(prev_wptr + ctypes.sizeof(am.struct_psp_gfx_rb_frame) // 4)
while self.fence_pm.cpu_view().cast('I')[0] != prev_wptr: pass
time.sleep(0.05)
resp = am.struct_psp_gfx_cmd_resp.from_address(self.cmd_pm.cpu_addr())
if resp.resp.status != 0: raise RuntimeError(f"PSP command failed {resp.cmd_id} {resp.resp.status}")
return resp
def _prep_ring_cmd(self, hdr):
ctypes.memset(self.cmd_pm.cpu_addr(), 0, 0x1000)
cmd = am.struct_psp_gfx_cmd_resp.from_address(self.cmd_pm.cpu_addr())
cmd.cmd_id = hdr
return cmd
def _load_ip_fw_cmd(self, psp_desc):
fw_type, fw_bytes = psp_desc
self._prep_msg1(fw_bytes)
cmd = self._prep_ring_cmd(am.GFX_CMD_ID_LOAD_IP_FW)
cmd.cmd.cmd_load_ip_fw.fw_phy_addr_hi, cmd.cmd.cmd_load_ip_fw.fw_phy_addr_lo = data64(self.msg1_pm.mc_addr())
cmd.cmd.cmd_load_ip_fw.fw_size = len(fw_bytes)
cmd.cmd.cmd_load_ip_fw.fw_type = fw_type
return self._ring_submit()
def _tmr_load_cmd(self):
cmd = self._prep_ring_cmd(am.GFX_CMD_ID_SETUP_TMR)
cmd.cmd.cmd_setup_tmr.buf_phy_addr_hi, cmd.cmd.cmd_setup_tmr.buf_phy_addr_lo = data64(self.tmr_pm.mc_addr())
cmd.cmd.cmd_setup_tmr.system_phy_addr_hi, cmd.cmd.cmd_setup_tmr.system_phy_addr_lo = data64(self.tmr_pm.paddr)
cmd.cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1
cmd.cmd.cmd_setup_tmr.buf_size = self.tmr_pm.size
return self._ring_submit()
def _load_toc_cmd(self, toc_size):
cmd = self._prep_ring_cmd(am.GFX_CMD_ID_LOAD_TOC)
cmd.cmd.cmd_load_toc.toc_phy_addr_hi, cmd.cmd.cmd_load_toc.toc_phy_addr_lo = data64(self.msg1_pm.mc_addr())
cmd.cmd.cmd_load_toc.toc_size = toc_size
return self._ring_submit()
def _rlc_autoload_cmd(self):
self._prep_ring_cmd(am.GFX_CMD_ID_AUTOLOAD_RLC)
return self._ring_submit()