small changes and test fixes from kernel is call

make disk tensor tests process safe (#14584 )
hotfix: disable slower asm gemm shape from llama seqlen 8192 (#14582 )
2026-08-14 15:38:27 +00:00 · 2026-02-06 16:08:02 +08:00 · 2026-02-06 15:39:55 +08:00 · 2026-02-06 15:05:19 +09:00 · 2026-02-06 14:54:00 +09:00 · 2026-02-06 00:07:31 -05:00
440 changed files with 184287 additions and 149298 deletions
@@ -11,5 +11,5 @@ runs:
        git fetch origin $CURRENT_SHA
        export COMMIT_MESSAGE=$(git show -s --format=%B "$CURRENT_SHA")
        export CURRENT_HEAD=$(git rev-parse HEAD)
-        cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && IGNORE_OOB=1 PYTHONPATH=. python3 process_replay.py
+        cp test/external/process_replay/process_replay.py ./process_replay.py && git fetch origin master && git -c advice.detachedHead=false checkout origin/master && CHECK_OOB=0 PYTHONPATH=. python3 process_replay.py
        git checkout $CURRENT_HEAD  # restore to branch
@@ -56,7 +56,15 @@ runs:

    # **** Caching packages ****

+    - name: Cache Python packages (PR)
+      if: github.event_name == 'pull_request'
+      id: restore-venv-pr
+      uses: actions/cache/restore@v4
+      with:
+        path: ${{ github.workspace }}/.venv
+        key: venv-${{ runner.os }}-python-${{ steps.setup-python.outputs.python-version }}-${{ inputs.deps }}-${{ inputs.pydeps }}-${{ env.CACHE_VERSION }}
    - name: Cache Python packages
+      if: github.event_name != 'pull_request'
      id: restore-venv
      uses: actions/cache@v4
      with:
@@ -65,23 +73,23 @@ runs:

    # **** Caching downloads ****

-    - name: Cache downloads (Linux)
-      if: inputs.key != '' && runner.os == 'Linux'
-      uses: actions/cache@v4
+    - name: Cache downloads (PR)
+      if: inputs.key != '' && github.event_name == 'pull_request'
+      uses: actions/cache/restore@v4
      with:
-        path: ~/.cache/tinygrad/downloads/
+        path: ${{ runner.os == 'Linux' && '~/.cache/tinygrad/downloads/' || '~/Library/Caches/tinygrad/downloads/' }}
        key: downloads-${{ github.job }}-${{ inputs.key }}-${{ env.CACHE_VERSION }}
-    - name: Cache downloads (macOS)
-      if: inputs.key != '' && runner.os == 'macOS'
+    - name: Cache downloads
+      if: inputs.key != '' && github.event_name != 'pull_request'
      uses: actions/cache@v4
      with:
-        path: ~/Library/Caches/tinygrad/downloads/
+        path: ${{ runner.os == 'Linux' && '~/.cache/tinygrad/downloads/' || '~/Library/Caches/tinygrad/downloads/' }}
        key: downloads-${{ github.job }}-${{ inputs.key }}-${{ env.CACHE_VERSION }}

    # **** Python deps ****

    - name: Install dependencies in venv (with extra)
-      if: inputs.deps != '' && steps.restore-venv.outputs.cache-hit != 'true'
+      if: inputs.deps != '' && steps.restore-venv-pr.outputs.cache-hit != 'true' && steps.restore-venv.outputs.cache-hit != 'true'
      shell: bash
      run: |
        python -m venv .venv
@@ -92,7 +100,7 @@ runs:
        fi
        python -m pip install -e ".[${{ inputs.deps }}]" ${{ inputs.pydeps }} --extra-index-url https://download.pytorch.org/whl/cpu --extra-index-url https://aiinfra.pkgs.visualstudio.com/PublicPackages/_packaging/Triton-Nightly/pypi/simple/
    - name: Install dependencies in venv (without extra)
-      if: inputs.deps == '' && steps.restore-venv.outputs.cache-hit != 'true'
+      if: inputs.deps == '' && steps.restore-venv-pr.outputs.cache-hit != 'true' && steps.restore-venv.outputs.cache-hit != 'true'
      shell: bash
      run: |
        python -m venv .venv
@@ -182,8 +190,14 @@ runs:
        echo "pkgs=$pkgs" >> "$GITHUB_OUTPUT"
        echo "hash=$(echo -n "$pkgs" | sha256sum | cut -d' ' -f1)" >> "$GITHUB_OUTPUT"

+    - name: Cache apt (PR)
+      if: runner.os == 'Linux' && (inputs.opencl == 'true' || inputs.amd == 'true' || inputs.cuda == 'true' || inputs.webgpu == 'true' || inputs.llvm == 'true') && github.event_name == 'pull_request'
+      uses: actions/cache/restore@v4
+      with:
+        path: /var/cache/apt/archives/
+        key: ${{ runner.os }}-apt-${{ steps.apt-pkgs.outputs.hash }}-${{ env.CACHE_VERSION }}
    - name: Cache apt
-      if: runner.os == 'Linux' && (inputs.opencl == 'true' || inputs.amd == 'true' || inputs.cuda == 'true' || inputs.webgpu == 'true' || inputs.llvm == 'true')
+      if: runner.os == 'Linux' && (inputs.opencl == 'true' || inputs.amd == 'true' || inputs.cuda == 'true' || inputs.webgpu == 'true' || inputs.llvm == 'true') && github.event_name != 'pull_request'
      uses: actions/cache@v4
      with:
        path: /var/cache/apt/archives/
@@ -239,8 +253,17 @@ runs:
        ln -s /opt/homebrew/opt/[email protected] /opt/homebrew/opt/boost || true
        ln -s /opt/homebrew/opt/boost/lib/libboost_atomic-mt.dylib /opt/homebrew/opt/boost/lib/libboost_atomic.dylib || true
        ln -s /opt/homebrew/opt/boost/lib/libboost_thread-mt.dylib /opt/homebrew/opt/boost/lib/libboost_thread.dylib || true
+    - name: Cache gpuocelot (PR)
+      if: inputs.ocelot == 'true' && github.event_name == 'pull_request'
+      id: cache-build-pr
+      uses: actions/cache/restore@v4
+      env:
+        cache-name: cache-gpuocelot-build-1
+      with:
+        path: ${{ github.workspace }}/gpuocelot/ocelot
+        key: ${{ runner.os }}-gpuocelot-b16039dc940dc6bc4ea0a98380495769ff35ed99-rebuild-${{ env.CACHE_VERSION }}
    - name: Cache gpuocelot
-      if: inputs.ocelot == 'true'
+      if: inputs.ocelot == 'true' && github.event_name != 'pull_request'
      id: cache-build
      uses: actions/cache@v4
      env:
@@ -249,7 +272,7 @@ runs:
        path: ${{ github.workspace }}/gpuocelot/ocelot
        key: ${{ runner.os }}-gpuocelot-b16039dc940dc6bc4ea0a98380495769ff35ed99-rebuild-${{ env.CACHE_VERSION }}
    - name: Clone/compile gpuocelot
-      if: inputs.ocelot == 'true' && steps.cache-build.outputs.cache-hit != 'true'
+      if: inputs.ocelot == 'true' && steps.cache-build-pr.outputs.cache-hit != 'true' && steps.cache-build.outputs.cache-hit != 'true'
      shell: bash
      run: |
        git clone --recurse-submodules https://github.com/gpuocelot/gpuocelot.git ${{ github.workspace }}/gpuocelot
@@ -40,30 +40,20 @@ jobs:
        mesa: 'true'
        pydeps: 'pyyaml mako'
    - name: Install autogen support packages
-      run: sudo apt-get install -y --no-install-recommends libclang-20-dev llvm-20-dev hip-dev libusb-1.0-0-dev
+      run: sudo apt-get install -y --no-install-recommends libclang-20-dev llvm-20-dev hip-dev libusb-1.0-0-dev libdrm-dev
    - name: Regenerate autogen files
      run: |
-        rm tinygrad/runtime/autogen/opencl.py
+        find tinygrad/runtime/autogen -type f -name "*.py" -not -name "__init__.py" -not -name "comgr_3.py" -not -name "metal.py" -not -name "iokit.py" -not -name "corefoundation.py" -not -name "libclang.py" -delete
        python3 -c "from tinygrad.runtime.autogen import opencl"
-        rm tinygrad/runtime/autogen/{cuda,nvrtc,nvjitlink,nv_570,nv}.py
-        python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv"
-        rm tinygrad/runtime/autogen/{comgr,hsa,hip,amd_gpu,sqtt,rocprof}.py
-        python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof"
-        rm tinygrad/runtime/autogen/am/{am,pm4_soc15,pm4_nv,sdma_4_0_0,sdma_5_0_0,sdma_6_0_0,smu_v13_0_0,smu_v14_0_2}.py
-        python3 -c "from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v14_0_2"
-        rm tinygrad/runtime/autogen/{libc,kfd,io_uring,ib,pci,vfio}.py
+        python3 -c "from tinygrad.runtime.autogen import cuda, nvrtc, nvjitlink, nv_570, nv_580, nv"
+        python3 -c "from tinygrad.runtime.autogen import comgr, hsa, hip, amd_gpu, sqtt, rocprof, amdgpu_kd, amdgpu_drm"
+        python3 -c "from tinygrad.runtime.autogen.am import am, pm4_soc15, pm4_nv, sdma_4_0_0, sdma_5_0_0, sdma_6_0_0, smu_v13_0_0, smu_v13_0_6, smu_v14_0_2"
        python3 -c "from tinygrad.runtime.autogen import libc, kfd, io_uring, ib, pci, vfio"
-        rm tinygrad/runtime/autogen/llvm.py
        python3 -c "from tinygrad.runtime.autogen import llvm"
-        rm tinygrad/runtime/autogen/webgpu.py
        python3 -c "from tinygrad.runtime.autogen import webgpu"
-        rm tinygrad/runtime/autogen/{kgsl,qcom_dsp}.py
        python3 -c "from tinygrad.runtime.autogen import kgsl, qcom_dsp"
-        rm tinygrad/runtime/autogen/libusb.py
        python3 -c "from tinygrad.runtime.autogen import libusb"
-        rm tinygrad/runtime/autogen/mesa.py
        python3 -c "from tinygrad.runtime.autogen import mesa"
-        rm tinygrad/runtime/autogen/avcodec.py
        python3 -c "from tinygrad.runtime.autogen import avcodec"
        REGEN=1 python3 -c "from tinygrad.runtime.autogen import libclang"
    - name: Check for differences
@@ -93,8 +83,8 @@ jobs:
        llvm: 'true'
    - name: Regenerate autogen files
      run: |
-        rm tinygrad/runtime/autogen/metal.py
-        LIBCLANG_PATH=/opt/homebrew/opt/llvm@20/lib/libclang.dylib python3 -c "from tinygrad.runtime.autogen import metal"
+        rm tinygrad/runtime/autogen/metal.py tinygrad/runtime/autogen/iokit.py tinygrad/runtime/autogen/corefoundation.py
+        python3 -c "from tinygrad.runtime.autogen import metal, iokit, corefoundation"
    - name: Check for differences
      run: |
        if ! git diff --quiet; then
@@ -16,6 +16,48 @@ on:
  workflow_dispatch:

 jobs:
+  # the goal of this test is to replicate a normal person on a laptop running the test
+  # no process replay, no benchmarks, no CI, just a normal laptop person
+  # the 3 minute timeout should not be raised
+  testmacpytest:
+    name: Mac pytest
+    runs-on: [self-hosted, macOS]
+    timeout-minutes: 3
+    defaults:
+      run:
+        shell: bash -e -o pipefail {0}
+    if: github.repository_owner == 'tinygrad'
+    steps:
+    - name: Checkout Code
+      uses: actions/checkout@v4
+    # brew install uv
+    - name: setup python environment
+      run: |
+        rm -rf /tmp/tinygrad_pytest_ci
+        uv venv /tmp/tinygrad_pytest_ci
+        source /tmp/tinygrad_pytest_ci/bin/activate
+        uv pip install .[testing]
+    - name: setup staging db
+      run: |
+        echo "CACHEDB=/tmp/pytest-db-ci.db" >> $GITHUB_ENV
+        rm -f /tmp/pytest-db-ci*
+    # TODO: remove this step once all old caches are migrated
+    - name: Migrate old huggingface cache (symlinks break onnxruntime 1.24+)
+      run: |
+        cd ~/Library/Caches/tinygrad/downloads/models 2>/dev/null || exit 0
+        for old_dir in models--*; do
+          [ -d "$old_dir" ] || continue
+          repo_id=$(echo "$old_dir" | sed 's/models--//; s/--/\//g')
+          snapshot=$(ls -1 "$old_dir/snapshots" 2>/dev/null | head -1)
+          [ -n "$snapshot" ] || continue
+          mkdir -p "$repo_id"
+          cp -RLn "$old_dir/snapshots/$snapshot/"* "$repo_id/" 2>/dev/null || true
+        done
+    - name: Run pytest -nauto
+      run: |
+        source /tmp/tinygrad_pytest_ci/bin/activate
+        pytest -nauto --durations=20
+
  testmacbenchmark:
    name: Mac Benchmark
    env:
@@ -145,6 +187,10 @@ jobs:
      run: |
        echo "CACHEDB=/tmp/staging.db" >> $GITHUB_ENV
        rm -f /tmp/staging.db /tmp/staging.db-shm /tmp/staging.db-wal
+    - name: Kill stale pids
+      run: |
+        PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
+        PYTHONPATH=. ./extra/hcq/hcq_smi.py nv kill_pids
    - name: UsbGPU boot time
      run: sudo -E PYTHONPATH=. DEBUG=2 AM_RESET=1 AMD=1 AMD_IFACE=USB time python3.11 test/test_tiny.py TestTiny.test_plus
    - name: UsbGPU tiny tests
@@ -329,10 +375,12 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Remove amdgpu
-      run: sudo rmmod amdgpu || true
-    - name: Cleanup running AM processes
-      run: python extra/amdpci/am_smi.py --pids --kill
+    - name: Setcap to python
+      run: ./extra/amdpci/setup_python_cap.sh
+    - name: Remove amd modules
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
+    - name: Kill stale pids
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
    #- name: Insert amdgpu
    #  run: sudo modprobe amdgpu
    - name: Symlink models and datasets
@@ -439,10 +487,12 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Remove amdgpu
-      run: sudo rmmod amdgpu || true
-    - name: Cleanup running AM processes
-      run: python extra/amdpci/am_smi.py --pids --kill
+    - name: Setcap to python
+      run: ./extra/amdpci/setup_python_cap.sh
+    - name: Remove amd modules
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
+    - name: Kill stale pids
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -489,10 +539,12 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
-    - name: Remove amdgpu
-      run: sudo rmmod amdgpu || true
-    - name: Cleanup running AM processes
-      run: python extra/amdpci/am_smi.py --pids --kill
+    - name: Setcap to python
+      run: ./extra/amdpci/setup_python_cap.sh
+    - name: Remove amd modules
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
+    - name: Kill stale pids
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -541,7 +593,7 @@ jobs:
    - name: reset process replay
      run: test/external/process_replay/reset.py
    - name: openpilot compile3 0.10.0 driving_policy
-      run: BENCHMARK_LOG=openpilot_0_10_0_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=4 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.10.0/selfdrive/modeld/models/driving_policy.onnx
+      run: BENCHMARK_LOG=openpilot_0_10_0_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=3 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.10.0/selfdrive/modeld/models/driving_policy.onnx
    - name: openpilot compile3 0.10.0 dmonitoring
      run: BENCHMARK_LOG=openpilot_0_10_0_dmonitoring PYTHONPATH="." ASSERT_MIN_STEP_TIME=11 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.10.0/selfdrive/modeld/models/dmonitoring_model.onnx
    - name: DEBUG=2 openpilot compile3 0.10.1 driving_vision
@@ -553,9 +605,9 @@ jobs:
    - name: openpilot compile3 0.10.1 driving_vision
      run: BENCHMARK_LOG=openpilot_0_10_1_vision PYTHONPATH="." ASSERT_MIN_STEP_TIME=17 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_vision.onnx
    - name: openpilot compile3 0.10.1 driving_policy
-      run: BENCHMARK_LOG=openpilot_0_10_1_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=4 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_policy.onnx
+      run: BENCHMARK_LOG=openpilot_0_10_1_policy PYTHONPATH="." ASSERT_MIN_STEP_TIME=3 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/driving_policy.onnx
    - name: openpilot compile3 0.10.1 dmonitoring
-      run: BENCHMARK_LOG=openpilot_0_10_1_dmonitoring PYTHONPATH="." ASSERT_MIN_STEP_TIME=10 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/dmonitoring_model.onnx
+      run: BENCHMARK_LOG=openpilot_0_10_1_dmonitoring PYTHONPATH="." ASSERT_MIN_STEP_TIME=11 DEV=QCOM FLOAT16=1 IMAGE=2 NOLOCALS=1 taskset -c 4-7 python3 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/720392c9a5b986981fdbed1bb8c47a6c5573a50e/selfdrive/modeld/models/dmonitoring_model.onnx
    - name: benchmark MobileNetV2 on DSP
      run: |
        # generate quantized weights
@@ -578,10 +630,12 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
+    - name: Setcap to python
+      run: ./extra/amdpci/setup_python_cap.sh
    - name: Remove amd modules
-      run: ./extra/hcq/hcq_smi.py amd rmmod
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd rmmod
    - name: Kill stale pids
-      run: ./extra/hcq/hcq_smi.py amd kill_pids
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py amd kill_pids
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -640,10 +694,12 @@ jobs:
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
+    - name: Setcap to python
+      run: ./extra/amdpci/setup_python_cap.sh
    - name: Remove nv modules
-      run: ./extra/hcq/hcq_smi.py nv rmmod
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py nv rmmod
    - name: Kill stale pids
-      run: ./extra/hcq/hcq_smi.py nv kill_pids
+      run: PYTHONPATH=. ./extra/hcq/hcq_smi.py nv kill_pids
    - name: Symlink models and datasets
      run: |
        mkdir -p weights
@@ -5,7 +5,7 @@ env:
  CAPTURE_PROCESS_REPLAY: 1
  GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}
  PYTHONPATH: ${{ github.workspace }}
-  IGNORE_OOB: 0
+  CHECK_OOB: 1

 on:
  push:
@@ -26,19 +26,19 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: llvm-speed
-        deps: testing_minimal
+        deps: testing_unit
        llvm: 'true'
    - name: Speed Test
-      run: CPU=1 CPU_LLVM=1 python3 test/speed/external_test_speed_v_torch.py
+      run: CPU=1 CPU_LLVM=1 THREADS=0 python3 test/speed/external_test_speed_v_torch.py
    - name: Speed Test (BEAM=2)
-      run: BEAM=2 CPU=1 CPU_LLVM=1 python3 test/speed/external_test_speed_v_torch.py
+      run: BEAM=2 CPU=1 CPU_LLVM=1 THREADS=0 python3 test/speed/external_test_speed_v_torch.py

  docs:
    name: Docs
    runs-on: ubuntu-22.04
    timeout-minutes: 10
    env:
-      IGNORE_OOB: 1
+      CHECK_OOB: 0
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -98,7 +98,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: torch-backend-pillow-torchvision-et-pt
-        deps: testing_minimal
+        deps: testing_unit
        pydeps: "pillow torchvision expecttest"
        llvm: 'true'
    - name: Install ninja
@@ -110,7 +110,7 @@ jobs:
    - name: Test ResNet-18
      run: DEBUG=2 python3 extra/torch_backend/example.py
    - name: custom tests
-      run: python3 extra/torch_backend/test.py
+      run: python3 -m pytest -n auto extra/torch_backend/test.py --durations=20
    - name: Test one op in torch tests
      run: DEBUG=2 python3 extra/torch_backend/torch_tests.py TestTinyBackendPRIVATEUSE1.test_unary_log_tiny_float32
    - name: Test Ops with TINY_BACKEND
@@ -134,7 +134,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: torch-backend-pillow-torchvision-et-pt
-        deps: testing_minimal
+        deps: testing_unit
        llvm: 'true'
    - name: Install ninja
      run: |
@@ -156,7 +156,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: be-minimal
-        deps: testing_minimal
+        deps: testing_unit
    - name: Test dtype with Python emulator
      run: DEBUG=1 PYTHON=1 python3 -m pytest -n=auto test/test_dtype.py test/test_dtype_alu.py
    - name: Test ops with Python emulator
@@ -207,11 +207,11 @@ jobs:
      run: DEBUG=2 AMX=1 EMULATE=AMX FORWARD_ONLY=1 PYTHON=1 python3 test/opt/test_tensor_cores.py
    - name: Test device flop counts
      run: |
-        DEBUG=2 EMULATE=METAL PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf
-        DEBUG=2 EMULATE=AMD PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf
-        DEBUG=2 EMULATE=CUDA PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf
-        DEBUG=2 EMULATE=INTEL PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf
-        DEBUG=2 AMX=1 EMULATE=AMX PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStats.test_simple_matmul
+        DEBUG=2 EMULATE=METAL PYTHON=1 python3 ./test/null/test_uops_stats.py TestUOpsStatsMatmulHalf
+        DEBUG=2 EMULATE=AMD PYTHON=1 python3 ./test/null/test_uops_stats.py TestUOpsStatsMatmulHalf
+        DEBUG=2 EMULATE=CUDA PYTHON=1 python3 ./test/null/test_uops_stats.py TestUOpsStatsMatmulHalf
+        DEBUG=2 EMULATE=INTEL PYTHON=1 python3 ./test/null/test_uops_stats.py TestUOpsStatsMatmulHalf
+        DEBUG=2 AMX=1 EMULATE=AMX PYTHON=1 python3 ./test/null/test_uops_stats.py TestUOpsStats.test_simple_matmul

  linter:
    name: Linters
@@ -229,19 +229,20 @@ jobs:
        deps: linting
    - name: Lint bad-indentation and trailing-whitespace with pylint
      run: python -m pylint --disable=all -e W0311 -e C0303 --jobs=0 --indent-string='  ' --recursive=y .
-    - name: Lint with ruff
+    - name: Run pre-commit linting hooks
+      run: SKIP=tiny,tests,example pre-commit run --all-files
+    - name: Lint additional files with ruff
      run: |
-        pip3 install --upgrade --force-reinstall ruff==0.14.10
-        pre-commit run ruff --all-files
        python3 -m ruff check examples/mlperf/ --ignore E501
        python3 -m ruff check extra/thunder/tiny/ --ignore E501 --ignore F841 --ignore E722
        python3 -m ruff check extra/torch_backend/backend.py
-    - name: Run mypy
+    - name: Run mypy with lineprecision report
      run: |
        python -m mypy --lineprecision-report .
+        grep -v autogen lineprecision.txt | awk 'NR>2 {lines+=$2; precise+=$3; imprecise+=$4; any+=$5; empty+=$6} END {t=lines-empty; printf "TOTAL: %d lines, %d precise (%.1f%%), %d imprecise (%.1f%%), %d any (%.1f%%)\n", t, precise, 100*precise/t, imprecise, 100*imprecise/t, any, 100*any/t}'
        cat lineprecision.txt
    - name: Run TYPED=1
-      run: TYPED=1 python -c "import tinygrad"
+      run: CHECK_OOB=0 DEV=CPU TYPED=1 python test/test_tiny.py

  unittest:
    name: Unit Tests
@@ -254,25 +255,30 @@ jobs:
    - name: Setup Environment
      uses: ./.github/actions/setup-tinygrad
      with:
-        key: unittest-12
-        pydeps: "pillow numpy ftfy regex"
+        key: unittest-13
+        pydeps: "pillow ftfy regex pre-commit"
        deps: testing_unit
        llvm: 'true'
+        amd: 'true'
+    - name: Run pre-commit test hooks
+      run: SKIP=ruff,mypy pre-commit run --all-files
    - name: Check Device.DEFAULT
      run: python -c "from tinygrad import Device; assert Device.DEFAULT == 'CPU', Device.DEFAULT"
    - name: Run unit tests
      run: |
-        CPU=1 python test/unit/test_device.py TestRunAsModule.test_module_runs
-        CPU=1 python -m pytest -n=auto test/unit/ --durations=20 --deselect=test/unit/test_device.py::TestRunAsModule::test_module_runs
+        CPU=1 python test/null/test_device.py TestRunAsModule.test_module_runs
+        CPU=1 python -m pytest -n=auto test/unit/ --durations=20
+    - name: Run NULL backend tests
+      run: NULL=1 python -m pytest -n=auto test/null/ --durations=20
    - name: Run targetted tests on NULL backend
-      run: NULL=1 python3 -m unittest test.test_multitensor.TestMultiTensor.test_data_parallel_resnet_train_step test/device/test_null.py
+      run: NULL=1 python3 -m unittest test.test_multitensor.TestMultiTensor.test_data_parallel_resnet_train_step
    # TODO: too slow
    # - name: Run SDXL on NULL backend
    #   run: NULL=1 DEBUG=1 python3 examples/sdxl.py --seed 0 --noshow --timing --fakeweights
    - name: Run Clip tests for SD MLPerf on NULL backend
      run: NULL=1 python -m pytest -n=auto test/external/mlperf_stable_diffusion/external_test_models.py::TestOpenClip --durations=20
    - name: Run AMD emulated BERT training on NULL backend
-      run: EMULATE=AMD_RDNA4 NULL=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+      run: EMULATE=AMD_RDNA4 NULL=1 NULL_ALLOW_COPYOUT=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=1 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
    # TODO: support fake weights
    #- name: Run LLaMA 7B on 4 fake devices
    #  run: NULL=1 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 3 --temperature 0 --timing
@@ -310,7 +316,7 @@ jobs:
        deps: testing_unit
        python-version: '3.14'
    - name: Test SPEC=2
-      run: SPEC=2 pytest --maxfail=10 -n auto --durations=30 --ignore=test/models --ignore test/test_custom_kernel.py --ignore test/unit/test_hashing.py --ignore test/unit/test_autogen.py --timeout 60 -k "not test_setitem_big" --splits 2 --group ${{ matrix.group }}
+      run: SPEC=2 pytest --maxfail=10 -n auto --durations=30 --ignore=test/models --ignore=test/null --ignore test/test_custom_kernel.py --ignore test/unit/test_hashing.py --timeout 60 -k "not test_setitem_big" --splits 2 --group ${{ matrix.group }}

  fuzzing:
    name: Fuzzing
@@ -344,7 +350,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: gpu-image
-          deps: testing_minimal
+          deps: testing_unit
          opencl: 'true'
      - name: Test CL IMAGE=2 ops
        run: |
@@ -365,7 +371,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: gen-dataset
-          deps: testing_minimal
+          deps: testing
          opencl: 'true'
      - name: Generate Dataset
        run: CL=1 extra/optimization/generate_dataset.sh
@@ -420,7 +426,7 @@ jobs:
        with:
          key: onnxoptc
          deps: testing
-          python-version: '3.11'
+          python-version: '3.12'
          llvm: 'true'
      - name: Test ONNX (CPU)
        run: CPU=1 CPU_LLVM=0 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
@@ -448,7 +454,7 @@ jobs:
          key: onnxoptl
          deps: testing
          pydeps: "tensorflow==2.19"
-          python-version: '3.11'
+          python-version: '3.12'
          opencl: 'true'
      - name: Test ONNX (CL)
        run: CL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
@@ -461,11 +467,11 @@ jobs:
      - name: Test MLPerf stuff
        run: CL=1 python -m pytest -n=auto test/external/external_test_optim.py test/external/external_test_losses.py test/external/external_test_metrics.py test/external/external_test_datasets.py --durations=20
      - name: NULL=1 beautiful_mnist_multigpu
-        run: NULL=1 python examples/beautiful_mnist_multigpu.py
+        run: NULL=1 NULL_ALLOW_COPYOUT=1 python examples/beautiful_mnist_multigpu.py
      - name: Test Bert training
-        run: NULL=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=24 GPUS=4 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
+        run: NULL=1 NULL_ALLOW_COPYOUT=1 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=24 GPUS=4 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py
      - name: Test llama 3 training
-        run: NULL=1 SAMPLES=300 BS=8 SEQLEN=512 GRADIENT_ACC_STEPS=1 FAKEDATA=1 DEFAULT_FLOAT=bfloat16 OPTIM_DTYPE=bfloat16 LLAMA3_SIZE=1B MODEL=llama3 python3 examples/mlperf/model_train.py
+        run: NULL=1 NULL_ALLOW_COPYOUT=1 SAMPLES=300 BS=8 SEQLEN=512 GRADIENT_ACC_STEPS=1 FAKEDATA=1 DEFAULT_FLOAT=bfloat16 OPTIM_DTYPE=bfloat16 LLAMA3_SIZE=1B MODEL=llama3 python3 examples/mlperf/model_train.py
      - name: Run process replay tests
        uses: ./.github/actions/process-replay

@@ -474,7 +480,7 @@ jobs:
    runs-on: ubuntu-24.04
    timeout-minutes: 15
    env:
-      IGNORE_OOB: 1
+      CHECK_OOB: 0
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -522,7 +528,7 @@ jobs:
      with:
        key: metal
        deps: testing
-        python-version: '3.11'
+        python-version: '3.12'
    - name: Test models (Metal)
      run: METAL=1 python -m pytest -n=auto test/models --durations=20
    - name: Test LLaMA compile speed
@@ -541,7 +547,7 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: devectorize-minimal
-        deps: testing_minimal
+        deps: testing_unit
        pydeps: "pillow"
        llvm: "true"
    - name: Test LLVM=1 DEVECTORIZE=0
@@ -562,8 +568,8 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: dsp-minimal
-        deps: testing_minimal
-        pydeps: "onnx==1.18.0 onnxruntime pillow"
+        deps: testing_unit
+        pydeps: "onnx==1.18.0 onnxruntime ml_dtypes"
        llvm: "true"
    - name: Set up Docker Buildx
      uses: docker/setup-buildx-action@v3
@@ -596,8 +602,8 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: webgpu-minimal
-        deps: testing_minimal
-        python-version: '3.11'
+        deps: testing_unit
+        python-version: '3.12'
        webgpu: 'true'
    - name: Check Device.DEFAULT (WEBGPU) and print some source
      run: |
@@ -605,7 +611,7 @@ jobs:
        WEBGPU=1 DEBUG=4 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
    - name: Run selected webgpu tests
      run: |
-          WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
+          WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Vulkan" python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore=test/null --durations=20
    - name: Run process replay tests
      uses: ./.github/actions/process-replay

@@ -630,7 +636,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_minimal
+          deps: testing_unit
          amd: 'true'
          llvm: ${{ matrix.backend == 'amdllvm' && 'true' }}
      - name: Check Device.DEFAULT and print some source
@@ -648,16 +654,23 @@ jobs:
        run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20
      - name: Run TestOps.test_add with SQTT
        run: |
-          VIZ=1 PMC=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add
-          VIZ=1 SQTT=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add
+          VIZ=-2 DEBUG=5 python3 test/test_ops.py TestOps.test_add
          extra/sqtt/rgptool.py create "/tmp/profile.pkl.$USER" -o /tmp/gpu0.rgp
+      - name: Run AMD emulated mmapeak on NULL backend
+        env:
+          AMD: 0
+        run: PYTHONPATH=. NULL=1 EMULATE=AMD python extra/mmapeak/mmapeak.py
      - name: Run process replay tests
        uses: ./.github/actions/process-replay

  testamdasm:
    name: AMD ASM IDE
    runs-on: ubuntu-24.04
-    timeout-minutes: 10
+    timeout-minutes: 20
+    env:
+      AMD: 1
+      PYTHON_REMU: 1
+      MOCKGPU: 1
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -665,12 +678,12 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: rdna3-emu
-          deps: testing_minimal
+          deps: testing_unit
          amd: 'true'
-          python-version: '3.13'
+          python-version: '3.14'
      - name: Verify AMD autogen is up to date
        run: |
-          python -m extra.assembly.amd.pdf
+          python -m extra.assembly.amd.generate
          git diff --exit-code extra/assembly/amd/autogen/
      - name: Install LLVM 21
        run: |
@@ -683,16 +696,18 @@ jobs:
      - name: Install rocprof-trace-decoder
        run: sudo PYTHONPATH="." ./extra/sqtt/install_sqtt_decoder.py
      - name: Run RDNA3 emulator tests
-        run: python -m pytest -n=auto extra/assembly/amd/ --durations 20
+        run: AMD_LLVM=0 python -m pytest -n=auto extra/assembly/amd/ --durations 20
      - name: Run RDNA3 emulator tests (AMD_LLVM=1)
        run: AMD_LLVM=1 python -m pytest -n=auto extra/assembly/amd/ --durations 20
      - name: Run RDNA3 dtype tests
-        run: AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py
+        run: AMD_LLVM=0 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py --durations 20
      - name: Run RDNA3 dtype tests (AMD_LLVM=1)
-        run: AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=1 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py
+        run: AMD_LLVM=1 pytest -n=auto test/test_dtype_alu.py test/test_dtype.py --durations 20
      # TODO: run all once emulator is faster
      - name: Run RDNA3 ops tests
-        run: SKIP_SLOW_TEST=1 AMD=1 PYTHON_REMU=1 MOCKGPU=1 AMD_LLVM=0 pytest -n=auto test/test_ops.py -k "test_sparse_categorical_crossentropy or test_tril"
+        run: SKIP_SLOW_TEST=1 AMD_LLVM=0 pytest -n=auto test/test_ops.py -k "test_sparse_categorical_crossentropy or test_tril or test_nonzero or test_softmax_argmax" --durations 20
+      - name: Run RDNA4 emulator tests
+        run: MOCKGPU_ARCH=rdna4 python -m pytest test/test_tiny.py -v --durations 20

  testnvidia:
    strategy:
@@ -713,7 +728,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_minimal
+          deps: testing_unit
          cuda: 'true'
          ocelot: 'true'
      - name: Set env
@@ -724,7 +739,9 @@ jobs:
          DEBUG=5 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
      - name: Run pytest (cuda)
        # skip multitensor because it's slow
-        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore test/test_gc.py --ignore test/test_multitensor.py --durations=20
+        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore=test/null --ignore test/test_gc.py --ignore test/test_multitensor.py --durations=20
+      - name: Run TestOps.test_add with PMA
+        run: VIZ=-1 PMA=1 DEBUG=5 python3 test/test_ops.py TestOps.test_add
      - name: Run process replay tests
        uses: ./.github/actions/process-replay

@@ -744,7 +761,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_minimal
+          deps: testing_unit
          opencl: ${{ matrix.backend == 'opencl' && 'true' }}
          llvm: ${{ matrix.backend == 'llvm' || matrix.backend == 'lvp' }}
          mesa: ${{ matrix.backend == 'lvp' && 'true' }}
@@ -755,7 +772,7 @@ jobs:
          python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['CPU','CL'], Device.DEFAULT"
          DEBUG=5 FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
      - name: Run pytest (${{ matrix.backend }})
-        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
+        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore=test/null --durations=20
      - name: Run TRANSCENDENTAL math
        run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20
      - name: Run process replay tests
@@ -775,15 +792,15 @@ jobs:
      with:
        key: metal
        deps: testing
-        python-version: '3.11'
+        python-version: '3.12'
        amd: 'true'
        cuda: 'true'
        ocelot: 'true'
        llvm: 'true'
    - name: Run unit tests
-      env:
-        LIBCLANG_PATH: '/opt/homebrew/opt/llvm@20/lib/libclang.dylib'
      run: METAL=1 python -m pytest -n=auto test/unit/ --durations=20
+    - name: Run NULL backend tests
+      run: NULL=1 python -m pytest -n=auto test/null/ --durations=20
    - name: Run ONNX
      run: METAL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
    - name: Test tensor core ops (fake)
@@ -875,8 +892,7 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: macos-${{ matrix.backend }}-minimal
-          deps: testing_minimal
-          pydeps: "capstone"
+          deps: testing_unit
          llvm: ${{ matrix.backend == 'llvm' || matrix.backend == 'lvp' }}
          mesa: ${{ matrix.backend == 'lvp' && 'true' }}
      - name: Set env
@@ -886,7 +902,7 @@ jobs:
          python -c "from tinygrad import Device; assert Device.DEFAULT == {'LLVM':'CPU','LVP':'CPU'}.get(x:='${{ matrix.backend }}'.upper(), x), Device.DEFAULT"
          DEBUG=4 python3 test/test_tiny.py TestTiny.test_plus
      - name: Run pytest (${{ matrix.backend }})
-        run: python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
+        run: python3 -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore=test/null --durations=20
      - name: Run process replay tests
        uses: ./.github/actions/process-replay
      - name: Run macOS-specific unit test
@@ -919,7 +935,11 @@ jobs:
      - name: Run unit tests
        if: matrix.backend=='llvm'
        # test_newton_schulz hits RecursionError
-        run: python -m pytest -n=auto test/unit/ --ignore=test/unit/test_disk_tensor.py --ignore=test/unit/test_elf.py --ignore=test/unit/test_tar.py --ignore=test/unit/test_linalg.py --durations=20
+        run: python -m pytest -n=auto test/unit/ --ignore=test/unit/test_disk_tensor.py --ignore=test/unit/test_tar.py --ignore=test/unit/test_linalg.py --durations=20
+      - name: Run NULL backend tests
+        if: matrix.backend=='llvm'
+        shell: bash
+        run: CPU=0 CPU_LLVM=0 NULL=1 python -m pytest -n=auto test/null/ --ignore=test/null/test_elf.py --durations=20
      - name: Run pytest (${{ matrix.backend }})
        shell: bash
        run: |
@@ -943,12 +963,12 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: compile-${{ matrix.backend }}
-          deps: testing_minimal
+          deps: testing_unit
          mesa: ${{ (matrix.backend == 'ir3' || matrix.backend == 'nak') && 'true' }}
-          python-version: '3.14'
+          python-version: '3.12'
      - name: Set env
        shell: bash
-        run: printf "NULL=1\n${{ matrix.backend == 'ir3' && 'NULL_IR3=1' || matrix.backend == 'nak' && 'NULL_NAK=1' }}" >> $GITHUB_ENV
+        run: printf "NULL=1\nNULL_ALLOW_COPYOUT=1\n${{ matrix.backend == 'ir3' && 'NULL_IR3=1' || matrix.backend == 'nak' && 'NULL_NAK=1' }}" >> $GITHUB_ENV
      - name: Run test_ops
        shell: bash
        run: |
@@ -58,10 +58,11 @@ weights
 *.lprof
 comgr_*
 *.pkl
+!extra/sqtt/examples/**/*.pkl
 site/
 profile_stats
 *.log
 target
 .mypy_cache
 mutants
-.mutmut-cache
+.mutmut-cache
@@ -28,7 +28,7 @@ repos:
        pass_filenames: false
      - id: tests
        name: comprehensive test suite
-        entry: env OMP_NUM_THREADS=1 SKIP_SLOW_TEST=1 PYTHONPATH="." python3 -m pytest -n=6 test/test_ops.py test/test_schedule.py test/test_assign.py test/test_tensor.py test/test_jit.py test/unit/test_schedule_cache.py test/unit/test_pattern_matcher.py test/unit/test_uop_symbolic.py test/unit/test_helpers.py
+        entry: env OMP_NUM_THREADS=1 SKIP_SLOW_TEST=1 PYTHONPATH="." python3 -m pytest -n=6 test/test_ops.py test/test_schedule.py test/unit/test_assign.py test/test_tensor.py test/test_jit.py test/unit/test_schedule_cache.py test/null/test_pattern_matcher.py test/null/test_uop_symbolic.py test/unit/test_helpers.py
        language: system
        always_run: true
        pass_filenames: false
@@ -6,6 +6,7 @@ Elementwise ops operate on a per element basis. They don't change the shape of t
 ::: tinygrad.Tensor.neg
 ::: tinygrad.Tensor.log
 ::: tinygrad.Tensor.log2
+::: tinygrad.Tensor.log10
 ::: tinygrad.Tensor.exp
 ::: tinygrad.Tensor.exp2
 ::: tinygrad.Tensor.sqrt
@@ -87,4 +88,8 @@ Elementwise ops operate on a per element basis. They don't change the shape of t
 ::: tinygrad.Tensor.float
 ::: tinygrad.Tensor.half
 ::: tinygrad.Tensor.int
-::: tinygrad.Tensor.bool
+::: tinygrad.Tensor.bool
+::: tinygrad.Tensor.bfloat16
+::: tinygrad.Tensor.double
+::: tinygrad.Tensor.long
+::: tinygrad.Tensor.short
@@ -27,5 +27,6 @@
 ::: tinygrad.Tensor.flatten
 ::: tinygrad.Tensor.unflatten
 ::: tinygrad.Tensor.diag
+::: tinygrad.Tensor.diagonal
 ::: tinygrad.Tensor.roll
 ::: tinygrad.Tensor.rearrange
@@ -7,6 +7,7 @@
 ::: tinygrad.Tensor.any
 ::: tinygrad.Tensor.all
 ::: tinygrad.Tensor.isclose
+::: tinygrad.Tensor.allclose
 ::: tinygrad.Tensor.mean
 ::: tinygrad.Tensor.var
 ::: tinygrad.Tensor.var_mean
@@ -30,7 +31,9 @@
 ::: tinygrad.Tensor.matmul
 ::: tinygrad.Tensor.einsum
 ::: tinygrad.Tensor.cumsum
+::: tinygrad.Tensor.cumprod
 ::: tinygrad.Tensor.cummax
+::: tinygrad.Tensor.cummin
 ::: tinygrad.Tensor.triu
 ::: tinygrad.Tensor.tril
 ::: tinygrad.Tensor.interpolate
@@ -38,7 +41,9 @@
 ::: tinygrad.Tensor.scatter_reduce
 ::: tinygrad.Tensor.masked_select
 ::: tinygrad.Tensor.masked_fill
+::: tinygrad.Tensor.nonzero
 ::: tinygrad.Tensor.sort
+::: tinygrad.Tensor.argsort
 ::: tinygrad.Tensor.topk
 ::: tinygrad.Tensor.multinomial

@@ -56,3 +61,8 @@
 ::: tinygrad.Tensor.sparse_categorical_crossentropy
 ::: tinygrad.Tensor.cross_entropy
 ::: tinygrad.Tensor.nll_loss
+
+## Linear Algebra
+
+::: tinygrad.Tensor.qr
+::: tinygrad.Tensor.svd
@@ -0,0 +1,196 @@
+from tinygrad import Tensor, dtypes, Context, getenv, UOp, fetch
+from tinygrad.uop.ops import Ops, PatternMatcher, UPat
+from tinygrad.uop.symbolic import symbolic
+from tinygrad.codegen import Renderer
+from tinygrad.codegen.opt import Opt, OptOps
+
+# ************************* implementation of the problem ************************
+
+def myhash(a: Tensor) -> Tensor:
+  a = (a + 0x7ED55D16) + (a << 12)
+  a = (a ^ 0xC761C23C) ^ (a >> 19)
+  a = (a + 0x165667B1) + (a << 5)
+  a = (a + 0xD3A2646C) ^ (a << 9)
+  a = (a + 0xFD7046C5) + (a << 3)
+  a = (a ^ 0xB55A4F09) ^ (a >> 16)
+  return a
+
+def select_with_where_tree(values: Tensor, relative_idx: Tensor) -> Tensor:
+  n = values.shape[0]
+  if n == 1: return values[0].expand(relative_idx.shape)
+
+  mid = n // 2
+  left = select_with_where_tree(values[:mid], relative_idx)
+  right = select_with_where_tree(values[mid:], relative_idx - mid)
+
+  go_left = relative_idx < mid
+  return go_left.where(left, right)
+
+def tree_traversal(forest: Tensor, val: Tensor, height: int, rounds: int, where_tree_threshold=3) -> Tensor:
+  # All walkers start at idx=0
+  idx = Tensor.zeros(val.shape, device=val.device, dtype=dtypes.uint32)
+
+  for r in range(rounds):
+    level = r % (height + 1)
+    level_start = (1 << level) - 1
+    level_size = 1 << level
+
+    if level == 0:
+      # At root (level 0), all walkers are at idx=0
+      # No gather needed, just broadcast the root value
+      node_val = forest[0].expand(val.shape)
+      idx = idx * 0  # Reset to 0
+    elif level <= where_tree_threshold:
+      # Small level: use where-tree
+      level_values = forest[level_start : level_start + level_size]
+      relative_idx = (idx - level_start)
+      node_val = select_with_where_tree(level_values, relative_idx)
+    else:
+      # Large level: use gather
+      node_val = forest.gather(0, idx)
+
+    val = myhash(val ^ node_val)
+    idx = (idx << 1) + (1 + (val & 1))
+
+    # No wrap check needed! At round 10 (level becomes 0), we reset idx above.
+
+  return val.contiguous(arg=(Opt(OptOps.UPCAST, 0, 8),))
+
+# ************************* renderer for VLIW machine *************************
+
+def loop_unrolling(sink:UOp):
+  rng = [x for x in sink.toposort() if x.op is Ops.RANGE]
+  if len(rng) == 0: return None
+  print(f"unrolling loop with size {rng[0].vmax+1}")
+  unrolled_sinks = [sink.substitute({rng[0]:rng[0].const_like(i)}).src[0] for i in range(rng[0].vmax+1)]
+  return UOp.sink(*unrolled_sinks, arg=sink.arg)
+
+global_addrs = []
+vliw_prepare = PatternMatcher([
+  # loop unrolling (should be a part of tinygrad)
+  (UPat(Ops.SINK, name="sink"), loop_unrolling),
+  # cast is fake
+  (UPat(Ops.CAST, name="c"), lambda c: c.src[0]),
+  # rewrites to hardcode the addresses in memory
+  (UPat(Ops.PARAM, name="dg"), lambda dg: UOp.const(dtypes.uint, global_addrs[dg.arg])),
+  # INDEX is just plus
+  (UPat(Ops.INDEX, name="i"), lambda i: i.src[0]+i.src[1]),
+])+symbolic
+
+class VLIWRenderer(Renderer):
+  has_local = False  # TODO: this should be the default / cleaned up
+  # this says this backend supports MULACC + more. decompositions uses this
+  code_for_op: dict = {Ops.MULACC: None, Ops.ADD: "+", Ops.MUL: "*",
+                       Ops.XOR: "^", Ops.AND: "&", Ops.OR: "|",
+                       Ops.SHL: "<<", Ops.SHR: ">>", Ops.CMPLT: "<"}
+  # this matcher runs while still in graph form
+  pre_matcher = vliw_prepare
+
+  def render(self, uops:list[UOp]):
+
+    # TODO: this is a minimal renderer. for low cycle count, make it good
+    # to get speed, you need to add VLIW packing
+    # to get under 1536 regs, you need to add a register allocator
+    # we left the fun parts to you
+
+    print(f"rendering with {len(uops)} uops")
+    reg, inst = 0, []
+    r: dict[UOp, int] = {}
+    for u in uops:
+      assert u.dtype.count in (1,8), "dtype count must be 1 or 8"
+
+      # dumb register allocator
+      if u.op not in {Ops.STORE, Ops.SINK, Ops.GEP}:
+        r[u] = reg
+        reg += u.dtype.count
+
+      # render UOps to instructions
+      match u.op:
+        case Ops.SINK:
+          inst.append({"flow": [("halt",)]})
+        case Ops.CONST:
+          inst.append({"load": [("const", r[u], u.arg)]})
+        case Ops.GEP:
+          # a GEP is just an alias to a special register in the vector
+          r[u] = r[u.src[0]] + u.arg[0]
+        case Ops.VECTORIZE:
+          if all(s == u.src[0] for s in u.src):
+            # if all sources are the same, we can broadcast
+            inst.append({"valu": [("vbroadcast", r[u], r[u.src[0]])]})
+          else:
+            # this is a copy into a contiguous chunk of registers
+            inst.extend({"flow": [("add_imm", r[u]+i, r[s], 0)]} for i,s in enumerate(u.src) if r[s] != r[u]+i)
+        case Ops.LOAD:
+          op = "vload" if u.dtype.count > 1 else "load"
+          inst.append({"load": [(op, r[u], r[u.src[0]])]})
+        case Ops.STORE:
+          op = "vstore" if u.src[1].dtype.count > 1 else "store"
+          inst.append({"store": [(op, r[u.src[0]], r[u.src[1]])]})
+        case Ops.MULACC:
+          assert u.dtype.count == 8
+          inst.append({"valu": [("multiply_add", r[u], r[u.src[0]], r[u.src[1]], r[u.src[2]])]})
+        case Ops.WHERE:
+          assert u.dtype.count == 8
+          inst.append({"flow": [("vselect", r[u], r[u.src[0]], r[u.src[1]], r[u.src[2]])]})
+        case _ if u.op in self.code_for_op:
+          cat = "valu" if u.dtype.count > 1 else "alu"
+          inst.append({cat: [(self.code_for_op[u.op], r[u], r[u.src[0]], r[u.src[1]])]})
+        case _:
+          raise NotImplementedError(f"unhandled op {u.op}")
+    return repr(inst)
+
+# ************************* test and render *************************
+
+import sys, types
+PROBLEM_URL = "https://raw.githubusercontent.com/anthropics/original_performance_takehome/refs/heads/main/tests/frozen_problem.py"
+sys.modules["problem"] = problem = types.ModuleType("problem")
+exec(fetch(PROBLEM_URL).read_text(), problem.__dict__)
+
+if __name__ == "__main__":
+  batch_size = getenv("BS", 256)
+  height = 10
+  rounds = getenv("ROUNDS", 16)
+
+  # build problem
+  tree = problem.Tree.generate(height)
+  inp = problem.Input.generate(tree, batch_size, rounds)
+  mem = problem.build_mem_image(tree, inp)
+  global_addrs.extend([mem[6], mem[6], mem[4]])  # output, input, forest
+
+  # *** verify the kernel in tinygrad compared to reference ***
+
+  forest_t = Tensor(tree.values, dtype=dtypes.uint32)
+  val_t = Tensor(inp.values, dtype=dtypes.uint32)
+
+  if getenv("VERIFY", 1):
+    # verify on normal tinygrad device
+    with Context(PCONTIG=2):
+      out = tree_traversal(forest_t, val_t, height, rounds)
+      val_out = out.tolist()
+    problem.reference_kernel(tree, inp)
+    assert val_out == inp.values
+    print("verification passed")
+
+  # *** render to device ***
+
+  from tinygrad.codegen import get_program
+  with Context(PCONTIG=2, DEVECTORIZE=2, SPEC=0):
+    out = tree_traversal(forest_t, val_t, height, rounds)
+    sink = out.schedule()[-1].ast
+    prg = get_program(sink, VLIWRenderer())
+
+  # *** run on Machine and compare ***
+
+  # NOTE: the scratch size needs to be reduced to 1536 when you have a register allocator
+  src = eval(prg.src)
+  max_regs = max(t[1] for instr in src for v in instr.values() for t in v if len(t) > 1) + 8
+  print(f"{max_regs:5d} regs used" + ("" if max_regs <= 1536 else "       <-- WARNING: TOO MANY REGISTERS, MUST BE <= 1536"))
+  machine = problem.Machine(mem, src, problem.DebugInfo(scratch_map={}), n_cores=1, trace=False, scratch_size=max_regs)
+  machine.run()
+  print(f"ran for {machine.cycle:5d} cycles" + ("" if machine.cycle <= 1363 else "  <-- EVEN CLAUDE GOT 1363"))
+
+  # compare to reference
+  ref_mem = mem.copy()
+  for _ in problem.reference_kernel2(ref_mem, {}): pass
+  assert machine.mem[mem[6]:mem[6]+mem[2]] == ref_mem[mem[6]:mem[6]+mem[2]]
+  print("compare passed!")
@@ -0,0 +1,79 @@
+from typing import Optional
+from tinygrad import Tensor
+from tinygrad.dtype import DTypeLike, dtypes
+import math
+
+# rewritten from numpy
+def rfftfreq(n: int, d: float = 1.0, device=None) -> Tensor:
+  val = 1.0 / (n * d)
+  N = n // 2 + 1
+  results = Tensor.arange(N, device=device)
+  return results * val
+
+# just like in librosa
+def fft_frequencies(sr: float, n_fft: int) -> Tensor:
+  return rfftfreq(n=n_fft, d=1.0 / sr)
+
+def hz_to_mel(freq: Tensor) -> Tensor:
+  # linear part
+  f_min = 0.0
+  f_sp = 200.0 / 3
+  mels = (freq - f_min) / f_sp
+
+  # log-scale part
+  min_log_hz = 1000.0  # beginning of log region (Hz)
+  mask = freq >= min_log_hz
+  return mask.where(((min_log_hz - f_min) / f_sp) + (freq / min_log_hz).log() / (math.log(6.4) / 27.0), mels)
+
+def mel_to_hz(mels: Tensor) -> Tensor:
+  # linear scale
+  f_min = 0.0
+  f_sp = 200.0 / 3
+  freqs = f_min + f_sp * mels
+
+  # nonlinear scale
+  min_log_hz = 1000.0  # beginning of log region (Hz)
+  min_log_mel = (min_log_hz - f_min) / f_sp  # same (Mels)
+  logstep = math.log(6.4) / 27.0  # step size for log region
+
+  log_t = mels >= min_log_mel
+  freqs = log_t.where(min_log_hz * ((logstep * (mels - min_log_mel)).exp()), freqs)
+  return freqs
+
+def mel_frequencies(n_mels: int = 128, *, fmin: float = 0.0, fmax: float = 11025.0) -> Tensor:
+  # center freqs of mel bands - uniformly spaced between limits
+  min_max_mel = hz_to_mel(Tensor([fmin, fmax]))
+
+  mels = Tensor.linspace(min_max_mel[0], min_max_mel[1], n_mels)
+  hz = mel_to_hz(mels)
+  return hz
+
+def mel(
+  *,
+  sr: float,
+  n_fft: int,
+  n_mels: int = 128,
+  fmin: float = 0.0,
+  fmax: Optional[float] = None,
+  dtype: DTypeLike = dtypes.default_float,
+) -> Tensor:
+  if fmax is None:
+    fmax = float(sr) / 2
+
+  n_mels = int(n_mels)
+
+  fftfreqs = fft_frequencies(sr=sr, n_fft=n_fft)  # center freqs of each FFT bin
+  mel_f = mel_frequencies(n_mels + 2, fmin=fmin, fmax=fmax)  # center freqs of mel bands
+
+  fdiff = mel_f[1:] - mel_f[:-1]
+  ramps = mel_f[None].T.expand(-1, fftfreqs.shape[-1]) - fftfreqs
+
+  lower = -ramps[:n_mels] / fdiff[:n_mels][None].T
+  upper = ramps[2 : n_mels + 2] / fdiff[1 : n_mels + 1][None].T
+  weights = lower.minimum(upper).maximum(0)
+
+  # Slaney-style mel is scaled to be approx constant energy per channel
+  enorm = 2.0 / (mel_f[2 : n_mels + 2] - mel_f[:n_mels])
+  weights *= enorm[:, None]
+
+  return weights
@@ -72,7 +72,7 @@ def loader_process(q_in, q_out, X:Tensor, seed):
      #storage_tensor._copyin(img_tensor.numpy())

      # faster
-      X[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = img.tobytes()
+      X[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = img.tobytes()

      # ideal
      #X[idx].assign(img.tobytes())   # NOTE: this is slow!
@@ -264,8 +264,8 @@ def load_unet3d_data(preprocessed_dataset_dir, seed, queue_in, queue_out, X:Tens
      x = random_brightness_augmentation(x)
      x = gaussian_noise(x)

-    X[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = x.tobytes()
-    Y[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = y.tobytes()
+    X[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = x.tobytes()
+    Y[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = y.tobytes()

    queue_out.put(idx)
  queue_out.put(None)
@@ -379,12 +379,12 @@ def load_retinanet_data(base_dir:Path, val:bool, queue_in:Queue, queue_out:Queue
      clipped_match_idxs = np.clip(match_idxs, 0, None)
      clipped_boxes, clipped_labels = tgt["boxes"][clipped_match_idxs], tgt["labels"][clipped_match_idxs]

-      boxes[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = clipped_boxes.tobytes()
-      labels[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = clipped_labels.tobytes()
-      matches[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = match_idxs.tobytes()
-      anchors[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = anchor.tobytes()
+      boxes[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = clipped_boxes.tobytes()
+      labels[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = clipped_labels.tobytes()
+      matches[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = match_idxs.tobytes()
+      anchors[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = anchor.tobytes()

-    imgs[idx].contiguous().realize().uop.base.realized.as_buffer(force_zero_copy=True)[:] = img.tobytes()
+    imgs[idx].contiguous().realize().uop.base.realized.as_memoryview(force_zero_copy=True)[:] = img.tobytes()

    queue_out.put(idx)
  queue_out.put(None)
@@ -3,7 +3,7 @@ from pathlib import Path
 import multiprocessing

 from tinygrad import Device, GlobalCounters, Tensor, TinyJit, dtypes
-from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, Profiling
+from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, Profiling, profile_marker
 from tinygrad.nn.state import get_parameters, get_state_dict, load_state_dict, safe_load, safe_save
 from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, Adam, AdamW

@@ -1286,17 +1286,23 @@ def train_llama3():
  from examples.llama3 import MODEL_PARAMS
  from examples.mlperf.lr_schedulers import CosineAnnealingLRWithWarmup

+  BENCHMARK = getenv("BENCHMARK")
+
  config = {}
  BASEDIR            = config["BASEDIR"]                = Path(getenv("BASEDIR", "/raid/datasets/c4/"))
  BS                 = config["BS"]                     = getenv("BS", 16)
  grad_acc           = config["GRADIENT_ACC_STEPS"]     = getenv("GRADIENT_ACC_STEPS", 1)
-  assert grad_acc == 1, f"{grad_acc=} is not supported"
  GBS                = config["GLOBAL_BATCH_SIZE"]      = BS * grad_acc
  SEED               = config["SEED"]                   = getenv("SEED", 5760)
  SEQLEN             = config["SEQLEN"]                 = getenv("SEQLEN", 8192)
  TRAIN_ON_VAL       = config["TRAIN_ON_VAL"]           = getenv("TRAIN_ON_VAL", 0)
  SMALL              = config["SMALL"]                  = getenv("SMALL", 0)
  SAMPLES            = config["SAMPLES"]                = getenv("SAMPLES", 5_760 if TRAIN_ON_VAL else 1_200_000 * 1152)
+  EVAL_SAMPLES       = config["EVAL_SAMPLES"]           = getenv("EVAL_SAMPLES", 5760 if not SMALL else 1024)
+  MAX_STEPS          = config["MAX_STEPS"]              = getenv("MAX_STEPS", math.ceil(1_200_000 * 1152 / GBS))
+  WARMUP_STEPS       = config["WARMUP_STEPS"]           = getenv("WARMUP_STEPS", math.ceil(8000 * 1152 / GBS))
+  LR                 = config["LR"]                     = getenv("LR", 8e-5 * GBS / 1152)
+  END_LR             = config["END_LR"]                 = getenv("END_LR", 8e-7)
  EVAL_FREQ          = config["EVAL_FREQ"]              = getenv("EVAL_FREQ", 46080)
  EVAL_BS            = config["EVAL_BS"]                = getenv("EVAL_BS", 16)
  EVAL_TARGET        = config["EVAL_TARGET"]            = getenv("EVAL_TARGET", 5.6)
@@ -1310,10 +1316,12 @@ def train_llama3():
  opt_adamw_weight_decay = 0.1

  opt_gradient_clip_norm = 1.0
-  opt_learning_rate_warmup_steps = getenv("WARMUP_STEPS", math.ceil(8000 * 1152 / GBS))
-  opt_learning_rate_decay_steps = getenv("MAX_STEPS", math.ceil(1_200_000 * 1152 / GBS)) - opt_learning_rate_warmup_steps
-  opt_base_learning_rate = getenv("LR", 8e-5 * GBS / 1152)  # NOTE: cannot change for benchmark
-  opt_end_learning_rate = getenv("END_LR", 8e-7)
+  opt_learning_rate_warmup_steps = WARMUP_STEPS
+  opt_learning_rate_decay_steps = MAX_STEPS - opt_learning_rate_warmup_steps
+  opt_base_learning_rate = LR
+  opt_end_learning_rate = END_LR
+
+  Tensor.manual_seed(SEED)  # seed for weight initialization

  # ** init wandb **
  WANDB = getenv("WANDB")
@@ -1326,6 +1334,8 @@ def train_llama3():
  # vocab_size from the mixtral tokenizer
  if not SMALL: model_params |= {"vocab_size": 32000}
  if (llama_layers:=getenv("LLAMA_LAYERS")) != 0: model_params['n_layers'] = llama_layers
+  print(f"model parameters: {model_params}")
+
  model = Transformer(**model_params, max_context=SEQLEN, jit=False, disable_kv_cache=True)
  params = get_parameters(model)
  # weights are all bfloat16 for now
@@ -1361,6 +1371,12 @@ def train_llama3():

  optim = AdamW(get_parameters(model), lr=0.0,
                b1=opt_adamw_beta_1, b2=opt_adamw_beta_2, eps=opt_adamw_epsilon, weight_decay=opt_adamw_weight_decay)
+
+  # init grads
+  for p in optim.params:
+    p.grad = p.zeros_like().contiguous().realize()
+  grads = [p.grad for p in optim.params]
+
  scheduler = CosineAnnealingLRWithWarmup(optim, opt_base_learning_rate, opt_end_learning_rate, opt_learning_rate_warmup_steps, opt_learning_rate_decay_steps)

  if resume_ckpt := getenv("RESUME_CKPT"):
@@ -1373,9 +1389,7 @@ def train_llama3():
    load_state_dict(scheduler, safe_load(fn), realize=False)

  @TinyJit
-  @Tensor.train()
-  def train_step(model, tokens:Tensor):
-    optim.zero_grad()
+  def minibatch(tokens:Tensor):
    if (DP := getenv("DP", 1)) > 1:
      device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP))
      tokens = tokens.shard(device, 0)
@@ -1385,27 +1399,40 @@ def train_llama3():
    logits:Tensor = model(tokens[:, :-1], start_pos=0, temperature=math.nan)
    loss = logits.sparse_categorical_crossentropy(tokens[:, 1:])
    loss.backward()
+    assert all(p.grad is g for p,g in zip(optim.params, grads))
+    Tensor.realize(loss, *grads)
+    return loss
+
+  @TinyJit
+  def optim_step():
+    for p in optim.params:
+      p.grad.assign(p.grad / grad_acc)
+
    # L2 norm grad clip
    # https://github.com/NVIDIA/NeMo/blob/3368c3fc0b4a186ab33a1d68a504315100c0b2a6/nemo/collections/nlp/modules/common/megatron/clip_grads.py#L57
    # https://docs.pytorch.org/docs/stable/generated/torch.nn.utils.clip_grad_norm_.html
    if not getenv("DISABLE_GRAD_CLIP_NORM"):
      total_norm = Tensor(0.0, dtype=dtypes.float32, device=optim.params[0].device)
-      for p in optim.params:
-        total_norm += p.grad.float().square().sum()
-      total_norm = total_norm.sqrt().contiguous()
-      for p in optim.params:
-        p.grad = p.grad * (opt_gradient_clip_norm / (total_norm + 1e-6)).clamp(max_=1.0)
+      for g in grads:
+        total_norm += g.float().square().sum()
+      total_norm = total_norm.sqrt().contiguous().realize()
+      for g in grads:
+        g.assign((g * (opt_gradient_clip_norm / (total_norm + 1e-6)).clamp(max_=1.0)).cast(g.dtype)).realize()

    optim.step()
    scheduler.step()

+    for g in grads:
+      g.assign(g.zeros_like().contiguous()).realize()
+
    lr = optim.lr
-    loss.realize(lr)
-    return loss, lr
+    Tensor.realize(lr, *grads)
+
+    return lr

  @TinyJit
  @Tensor.train(False)
-  def eval_step(model, tokens:Tensor):
+  def eval_step(tokens:Tensor):
    if (DP := getenv("DP", 1)) > 1:
      device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP))
      tokens = tokens.shard(device, 0)
@@ -1432,39 +1459,73 @@ def train_llama3():
    eval_dataset = None
  else:
    from examples.mlperf.dataloader import get_llama3_dataset
-    eval_dataset = get_llama3_dataset(5760, SEQLEN, BASEDIR, val=True, small=bool(SMALL))
+    eval_dataset = get_llama3_dataset(EVAL_SAMPLES, SEQLEN, BASEDIR, val=True, small=bool(SMALL))

  def get_eval_iter():
    if eval_dataset is None:
-      return fake_data(EVAL_BS, 5760)
+      return fake_data(EVAL_BS, EVAL_SAMPLES)
    from examples.mlperf.dataloader import iterate_llama3_dataset
    return iterate_llama3_dataset(eval_dataset, EVAL_BS)

-  iter = get_train_iter()
+  num_params = sum(p.numel() for p in params) - model_params["vocab_size"]*model_params["dim"]
+  train_iter = get_train_iter()
  i, sequences_seen = resume_ckpt, 0
-  for tokens in tqdm(iter, total=SAMPLES//GBS):
+  step_times = []
+  while i < MAX_STEPS:
    GlobalCounters.reset()
    if getenv("TRAIN", 1):
-      t = time.perf_counter()
-      loss, lr = train_step(model, tokens)
+      profile_marker(f"train @ {i}")
+      st = time.perf_counter()
+
+      stopped = False
+      for _ in range(grad_acc):
+        ist = time.perf_counter()
+        try: tokens = next(train_iter)
+        except StopIteration:
+          stopped = True
+          break
+        dt = time.perf_counter()
+        loss = minibatch(tokens)
+      if stopped: break
+
+      gt = time.perf_counter()
+      lr = optim_step()
+      ot = time.perf_counter()
+
      loss = loss.float().item()
      lr = lr.item()

+      et = time.perf_counter()
+      step_time = et - st
+      gbs_time = gt - st
+      optim_time = ot - gt
+      data_time = dt - ist
+      dev_time = step_time - data_time * grad_acc
+      if BENCHMARK: step_times.append(step_time)
+
      i += 1
-      sequences_seen += tokens.shape[0]
+      sequences_seen += GBS

-      sec = time.perf_counter()-t
      mem_gb = GlobalCounters.mem_used / 1e9
-      gflops = GlobalCounters.global_ops / 1e9 / sec
+      gflops = GlobalCounters.global_ops / 1e9 / dev_time
+      mfu = ((6 * num_params * SEQLEN * GBS) / (dev_time * max(getenv("DP", 1), getenv("MP", 1)) * 2.3e15)) * 100
      tqdm.write(
-        f"{i:5} {sec:.2f} s run, {loss:.4f} loss, {lr:.12f} LR, {mem_gb:.2f} GB used, {gflops:9.2f} GFLOPS")
-
-      if (fname:=getenv("LOSS_FILE", "")):
-        with open(fname, "a") as f:
-          f.write(f"{i} {loss:.4f} {lr:.12f} {mem_gb:.2f}\n")
+          f"{i:5} {step_time:.3f} s step, {gbs_time:.3f} s gbs, {optim_time:.3f} s optim, {data_time:.3f} s data, {loss:.4f} loss, " \
+          f"{lr:.12f} LR, {mem_gb:.2f} GB used, {gflops:9.2f} GFLOPS, {mfu:5.2f}% MFU")

      if WANDB:
-        wandb.log({"lr": lr, "train/loss": loss, "train/step_time": sec, "train/GFLOPS": gflops, "train/sequences_seen": sequences_seen})
+        wandb.log({
+          "lr": lr, "train/loss": loss,
+          "train/step_time": step_time,
+          "train/gbs_time": gbs_time,
+          "train/optim_time": optim_time,
+          "train/dev_time": dev_time,
+          "train/data_time": data_time,
+          "train/mem": mem_gb,
+          "train/GFLOPS": gflops,
+          "train/MFU": mfu,
+          "train/sequences_seen": sequences_seen
+        })

      if (ckpt_freq := getenv("CKPT")) and (i % ckpt_freq == 0 and (i != 1 or ckpt_freq == 1)):
        tqdm.write("saving checkpoint")
@@ -1476,16 +1537,29 @@ def train_llama3():
        fn = f"{ckpt_dir}/llama3_{i}_optim.safe"
        safe_save(get_state_dict(scheduler), fn)

-    if sequences_seen % EVAL_FREQ == 0 and (i != 1 or EVAL_FREQ == 1):
+      if i == BENCHMARK:
+        median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2]
+        estimated_total_minutes = int(median_step_time * (SAMPLES // GBS) / 60)
+        print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m")
+        print(f"epoch global_ops: {GlobalCounters.global_ops:_}, "
+              f"epoch global_mem: {GlobalCounters.global_mem:_}")
+
+    if (sequences_seen % EVAL_FREQ == 0 and (i != 1 or EVAL_FREQ == 1)) or (BENCHMARK and i == BENCHMARK):
+      if EVAL_BS == 0: return
      tqdm.write(f"evaluating after {sequences_seen} sequences")
+      profile_marker(f"eval @ {i}")

      # run eval
      eval_losses = []
      eval_iter = get_eval_iter()
      tqdm.write(f"evaluating {5760//EVAL_BS} batches of {EVAL_BS} sequences")

-      for tokens in tqdm(eval_iter, total=5760//EVAL_BS):
-        eval_losses += eval_step(model, tokens).tolist()
+      for j,tokens in tqdm(enumerate(eval_iter), total=EVAL_SAMPLES//EVAL_BS):
+        eval_losses += eval_step(tokens).tolist()
+
+        if BENCHMARK and (j+1) == min(BENCHMARK, EVAL_SAMPLES//EVAL_BS):
+          return
+
      log_perplexity = Tensor(eval_losses).mean().float().item()

      tqdm.write(f"eval log perplexity: {log_perplexity:.4f}")
@@ -1571,7 +1645,7 @@ def train_stable_diffusion():
    loss, out_lr = loss.detach().to("CPU"), optimizer.lr.to("CPU")
    Tensor.realize(loss, out_lr)
    return loss, out_lr
-    
+
  # checkpointing takes ~9 minutes without this, and ~1 minute with this
  @TinyJit
  def ckpt_to_cpu():
@@ -1610,7 +1684,7 @@ def train_stable_diffusion():
    if i == 3:
      for _ in range(3): ckpt_to_cpu() # do this at the beginning of run to prevent OOM surprises when checkpointing
      print("BEAM COMPLETE", flush=True) # allows wrapper script to detect BEAM search completion and retry if it failed
-      
+
    total_train_time = time.perf_counter() - train_start_time
    if WANDB:
      wandb.log({"train/loss": loss_item, "train/lr": lr_item, "train/loop_time_prev": loop_time, "train/dl_time": dl_time, "train/step": i,
@@ -4,7 +4,7 @@ export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" GPUS=1 BS=128 EVAL_BS=128

-export IGNORE_OOB=1
+export CHECK_OOB=0

 export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
@@ -5,7 +5,7 @@ export MODEL="bert"
 export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -8,7 +8,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -11,7 +11,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -0,0 +1,20 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1 DEBUG=0 JIT=1 FLASH_ATTENTION=1
+export MODEL="bert"
+export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
+
+# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54
+export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
+export TRAIN_STEPS=3900
+
+export CHECK_OOB=0
+export REWRITE_STACK_LIMIT=5000000
+
+export BEAM=0 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
+export BASEDIR="/raid/datasets/wiki"
+
+export WANDB=1 PARALLEL=0
+
+RUNMLPERF=1 python3 examples/mlperf/model_train.py
@@ -8,7 +8,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=5000000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -11,7 +11,7 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
 export TRAIN_STEPS=3900

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=5000000

 export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." NV=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=72 EVAL_BS=72

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." NV=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=72 EVAL_BS=72

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -7,7 +7,7 @@ export MODEL="bert"
 export SUBMISSION_PLATFORM="tinybox_green"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=72 EVAL_BS=72

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -4,7 +4,7 @@ export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -7,7 +7,7 @@ export MODEL="bert"
 export SUBMISSION_PLATFORM="tinybox_red"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export IGNORE_OOB=1
+export CHECK_OOB=0
 export REWRITE_STACK_LIMIT=500000

 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
@@ -0,0 +1,34 @@
+#!/usr/bin/env bash
+
+export PYTHONPATH="."
+export DEV=${DEV:-AMD}
+export CHECK_OOB=0
+export REWRITE_STACK_LIMIT=5000000 HCQDEV_WAIT_TIMEOUT_MS=240000
+
+export DEBUG=${DEBUG:-2}
+export FLASH_ATTENTION=${FLASH_ATTENTION:-1}
+export ALL2ALL=${ALL2ALL:-1}
+export USE_ATOMICS=${USE_ATOMICS:-1}
+export ASM_GEMM=${ASM_GEMM:-1}
+
+export DEFAULT_FLOAT="bfloat16" OPTIM_DTYPE="bfloat16"
+export DP=8 BS=16 EVAL_BS=8 GRADIENT_ACC_STEPS=1
+export GBS=$((BS * GRADIENT_ACC_STEPS))
+
+export MODEL="llama3"
+export BASEDIR="/raid/datasets/c4-8b/"
+export SMALL=1
+export LLAMA3_SIZE=${LLAMA3_SIZE:-"8B"}
+export EVAL_TARGET=3.3 EVAL_FREQ=12288
+export LR="2.5e-4" END_LR="2.5e-5" WARMUP_SAMPLES=256 MAX_STEPS=1200000
+export WARMUP_STEPS=$((WARMUP_SAMPLES / GBS))
+export SAMPLES=$((MAX_STEPS * GBS))
+
+export SEED=5760
+
+export JITBEAM=3
+export BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+
+export FAKEDATA=1 BENCHMARK=10 LLAMA_LAYERS=2
+
+python3 examples/mlperf/model_train.py
@@ -0,0 +1,33 @@
+#!/usr/bin/env bash
+
+export PYTHONPATH="."
+export DEV=${DEV:-AMD}
+export EMULATE="AMD_CDNA4"
+export CHECK_OOB=0
+export REWRITE_STACK_LIMIT=5000000 HCQDEV_WAIT_TIMEOUT_MS=240000
+
+export DEBUG=${DEBUG:-0}
+export FLASH_ATTENTION=${FLASH_ATTENTION:-1}
+export ALL2ALL=${ALL2ALL:-1}
+export USE_ATOMICS=${USE_ATOMICS:-1}
+export ASM_GEMM=${ASM_GEMM:-1}
+
+export DEFAULT_FLOAT="bfloat16" OPTIM_DTYPE="bfloat16"
+export DP=${DP:-8} BS=${BS:-16} EVAL_BS=${EVAL_BS:-8} GRADIENT_ACC_STEPS=${GRADIENT_ACC_STEPS:-1}
+export GBS=$((BS * GRADIENT_ACC_STEPS))
+
+export MODEL="llama3"
+export BASEDIR="/raid/datasets/c4-8b/"
+export SMALL=1
+export LLAMA3_SIZE=${LLAMA3_SIZE:-"8B"}
+export EVAL_TARGET=3.3 EVAL_FREQ=12288
+export LR="2.5e-4" END_LR="2.5e-5" WARMUP_SAMPLES=256 MAX_STEPS=1200000
+export WARMUP_STEPS=$((WARMUP_SAMPLES / GBS))
+export SAMPLES=$((MAX_STEPS * GBS))
+
+export SEED=${SEED:-5760}
+
+export JITBEAM=${JITBEAM:-3}
+export BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+
+python3 examples/mlperf/model_train.py
@@ -0,0 +1,10 @@
+#!/bin/bash
+export BENCHMARK=5
+export EVAL_BS=0
+export FAKEDATA=1
+export NULL_ALLOW_COPYOUT=1
+export HIP_VISIBLE_DEVICES=""
+export DEV=NULL
+export JITBEAM=0
+export LLAMA_LAYERS=${LLAMA_LAYERS:-"2"}
+time examples/mlperf/training_submission_v6.0/tinycorp/benchmarks/llama8b/implementations/tinybox_8xMI350X/dev_run.sh
@@ -6,7 +6,6 @@ import argparse, time
 from collections import namedtuple
 from typing import Dict, Any

-from PIL import Image
 import numpy as np
 from tinygrad import Device, GlobalCounters, dtypes, Tensor, TinyJit
 from tinygrad.helpers import Timing, Context, getenv, fetch, colored, tqdm, flatten, profile_marker
@@ -336,6 +335,7 @@ if __name__ == "__main__":
  print(x.shape)

  profile_marker("save image")
+  from PIL import Image
  im = Image.fromarray(x.numpy())
  print(f"saving {args.out}")
  im.save(args.out)
@@ -48,7 +48,7 @@ def prepare_browser_chunks(model):
        weight_metadata = metadata.get(name, default)
        weight_metadata["parts"][part_num] = {"file": i, "file_start_pos": cursor, "size": size}
        metadata[name] = weight_metadata
-        data = bytes(state_dict[name].uop.base.realized.as_buffer())
+        data = bytes(state_dict[name].uop.base.realized.as_memoryview())
        data = data if not offsets else data[offsets[0]:offsets[1]]
        writer.write(data)
        cursor += size
@@ -93,7 +93,7 @@ if __name__ == "__main__":
    forward: Any = None

  sub_steps = [
-    Step(name = "textModel", input = [Tensor.randn(1, 77)], forward = model.cond_stage_model.transformer.text_model),
+    Step(name = "textModel", input = [Tensor.randint(1, 77, low=0, high=49408, dtype=dtypes.int32)], forward = model.cond_stage_model.transformer.text_model),
    Step(name = "diffusor", input = [Tensor.randn(1, 77, 768), Tensor.randn(1, 77, 768), Tensor.randn(1,4,64,64), Tensor.rand(1), Tensor.randn(1), Tensor.randn(1), Tensor.randn(1)], forward = model),
    Step(name = "decoder", input = [Tensor.randn(1,4,64,64)], forward = model.decode),
    Step(name = "f16tof32", input = [Tensor.randn(2097120, dtype=dtypes.uint32)], forward = u32_to_f16)
@@ -7,6 +7,7 @@ from tinygrad import Tensor, TinyJit, Variable, nn, dtypes
 from tinygrad.nn.state import torch_load, load_state_dict
 from tinygrad.helpers import getenv, fetch

+from examples.audio_helpers import mel
 import numpy as np
 import librosa

@@ -159,7 +160,7 @@ def prep_audio(waveforms: List[np.ndarray], batch_size: int, truncate=False) ->

  stft = librosa.stft(waveforms, n_fft=N_FFT, hop_length=HOP_LENGTH, window='hann', dtype=np.csingle)
  magnitudes = np.absolute(stft[..., :-1]) ** 2
-  mel_spec = librosa.filters.mel(sr=RATE, n_fft=N_FFT, n_mels=N_MELS) @ magnitudes
+  mel_spec = mel(sr=RATE, n_fft=N_FFT, n_mels=N_MELS).numpy() @ magnitudes

  log_spec = np.log10(np.clip(mel_spec, 1e-10, None))
  log_spec = np.maximum(log_spec, log_spec.max((1,2), keepdims=True) - 8.0)
@@ -19,8 +19,9 @@ amdev = importlib.import_module("tinygrad.runtime.support.am.amdev")
 amdev.AMDev = AMDFake
 from tinygrad.runtime.ops_amd import PCIIface

-def parse_amdgpu_logs(log_content, register_names=None, *, only_xcc0: bool = False):
+def parse_amdgpu_logs(log_content, register_names=None, register_objects=None, *, only_xcc0: bool = False):
  register_map = register_names or {}
+  register_objs = register_objects or {}

  def replace_register(match):
    reg = match.group(1)
@@ -37,6 +38,28 @@ def parse_amdgpu_logs(log_content, register_names=None, *, only_xcc0: bool = Fal
  # remove timing prefix
  processed_log = re.sub(r'^\[\s*\d+(?:\.\d+)?\]\s*', '', processed_log, flags=re.MULTILINE)

+  # decode register values into field dicts
+  def decode_value(match):
+    reg_name = match.group(1)
+    xcc_part = match.group(2)  # "xcc=0 " or ""
+    val_str = match.group(3)
+    val = int(val_str, 16)
+
+    reg_obj = register_objs.get(reg_name)
+    if reg_obj is not None and reg_obj.fields:
+      fields = reg_obj.decode(val)
+      # show raw for unaccounted bits
+      accounted = 0
+      for name, (start, end) in reg_obj.fields.items():
+        accounted |= (((1 << (end - start + 1)) - 1) << start)
+      unaccounted = val & ~accounted
+      parts = {k: v for k, v in fields.items() if v != 0}
+      if unaccounted: parts['_raw_unaccounted'] = hex(unaccounted)
+      return f"register {reg_name}, {xcc_part}with value {val_str} {parts}"
+    return match.group(0)
+
+  processed_log = re.sub(r'register (reg\w+), ((?:xcc=\d+ )?)with value (0x[0-9a-fA-F]+)', decode_value, processed_log)
+
  # keep only xcc=0 lines (but keep lines with no xcc at all)
  if only_xcc0:
    kept = []
@@ -50,16 +73,18 @@ def main():
  only_xcc0 = bool(getenv("ONLY_XCC0", 0))

  reg_names = {}
+  reg_objs = {}
  dev = PCIIface(None, 0)
  for x, y in dev.dev_impl.__dict__.items():
    if isinstance(y, AMRegister):
      for xcc, addr in y.addr.items():
        reg_names[addr] = f"{x}, xcc={xcc}"
+      reg_objs[x] = y

  with open(sys.argv[1], 'r') as f:
    log_content = f.read()

-  processed_log = parse_amdgpu_logs(log_content, reg_names, only_xcc0=only_xcc0)
+  processed_log = parse_amdgpu_logs(log_content, reg_names, reg_objs, only_xcc0=only_xcc0)

  with open(sys.argv[2], 'w') as f:
    f.write(processed_log)
@@ -0,0 +1,67 @@
+# Instruction format detection and decoding
+from __future__ import annotations
+from extra.assembly.amd.dsl import Inst, FixedBitField, EnumBitField
+
+# SDWA/DPP variant detection: src0 field (bits 0-8) encodes the variant
+# 0xf9 (249) = SDWA, 0xfa (250) = DPP16 for CDNA (GFX9)
+_VARIANT_SRC0 = {"_SDWA_SDST": 0xf9, "_SDWA": 0xf9, "_DPP16": 0xfa}
+
+def _matches(data: bytes, cls: type[Inst]) -> bool:
+  """Check if data matches all FixedBitFields and op is in allowed."""
+  for _, field in cls._fields:
+    dword_idx = field.lo // 32
+    if len(data) < (dword_idx + 1) * 4: return False
+    word = int.from_bytes(data[dword_idx*4:(dword_idx+1)*4], 'little')
+    field_lo = field.lo % 32
+    if isinstance(field, FixedBitField):
+      if ((word >> field_lo) & field.mask) != field.default: return False
+    if isinstance(field, EnumBitField) and field.allowed is not None:
+      try: opcode = field.decode((word >> field_lo) & field.mask)
+      except ValueError: return False  # opcode not in enum
+      if opcode not in field.allowed: return False
+  # Check SDWA/DPP variant based on src0 field (bits 0-8) - only for variant classes
+  name = cls.__name__
+  word = int.from_bytes(data[:4], 'little')
+  for suffix, expected_src0 in _VARIANT_SRC0.items():
+    if name.endswith(suffix): return (word & 0x1ff) == expected_src0
+  return True
+
+# Import instruction classes for each architecture
+from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP1_SDST, VOP1_LIT, VOP2, VOP2_LIT, VOP3, VOP3_SDST, VOP3SD, VOP3P, VOPC, VOPD, VINTERP,
+  SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPK, SOPK_LIT, SOPP, SMEM, DS, FLAT, GLOBAL, SCRATCH)
+from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP1_SDST as R4_VOP1_SDST, VOP1_LIT as R4_VOP1_LIT,
+  VOP2 as R4_VOP2, VOP2_LIT as R4_VOP2_LIT, VOP3 as R4_VOP3, VOP3_SDST as R4_VOP3_SDST, VOP3SD as R4_VOP3SD, VOP3P as R4_VOP3P,
+  VOPC as R4_VOPC, VOPD as R4_VOPD, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP1_LIT as R4_SOP1_LIT,
+  SOP2 as R4_SOP2, SOP2_LIT as R4_SOP2_LIT, SOPC as R4_SOPC, SOPC_LIT as R4_SOPC_LIT,
+  SOPK as R4_SOPK, SOPK_LIT as R4_SOPK_LIT, SOPP as R4_SOPP,
+  SMEM as R4_SMEM, DS as R4_DS, VFLAT as R4_FLAT, VGLOBAL as R4_GLOBAL, VSCRATCH as R4_SCRATCH)
+from extra.assembly.amd.autogen.cdna.ins import (VOP1 as C_VOP1, VOP1_SDWA as C_VOP1_SDWA, VOP1_DPP16 as C_VOP1_DPP16,
+  VOP2 as C_VOP2, VOP2_LIT as C_VOP2_LIT, VOP2_SDWA as C_VOP2_SDWA, VOP2_DPP16 as C_VOP2_DPP16,
+  VOPC as C_VOPC, VOPC_SDWA_SDST as C_VOPC_SDWA_SDST,
+  VOP3 as C_VOP3, VOP3_SDST as C_VOP3_SDST, VOP3SD as C_VOP3SD, VOP3P as C_VOP3P, VOP3P_MFMA as C_VOP3P_MFMA, VOP3PX2 as C_VOP3PX2,
+  SOP1 as C_SOP1, SOP2 as C_SOP2, SOPC as C_SOPC, SOPK as C_SOPK, SOPK_LIT as C_SOPK_LIT, SOPP as C_SOPP, SMEM as C_SMEM, DS as C_DS,
+  FLAT as C_FLAT, GLOBAL as C_GLOBAL, SCRATCH as C_SCRATCH, MUBUF as C_MUBUF)
+
+# Order matters: more specific encodings first, catch-alls (SOP2, VOP2) last
+# Order: base before _LIT (base matches regular ops, _LIT catches lit-only ops excluded from base)
+_FORMATS = {
+  "rdna3": [VOPD, VOP3P, VINTERP, VOP3SD, VOP3_SDST, VOP3, DS, GLOBAL, SCRATCH, FLAT, SMEM,
+            SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPK, SOPK_LIT, SOPP, VOPC, VOP1_SDST, VOP1, VOP1_LIT, VOP2, VOP2_LIT],
+  "rdna4": [R4_VOPD, R4_VOP3P, R4_VINTERP, R4_VOP3SD, R4_VOP3_SDST, R4_VOP3, R4_DS, R4_GLOBAL, R4_SCRATCH, R4_FLAT, R4_SMEM,
+            R4_SOP1, R4_SOP1_LIT, R4_SOPC, R4_SOPC_LIT, R4_SOPP, R4_SOPK, R4_SOPK_LIT, R4_VOPC, R4_VOP1_SDST, R4_VOP1, R4_VOP1_LIT,
+            R4_SOP2, R4_SOP2_LIT, R4_VOP2, R4_VOP2_LIT],
+  "cdna": [C_VOP3PX2, C_VOP3P_MFMA, C_VOP3P, C_VOP3SD, C_VOP3_SDST, C_VOP3, C_DS, C_GLOBAL, C_SCRATCH, C_FLAT, C_MUBUF, C_SMEM,
+            C_SOP1, C_SOPC, C_SOPP, C_SOPK, C_SOPK_LIT, C_VOPC_SDWA_SDST, C_VOPC,
+            C_VOP1_DPP16, C_VOP1_SDWA, C_VOP1, C_VOP2_DPP16, C_VOP2_SDWA, C_SOP2, C_VOP2, C_VOP2_LIT],
+}
+
+def detect_format(data: bytes, arch: str = "rdna3") -> type[Inst]:
+  """Detect instruction format from machine code bytes."""
+  assert len(data) >= 4, f"need at least 4 bytes, got {len(data)}"
+  for cls in _FORMATS[arch]:
+    if _matches(data, cls): return cls
+  raise ValueError(f"unknown {arch} format word={int.from_bytes(data[:4], 'little'):#010x}")
+
+def decode_inst(data: bytes, arch: str = "rdna3") -> Inst:
+  """Decode machine code bytes into an instruction."""
+  return detect_format(data, arch).from_bytes(data)
@@ -0,0 +1,324 @@
+# autogenerated from AMD ISA XML - do not edit
+from enum import Enum, auto
+
+class ReprEnum(Enum):
+  """Enum with clean repr that roundtrips with eval()."""
+  def __repr__(self): return f"{type(self).__name__}.{self.name}"
+
+class Fmt(Enum):
+  FMT_ANY = auto()
+  FMT_BUF = auto()
+  FMT_IMG = auto()
+  FMT_IMG_BVH = auto()
+  FMT_NUM_B1 = auto()
+  FMT_NUM_B1024 = auto()
+  FMT_NUM_B128 = auto()
+  FMT_NUM_B16 = auto()
+  FMT_NUM_B256 = auto()
+  FMT_NUM_B32 = auto()
+  FMT_NUM_B512 = auto()
+  FMT_NUM_B64 = auto()
+  FMT_NUM_B8 = auto()
+  FMT_NUM_B96 = auto()
+  FMT_NUM_BF16 = auto()
+  FMT_NUM_BF6 = auto()
+  FMT_NUM_BF8 = auto()
+  FMT_NUM_F16 = auto()
+  FMT_NUM_F32 = auto()
+  FMT_NUM_F64 = auto()
+  FMT_NUM_FP4 = auto()
+  FMT_NUM_FP6 = auto()
+  FMT_NUM_FP8 = auto()
+  FMT_NUM_I16 = auto()
+  FMT_NUM_I24 = auto()
+  FMT_NUM_I32 = auto()
+  FMT_NUM_I4 = auto()
+  FMT_NUM_I64 = auto()
+  FMT_NUM_I8 = auto()
+  FMT_NUM_IU4 = auto()
+  FMT_NUM_IU8 = auto()
+  FMT_NUM_M64 = auto()
+  FMT_NUM_PK16_BF16 = auto()
+  FMT_NUM_PK16_BF8 = auto()
+  FMT_NUM_PK16_F16 = auto()
+  FMT_NUM_PK16_F32 = auto()
+  FMT_NUM_PK16_FP8 = auto()
+  FMT_NUM_PK16_I32 = auto()
+  FMT_NUM_PK16_I8 = auto()
+  FMT_NUM_PK2_B16 = auto()
+  FMT_NUM_PK2_B32 = auto()
+  FMT_NUM_PK2_B64 = auto()
+  FMT_NUM_PK2_BF16 = auto()
+  FMT_NUM_PK2_BF8 = auto()
+  FMT_NUM_PK2_F16 = auto()
+  FMT_NUM_PK2_F32 = auto()
+  FMT_NUM_PK2_FP4 = auto()
+  FMT_NUM_PK2_FP8 = auto()
+  FMT_NUM_PK2_I16 = auto()
+  FMT_NUM_PK2_I8 = auto()
+  FMT_NUM_PK2_U16 = auto()
+  FMT_NUM_PK2_U8 = auto()
+  FMT_NUM_PK32_BF16 = auto()
+  FMT_NUM_PK32_BF6 = auto()
+  FMT_NUM_PK32_BF8 = auto()
+  FMT_NUM_PK32_F16 = auto()
+  FMT_NUM_PK32_F32 = auto()
+  FMT_NUM_PK32_FP6 = auto()
+  FMT_NUM_PK32_FP8 = auto()
+  FMT_NUM_PK32_I32 = auto()
+  FMT_NUM_PK32_I8 = auto()
+  FMT_NUM_PK4_B8 = auto()
+  FMT_NUM_PK4_BF16 = auto()
+  FMT_NUM_PK4_BF8 = auto()
+  FMT_NUM_PK4_F16 = auto()
+  FMT_NUM_PK4_F32 = auto()
+  FMT_NUM_PK4_F64 = auto()
+  FMT_NUM_PK4_FP8 = auto()
+  FMT_NUM_PK4_I32 = auto()
+  FMT_NUM_PK4_I8 = auto()
+  FMT_NUM_PK4_IU8 = auto()
+  FMT_NUM_PK4_U8 = auto()
+  FMT_NUM_PK8_B32 = auto()
+  FMT_NUM_PK8_BF16 = auto()
+  FMT_NUM_PK8_BF8 = auto()
+  FMT_NUM_PK8_F16 = auto()
+  FMT_NUM_PK8_FP8 = auto()
+  FMT_NUM_PK8_I4 = auto()
+  FMT_NUM_PK8_I8 = auto()
+  FMT_NUM_PK8_IU4 = auto()
+  FMT_NUM_PK8_U4 = auto()
+  FMT_NUM_PK8_U8 = auto()
+  FMT_NUM_PK_F16 = auto()
+  FMT_NUM_PK_I16 = auto()
+  FMT_NUM_PK_I8 = auto()
+  FMT_NUM_PK_U16 = auto()
+  FMT_NUM_PK_U8 = auto()
+  FMT_NUM_U16 = auto()
+  FMT_NUM_U24 = auto()
+  FMT_NUM_U32 = auto()
+  FMT_NUM_U4 = auto()
+  FMT_NUM_U64 = auto()
+  FMT_NUM_U8 = auto()
+  FMT_RSRC = auto()
+  FMT_RSRC_SCALAR = auto()
+  FMT_RSRC_SCRATCH = auto()
+  FMT_RSRC_SCRATCH_BYTE = auto()
+  FMT_RSRC_SCRATCH_STRIDE = auto()
+  FMT_RSRC_TYPED = auto()
+  FMT_RSRC_TYPED_BYTE = auto()
+  FMT_RSRC_TYPED_SCRATCH = auto()
+  FMT_RSRC_TYPED_STRIDE = auto()
+  FMT_RSRC_VECTOR = auto()
+  FMT_RSRC_VECTOR_BYTE = auto()
+  FMT_RSRC_VECTOR_STRIDE = auto()
+  FMT_SAMP = auto()
+  FMT_WMMA_AB_16X16_BF16 = auto()
+  FMT_WMMA_AB_16X16_BF8 = auto()
+  FMT_WMMA_AB_16X16_F16 = auto()
+  FMT_WMMA_AB_16X16_FP8 = auto()
+  FMT_WMMA_AB_16X16_IU4 = auto()
+  FMT_WMMA_AB_16X16_IU8 = auto()
+  FMT_WMMA_AB_16X32_BF16 = auto()
+  FMT_WMMA_AB_16X32_BF8 = auto()
+  FMT_WMMA_AB_16X32_F16 = auto()
+  FMT_WMMA_AB_16X32_FP8 = auto()
+  FMT_WMMA_AB_16X32_IU4 = auto()
+  FMT_WMMA_AB_16X32_IU8 = auto()
+  FMT_WMMA_AB_16X64_IU4 = auto()
+  FMT_WMMA_AB_BF16 = auto()
+  FMT_WMMA_AB_F16 = auto()
+  FMT_WMMA_AB_IU4 = auto()
+  FMT_WMMA_AB_IU8 = auto()
+  FMT_WMMA_DC_16X16_BF16 = auto()
+  FMT_WMMA_DC_16X16_F16 = auto()
+  FMT_WMMA_DC_16X16_F32 = auto()
+  FMT_WMMA_DC_16X16_I32 = auto()
+  FMT_WMMA_DC_BF16 = auto()
+  FMT_WMMA_DC_F16 = auto()
+  FMT_WMMA_DC_F32 = auto()
+  FMT_WMMA_DC_I32 = auto()
+  FMT_WMMA_INDEX_SET = auto()
+
+FMT_BITS = {
+  Fmt.FMT_ANY: 1,
+  Fmt.FMT_BUF: 64,
+  Fmt.FMT_IMG: 256,
+  Fmt.FMT_IMG_BVH: 128,
+  Fmt.FMT_NUM_B1: 1,
+  Fmt.FMT_NUM_B1024: 1024,
+  Fmt.FMT_NUM_B128: 128,
+  Fmt.FMT_NUM_B16: 16,
+  Fmt.FMT_NUM_B256: 256,
+  Fmt.FMT_NUM_B32: 32,
+  Fmt.FMT_NUM_B512: 512,
+  Fmt.FMT_NUM_B64: 64,
+  Fmt.FMT_NUM_B8: 8,
+  Fmt.FMT_NUM_B96: 96,
+  Fmt.FMT_NUM_BF16: 16,
+  Fmt.FMT_NUM_BF6: 6,
+  Fmt.FMT_NUM_BF8: 8,
+  Fmt.FMT_NUM_F16: 16,
+  Fmt.FMT_NUM_F32: 32,
+  Fmt.FMT_NUM_F64: 64,
+  Fmt.FMT_NUM_FP4: 4,
+  Fmt.FMT_NUM_FP6: 6,
+  Fmt.FMT_NUM_FP8: 8,
+  Fmt.FMT_NUM_I16: 16,
+  Fmt.FMT_NUM_I24: 24,
+  Fmt.FMT_NUM_I32: 32,
+  Fmt.FMT_NUM_I4: 4,
+  Fmt.FMT_NUM_I64: 64,
+  Fmt.FMT_NUM_I8: 8,
+  Fmt.FMT_NUM_IU4: 4,
+  Fmt.FMT_NUM_IU8: 8,
+  Fmt.FMT_NUM_M64: 64,
+  Fmt.FMT_NUM_PK16_BF16: 256,
+  Fmt.FMT_NUM_PK16_BF8: 128,
+  Fmt.FMT_NUM_PK16_F16: 256,
+  Fmt.FMT_NUM_PK16_F32: 512,
+  Fmt.FMT_NUM_PK16_FP8: 128,
+  Fmt.FMT_NUM_PK16_I32: 512,
+  Fmt.FMT_NUM_PK16_I8: 128,
+  Fmt.FMT_NUM_PK2_B16: 32,
+  Fmt.FMT_NUM_PK2_B32: 64,
+  Fmt.FMT_NUM_PK2_B64: 128,
+  Fmt.FMT_NUM_PK2_BF16: 32,
+  Fmt.FMT_NUM_PK2_BF8: 16,
+  Fmt.FMT_NUM_PK2_F16: 32,
+  Fmt.FMT_NUM_PK2_F32: 64,
+  Fmt.FMT_NUM_PK2_FP4: 8,
+  Fmt.FMT_NUM_PK2_FP8: 16,
+  Fmt.FMT_NUM_PK2_I16: 32,
+  Fmt.FMT_NUM_PK2_I8: 16,
+  Fmt.FMT_NUM_PK2_U16: 32,
+  Fmt.FMT_NUM_PK2_U8: 16,
+  Fmt.FMT_NUM_PK32_BF16: 512,
+  Fmt.FMT_NUM_PK32_BF6: 192,
+  Fmt.FMT_NUM_PK32_BF8: 256,
+  Fmt.FMT_NUM_PK32_F16: 512,
+  Fmt.FMT_NUM_PK32_F32: 1024,
+  Fmt.FMT_NUM_PK32_FP6: 192,
+  Fmt.FMT_NUM_PK32_FP8: 256,
+  Fmt.FMT_NUM_PK32_I32: 1024,
+  Fmt.FMT_NUM_PK32_I8: 256,
+  Fmt.FMT_NUM_PK4_B8: 32,
+  Fmt.FMT_NUM_PK4_BF16: 64,
+  Fmt.FMT_NUM_PK4_BF8: 32,
+  Fmt.FMT_NUM_PK4_F16: 64,
+  Fmt.FMT_NUM_PK4_F32: 128,
+  Fmt.FMT_NUM_PK4_F64: 256,
+  Fmt.FMT_NUM_PK4_FP8: 32,
+  Fmt.FMT_NUM_PK4_I32: 128,
+  Fmt.FMT_NUM_PK4_I8: 32,
+  Fmt.FMT_NUM_PK4_IU8: 32,
+  Fmt.FMT_NUM_PK4_U8: 32,
+  Fmt.FMT_NUM_PK8_B32: 256,
+  Fmt.FMT_NUM_PK8_BF16: 128,
+  Fmt.FMT_NUM_PK8_BF8: 64,
+  Fmt.FMT_NUM_PK8_F16: 128,
+  Fmt.FMT_NUM_PK8_FP8: 64,
+  Fmt.FMT_NUM_PK8_I4: 32,
+  Fmt.FMT_NUM_PK8_I8: 64,
+  Fmt.FMT_NUM_PK8_IU4: 32,
+  Fmt.FMT_NUM_PK8_U4: 32,
+  Fmt.FMT_NUM_PK8_U8: 64,
+  Fmt.FMT_NUM_PK_F16: 32,
+  Fmt.FMT_NUM_PK_I16: 32,
+  Fmt.FMT_NUM_PK_I8: 32,
+  Fmt.FMT_NUM_PK_U16: 32,
+  Fmt.FMT_NUM_PK_U8: 32,
+  Fmt.FMT_NUM_U16: 16,
+  Fmt.FMT_NUM_U24: 24,
+  Fmt.FMT_NUM_U32: 32,
+  Fmt.FMT_NUM_U4: 4,
+  Fmt.FMT_NUM_U64: 64,
+  Fmt.FMT_NUM_U8: 8,
+  Fmt.FMT_RSRC: 128,
+  Fmt.FMT_RSRC_SCALAR: 128,
+  Fmt.FMT_RSRC_SCRATCH: 128,
+  Fmt.FMT_RSRC_SCRATCH_BYTE: 128,
+  Fmt.FMT_RSRC_SCRATCH_STRIDE: 128,
+  Fmt.FMT_RSRC_TYPED: 128,
+  Fmt.FMT_RSRC_TYPED_BYTE: 128,
+  Fmt.FMT_RSRC_TYPED_SCRATCH: 128,
+  Fmt.FMT_RSRC_TYPED_STRIDE: 128,
+  Fmt.FMT_RSRC_VECTOR: 128,
+  Fmt.FMT_RSRC_VECTOR_BYTE: 128,
+  Fmt.FMT_RSRC_VECTOR_STRIDE: 128,
+  Fmt.FMT_SAMP: 128,
+  Fmt.FMT_WMMA_AB_16X16_BF16: 128,
+  Fmt.FMT_WMMA_AB_16X16_BF8: 64,
+  Fmt.FMT_WMMA_AB_16X16_F16: 128,
+  Fmt.FMT_WMMA_AB_16X16_FP8: 64,
+  Fmt.FMT_WMMA_AB_16X16_IU4: 32,
+  Fmt.FMT_WMMA_AB_16X16_IU8: 64,
+  Fmt.FMT_WMMA_AB_16X32_BF16: 256,
+  Fmt.FMT_WMMA_AB_16X32_BF8: 128,
+  Fmt.FMT_WMMA_AB_16X32_F16: 256,
+  Fmt.FMT_WMMA_AB_16X32_FP8: 128,
+  Fmt.FMT_WMMA_AB_16X32_IU4: 64,
+  Fmt.FMT_WMMA_AB_16X32_IU8: 128,
+  Fmt.FMT_WMMA_AB_16X64_IU4: 128,
+  Fmt.FMT_WMMA_AB_BF16: 256,
+  Fmt.FMT_WMMA_AB_F16: 256,
+  Fmt.FMT_WMMA_AB_IU4: 64,
+  Fmt.FMT_WMMA_AB_IU8: 128,
+  Fmt.FMT_WMMA_DC_16X16_BF16: 128,
+  Fmt.FMT_WMMA_DC_16X16_F16: 128,
+  Fmt.FMT_WMMA_DC_16X16_F32: 256,
+  Fmt.FMT_WMMA_DC_16X16_I32: 256,
+  Fmt.FMT_WMMA_DC_BF16: 256,
+  Fmt.FMT_WMMA_DC_F16: 256,
+  Fmt.FMT_WMMA_DC_F32: 256,
+  Fmt.FMT_WMMA_DC_I32: 256,
+  Fmt.FMT_WMMA_INDEX_SET: 32,
+}
+
+class OpType(Enum):
+  OPR_ACCVGPR = auto()
+  OPR_ATTR = auto()
+  OPR_CLAUSE = auto()
+  OPR_DELAY = auto()
+  OPR_EXEC = auto()
+  OPR_HWREG = auto()
+  OPR_LABEL = auto()
+  OPR_SDST = auto()
+  OPR_SDST_NULL = auto()
+  OPR_SENDMSG = auto()
+  OPR_SENDMSG_RTN = auto()
+  OPR_SIMM16 = auto()
+  OPR_SIMM24 = auto()
+  OPR_SIMM4 = auto()
+  OPR_SIMM5 = auto()
+  OPR_SIMM8 = auto()
+  OPR_SLEEP = auto()
+  OPR_SMEM_OFFSET = auto()
+  OPR_SMEM_OFFSET_NOK = auto()
+  OPR_SRC = auto()
+  OPR_SRC_ACCVGPR = auto()
+  OPR_SRC_NOLDS = auto()
+  OPR_SRC_NOLIT = auto()
+  OPR_SRC_SIMPLE = auto()
+  OPR_SRC_VGPR = auto()
+  OPR_SRC_VGPR_OR_ACCVGPR = auto()
+  OPR_SRC_VGPR_OR_ACCVGPR_OR_CONST = auto()
+  OPR_SRC_VGPR_OR_INLINE = auto()
+  OPR_SREG = auto()
+  OPR_SREG_LITERAL = auto()
+  OPR_SREG_M0 = auto()
+  OPR_SREG_M0_INL = auto()
+  OPR_SREG_NOVCC = auto()
+  OPR_SSRC = auto()
+  OPR_SSRC_BARRIER_ID = auto()
+  OPR_SSRC_LANESEL = auto()
+  OPR_SSRC_NOLIT = auto()
+  OPR_TGT = auto()
+  OPR_VERSION = auto()
+  OPR_VGPR = auto()
+  OPR_VGPR_OR_ACCVGPR = auto()
+  OPR_VGPR_OR_LDS = auto()
+  OPR_WAITCNT = auto()
+  OPR_WAITCNT_DEPCTR = auto()
+  OPR_WAIT_ALU = auto()
+  OPR_WAIT_EVENT = auto()
+  OPR_WAIT_MEM_DS = auto()
@@ -0,0 +1,907 @@
+# RDNA3/RDNA4/CDNA disassembler
+from __future__ import annotations
+import re, struct
+from typing import Callable
+from extra.assembly.amd.dsl import Inst, Reg
+
+# Special register mappings for disassembly
+SPECIAL_GPRS = {106: 'vcc_lo', 107: 'vcc_hi', 124: 'null', 125: 'm0', 126: 'exec_lo', 127: 'exec_hi',
+                128: '0', 240: '0.5', 241: '-0.5', 242: '1.0', 243: '-1.0', 244: '2.0', 245: '-2.0', 246: '4.0', 247: '-4.0', 248: '0x3e22f983', 253: 'scc'}
+SPECIAL_GPRS_CDNA = {106: 'vcc_lo', 107: 'vcc_hi', 124: 'm0', 126: 'exec_lo', 127: 'exec_hi',
+                     128: '0', 240: '0.5', 241: '-0.5', 242: '1.0', 243: '-1.0', 244: '2.0', 245: '-2.0', 246: '4.0', 247: '-4.0', 248: '0x3e22f983', 253: 'scc',
+                     102: 'flat_scratch_lo', 103: 'flat_scratch_hi', 104: 'xnack_mask_lo', 105: 'xnack_mask_hi',
+                     251: 'src_vccz', 252: 'src_execz'}
+SPECIAL_PAIRS = {106: 'vcc', 126: 'exec'}
+SPECIAL_PAIRS_CDNA = {106: 'vcc', 126: 'exec', 102: 'flat_scratch', 104: 'xnack_mask'}
+
+def decode_src(v, cdna: bool = False) -> str:
+  """Decode a source operand encoding to its string representation."""
+  v = _unwrap(v)
+  gprs = SPECIAL_GPRS_CDNA if cdna else SPECIAL_GPRS
+  if v in gprs: return gprs[v]
+  if v < 106: return f's{v}'
+  if 108 <= v < 124: return f'ttmp{v - 108}'
+  if 129 <= v <= 192: return str(v - 128)  # positive integers 1-64
+  if 193 <= v <= 208: return str(-(v - 192))  # negative integers -1 to -16
+  if v >= 256: return f'v{v - 256}'
+  return f's{v}'
+
+def _unwrap(v) -> int:
+  """Unwrap Reg to int offset, or return int as-is."""
+  return v.offset if isinstance(v, Reg) else v
+
+def _vi(v) -> int:
+  """Get VGPR index from Reg or int (for v[N] fields that encode as 256+N)."""
+  off = _unwrap(v)
+  return off - 256 if off >= 256 else off
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# LITERAL FORMATTING
+# ═══════════════════════════════════════════════════════════════════════════════
+
+_FLOAT_DEC = {240: 0.5, 241: -0.5, 242: 1.0, 243: -1.0, 244: 2.0, 245: -2.0, 246: 4.0, 247: -4.0}
+
+def _lit(inst, v, neg=0, cdna=None) -> str:
+  """Format literal/inline constant value."""
+  if cdna is None: cdna = _is_cdna(inst)
+  v = _unwrap(v)
+  if v == 255:
+    lit = inst._literal
+    if lit is None: return "0"
+    s = f"0x{lit:x}"
+  elif v in _FLOAT_DEC: s = str(_FLOAT_DEC[v])
+  elif 128 <= v <= 192: s = str(v - 128)
+  elif 193 <= v <= 208: s = str(-(v - 192))
+  elif v < 128: s = decode_src(v, cdna)
+  elif v >= 256: s = f"v{v - 256}"
+  else: s = decode_src(v, cdna)
+  return f"-{s}" if neg else s
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# INSTRUCTION METADATA - fallback functions when inst.num_srcs()/inst.operands unavailable
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _num_srcs(inst) -> int:
+  """Fallback: get number of source operands from instruction name."""
+  name = getattr(inst, 'op_name', '') or ''
+  n = name.upper()
+  # FMAC/MAC ops are 2-source (dst is implicit accumulator), but FMA/MAD ops are 3-source
+  if 'FMAC' in n or 'V_MAC_' in n: return 2
+  if any(x in n for x in ('FMA', 'MAD', 'CNDMASK', 'BFE', 'BFI', 'LERP', 'MED3', 'SAD', 'DIV_FMAS', 'DIV_FIXUP', 'DIV_SCALE', 'CUBE')): return 3
+  # PERMLANE_VAR ops are 2-source, but PERMLANE (non-VAR) are 3-source
+  if 'PERMLANE' in n and '_VAR' not in n: return 3
+  if any(x in n for x in ('_ADD3', '_LSHL_ADD', '_ADD_LSHL', '_LSHL_OR', '_AND_OR', 'OR3_B32', 'AND_OR_B32', 'ALIGNBIT', 'ALIGNBYTE', 'V_PERM_', 'XOR3', 'XAD', 'MULLIT', 'MINMAX', 'MAXMIN', 'MINIMUMMAXIMUM', 'MAXIMUMMINIMUM', 'MINIMUM3', 'MAXIMUM3', 'MIN3', 'MAX3', 'DOT2', 'CVT_PK_U8_F32', 'DOT4', 'DOT8', 'WMMA', 'SWMMAC')): return 3
+  return 2
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# IMPORTS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+from extra.assembly.amd.autogen.rdna3.ins import (VOP1, VOP1_SDST, VOP1_SDST_LIT, VOP1_LIT, VOP2, VOP2_LIT, VOP3, VOP3_SDST, VOP3_SDST_LIT,
+  VOP3_LIT, VOP3SD, VOP3SD_LIT, VOP3P, VOP3P_LIT, VOPC, VOPC_LIT, VOPD, VOPD_LIT, VINTERP, SOP1, SOP1_LIT, SOP2, SOP2_LIT, SOPC, SOPC_LIT,
+  SOPK, SOPK_LIT, SOPP, SMEM, DS, FLAT, GLOBAL, SCRATCH, VOP2Op, VOPDOp, SOPPOp, HWREG, MSG)
+from extra.assembly.amd.autogen.rdna4.ins import (VOP1 as R4_VOP1, VOP1_SDST as R4_VOP1_SDST, VOP1_SDST_LIT as R4_VOP1_SDST_LIT, VOP1_LIT as R4_VOP1_LIT,
+  VOP2 as R4_VOP2, VOP2_LIT as R4_VOP2_LIT, VOP3 as R4_VOP3, VOP3_SDST as R4_VOP3_SDST, VOP3_SDST_LIT as R4_VOP3_SDST_LIT, VOP3_LIT as R4_VOP3_LIT,
+  VOP3SD as R4_VOP3SD, VOP3SD_LIT as R4_VOP3SD_LIT, VOP3P as R4_VOP3P, VOP3P_LIT as R4_VOP3P_LIT, VOPC as R4_VOPC, VOPC_LIT as R4_VOPC_LIT,
+  VOPD as R4_VOPD, VOPD_LIT as R4_VOPD_LIT, VINTERP as R4_VINTERP, SOP1 as R4_SOP1, SOP1_LIT as R4_SOP1_LIT, SOP2 as R4_SOP2, SOP2_LIT as R4_SOP2_LIT,
+  SOPC as R4_SOPC, SOPC_LIT as R4_SOPC_LIT, SOPK as R4_SOPK, SOPK_LIT as R4_SOPK_LIT, SOPP as R4_SOPP, SMEM as R4_SMEM, DS as R4_DS,
+  VOPDOp as R4_VOPDOp, HWREG as HWREG_RDNA4, VFLAT as R4_FLAT, VGLOBAL as R4_GLOBAL, VSCRATCH as R4_SCRATCH)
+from extra.assembly.amd.autogen.cdna.ins import FLAT as C_FLAT, HWREG as HWREG_CDNA
+
+def _is_cdna(inst: Inst) -> bool: return 'cdna' in inst.__class__.__module__
+def _is_r4(inst: Inst) -> bool: return 'rdna4' in inst.__class__.__module__
+
+# CDNA opcode name aliases for disasm (new name -> old name expected by tests)
+_CDNA_DISASM_ALIASES = {'v_fmac_f64': 'v_mul_legacy_f32', 'v_dot2c_f32_bf16': 'v_mac_f32', 'v_fmamk_f32': 'v_madmk_f32', 'v_fmaak_f32': 'v_madak_f32'}
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# HELPERS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _reg(p: str, b: int, n: int = 1) -> str: return f"{p}{_unwrap(b)}" if n == 1 else f"{p}[{_unwrap(b)}:{_unwrap(b)+n-1}]"
+def _sreg(b: int, n: int = 1) -> str: return _reg("s", _unwrap(b), n)
+def _vreg(b: int, n: int = 1) -> str: b = _unwrap(b); return _reg("v", b - 256 if b >= 256 else b, n)
+def _areg(b: int, n: int = 1) -> str: b = _unwrap(b); return _reg("a", b - 256 if b >= 256 else b, n)  # accumulator registers for GFX90a
+def _ttmp(b, n: int = 1) -> str | None: b = _unwrap(b); return _reg("ttmp", b - 108, n) if 108 <= b <= 123 else None
+
+def _fmt_sdst(v, n: int = 1, cdna: bool = False) -> str:
+  v = _unwrap(v)
+  if t := _ttmp(v, n): return t
+  pairs = SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS
+  gprs = SPECIAL_GPRS_CDNA if cdna else SPECIAL_GPRS
+  if n > 1: return pairs.get(v) or gprs.get(v) or _sreg(v, n)  # also check gprs for null/m0
+  return gprs.get(v, f"s{v}")
+
+def _fmt_src(v, n: int = 1, cdna: bool = False) -> str:
+  v = _unwrap(v)
+  if v == 253: return "src_scc"  # SCC as source operand
+  if n == 1: return decode_src(v, cdna)
+  if v >= 256: return _vreg(v, n)
+  if v <= 101: return _sreg(v, n)  # s0-s101 can be pairs, but 102+ are special on CDNA
+  pairs = SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS
+  if n == 2 and v in pairs: return pairs[v]
+  if v <= 105: return _sreg(v, n)  # s102-s105 regular pairs for RDNA
+  if t := _ttmp(v, n): return t
+  return decode_src(v, cdna)
+
+def _fmt_v16(v, base: int = 256, hi_thresh: int = 384) -> str:
+  v = _unwrap(v)
+  return f"v{(v - base) & 0x7f}.{'h' if v >= hi_thresh else 'l'}"
+
+def _has(op: str, *subs) -> bool: return any(s in op for s in subs)
+def _omod(v: int) -> str: return {1: " mul:2", 2: " mul:4", 3: " div:2"}.get(v, "")
+def _src16(inst, v: int) -> str: v = _unwrap(v); return _fmt_v16(v) if v >= 256 else _lit(inst, v)  # format 16-bit src: vgpr.h/l or literal
+def _mods(*pairs) -> str: return " ".join(m for c, m in pairs if c)
+def _fmt_bits(label: str, val: int, count: int) -> str: return f"{label}:[{','.join(str((val >> i) & 1) for i in range(count))}]"
+
+def _vop3_src(inst, v: int, neg: int, abs_: int, hi: int, n: int, f16: bool) -> str:
+  """Format VOP3 source operand with modifiers."""
+  v = _unwrap(v)
+  if v == 255: s = _lit(inst, v)  # literal constant takes priority
+  elif n > 1: s = _fmt_src(v, n)
+  elif f16 and v >= 256: s = f"v{v - 256}.h" if hi else f"v{v - 256}.l"
+  elif v == 253: s = "src_scc"  # VOP3 sources use src_scc not scc
+  else: s = _lit(inst, v)
+  if abs_: s = f"|{s}|"
+  return f"-{s}" if neg else s
+
+def _opsel_str(opsel: int, n: int, need: bool, is16_d: bool) -> str:
+  """Format op_sel modifier string."""
+  if not need: return ""
+  dst_hi = (opsel >> 3) & 1
+  if n == 1: return f" op_sel:[{opsel & 1},{dst_hi}]"
+  # Use 4-element format if bit 2 is set (src2 selection used) or if 3+ sources
+  if n == 2 and not ((opsel >> 2) & 1): return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{dst_hi}]"
+  return f" op_sel:[{opsel & 1},{(opsel >> 1) & 1},{(opsel >> 2) & 1},{dst_hi}]"
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# DISASSEMBLER
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _disasm_vop1(inst: VOP1) -> str:
+  name, cdna = inst.op_name.lower() or f'vop1_op_{inst.op}', _is_cdna(inst)
+  name = name.replace('_e32', '')  # Strip _e32 suffix
+  if any(x in name for x in ('v_nop', 'v_pipeflush', 'v_clrexcp')): return name  # no operands
+  if 'readfirstlane' in name:
+    src = inst.src0.fmt() if inst.src0.offset >= 256 else decode_src(inst.src0.offset, cdna)
+    vdst_off = inst.vdst.offset - 256 if inst.vdst.offset >= 256 else inst.vdst.offset
+    return f"{name} {_fmt_sdst(vdst_off, 1, cdna)}, {src}"
+  bits = inst.canonical_op_bits
+  is16_dst, is16_src = not cdna and bits['d'] == 16, not cdna and bits['s0'] == 16
+  # Format dst
+  if is16_dst: dst = _fmt_v16(inst.vdst)
+  else: dst = inst.vdst.fmt()
+  # Format src
+  if inst.src0.offset == 255: src = _lit(inst, inst.src0)
+  elif is16_src and inst.src0.offset >= 256: src = _fmt_v16(inst.src0)
+  elif inst.src0.sz > 1: src = _fmt_src(inst.src0, inst.src0.sz, cdna)
+  else: src = _lit(inst, inst.src0)
+  return f"{name} {dst}, {src}"
+
+_VOP2_CARRY_OUT = {'v_add_co_u32', 'v_sub_co_u32', 'v_subrev_co_u32'}  # carry out only
+_VOP2_CARRY_INOUT = {'v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'}  # carry in and out (CDNA)
+_VOP2_CARRY_INOUT_RDNA = {'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'}  # carry in and out (RDNA)
+def _disasm_vop2(inst: VOP2) -> str:
+  name, cdna = inst.op_name.lower(), _is_cdna(inst)
+  if cdna: name = _CDNA_DISASM_ALIASES.get(name, name)  # apply CDNA aliases
+  suf = "" if cdna or name.endswith('_e32') or (not cdna and inst.op == VOP2Op.V_DOT2ACC_F32_F16_E32) else "_e32"
+  lit = inst._literal
+  is16 = not cdna and inst.canonical_op_bits['d'] == 16
+  # fmaak/madak: dst = src0 * vsrc1 + K, fmamk/madmk: dst = src0 * K + vsrc1
+  if 'fmaak' in name or 'madak' in name or (not cdna and inst.op in (VOP2Op.V_FMAAK_F32_E32, VOP2Op.V_FMAAK_F16_E32)):
+    if lit is None: return f"op_{inst.op.value if hasattr(inst.op, 'value') else inst.op}"
+    if is16: return f"{name}{suf} {_fmt_v16(inst.vdst)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1)}, 0x{lit:x}"
+    return f"{name}{suf} {inst.vdst.fmt()}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}, 0x{lit:x}"
+  if 'fmamk' in name or 'madmk' in name or (not cdna and inst.op in (VOP2Op.V_FMAMK_F32_E32, VOP2Op.V_FMAMK_F16_E32)):
+    if lit is None: return f"op_{inst.op.value if hasattr(inst.op, 'value') else inst.op}"
+    if is16: return f"{name}{suf} {_fmt_v16(inst.vdst)}, {_src16(inst, inst.src0)}, 0x{lit:x}, {_fmt_v16(inst.vsrc1)}"
+    return f"{name}{suf} {inst.vdst.fmt()}, {_lit(inst, inst.src0)}, 0x{lit:x}, {inst.vsrc1.fmt()}"
+  if is16: return f"{name}{suf} {_fmt_v16(inst.vdst)}, {_src16(inst, inst.src0)}, {_fmt_v16(inst.vsrc1)}"
+  vcc = "vcc" if cdna else "vcc_lo"
+  basename = name.replace('_e32', '')
+  if cdna and basename in _VOP2_CARRY_OUT: return f"{name}{suf} {inst.vdst.fmt()}, {vcc}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}"
+  if cdna and basename in _VOP2_CARRY_INOUT: return f"{name}{suf} {inst.vdst.fmt()}, {vcc}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}, {vcc}"
+  if not cdna and basename in _VOP2_CARRY_INOUT_RDNA: return f"{name}{suf} {inst.vdst.fmt()}, {vcc}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}, {vcc}"
+  sn0 = inst.canonical_op_regs.get('s0', 1)
+  if inst.vdst.sz > 1 or sn0 > 1 or inst.vsrc1.sz > 1:
+    src0 = _lit(inst, inst.src0) if inst.src0.offset == 255 else _fmt_src(inst.src0, sn0, cdna)
+    return f"{name.replace('_e32', '')} {inst.vdst.fmt()}, {src0}, {inst.vsrc1.fmt()}"
+  return f"{name}{suf} {inst.vdst.fmt()}, {_lit(inst, inst.src0)}, {inst.vsrc1.fmt()}" + (f", {vcc}" if name == 'v_cndmask_b32' else "")
+
+def _disasm_vopc(inst: VOPC) -> str:
+  name, cdna = inst.op_name.lower(), _is_cdna(inst)
+  bits = inst.canonical_op_bits
+  is16 = bits['s0'] == 16
+  if cdna:
+    s0 = _lit(inst, inst.src0) if inst.src0.offset == 255 else _fmt_src(inst.src0, inst.src0.sz, cdna)
+    return f"{name} vcc, {s0}, {inst.vsrc1.fmt()}"  # CDNA VOPC always outputs vcc
+  # RDNA: v_cmpx_* writes to exec (no vcc), v_cmp_* writes to vcc_lo
+  has_vcc = 'cmpx' not in name
+  s0 = _lit(inst, inst.src0) if inst.src0.offset == 255 else inst.src0.fmt() if inst.src0.sz > 1 else _src16(inst, inst.src0.offset) if is16 else _lit(inst, inst.src0)
+  s1 = inst.vsrc1.fmt() if inst.vsrc1.sz > 1 else _fmt_v16(inst.vsrc1) if is16 else inst.vsrc1.fmt()
+  suf = "" if name.endswith('_e32') else "_e32"
+  return f"{name}{suf} vcc_lo, {s0}, {s1}" if has_vcc else f"{name}{suf} {s0}, {s1}"
+
+NO_ARG_SOPP = {SOPPOp.S_BARRIER, SOPPOp.S_WAKEUP, SOPPOp.S_ICACHE_INV,
+               SOPPOp.S_WAIT_IDLE, SOPPOp.S_ENDPGM_SAVED, SOPPOp.S_CODE_END, SOPPOp.S_ENDPGM_ORDERED_PS_DONE, SOPPOp.S_TTRACEDATA}
+
+def _disasm_sopp(inst: SOPP) -> str:
+  name, cdna = inst.op_name.lower(), _is_cdna(inst)
+  is_rdna4 = _is_r4(inst)
+  # Ops that have no argument when simm16 == 0
+  no_arg_zero = {'s_barrier', 's_wakeup', 's_icache_inv', 's_ttracedata', 's_wait_idle', 's_endpgm_saved',
+                 's_endpgm_ordered_ps_done', 's_code_end'}
+  if name in no_arg_zero: return name if inst.simm16 == 0 else f"{name} {inst.simm16}"
+  if name == 's_endpgm': return name if inst.simm16 == 0 else f"{name} {inst.simm16}"
+  if cdna:
+    if name == 's_waitcnt':
+      # GFX9 format: vmcnt[3:0]=bits[3:0], vmcnt[5:4]=bits[15:14], expcnt=bits[6:4], lgkmcnt=bits[11:8] (4 bits, max 15)
+      vm_lo, exp, lgkm, vm_hi = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 8) & 0xf, (inst.simm16 >> 14) & 0x3
+      vm = vm_lo | (vm_hi << 4)
+      p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0xf else ""]
+      return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
+    if name.startswith(('s_cbranch', 's_branch')): return f"{name} {inst.simm16}"
+    if name == 's_set_gpr_idx_mode':
+      flags = [n for i, n in enumerate(['SRC0', 'SRC1', 'SRC2', 'DST']) if inst.simm16 & (1 << i)]
+      return f"{name} gpr_idx({','.join(flags)})"
+    return f"{name} 0x{inst.simm16:x}" if inst.simm16 else name
+  # RDNA (use name-based checks instead of enum-based for cross-arch compatibility)
+  if name == 's_waitcnt':
+    if is_rdna4:
+      return f"{name} {inst.simm16}" if inst.simm16 else f"{name} 0"
+    vm, exp, lgkm = (inst.simm16 >> 10) & 0x3f, inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x3f
+    p = [f"vmcnt({vm})" if vm != 0x3f else "", f"expcnt({exp})" if exp != 7 else "", f"lgkmcnt({lgkm})" if lgkm != 0x3f else ""]
+    return f"s_waitcnt {' '.join(x for x in p if x) or '0'}"
+  if name == 's_delay_alu':
+    deps = ['VALU_DEP_1','VALU_DEP_2','VALU_DEP_3','VALU_DEP_4','TRANS32_DEP_1','TRANS32_DEP_2','TRANS32_DEP_3','FMA_ACCUM_CYCLE_1','SALU_CYCLE_1','SALU_CYCLE_2','SALU_CYCLE_3']
+    skips = ['SAME','NEXT','SKIP_1','SKIP_2','SKIP_3','SKIP_4']
+    id0, skip, id1 = inst.simm16 & 0xf, (inst.simm16 >> 4) & 0x7, (inst.simm16 >> 7) & 0xf
+    dep = lambda v: deps[v-1] if 0 < v <= len(deps) else str(v)
+    p = [f"instid0({dep(id0)})" if id0 else "", f"instskip({skips[skip]})" if skip else "", f"instid1({dep(id1)})" if id1 else ""]
+    return f"s_delay_alu {' | '.join(x for x in p if x) or '0'}"
+  if name.startswith(('s_cbranch', 's_branch')): return f"{name} {inst.simm16}"
+  return f"{name} 0x{inst.simm16:x}"
+
+def _disasm_smem(inst: SMEM) -> str:
+  name, cdna = inst.op_name.lower(), _is_cdna(inst)
+  if name in ('s_gl1_inv', 's_dcache_inv', 's_dcache_inv_vol', 's_dcache_wb', 's_dcache_wb_vol', 's_icache_inv'): return name
+  soe, imm = getattr(inst, 'soe', 0) or getattr(inst, 'soffset_en', 0), getattr(inst, 'imm', 1)
+  is_rdna4 = _is_r4(inst)
+  offset = inst.ioffset if is_rdna4 else getattr(inst, 'offset', 0)
+  if cdna:
+    if soe and imm: off_s = f"{decode_src(inst.soffset, cdna)} offset:0x{offset:x}"
+    elif imm: off_s = f"0x{offset:x}"
+    elif offset < 256: off_s = decode_src(offset, cdna)
+    else: off_s = decode_src(inst.soffset, cdna)
+  elif offset and inst.soffset != 124: off_s = f"{decode_src(inst.soffset, cdna)} offset:0x{offset:x}"
+  elif offset: off_s = f"0x{offset:x}"
+  else: off_s = decode_src(inst.soffset, cdna)
+  is_buffer = 'buffer' in name or 's_atc_probe_buffer' == name
+  sbase_idx, sbase_count = _unwrap(inst.sbase), 4 if is_buffer else 2
+  sbase_str = _fmt_src(sbase_idx, sbase_count, cdna) if sbase_count == 2 else _sreg(sbase_idx, sbase_count) if sbase_idx <= 105 else _reg("ttmp", sbase_idx - 108, sbase_count)
+  if name in ('s_atc_probe', 's_atc_probe_buffer'): return f"{name} {_unwrap(inst.sdata)}, {sbase_str}, {off_s}"
+  if 'prefetch' in name:
+    off = getattr(inst, 'ioffset', getattr(inst, 'offset', 0))
+    if off >= 0x800000: off = off - 0x1000000
+    off_s = f"0x{off:x}" if off > 255 else str(off)
+    soff_s = decode_src(inst.soffset, cdna) if inst.soffset != 124 else ("m0" if cdna else "null")
+    if 'pc_rel' in name: return f"{name} {off_s}, {soff_s}, {_unwrap(inst.sdata)}"
+    return f"{name} {sbase_str}, {off_s}, {soff_s}, {_unwrap(inst.sdata)}"
+  # Use get_field_bits for register count
+  dst_n = inst.canonical_op_regs.get('d', 1)
+  th, scope = getattr(inst, 'th', 0), getattr(inst, 'scope', 0)
+  if is_rdna4:  # RDNA4 uses th/scope instead of glc/dlc
+    th_names = ['TH_LOAD_RT', 'TH_LOAD_NT', 'TH_LOAD_HT', 'TH_LOAD_LU']
+    scope_names = ['SCOPE_CU', 'SCOPE_SE', 'SCOPE_DEV', 'SCOPE_SYS']
+    mods = (f" th:{th_names[th]}" if th else "") + (f" scope:{scope_names[scope]}" if scope else "")
+    return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}, {sbase_str}, {off_s}{mods}"
+  if th or scope:
+    th_names = ['TH_LOAD_RT', 'TH_LOAD_NT', 'TH_LOAD_HT', 'TH_LOAD_LU']
+    scope_names = ['SCOPE_CU', 'SCOPE_SE', 'SCOPE_DEV', 'SCOPE_SYS']
+    mods = (f" th:{th_names[th]}" if th else "") + (f" scope:{scope_names[scope]}" if scope else "")
+    return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}, {sbase_str}, {off_s}{mods}"
+  if 'discard' in name: return f"{name} {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (getattr(inst, 'dlc', 0), " dlc"))
+  if name in ('s_memrealtime', 's_memtime'): return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}"
+  return f"{name} {_fmt_sdst(inst.sdata, dst_n, cdna)}, {sbase_str}, {off_s}" + _mods((inst.glc, " glc"), (getattr(inst, 'dlc', 0), " dlc"))
+
+def _disasm_flat(inst: FLAT) -> str:
+  name, cdna, r4 = inst.op_name.lower(), _is_cdna(inst), _is_r4(inst)
+  acc = getattr(inst, 'acc', 0)
+  reg_fn = _areg if acc else _vreg
+  if r4: seg = 'flat' if (cls_name:=inst.__class__.__name__) == 'VFLAT' else ('global' if cls_name == 'VGLOBAL' else 'scratch')
+  else: seg = ['flat', 'scratch', 'global'][inst.seg] if inst.seg < 3 else 'flat'
+  instr = f"{seg}_{name.split('_', 1)[1] if '_' in name else name}"
+  # Global/scratch uses 13-bit signed offset
+  offset = inst.ioffset if r4 else inst.offset
+  if seg != 'flat':
+    if cdna:
+      # CDNA: bit 12 is sign bit but not in offset field
+      raw = int.from_bytes(inst.to_bytes(), 'little')
+      off_val = offset | ((raw >> 12) & 1) << 12  # get bit 12
+    else:
+      off_val = offset
+    off_val = off_val if off_val < 4096 else off_val - 8192  # sign extend 13-bit
+  else:
+    off_val = offset
+  # Use get_field_bits: data for stores/atomics, d for loads
+  regs = inst.canonical_op_regs
+  w = regs.get('data', regs.get('d', 1)) if 'store' in name or 'atomic' in name else regs.get('d', 1)
+  off_s = f" offset:{off_val}" if off_val else ""
+  if cdna: mods = f"{off_s}{' sc0' if inst.sc0 else ''}{' nt' if inst.nt else ''}{' sc1' if getattr(inst, 'sc1', 0) else ''}"
+  elif r4: mods = f"{off_s}{' scope' if inst.scope else ''}{' th' if inst.th else ''}"
+  else: mods = f"{off_s}{' glc' if inst.glc else ''}{' slc' if inst.slc else ''}{' dlc' if inst.dlc else ''}"
+  if seg == 'flat': saddr_s = ""
+  elif _unwrap(inst.saddr) in (0x7F, 124): saddr_s = ", off"
+  elif seg == 'scratch': saddr_s = f", {decode_src(inst.saddr, cdna)}"
+  elif _unwrap(inst.saddr) in (SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS): saddr_s = f", {(SPECIAL_PAIRS_CDNA if cdna else SPECIAL_PAIRS)[_unwrap(inst.saddr)]}"
+  elif t := _ttmp(inst.saddr, 2): saddr_s = f", {t}"
+  else: saddr_s = f", {_sreg(inst.saddr, 2) if _unwrap(inst.saddr) < 106 else decode_src(_unwrap(inst.saddr), cdna)}"
+  if 'addtid' in name: return f"{instr} {reg_fn(inst.data if 'store' in name else inst.vdst)}{saddr_s}{mods}"
+  # RDNA4: vaddr instead of addr, vsrc instead of data
+  addr = inst.vaddr if r4 else inst.addr
+  data = inst.vsrc if r4 else inst.data
+  # load_lds_* instructions: vaddr, saddr (no vdst, data goes to LDS)
+  if 'load_lds' in name:
+    addr_w = 1 if seg == 'scratch' or (_unwrap(inst.saddr) not in (0x7F, 124)) else 2
+    addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(addr, addr_w)
+    return f"{instr} {addr_s}{saddr_s}{mods}"
+  if seg == 'flat': addr_w = 2  # flat always uses 64-bit vaddr
+  elif cdna: addr_w = 1 if seg == 'scratch' or (_unwrap(inst.saddr) not in (0x7F, 124)) else 2
+  else: addr_w = 1 if seg == 'scratch' or (_unwrap(inst.saddr) not in (0x7F, 124)) else 2
+  addr_s = "off" if not inst.sve and seg == 'scratch' else _vreg(addr, addr_w)
+  data_s, vdst_s = reg_fn(data, w), reg_fn(inst.vdst, w // 2 if 'cmpswap' in name else w)
+  if 'atomic' in name:
+    glc_or_sc0 = inst.sc0 if cdna else inst.glc
+    return f"{instr} {vdst_s}, {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}" if glc_or_sc0 else f"{instr} {addr_s}, {data_s}{saddr_s if seg != 'flat' else ''}{mods}"
+  if 'store' in name: return f"{instr} {addr_s}, {data_s}{saddr_s}{mods}"
+  return f"{instr} {reg_fn(inst.vdst, w)}, {addr_s}{saddr_s}{mods}"
+
+def _disasm_ds(inst: DS) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  acc = getattr(inst, 'acc', 0)
+  reg_fn = _areg if acc else _vreg
+  gds = " gds" if getattr(inst, 'gds', 0) else ""
+  off = f" offset:{inst.offset0 | (inst.offset1 << 8)}" if inst.offset0 or inst.offset1 else ""
+  off2 = (" offset0:" + str(inst.offset0) if inst.offset0 else "") + (" offset1:" + str(inst.offset1) if inst.offset1 else "")
+  # Use get_field_bits: data for stores/writes/atomics, d for loads
+  regs = inst.canonical_op_regs
+  w = regs.get('data', regs.get('d', 1)) if 'store' in name or 'write' in name or ('load' not in name and 'read' not in name) else regs.get('d', 1)
+  d0, d1, dst, addr = reg_fn(inst.data0, w), reg_fn(inst.data1, w), reg_fn(inst.vdst, w), _vreg(inst.addr)
+
+  if name == 'ds_nop': return name
+  if name == 'ds_bvh_stack_rtn_b32': return f"{name} {_vreg(inst.vdst)}, {addr}, {_vreg(inst.data0)}, {_vreg(inst.data1, 4)}{off}{gds}"
+  if 'bvh_stack_push' in name:
+    d1_regs = 8 if 'push8' in name else 4
+    vdst_regs = 2 if 'pop2' in name else 1
+    vdst_s = _vreg(inst.vdst, vdst_regs) if vdst_regs > 1 else _vreg(inst.vdst)
+    return f"{name} {vdst_s}, {addr}, {_vreg(inst.data0)}, {_vreg(inst.data1, d1_regs)}{off}{gds}"
+  if 'gws_sema' in name and 'sema_br' not in name: return f"{name}{off}{gds}"
+  if 'gws_' in name: return f"{name} {addr}{off}{gds}"
+  if name in ('ds_consume', 'ds_append'): return f"{name} {reg_fn(inst.vdst)}{off}{gds}"
+  if 'gs_reg' in name: return f"{name} {reg_fn(inst.vdst, 2)}, {reg_fn(inst.data0)}{off}{gds}"
+  if '2addr' in name:
+    if 'load' in name: return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}{off2}{gds}"
+    if 'store' in name and 'xchg' not in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
+    return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}, {d0}, {d1}{off2}{gds}"
+  if 'write2' in name: return f"{name} {addr}, {d0}, {d1}{off2}{gds}"
+  if 'read2' in name: return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}{off2}{gds}"
+  if 'xchg2' in name: return f"{name} {reg_fn(inst.vdst, regs.get('d', 1))}, {addr}, {d0}, {d1}{off2}{gds}"
+  if 'load' in name or ('read' in name and 'read2' not in name): return f"{name} {reg_fn(inst.vdst)}{off}{gds}" if 'addtid' in name else f"{name} {dst}, {addr}{off}{gds}"
+  if ('store' in name or 'write' in name) and not _has(name, 'cmp', 'xchg', 'write2'):
+    return f"{name} {reg_fn(inst.data0)}{off}{gds}" if 'addtid' in name else f"{name} {addr}, {d0}{off}{gds}"
+  if 'swizzle' in name or name == 'ds_ordered_count': return f"{name} {reg_fn(inst.vdst)}, {addr}{off}{gds}"
+  if 'permute' in name: return f"{name} {reg_fn(inst.vdst)}, {addr}, {reg_fn(inst.data0)}{off}{gds}"
+  if 'condxchg' in name: return f"{name} {reg_fn(inst.vdst, 2)}, {addr}, {reg_fn(inst.data0, 2)}{off}{gds}"
+  if _has(name, 'cmpst', 'mskor', 'wrap'):
+    return f"{name} {dst}, {addr}, {d0}, {d1}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}, {d1}{off}{gds}"
+  return f"{name} {dst}, {addr}, {d0}{off}{gds}" if '_rtn' in name else f"{name} {addr}, {d0}{off}{gds}"
+
+def _disasm_vop3(inst: VOP3) -> str:
+  op, name = inst.op, inst.op_name.lower()
+  n_up = name.upper()
+  bits = inst.canonical_op_bits
+
+  # RDNA4 v_s_* scalar VOP3 instructions - vdst is SGPR (VGPRField adds 256)
+  if name.startswith('v_s_'):
+    src = _lit(inst, inst.src0) if _unwrap(inst.src0) == 255 else ("src_scc" if _unwrap(inst.src0) == 253 else _fmt_src(inst.src0, max(1, bits['s0'] // 32)))
+    if inst.neg & 1: src = f"-{src}"
+    if inst.abs & 1: src = f"|{src}|"
+    clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
+    vdst_raw = _unwrap(inst.vdst)
+    return f"{name} s{vdst_raw - 256 if vdst_raw >= 256 else vdst_raw}, {src}" + (" clamp" if clamp else "") + _omod(inst.omod)
+
+  # Use get_field_bits for register sizes and 16-bit detection
+  r0, r1, r2 = max(1, bits['s0'] // 32), max(1, bits['s1'] // 32), max(1, bits['s2'] // 32)
+  dn = max(1, bits['d'] // 32)
+  is16_d, is16_s, is16_s2 = bits['d'] == 16, bits['s0'] == 16, bits['s2'] == 16
+
+  s0 = _vop3_src(inst, inst.src0, inst.neg&1, inst.abs&1, inst.opsel&1, r0, is16_s)
+  s1 = _vop3_src(inst, inst.src1, inst.neg&2, inst.abs&2, inst.opsel&2, r1, is16_s)
+  s2 = _vop3_src(inst, inst.src2, inst.neg&4, inst.abs&4, inst.opsel&4, r2, is16_s2)
+
+  # Format destination
+  if 'readlane' in name:
+    vdst_off = inst.vdst.offset - 256 if inst.vdst.offset >= 256 else inst.vdst.offset
+    dst = _fmt_sdst(vdst_off, 1)
+  elif is16_d: dst = f"{inst.vdst.fmt()}.h" if (inst.opsel & 8) else f"{inst.vdst.fmt()}.l"
+  else: dst = inst.vdst.fmt()
+
+  clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
+  cl, om = " clamp" if clamp else "", _omod(inst.omod)
+  nonvgpr_opsel = (inst.src0.offset < 256 and (inst.opsel & 1)) or (inst.src1.offset < 256 and (inst.opsel & 2)) or (inst.src2.offset < 256 and (inst.opsel & 4))
+  need_opsel = nonvgpr_opsel or (inst.opsel and not is16_s)
+
+  op_val = inst.op.value if hasattr(inst.op, 'value') else inst.op
+  e64 = "" if name.endswith('_e64') else "_e64"
+  if op_val < 256:  # VOPC
+    vdst_off = inst.vdst.offset - 256 if inst.vdst.offset >= 256 else inst.vdst.offset
+    return f"{name}{e64} {s0}, {s1}{cl}" if name.startswith('v_cmpx') else f"{name}{e64} {_fmt_sdst(vdst_off, 1)}, {s0}, {s1}{cl}"
+  if op_val < 384:  # VOP2
+    n = inst.num_srcs() or 2
+    os = _opsel_str(inst.opsel, n, need_opsel, is16_d)
+    return f"{name}{e64} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name}{e64} {dst}, {s0}, {s1}{os}{cl}{om}"
+  if op_val < 512:  # VOP1
+    if re.match(r'v_cvt_f32_(bf|fp)8', name) and inst.opsel:
+      os = f" byte_sel:{((inst.opsel & 1) << 1) | ((inst.opsel >> 1) & 1)}"
+    else:
+      os = _opsel_str(inst.opsel, 1, need_opsel, is16_d)
+    if 'v_nop' in name or 'v_pipeflush' in name: return f"{name}{e64}"
+    return f"{name}{e64} {dst}, {s0}{os}{cl}{om}"
+  # Native VOP3
+  n = inst.num_srcs() or 2
+  os = f" byte_sel:{inst.opsel >> 2}" if 'cvt_sr' in name and inst.opsel else _opsel_str(inst.opsel, n, need_opsel, is16_d)
+  return f"{name} {dst}, {s0}, {s1}, {s2}{os}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{os}{cl}{om}"
+
+def _disasm_vop3sd(inst: VOP3SD) -> str:
+  name = inst.op_name.lower()
+  def src(reg, neg):
+    s = _lit(inst, reg.offset) if reg.offset == 255 else ("src_scc" if reg.offset == 253 else (reg.fmt() if reg.sz > 1 else _lit(inst, reg.offset)))
+    return f"neg({s})" if neg and reg.offset == 255 else (f"-{s}" if neg else s)
+  s0, s1, s2 = src(inst.src0, inst.neg & 1), src(inst.src1, inst.neg & 2), src(inst.src2, inst.neg & 4)
+  # VOP3SD: _co_ ops (add/sub) without _ci_ have only 2 sources, all others (mad, div_scale, _co_ci_) have 3 sources
+  has_only_two_srcs = '_co_' in name and '_ci_' not in name and 'mad' not in name
+  srcs = f"{s0}, {s1}" if has_only_two_srcs else f"{s0}, {s1}, {s2}"
+  clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
+  return f"{name} {inst.vdst.fmt()}, {_fmt_sdst(inst.sdst, 1)}, {srcs}{' clamp' if clamp else ''}{_omod(inst.omod)}"
+
+def _disasm_vopd(inst: VOPD) -> str:
+  lit = inst._literal
+  op_enum = R4_VOPDOp if _is_r4(inst) else VOPDOp
+  nx, ny = op_enum(inst.opx).name.lower(), op_enum(inst.opy).name.lower()
+  def half(n, vd, s0, vs1):
+    vd, vs1 = _vi(vd), _vi(vs1)
+    if 'mov' in n: return f"{n} v{vd}, {_lit(inst, s0)}"
+    if 'fmamk' in n and lit: return f"{n} v{vd}, {_lit(inst, s0)}, 0x{lit:x}, v{vs1}"
+    if 'fmaak' in n and lit: return f"{n} v{vd}, {_lit(inst, s0)}, v{vs1}, 0x{lit:x}"
+    return f"{n} v{vd}, {_lit(inst, s0)}, v{vs1}"
+  return f"{half(nx, inst.vdstx, inst.srcx0, inst.vsrcx1)} :: {half(ny, inst.vdsty, inst.srcy0, inst.vsrcy1)}"
+
+def _disasm_vop3p(inst: VOP3P) -> str:
+  name = inst.op_name.lower()
+  is_wmma, is_swmmac, n, is_fma_mix = 'wmma' in name, 'swmmac' in name, inst.num_srcs() or 2, 'fma_mix' in name
+  def get_src(reg):
+    return _lit(inst, reg.offset) if reg.offset == 255 else reg.fmt()
+  src0, src1, src2, dst = get_src(inst.src0), get_src(inst.src1), get_src(inst.src2), inst.vdst.fmt()
+  opsel_hi = inst.opsel_hi | (inst.opsel_hi2 << 2)
+  clamp = getattr(inst, 'cm', None) or getattr(inst, 'clmp', 0)
+  if is_fma_mix:
+    def m(s, neg, abs_): return f"-{f'|{s}|' if abs_ else s}" if neg else (f"|{s}|" if abs_ else s)
+    src0, src1, src2 = m(src0, inst.neg & 1, inst.neg_hi & 1), m(src1, inst.neg & 2, inst.neg_hi & 2), m(src2, inst.neg & 4, inst.neg_hi & 4)
+    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi else []) + (["clamp"] if clamp else [])
+  elif is_swmmac:
+    mods = ([f"index_key:{inst.opsel}"] if inst.opsel else []) + ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + \
+           ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if clamp else [])
+  else:
+    opsel_hi_default = 7 if n == 3 else 3
+    mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != opsel_hi_default else []) + \
+           ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if clamp else [])
+  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
+
+def _disasm_sop1(inst: SOP1) -> str:
+  op, name, cdna = inst.op, inst.op_name.lower(), _is_cdna(inst)
+  # Use get_field_bits for register sizes
+  regs = inst.canonical_op_regs
+  dst_regs, src_regs = regs.get('d', 1), regs.get('s0', 1)
+  src = _lit(inst, inst.ssrc0) if _unwrap(inst.ssrc0) == 255 else _fmt_src(inst.ssrc0, src_regs, cdna)
+  if not cdna:
+    if 'getpc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2)}"
+    if 'setpc_b64' in name or 'rfe_b64' in name: return f"{name} {src}"
+    if 'swappc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2)}, {src}"
+    if 'sendmsg_rtn' in name:
+      v = _unwrap(inst.ssrc0)
+      try: msg_str = MSG(v).name if v != 255 else None  # MSG_RTN_ILLEGAL_MSG (255) not supported by LLVM
+      except ValueError: msg_str = None
+      return f"{name} {_fmt_sdst(inst.sdst, dst_regs)}, sendmsg({msg_str})" if msg_str else f"{name} {_fmt_sdst(inst.sdst, dst_regs)}, 0x{v:x}"
+  sop1_src_only = ('S_ALLOC_VGPR', 'S_SLEEP_VAR', 'S_BARRIER_SIGNAL', 'S_BARRIER_SIGNAL_ISFIRST', 'S_BARRIER_INIT', 'S_BARRIER_JOIN', 'S_SET_GPR_IDX_IDX',
+                   'S_CBRANCH_JOIN')
+  if inst.op_name in sop1_src_only: return f"{name} {src}"
+  if cdna:
+    if 'getpc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2, cdna)}"
+    if 'setpc_b64' in name or 'rfe_b64' in name: return f"{name} {src}"
+    if 'swappc_b64' in name: return f"{name} {_fmt_sdst(inst.sdst, 2, cdna)}, {src}"
+  return f"{name} {_fmt_sdst(inst.sdst, dst_regs, cdna)}, {src}"
+
+def _disasm_sop2(inst: SOP2) -> str:
+  cdna, name = _is_cdna(inst), inst.op_name.lower()
+  lit = inst._literal
+  # Use get_field_bits for register sizes
+  regs = inst.canonical_op_regs
+  dn, s0n, s1n = regs['d'], regs['s0'], regs['s1']
+  s0 = _lit(inst, inst.ssrc0) if _unwrap(inst.ssrc0) == 255 else _fmt_src(inst.ssrc0, s0n, cdna)
+  s1 = _lit(inst, inst.ssrc1) if _unwrap(inst.ssrc1) == 255 else _fmt_src(inst.ssrc1, s1n, cdna)
+  dst = _fmt_sdst(inst.sdst, dn, cdna)
+  if 'fmamk' in name and lit is not None: return f"{name} {dst}, {s0}, 0x{lit:x}, {s1}"
+  if 'fmaak' in name and lit is not None: return f"{name} {dst}, {s0}, {s1}, 0x{lit:x}"
+  if name in ('s_cbranch_g_fork', 's_rfe_restore_b64'): return f"{name} {s0}, {s1}"  # no destination
+  return f"{name} {dst}, {s0}, {s1}"
+
+def _disasm_sopc(inst: SOPC) -> str:
+  cdna, regs, name = _is_cdna(inst), inst.canonical_op_regs, inst.op_name.lower()
+  s0 = _lit(inst, inst.ssrc0) if _unwrap(inst.ssrc0) == 255 else _fmt_src(inst.ssrc0, regs['s0'], cdna)
+  if name == 's_set_gpr_idx_on':
+    imm = _unwrap(inst.ssrc1) & 0xf
+    flags = [n for i, n in enumerate(['SRC0', 'SRC1', 'SRC2', 'DST']) if imm & (1 << i)]
+    return f"{name} {s0}, gpr_idx({','.join(flags)})"
+  s1 = _lit(inst, inst.ssrc1) if _unwrap(inst.ssrc1) == 255 else _fmt_src(inst.ssrc1, regs['s1'], cdna)
+  return f"{name} {s0}, {s1}"
+
+_HWREG_BLACKLIST = {'HW_REG_PC_LO', 'HW_REG_PC_HI', 'HW_REG_IB_DBG1', 'HW_REG_FLUSH_IB', 'HW_REG_SHADER_TBA_LO', 'HW_REG_SHADER_TBA_HI',
+                    'HW_REG_SHADER_FLAT_SCRATCH_LO', 'HW_REG_SHADER_FLAT_SCRATCH_HI', 'HW_REG_SHADER_CYCLES'}
+_HWREG_BLACKLIST_CDNA = {'HW_REG_PC_LO', 'HW_REG_PC_HI', 'HW_REG_IB_DBG1', 'HW_REG_FLUSH_IB', 'HW_REG_SQ_SHADER_TBA_LO', 'HW_REG_SQ_SHADER_TBA_HI',
+                         'HW_REG_SQ_SHADER_TMA_LO', 'HW_REG_SQ_SHADER_TMA_HI', 'HW_REG_SQ_PERF_SNAPSHOT_DATA', 'HW_REG_SQ_PERF_SNAPSHOT_DATA1',
+                         'HW_REG_SQ_PERF_SNAPSHOT_PC_LO', 'HW_REG_SQ_PERF_SNAPSHOT_PC_HI', 'HW_REG_XCC_ID'}
+def _disasm_sopk(inst: SOPK) -> str:
+  op, name, cdna = inst.op, inst.op_name.lower(), _is_cdna(inst)
+  is_rdna4 = _is_r4(inst)
+  hw = HWREG_CDNA if cdna else (HWREG_RDNA4 if is_rdna4 else HWREG)
+  blacklist = _HWREG_BLACKLIST_CDNA if cdna else _HWREG_BLACKLIST
+  def fmt_hwreg(hid, hoff, hsz):
+    try: hr_name = hw(hid).name.replace("HW_REG_WAVE_", "HW_REG_")
+    except ValueError: return f"0x{inst.simm16:x}"
+    if hr_name in blacklist: return f"0x{inst.simm16:x}"
+    return f"hwreg({hr_name})" if hoff == 0 and hsz == 32 else f"hwreg({hr_name}, {hoff}, {hsz})"
+  if name == 's_setreg_imm32_b32':
+    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
+    return f"{name} {fmt_hwreg(hid, hoff, hsz)}, 0x{inst._literal:x}"
+  if name == 's_version': return f"{name} 0x{inst.simm16:x}"
+  if name in ('s_setreg_b32', 's_getreg_b32'):
+    hid, hoff, hsz = inst.simm16 & 0x3f, (inst.simm16 >> 6) & 0x1f, ((inst.simm16 >> 11) & 0x1f) + 1
+    hs = fmt_hwreg(hid, hoff, hsz)
+    return f"{name} {hs}, {_fmt_sdst(inst.sdst, 1, cdna)}" if 'setreg' in name else f"{name} {_fmt_sdst(inst.sdst, 1, cdna)}, {hs}"
+  if name in ('s_subvector_loop_begin', 's_subvector_loop_end'):
+    return f"{name} {_fmt_sdst(inst.sdst, 1)}, 0x{inst.simm16:x}"
+  return f"{name} {_fmt_sdst(inst.sdst, inst.canonical_op_regs['d'], cdna)}, 0x{inst.simm16:x}"
+
+def _disasm_vinterp(inst: VINTERP) -> str:
+  mods = _mods((inst.waitexp, f"wait_exp:{inst.waitexp}"), (inst.clmp, "clamp"))
+  return f"{inst.op_name.lower()} {inst.vdst.fmt()}, {_lit(inst, inst.src0, inst.neg & 1)}, {_lit(inst, inst.src1, inst.neg & 2)}, {_lit(inst, inst.src2, inst.neg & 4)}" + (" " + mods if mods else "")
+
+DISASM_HANDLERS: dict[type, Callable[..., str]] = {
+  VOP1: _disasm_vop1, VOP1_SDST: _disasm_vop1, VOP1_SDST_LIT: _disasm_vop1, VOP1_LIT: _disasm_vop1,
+  VOP2: _disasm_vop2, VOP2_LIT: _disasm_vop2, VOPC: _disasm_vopc, VOPC_LIT: _disasm_vopc,
+  VOP3: _disasm_vop3, VOP3_SDST: _disasm_vop3, VOP3_SDST_LIT: _disasm_vop3, VOP3_LIT: _disasm_vop3, VOP3SD: _disasm_vop3sd, VOP3SD_LIT: _disasm_vop3sd,
+  VOPD: _disasm_vopd, VOPD_LIT: _disasm_vopd, VOP3P: _disasm_vop3p, VOP3P_LIT: _disasm_vop3p,
+  VINTERP: _disasm_vinterp, SOPP: _disasm_sopp, SMEM: _disasm_smem, DS: _disasm_ds, FLAT: _disasm_flat, GLOBAL: _disasm_flat, SCRATCH: _disasm_flat,
+  SOP1: _disasm_sop1, SOP1_LIT: _disasm_sop1, SOP2: _disasm_sop2, SOP2_LIT: _disasm_sop2,
+  SOPC: _disasm_sopc, SOPC_LIT: _disasm_sopc, SOPK: _disasm_sopk, SOPK_LIT: _disasm_sopk,
+  # RDNA4
+  R4_VOP1: _disasm_vop1, R4_VOP1_SDST: _disasm_vop1, R4_VOP1_SDST_LIT: _disasm_vop1, R4_VOP1_LIT: _disasm_vop1,
+  R4_VOP2: _disasm_vop2, R4_VOP2_LIT: _disasm_vop2, R4_VOPC: _disasm_vopc, R4_VOPC_LIT: _disasm_vopc,
+  R4_VOP3: _disasm_vop3, R4_VOP3_SDST: _disasm_vop3, R4_VOP3_SDST_LIT: _disasm_vop3, R4_VOP3_LIT: _disasm_vop3,
+  R4_VOP3SD: _disasm_vop3sd, R4_VOP3SD_LIT: _disasm_vop3sd, R4_VOP3P: _disasm_vop3p, R4_VOP3P_LIT: _disasm_vop3p,
+  R4_FLAT: _disasm_flat, R4_GLOBAL: _disasm_flat, R4_SCRATCH: _disasm_flat,
+  R4_VOPD: _disasm_vopd, R4_VOPD_LIT: _disasm_vopd, R4_VINTERP: _disasm_vinterp, R4_SOPP: _disasm_sopp, R4_SMEM: _disasm_smem, R4_DS: _disasm_ds,
+  R4_SOP1: _disasm_sop1, R4_SOP1_LIT: _disasm_sop1, R4_SOP2: _disasm_sop2, R4_SOP2_LIT: _disasm_sop2,
+  R4_SOPC: _disasm_sopc, R4_SOPC_LIT: _disasm_sopc, R4_SOPK: _disasm_sopk, R4_SOPK_LIT: _disasm_sopk}
+
+def disasm(inst: Inst) -> str: return DISASM_HANDLERS[type(inst)](inst)
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# CDNA DISASSEMBLER SUPPORT
+# ═══════════════════════════════════════════════════════════════════════════════
+
+from extra.assembly.amd.autogen.cdna.ins import (VOP1 as CDNA_VOP1, VOP1_LIT as CDNA_VOP1_LIT,
+  VOP1_SDWA as CDNA_VOP1_SDWA, VOP1_DPP16 as CDNA_VOP1_DPP16,
+  VOP2 as CDNA_VOP2, VOP2_LIT as CDNA_VOP2_LIT, VOP2_SDWA as CDNA_VOP2_SDWA, VOP2_DPP16 as CDNA_VOP2_DPP16,
+  VOPC as CDNA_VOPC, VOPC_LIT as CDNA_VOPC_LIT, VOPC_SDWA_SDST as CDNA_VOPC_SDWA_SDST,
+  VOP3 as CDNA_VOP3, VOP3_SDST as CDNA_VOP3_SDST, VOP3SD as CDNA_VOP3SD, VOP3P as CDNA_VOP3P, VOP3P_MFMA as CDNA_VOP3P_MFMA, VOP3PX2 as CDNA_VOP3PX2,
+  SOP1 as CDNA_SOP1, SOP1_LIT as CDNA_SOP1_LIT, SOP2 as CDNA_SOP2, SOP2_LIT as CDNA_SOP2_LIT,
+  SOPC as CDNA_SOPC, SOPC_LIT as CDNA_SOPC_LIT, SOPK as CDNA_SOPK, SOPK_LIT as CDNA_SOPK_LIT,
+  SOPP as CDNA_SOPP, SMEM as CDNA_SMEM, DS as CDNA_DS,
+  FLAT as CDNA_FLAT, GLOBAL as CDNA_GLOBAL, SCRATCH as CDNA_SCRATCH, MUBUF as CDNA_MUBUF)
+
+def _cdna_src(inst, v, neg, abs_=0, n=1):
+  s = _lit(inst, v) if v == 255 else _fmt_src(v, n, cdna=True)
+  if abs_: s = f"|{s}|"
+  return f"neg({s})" if neg and v == 255 else (f"-{s}" if neg else s)
+
+_CDNA_VOP3_ALIASES = {'v_fmac_f64': 'v_mul_legacy_f32', 'v_dot2c_f32_bf16': 'v_mac_f32'}
+
+def _disasm_vop3a(inst) -> str:
+  op_val = inst.op.value if hasattr(inst.op, 'value') else inst.op
+  name = inst.op_name.lower() or f'vop3a_op_{op_val}'
+  n = inst.num_srcs() or _num_srcs(inst)
+  cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
+  # _sr_ instructions use 4-element op_sel (src2 for byte selection)
+  opsel_n = 3 if '_sr_' in name and n == 2 else n
+  opsel = _opsel_str(inst.opsel, opsel_n, inst.opsel != 0, False)
+  orig_name = name
+  name = _CDNA_VOP3_ALIASES.get(name, name)
+  if name != orig_name:
+    s0, s1 = _cdna_src(inst, inst.src0, inst.neg&1, inst.abs&1, 1), _cdna_src(inst, inst.src1, inst.neg&2, inst.abs&2, 1)
+    s2 = ""
+    dst = _vreg(inst.vdst)
+  else:
+    regs = inst.canonical_op_regs
+    dregs, r0, r1, r2 = regs['d'], regs['s0'], regs['s1'], regs['s2']
+    s0, s1, s2 = _cdna_src(inst, inst.src0, inst.neg&1, inst.abs&1, r0), _cdna_src(inst, inst.src1, inst.neg&2, inst.abs&2, r1), _cdna_src(inst, inst.src2, inst.neg&4, inst.abs&4, r2)
+    dst = _vreg(inst.vdst, dregs) if dregs > 1 else _vreg(inst.vdst)
+  if op_val >= 512:
+    return f"{name} {dst}, {s0}, {s1}, {s2}{opsel}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{opsel}{cl}{om}"
+  if op_val < 256:
+    # VOPC: vdst is actually sdst (SGPR pair), but VGPRField adds 256 to the offset
+    sdst_val = _unwrap(inst.vdst)
+    if sdst_val >= 256: sdst_val -= 256
+    sdst = _fmt_sdst(sdst_val, 2, cdna=True)
+    return f"{name} {sdst}, {s0}, {s1}{cl}"
+  if 320 <= op_val < 512:
+    if name in ('v_nop', 'v_clrexcp', 'v_nop_e64', 'v_clrexcp_e64'): return name.replace('_e64', '')
+    return f"{name} {dst}, {s0}{cl}{om}"
+  if name == 'v_cndmask_b32':
+    s2 = _fmt_src(inst.src2, 2, cdna=True)
+    return f"{name} {dst}, {s0}, {s1}, {s2}{cl}{om}"
+  return f"{name} {dst}, {s0}, {s1}, {s2}{opsel}{cl}{om}" if n == 3 else f"{name} {dst}, {s0}, {s1}{opsel}{cl}{om}"
+
+def _disasm_vop3b(inst) -> str:
+  op_val = inst.op.value if hasattr(inst.op, 'value') else inst.op
+  name, cdna = inst.op_name.lower() or f'vop3b_op_{op_val}', _is_cdna(inst)
+  n = inst.num_srcs() or _num_srcs(inst)
+  regs = inst.canonical_op_regs
+  dregs, r0, r1, r2 = regs['d'], regs['s0'], regs['s1'], regs['s2']
+  s0, s1, s2 = _cdna_src(inst, inst.src0, inst.neg&1, n=r0), _cdna_src(inst, inst.src1, inst.neg&2, n=r1), _cdna_src(inst, inst.src2, inst.neg&4, n=r2)
+  # CDNA VOP3_SDST uses vdst field for sdst (but vdst adds 256), RDNA uses separate sdst field
+  sdst_val = getattr(inst, 'sdst', None)
+  if sdst_val is None and hasattr(inst, 'vdst'):
+    sdst_val = _unwrap(inst.vdst)
+    if sdst_val >= 256: sdst_val -= 256  # VGPRField adds 256, remove it for SGPR
+  # For CDNA VOP3_SDST (VOPC->VOP3), vdst is the scalar dest (sdst), there's no vdst output
+  if cdna and 'v_cmp' in name:
+    sdst = _fmt_sdst(sdst_val, 2, cdna=True)
+    cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
+    return f"{name} {sdst}, {s0}, {s1}{cl}{om}"
+  dst = _vreg(inst.vdst, dregs) if dregs > 1 else _vreg(inst.vdst)
+  sdst = _fmt_sdst(sdst_val, 2, cdna=cdna)
+  cl, om = " clamp" if inst.clmp else "", _omod(inst.omod)
+  if name in ('v_addc_co_u32', 'v_subb_co_u32', 'v_subbrev_co_u32'):
+    s2 = _fmt_src(inst.src2, 2, cdna=cdna)
+  return f"{name} {dst}, {sdst}, {s0}, {s1}, {s2}{cl}{om}" if n == 3 else f"{name} {dst}, {sdst}, {s0}, {s1}{cl}{om}"
+
+def _disasm_cdna_vop3p(inst) -> str:
+  name, n = inst.op_name.lower(), inst.num_srcs() or 2
+  is_mfma = 'mfma' in name or 'smfmac' in name
+  is_accvgpr = 'accvgpr' in name
+  get_src = lambda v, sc: _lit(inst, v) if v == 255 else _fmt_src(v, sc, cdna=True)
+
+  # Handle accvgpr read/write (accumulator register operations)
+  if is_accvgpr:
+    src0_off = _unwrap(inst.src0)
+    vdst_off = _vi(inst.vdst)
+    if 'read' in name:
+      # v_accvgpr_read_b32 vN, aM - reads from accumulator to VGPR
+      return f"{name}_b32 v{vdst_off}, a{src0_off - 256 if src0_off >= 256 else src0_off}"
+    if 'write' in name:
+      # v_accvgpr_write_b32 aM, src - writes to accumulator from source
+      src = _lit(inst, inst.src0) if src0_off == 255 else (f"v{src0_off - 256}" if src0_off >= 256 else decode_src(src0_off, cdna=True))
+      return f"{name}_b32 a{vdst_off}, {src}"
+
+  # Handle v_mfma_ld_scale_b32 - special 2-operand format: v_mfma_ld_scale_b32 src0, src1
+  if 'ld_scale' in name:
+    src0, src1 = get_src(inst.src0, 1), get_src(inst.src1, 1)
+    mods = ([_fmt_bits("op_sel", inst.opsel, 2)] if inst.opsel else []) + \
+           ([_fmt_bits("op_sel_hi", inst.opsel_hi, 2)] if inst.opsel_hi != 3 else [])
+    return f"{name} {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
+
+  # Handle MFMA instructions with accumulator destinations
+  if is_mfma:
+    regs = inst.canonical_op_regs
+    dregs, r0, r1, r2 = regs['d'], regs['s0'], regs['s1'], regs['s2']
+    # Infer register counts from instruction name if not in operands table (e.g., v_mfma_f32_32x32x4_xf32)
+    if dregs == 1:
+      if '32x32' in name: dregs, r0, r1, r2 = 16, 2, 2, 16
+      elif '16x16' in name: dregs, r0, r1, r2 = 4, 2, 2, 4
+    # MFMA reuses VOP3P fields differently: clmp -> acc_cd (dest is acc), opsel_hi -> acc (src1/src2 are acc)
+    # acc field (bits 60-59): bit 0 = src2 is acc (always for MFMA), bit 1 = src1 is acc
+    acc = inst.opsel_hi  # opsel_hi field maps to acc for MFMA
+    acc_cd = inst.clmp   # clmp field maps to acc_cd for MFMA (dest is accumulator)
+    is_smfmac = 'smfmac' in name  # SMFMAC has different operand semantics
+    # Format sources: src0 is always VGPR, src1/src2 depend on acc bits
+    def mfma_src(v, sc, is_acc):
+      v = _unwrap(v)
+      if v == 255: return _lit(inst, v)
+      if 128 <= v <= 208 or 240 <= v <= 248: return _lit(inst, v)
+      base = v - 256 if v >= 256 else v
+      if is_acc: return _areg(base, sc)
+      return _vreg(base, sc)
+    src0 = get_src(inst.src0, r0)  # src0 is always VGPR
+    src1 = mfma_src(inst.src1, r1, acc & 2)  # bit 1 = src1 is acc
+    # For SMFMAC, src2 is always a VGPR index (1 register), not accumulator
+    src2 = _vreg(inst.src2) if is_smfmac else mfma_src(inst.src2, r2, acc_cd)
+    dst = _areg(inst.vdst, dregs) if acc_cd else _vreg(inst.vdst, dregs)
+    # MFMA uses neg:[...] not neg_lo:[...], and doesn't support op_sel_hi or clamp
+    # Only f64 MFMA instructions support neg modifier
+    # f8f6f4 MFMA instructions support cbsz/blgp modifiers
+    mods = []
+    if 'f8f6f4' in name:
+      if inst.neg_hi: mods.append(f"cbsz:{inst.neg_hi}")
+      if inst.neg: mods.append(f"blgp:{inst.neg}")
+    elif inst.neg and 'f64' in name:
+      mods.append(_fmt_bits("neg", inst.neg, n))
+    return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}"
+
+  # Standard VOP3P instructions
+  src0, src1, src2, dst = get_src(inst.src0, 1), get_src(inst.src1, 1), get_src(inst.src2, 1), _vreg(inst.vdst)
+  opsel_hi = inst.opsel_hi  # CDNA VOP3P only has 2 bits for opsel_hi (no opsel_hi2)
+  opsel_hi_default = 3  # CDNA default is 0b11 (2 bits), not 0b111 like RDNA
+  mods = ([_fmt_bits("op_sel", inst.opsel, n)] if inst.opsel else []) + ([_fmt_bits("op_sel_hi", opsel_hi, n)] if opsel_hi != opsel_hi_default else []) + \
+          ([_fmt_bits("neg_lo", inst.neg, n)] if inst.neg else []) + ([_fmt_bits("neg_hi", inst.neg_hi, n)] if inst.neg_hi else []) + (["clamp"] if inst.clmp else [])
+  return f"{name} {dst}, {src0}, {src1}, {src2}{' ' + ' '.join(mods) if mods else ''}" if n == 3 else f"{name} {dst}, {src0}, {src1}{' ' + ' '.join(mods) if mods else ''}"
+
+def _disasm_mubuf(inst) -> str:
+  name = inst.op_name.lower()
+  # Determine vdata register count from instruction name
+  nregs = 4 if 'xyzw' in name else 3 if 'xyz' in name else 2 if 'xy' in name or 'x2' in name or 'f64' in name or 'dwordx2' in name else 1
+  vdata = _vreg(inst.vdata, nregs)
+  vaddr = _vreg(inst.vaddr) if inst.offen or inst.idxen else None
+  srsrc = str(inst.srsrc)
+  soffset_val = _unwrap(inst.soffset)
+  soffset = f"s{soffset_val}" if soffset_val < 128 else "off"
+  offset = f" offset:{inst.offset}" if inst.offset else ""
+  offen = " offen" if inst.offen else ""
+  idxen = " idxen" if inst.idxen else ""
+  lds = " lds" if inst.lds else ""
+  sc0 = " sc0" if inst.sc0 else ""
+  sc1 = " sc1" if inst.sc1 else ""
+  nt = " nt" if inst.nt else ""
+  # Handle special cases
+  if name in ('buffer_wbl2', 'buffer_inv'):
+    return f"{name}{sc0}{sc1}"
+  if vaddr:
+    return f"{name} {vdata}, {vaddr}, {srsrc}, {soffset}{offen}{idxen}{offset}{sc0}{nt}{sc1}{lds}"
+  return f"{name} {vdata}, off, {srsrc}, {soffset}{offset}{sc0}{nt}{sc1}{lds}"
+
+_SDWA_SEL = {0: 'BYTE_0', 1: 'BYTE_1', 2: 'BYTE_2', 3: 'BYTE_3', 4: 'WORD_0', 5: 'WORD_1', 6: 'DWORD'}
+
+def _disasm_vop1_sdwa(inst) -> str:
+  name = inst.op_name.lower().replace('_e32', '')
+  regs = inst.canonical_op_regs
+  dst = _vreg(inst.vdst, regs['d'])
+  # When s0=1, vsrc0 is SGPR/constant (VGPRField adds 256, so subtract it back)
+  if inst.s0 == 0: src0 = _vreg(inst.vsrc0, regs['s0'])
+  else:
+    raw = _unwrap(inst.vsrc0) - 256  # VGPRField adds 256
+    src0 = decode_src(raw, cdna=True)  # handles SGPRs, constants, specials
+  src0_sel = _SDWA_SEL.get(inst.src0_sel, f'SEL{inst.src0_sel}')
+  mods = []
+  if inst.clmp: mods.append("clamp")
+  if inst.omod == 1: mods.append("mul:2")
+  elif inst.omod == 2: mods.append("mul:4")
+  elif inst.omod == 3: mods.append("div:2")
+  mods.append(f"src0_sel:{src0_sel}")
+  return f"{name}_sdwa {dst}, {src0} {' '.join(mods)}"
+
+def _decode_dpp(dpp: int) -> str:
+  """Decode DPP control value to string."""
+  if dpp < 0x100: return f"quad_perm:[{dpp&3},{(dpp>>2)&3},{(dpp>>4)&3},{(dpp>>6)&3}]"
+  if 0x100 <= dpp <= 0x10f: return f"row_shl:{dpp & 0xf}"
+  if 0x110 <= dpp <= 0x11f: return f"row_shr:{dpp & 0xf}"
+  if 0x120 <= dpp <= 0x12f: return f"row_ror:{dpp & 0xf}"
+  if dpp == 0x130: return "wave_shl:1"
+  if dpp == 0x134: return "wave_rol:1"
+  if dpp == 0x138: return "wave_shr:1"
+  if dpp == 0x13c: return "wave_ror:1"
+  if dpp == 0x140: return "row_mirror"
+  if dpp == 0x141: return "row_half_mirror"
+  if dpp == 0x142: return "row_bcast:15"
+  if dpp == 0x143: return "row_bcast:31"
+  if 0x150 <= dpp <= 0x15f: return f"row_newbcast:{dpp & 0xf}"
+  if 0x160 <= dpp <= 0x16f: return f"row_share:{dpp & 0xf}"
+  if 0x170 <= dpp <= 0x17f: return f"row_xmask:{dpp & 0xf}"
+  return f"dpp:{dpp:#x}"
+
+def _disasm_vop1_dpp(inst) -> str:
+  name = inst.op_name.lower().replace('_e32', '')
+  regs = inst.canonical_op_regs
+  dst, src0 = _vreg(inst.vdst, regs['d']), _vreg(inst.vsrc0, regs['s0'])
+  dpp_str = _decode_dpp(inst.dpp)
+  mods = [dpp_str]
+  if inst.row_mask != 0xf: mods.append(f"row_mask:{inst.row_mask:#x}")
+  if inst.bank_mask != 0xf: mods.append(f"bank_mask:{inst.bank_mask:#x}")
+  if inst.bc: mods.append("bound_ctrl:1")
+  return f"{name}_dpp {dst}, {src0} {' '.join(mods)}"
+
+def _disasm_vop2_sdwa(inst) -> str:
+  name, cdna = inst.op_name.lower().replace('_e32', ''), _is_cdna(inst)
+  regs = inst.canonical_op_regs
+  dst = _vreg(inst.vdst, regs['d'])
+  # When s0/s1=1, vsrc is SGPR/constant (VGPRField adds 256, so subtract it back)
+  src0 = _vreg(inst.vsrc0, regs['s0']) if inst.s0 == 0 else decode_src(_unwrap(inst.vsrc0) - 256, cdna)
+  src1 = _vreg(inst.vsrc1, regs['s1']) if inst.s1 == 0 else decode_src(_unwrap(inst.vsrc1) - 256, cdna)
+  src0_sel = _SDWA_SEL.get(inst.src0_sel, f'SEL{inst.src0_sel}')
+  src1_sel = _SDWA_SEL.get(inst.src1_sel, f'SEL{inst.src1_sel}')
+  mods = []
+  if inst.clmp: mods.append("clamp")
+  if inst.omod == 1: mods.append("mul:2")
+  elif inst.omod == 2: mods.append("mul:4")
+  elif inst.omod == 3: mods.append("div:2")
+  if inst.src0_sel != 6: mods.append(f"src0_sel:{src0_sel}")
+  if inst.src1_sel != 6: mods.append(f"src1_sel:{src1_sel}")
+  mods_str = ' '.join(mods) if mods else ""
+  # CDNA carry instructions and cndmask need vcc operands
+  if cdna and name in _VOP2_CARRY_OUT: return f"{name}_sdwa {dst}, vcc, {src0}, {src1} {mods_str}".strip()
+  if cdna and name in _VOP2_CARRY_INOUT: return f"{name}_sdwa {dst}, vcc, {src0}, {src1}, vcc {mods_str}".strip()
+  if cdna and name == 'v_cndmask_b32': return f"{name}_sdwa {dst}, {src0}, {src1}, vcc {mods_str}".strip()
+  return f"{name}_sdwa {dst}, {src0}, {src1} {mods_str}".strip()
+
+def _disasm_vop2_dpp(inst) -> str:
+  name, cdna = inst.op_name.lower().replace('_e32', ''), _is_cdna(inst)
+  regs = inst.canonical_op_regs
+  dst, src0, src1 = _vreg(inst.vdst, regs['d']), _vreg(inst.vsrc0, regs['s0']), _vreg(inst.vsrc1, regs['s1'])
+  dpp_str = _decode_dpp(inst.dpp)
+  mods = [dpp_str]
+  if inst.row_mask != 0xf: mods.append(f"row_mask:{inst.row_mask:#x}")
+  if inst.bank_mask != 0xf: mods.append(f"bank_mask:{inst.bank_mask:#x}")
+  if inst.bc: mods.append("bound_ctrl:1")
+  # CDNA carry instructions and cndmask need vcc operands
+  if cdna and name in _VOP2_CARRY_OUT: return f"{name}_dpp {dst}, vcc, {src0}, {src1} {' '.join(mods)}"
+  if cdna and name in _VOP2_CARRY_INOUT: return f"{name}_dpp {dst}, vcc, {src0}, {src1}, vcc {' '.join(mods)}"
+  if cdna and name == 'v_cndmask_b32': return f"{name}_dpp {dst}, {src0}, {src1}, vcc {' '.join(mods)}"
+  return f"{name}_dpp {dst}, {src0}, {src1} {' '.join(mods)}"
+
+def _disasm_vopc_sdwa(inst) -> str:
+  name = inst.op_name.lower().replace('_e32', '')
+  regs = inst.canonical_op_regs
+  sdst = _fmt_sdst(inst.sdst, 2, cdna=True)
+  src0 = _vreg(inst.vsrc0, regs['s0']) if getattr(inst, 's0', 0) == 0 else decode_src(_unwrap(inst.vsrc0) - 256, cdna=True)
+  src1 = _vreg(inst.vsrc1, regs['s1']) if getattr(inst, 's1', 0) == 0 else decode_src(_unwrap(inst.vsrc1) - 256, cdna=True)
+  src0_sel = _SDWA_SEL.get(inst.src0_sel, f'SEL{inst.src0_sel}')
+  src1_sel = _SDWA_SEL.get(inst.src1_sel, f'SEL{inst.src1_sel}')
+  mods = []
+  if inst.src0_sel != 6: mods.append(f"src0_sel:{src0_sel}")
+  if inst.src1_sel != 6: mods.append(f"src1_sel:{src1_sel}")
+  return f"{name}_sdwa {sdst}, {src0}, {src1} {' '.join(mods)}".strip()
+
+def _disasm_vop3px2(inst) -> str:
+  """VOP3PX2 disassembler for scaled MFMA instructions."""
+  name = inst.op_name.lower()
+  regs = inst.canonical_op_regs
+  dregs, r2 = regs['d'], regs['s2']
+  # F8F6F4 MFMA: CBSZ selects matrix A format, BLGP selects matrix B format
+  # VGPRs: FP8/BF8(0,1)=8, FP6/BF6(2,3)=6, FP4(4)=4
+  vgprs = {0: 8, 1: 8, 2: 6, 3: 6, 4: 4}
+  r0, r1 = vgprs.get(inst.cbsz, 8), vgprs.get(inst.blgp, 8)
+  def mfma_src(v, sc, is_acc):
+    v = _unwrap(v)
+    if v == 255: return _lit(inst, v)
+    base = v - 256 if v >= 256 else v
+    return _areg(base, sc) if is_acc else _vreg(base, sc)
+  src0, src1, src2 = mfma_src(inst.src0, r0, False), mfma_src(inst.src1, r1, inst.acc & 2), mfma_src(inst.src2, r2, inst.acc_cd)
+  dst = _areg(inst.vdst, dregs) if inst.acc_cd else _vreg(inst.vdst, dregs)
+  scale_src0, scale_src1 = _vreg(inst.scale_src0), _vreg(inst.scale_src1)
+  mods = []
+  if inst.opsel: mods.append(_fmt_bits("op_sel", inst.opsel, 3))
+  if inst.opsel_hi != 0: mods.append(_fmt_bits("op_sel_hi", inst.opsel_hi, 3))
+  if inst.neg: mods.append(_fmt_bits("neg", inst.neg, 3))
+  if inst.cbsz: mods.append(f"cbsz:{inst.cbsz}")
+  if inst.blgp: mods.append(f"blgp:{inst.blgp}")
+  return f"{name} {dst}, {src0}, {src1}, {src2}, {scale_src0}, {scale_src1}{' ' + ' '.join(mods) if mods else ''}"
+
+DISASM_HANDLERS.update({CDNA_VOP1: _disasm_vop1, CDNA_VOP1_LIT: _disasm_vop1,
+  CDNA_VOP1_SDWA: _disasm_vop1_sdwa, CDNA_VOP1_DPP16: _disasm_vop1_dpp,
+  CDNA_VOP2: _disasm_vop2, CDNA_VOP2_LIT: _disasm_vop2,
+  CDNA_VOP2_SDWA: _disasm_vop2_sdwa, CDNA_VOP2_DPP16: _disasm_vop2_dpp,
+  CDNA_VOPC: _disasm_vopc, CDNA_VOPC_LIT: _disasm_vopc, CDNA_VOPC_SDWA_SDST: _disasm_vopc_sdwa,
+  CDNA_SOP1: _disasm_sop1, CDNA_SOP1_LIT: _disasm_sop1, CDNA_SOP2: _disasm_sop2, CDNA_SOP2_LIT: _disasm_sop2,
+  CDNA_SOPC: _disasm_sopc, CDNA_SOPC_LIT: _disasm_sopc, CDNA_SOPK: _disasm_sopk, CDNA_SOPK_LIT: _disasm_sopk, CDNA_SOPP: _disasm_sopp,
+  CDNA_SMEM: _disasm_smem, CDNA_DS: _disasm_ds, CDNA_FLAT: _disasm_flat, CDNA_GLOBAL: _disasm_flat, CDNA_SCRATCH: _disasm_flat,
+  CDNA_VOP3: _disasm_vop3a, CDNA_VOP3_SDST: _disasm_vop3b, CDNA_VOP3SD: _disasm_vop3b, CDNA_VOP3P: _disasm_cdna_vop3p, CDNA_VOP3P_MFMA: _disasm_cdna_vop3p,
+  CDNA_MUBUF: _disasm_mubuf, CDNA_VOP3PX2: _disasm_vop3px2})
@@ -0,0 +1,480 @@
+# AMD ISA code generator - generates enum.py, ins.py, operands.py, str_pcode.py
+# Sources: XML from https://gpuopen.com/download/machine-readable-isa/latest/
+#          PDF manuals from AMD documentation
+import re, zlib, xml.etree.ElementTree as ET, zipfile
+from tinygrad.helpers import fetch
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# Configuration
+# ═══════════════════════════════════════════════════════════════════════════════
+
+ARCHS = {
+  "rdna3": {"xml": "amdgpu_isa_rdna3_5.xml", "pdf": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content"},
+  "rdna4": {"xml": "amdgpu_isa_rdna4.xml", "pdf": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content"},
+  "cdna": {"xml": "amdgpu_isa_cdna4.xml", "pdf": "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf"},
+}
+XML_URL = "https://gpuopen.com/download/machine-readable-isa/latest/"
+# Map XML encoding names to codebase names
+NAME_MAP = {"VOP3_SDST_ENC": "VOP3SD", "VOP3_SDST_ENC_LIT": "VOP3SD_LIT", "VOP3_SDST_ENC_DPP16": "VOP3SD_DPP16",
+            "VOP3_SDST_ENC_DPP8": "VOP3SD_DPP8", "VOPDXY": "VOPD", "VOPDXY_LIT": "VOPD_LIT", "VDS": "DS"}
+# Instructions missing from XML but present in PDF
+FIXES = {"rdna3": {"SOPK": {22: "S_SUBVECTOR_LOOP_BEGIN", 23: "S_SUBVECTOR_LOOP_END"}, "FLAT": {55: "FLAT_ATOMIC_CSUB_U32"}},
+         "rdna4": {"SOP1": {80: "S_GET_BARRIER_STATE", 81: "S_BARRIER_INIT", 82: "S_BARRIER_JOIN"}, "SOPP": {9: "S_WAITCNT", 21: "S_BARRIER_LEAVE"}},
+         "cdna": {"DS": {152: "DS_GWS_SEMA_RELEASE_ALL", 154: "DS_GWS_SEMA_V", 156: "DS_GWS_SEMA_P"},
+                  "VOP3P": {44: "V_MFMA_LD_SCALE_B32", 62: "V_MFMA_F32_16X16X8_XF32", 63: "V_MFMA_F32_32X32X4_XF32"}}}
+# Fields missing from XML but present in hardware (format: {arch: {encoding: [(name, hi, lo), ...]}})
+FIELD_FIXES = {"cdna": {"VOP3P": [("opsel_hi2", 14, 14)]}}
+# Encoding suffixes to strip (variants we don't generate separate classes for)
+_ENC_SUFFIXES = ("_NSA1",)
+# Encoding suffix to class suffix mapping (for variants we DO generate)
+_ENC_SUFFIX_MAP = {"_INST_LITERAL": "_LIT", "_VOP_DPP16": "_DPP16", "_VOP_DPP": "_DPP16", "_VOP_DPP8": "_DPP8",
+                   "_VOP_SDWA": "_SDWA", "_VOP_SDWA_SDST_ENC": "_SDWA_SDST", "_MFMA": "_MFMA"}
+# Field name normalization
+_FIELD_RENAMES = {"opsel_hi_2": "opsel_hi2", "op_sel_hi_2": "opsel_hi2", "op_sel": "opsel", "bound_ctrl": "bc",
+                  "tgt": "target", "row_en": "row", "unorm": "unrm", "clamp": "clmp", "wait_exp": "waitexp",
+                  "simm32": "literal", "dpp_ctrl": "dpp", "acc_cd": "acc_cd", "acc": "acc",
+                  "dst_sel": "dst_sel", "dst_unused": "dst_unused", "src0_sel": "src0_sel", "src1_sel": "src1_sel"}
+# Encoding variants to skip entirely (NSA is for MIMG graphics instructions)
+_SKIP_ENCODINGS = ("NSA",)
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# XML parsing helpers
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def _strip_enc(name: str) -> str:
+  """Strip ENC_ prefix and normalize encoding suffixes."""
+  name = name.removeprefix("ENC_")
+  for sfx in _ENC_SUFFIXES: name = name.replace(sfx, "")
+  # Process longer suffixes first to avoid partial matches (e.g., _VOP_DPP8 before _VOP_DPP)
+  for old, new in sorted(_ENC_SUFFIX_MAP.items(), key=lambda x: -len(x[0])): name = name.replace(old, new)
+  return name
+
+def _norm_field(name: str) -> str:
+  """Normalize field name to match expected names."""
+  for old, new in _FIELD_RENAMES.items(): name = name.replace(old, new)
+  return name
+
+def _map_flat(enc_name: str, instr_name: str) -> str:
+  """Map FLAT/GLOBAL/SCRATCH encoding to correct enum based on instruction prefix."""
+  if enc_name in ("FLAT_GLBL", "FLAT_GLOBAL"): return "GLOBAL"
+  if enc_name == "FLAT_SCRATCH": return "SCRATCH"
+  if enc_name in ("FLAT", "VFLAT", "VGLOBAL", "VSCRATCH"):
+    v = "V" if enc_name.startswith("V") else ""
+    if instr_name.startswith("GLOBAL_"): return f"{v}GLOBAL"
+    if instr_name.startswith("SCRATCH_"): return f"{v}SCRATCH"
+    return f"{v}FLAT"
+  return enc_name
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# XML parsing
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def parse_xml(filename: str):
+  root = ET.fromstring(zipfile.ZipFile(fetch(XML_URL)).read(filename))
+  encodings, enums, types, fmts, op_types_set = {}, {}, {}, {}, set()
+  # Extract HWREG and MSG enums from OperandTypes
+  op_enum_map = {("OPR_HWREG", "ID"): "HWREG", ("OPR_SENDMSG_RTN", "MSG"): "MSG"}
+  for ot in root.findall(".//OperandTypes/OperandType"):
+    ot_name = ot.findtext("OperandTypeName")
+    for field in ot.findall(".//Field"):
+      if (enum_name := op_enum_map.get((ot_name, field.findtext("FieldName")))):
+        enums[enum_name] = {int(pv.findtext("Value")): pv.findtext("Name").upper() for pv in field.findall(".//PredefinedValue")}
+  # Extract DataFormats with BitCount
+  for df in root.findall("ISA/DataFormats/DataFormat"):
+    name, bits = df.findtext("DataFormatName"), df.findtext("BitCount")
+    if name and bits: fmts[name] = int(bits)
+  # Extract encoding definitions
+  for enc in root.findall("ISA/Encodings/Encoding"):
+    name = enc.findtext("EncodingName")
+    is_base = name.startswith("ENC_") or name in ("VOP3_SDST_ENC", "VOPDXY")
+    is_variant = any(sfx in name for sfx in _ENC_SUFFIX_MAP)
+    if not is_base and not is_variant: continue
+    if any(s in name for s in _SKIP_ENCODINGS): continue
+    fields = [(_norm_field(f.findtext("FieldName").lower()), int(f.find("BitLayout/Range").findtext("BitOffset") or 0) + int(f.find("BitLayout/Range").findtext("BitCount") or 0) - 1,
+               int(f.find("BitLayout/Range").findtext("BitOffset") or 0))
+              for f in enc.findall(".//MicrocodeFormat/BitMap/Field") if f.find("BitLayout/Range") is not None]
+    ident = (enc.findall("EncodingIdentifiers/EncodingIdentifier") or [None])[0]
+    enc_field = next((f for f in fields if f[0] == "encoding"), None)
+    # For multi-dword formats, encoding field may be in higher dword but identifier pattern is always in dword0; use % 32
+    enc_bits = "".join(ident.text[len(ident.text)-1-b] for b in range(enc_field[1] % 32, (enc_field[2] % 32)-1, -1)) if ident is not None and enc_field else None
+    base_name = _strip_enc(name)
+    encodings[NAME_MAP.get(base_name, base_name)] = (fields, enc_bits)
+  # Extract instruction opcodes and operand info
+  # Track which encodings each opcode appears in (for detecting LIT-only ops)
+  opcode_encs: dict[str, dict[int, set[str]]] = {}  # {base_fmt: {opcode: {enc_names}}}
+  for instr in root.findall("ISA/Instructions/Instruction"):
+    name = instr.findtext("InstructionName")
+    for enc in instr.findall("InstructionEncodings/InstructionEncoding"):
+      if enc.findtext("EncodingCondition") != "default": continue
+      base, opcode = _map_flat(_strip_enc(enc.findtext("EncodingName")), name), int(enc.findtext("Opcode") or 0)
+      enc_name = NAME_MAP.get(base, base)
+      # Encoding variants use the same Op enum as the base format
+      base_enum = enc_name
+      for sfx in ("_SDWA_SDST", "_DPP16", "_DPP8", "_SDWA", "_LIT", "_MFMA"):
+        base_enum = base_enum.replace(sfx, "")
+      # Track which encodings this opcode appears in
+      opcode_encs.setdefault(base_enum, {}).setdefault(opcode, set()).add(enc_name)
+      # ADDTID instructions go in both FLAT and GLOBAL enums (pcode uses FLATOp for these)
+      if "ADDTID" in name:
+        if base == "GLOBAL": enums.setdefault("FLAT", {})[opcode] = name
+        elif base == "VGLOBAL": enums.setdefault("VFLAT", {})[opcode] = name
+      enums.setdefault(base_enum, {})[opcode] = name
+      # Extract operand info
+      op_info = {op.findtext("FieldName").lower(): (op.findtext("DataFormatName"), int(op.findtext("OperandSize") or 0), op.findtext("OperandType"))
+                 for op in enc.findall("Operands/Operand") if op.findtext("FieldName")}
+      for fmt, _, otype in op_info.values():
+        if fmt and fmt not in fmts: fmts[fmt] = 0
+        if otype: op_types_set.add(otype)
+      if op_info: types[(name, base_enum)] = op_info
+  # Find opcodes that only exist in a specific variant encoding (no base format version)
+  suffix_only_ops: dict[str, dict[str, set[int]]] = {}  # {suffix: {base_fmt: {opcodes}}}
+  for base_fmt, opcodes in opcode_encs.items():
+    for opcode, encs in opcodes.items():
+      suffix = next((s for s in _ENC_SUFFIX_MAP.values() if all(s in e for e in encs)), None)
+      if suffix is not None: suffix_only_ops.setdefault(suffix, {}).setdefault(base_fmt, set()).add(opcode)
+  return encodings, enums, types, fmts, op_types_set, suffix_only_ops
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# PDF parsing
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def extract_pdf_text(url: str) -> list[list[tuple[float, float, str, str]]]:
+  """Extract positioned text from PDF. Returns list of text elements (x, y, text, font) per page."""
+  data = fetch(url).read_bytes()
+  # Parse xref table to locate objects
+  xref: dict[int, int] = {}
+  pos = int(re.search(rb'startxref\s+(\d+)', data).group(1)) + 4
+  while data[pos:pos+7] != b'trailer':
+    while data[pos:pos+1] in b' \r\n': pos += 1
+    line_end = data.find(b'\n', pos)
+    start_obj, count = map(int, data[pos:line_end].split()[:2])
+    pos = line_end + 1
+    for i in range(count):
+      if data[pos+17:pos+18] == b'n' and (off := int(data[pos:pos+10])) > 0: xref[start_obj + i] = off
+      pos += 20
+
+  def get_stream(n: int) -> bytes:
+    obj = data[xref[n]:data.find(b'endobj', xref[n])]
+    raw = obj[obj.find(b'stream\n') + 7:obj.find(b'\nendstream')]
+    return zlib.decompress(raw) if b'/FlateDecode' in obj else raw
+
+  pages = []
+  for n in sorted(xref):
+    if b'/Type /Page' not in data[xref[n]:xref[n]+500]: continue
+    if not (m := re.search(rb'/Contents (\d+) 0 R', data[xref[n]:xref[n]+500])): continue
+    stream = get_stream(int(m.group(1))).decode('latin-1')
+    elements, font = [], ''
+    for bt in re.finditer(r'BT(.*?)ET', stream, re.S):
+      x, y = 0.0, 0.0
+      for m in re.finditer(r'(/F[\d.]+) [\d.]+ Tf|([\d.+-]+) ([\d.+-]+) Td|[\d.+-]+ [\d.+-]+ [\d.+-]+ [\d.+-]+ ([\d.+-]+) ([\d.+-]+) Tm|<([0-9A-Fa-f]+)>.*?Tj|\[([^\]]+)\] TJ', bt.group(1)):
+        if m.group(1): font = m.group(1)
+        elif m.group(2): x, y = x + float(m.group(2)), y + float(m.group(3))
+        elif m.group(4): x, y = float(m.group(4)), float(m.group(5))
+        elif m.group(6) and (t := bytes.fromhex(m.group(6)).decode('latin-1')).strip(): elements.append((x, y, t, font))
+        elif m.group(7) and (t := ''.join(bytes.fromhex(h).decode('latin-1') for h in re.findall(r'<([0-9A-Fa-f]+)>', m.group(7)))).strip(): elements.append((x, y, t, font))
+    pages.append(sorted(elements, key=lambda e: (-e[1], e[0])))
+  return pages
+
+def extract_pcode(pages: list[list[tuple[float, float, str, str]]], name_to_op: dict[str, int]) -> dict[tuple[str, int], str]:
+  """Extract pseudocode for instructions. Returns {(name, opcode): pseudocode}."""
+  # First pass: find all instruction headers across all pages
+  all_instructions: list[tuple[int, float, str, int]] = []  # (page_idx, y, name, opcode)
+  for page_idx, page in enumerate(pages):
+    by_y: dict[int, list[tuple[float, str]]] = {}
+    for x, y, t, _ in page:
+      by_y.setdefault(round(y), []).append((x, t))
+    for y, items in sorted(by_y.items(), reverse=True):
+      left = [(x, t) for x, t in items if 55 < x < 65]
+      right = [(x, t) for x, t in items if 535 < x < 550]
+      if left and right and left[0][1] in name_to_op and right[0][1].isdigit():
+        all_instructions.append((page_idx, y, left[0][1], int(right[0][1])))
+
+  # Second pass: extract pseudocode between consecutive instructions
+  pcode: dict[tuple[str, int], str] = {}
+  for i, (page_idx, y, name, opcode) in enumerate(all_instructions):
+    if i + 1 < len(all_instructions):
+      next_page, next_y = all_instructions[i + 1][0], all_instructions[i + 1][1]
+    else:
+      next_page, next_y = page_idx, 0
+    # Collect F6 text from current position to next instruction (pseudocode is at x ≈ 69)
+    lines = []
+    for p in range(page_idx, next_page + 1):
+      start_y = y if p == page_idx else 800
+      end_y = next_y if p == next_page else 0
+      lines.extend((p, y2, t) for x, y2, t, f in pages[p] if f in ('/F6.0', '/F7.0') and end_y < y2 < start_y and 60 < x < 80)
+    if lines:
+      sorted_lines = sorted(lines, key=lambda x: (x[0], -x[1]))
+      # Stop at large Y gaps (>30) - indicates section break
+      filtered = [sorted_lines[0]]
+      for j in range(1, len(sorted_lines)):
+        prev_page, prev_y, _ = sorted_lines[j-1]
+        curr_page, curr_y, _ = sorted_lines[j]
+        if curr_page == prev_page and prev_y - curr_y > 30: break
+        if curr_page != prev_page and prev_y > 60 and curr_y < 730: break
+        filtered.append(sorted_lines[j])
+      pcode_lines = [t.replace('Ê', '').strip() for _, _, t in filtered]
+      if pcode_lines: pcode[(name, opcode)] = '\n'.join(pcode_lines)
+  return pcode
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# Code generation
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def write_common(all_fmts, all_op_types, path):
+  lines = ["# autogenerated from AMD ISA XML - do not edit", "from enum import Enum, auto", ""]
+  lines.append("class ReprEnum(Enum):")
+  lines.append('  """Enum with clean repr that roundtrips with eval()."""')
+  lines.append('  def __repr__(self): return f"{type(self).__name__}.{self.name}"')
+  lines.append("")
+  lines.append("class Fmt(Enum):")
+  for fmt in sorted(all_fmts.keys()): lines.append(f"  {fmt} = auto()")
+  lines.append("")
+  lines.append("FMT_BITS = {")
+  for fmt, bits in sorted(all_fmts.items()): lines.append(f"  Fmt.{fmt}: {bits},")
+  lines.append("}")
+  lines.append("")
+  lines.append("class OpType(Enum):")
+  for ot in sorted(all_op_types): lines.append(f"  {ot} = auto()")
+  with open(path, "w") as f: f.write("\n".join(lines))
+
+def write_enum(enums, path):
+  lines = ["# autogenerated from AMD ISA XML - do not edit", "from extra.assembly.amd.autogen.common import ReprEnum, Fmt, FMT_BITS, OpType  # noqa: F401", ""]
+  for name, ops in sorted(enums.items()):
+    if not ops: continue
+    suffix = "_E32" if name in ("VOP1", "VOP2", "VOPC") else "_E64" if name == "VOP3" else ""
+    lines.append(f"class {name}(ReprEnum):" if name in ("HWREG", "MSG") else f"class {name}Op(ReprEnum):")
+    aliases = []
+    for op, mem in sorted(ops.items()):
+      msuf = suffix if name != "VOP3" or op < 512 else ""
+      lines.append(f"  {mem}{msuf} = {op}")
+      if msuf: aliases.append((mem, msuf))
+    for mem, msuf in aliases: lines.append(f"  {mem} = {mem}{msuf}")
+    lines.append("")
+  with open(path, "w") as f: f.write("\n".join(lines))
+
+def write_ins(encodings, enums, suffix_only_ops, types, arch, path):
+  _VGPR_FIELDS = {"vdst", "vdstx", "vsrc0", "vsrc1", "vsrc2", "vsrc3", "vsrcx1", "vsrcy1", "vaddr", "vdata", "data", "data0", "data1", "addr", "vsrc"}
+  _VARIANT_SUFFIXES = ("_LIT", "_DPP16", "_DPP8", "_SDWA_SDST", "_SDWA", "_MFMA")
+  def get_base_fmt(fmt):
+    for sfx in _VARIANT_SUFFIXES: fmt = fmt.replace(sfx, "")
+    return fmt
+  def field_def(name, hi, lo, fmt, enc_bits=None):
+    bits = hi - lo + 1
+    base_fmt = get_base_fmt(fmt)
+    if name == "encoding" and enc_bits: return f"FixedBitField({hi}, {lo}, 0b{enc_bits})"
+    if name == "op" and fmt not in ("DPP", "SDWA"): return f"EnumBitField({hi}, {lo}, {base_fmt}Op)"
+    if name in ("opx", "opy"): return f"EnumBitField({hi}, {lo}, VOPDOp)"
+    if name == "vdsty": return f"VDSTYField({hi}, {lo})"
+    if name in _VGPR_FIELDS and bits == 8: return f"VGPRField({hi}, {lo})"
+    if name == "sbase" and bits == 6: return f"SBaseField({hi}, {lo})"
+    if name in ("srsrc", "ssamp") and bits == 5: return f"SRsrcField({hi}, {lo})"
+    if name in ("sdst", "sdata") and bits == 7: return f"SGPRField({hi}, {lo})"
+    if name in ("soffset", "saddr") and bits == 7: return f"SGPRField({hi}, {lo}, default=NULL)"
+    if name.startswith("ssrc") and bits == 8: return f"SSrcField({hi}, {lo})"
+    if name in ("saddr", "soffset") and bits == 8: return f"SSrcField({hi}, {lo}, default=NULL)"
+    if name.startswith("src") and bits == 9: return f"SrcField({hi}, {lo})"
+    # GLOBAL/SCRATCH: offset is 13-bit signed [12:0], FLAT: 12-bit unsigned (XML has 12-bit for all)
+    if name == "offset" and base_fmt in ("GLOBAL", "SCRATCH"): return f"BitField(12, {lo})"
+    if base_fmt == "VOP3P" and name == "opsel_hi": return f"BitField({hi}, {lo}, default=3)"
+    if base_fmt == "VOP3P" and name == "opsel_hi2": return f"BitField({hi}, {lo}, default=1)"
+    return f"BitField({hi}, {lo})"
+  ORDER = ['encoding', 'op', 'opx', 'opy', 'vdst', 'vdstx', 'vdsty', 'sdst', 'vdata', 'sdata', 'addr', 'vaddr', 'data', 'data0', 'data1',
+           'src0', 'srcx0', 'srcy0', 'vsrc0', 'ssrc0', 'src1', 'vsrc1', 'vsrcx1', 'vsrcy1', 'ssrc1', 'src2', 'vsrc2', 'src3', 'vsrc3',
+           'saddr', 'sbase', 'srsrc', 'ssamp', 'soffset', 'offset', 'simm16', 'literal', 'en', 'target', 'attr', 'attr_chan',
+           'omod', 'neg', 'neg_hi', 'abs', 'clmp', 'opsel', 'opsel_hi', 'waitexp', 'wait_va',
+           'dmask', 'dim', 'seg', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe', 'unrm', 'done', 'row',
+           'dpp', 'fi', 'bc', 'row_mask', 'bank_mask', 'src0_neg', 'src0_abs', 'src1_neg', 'src1_abs',
+           'cbsz', 'abid', 'acc_cd', 'acc', 'blgp', 'lane_sel_0', 'lane_sel_1', 'lane_sel_2', 'lane_sel_3',
+           'lane_sel_4', 'lane_sel_5', 'lane_sel_6', 'lane_sel_7', 'dst_sel', 'dst_unused', 'src0_sel', 'src1_sel']
+  sort_fields = lambda fields: sorted(fields, key=lambda f: (ORDER.index(f[0]) if f[0] in ORDER else 999, f[2]))
+
+  # Separate base encodings from variants
+  base_encodings, variant_encodings = {}, {}
+  for enc_name, data in encodings.items():
+    base = get_base_fmt(enc_name)
+    if base == enc_name: base_encodings[enc_name] = data
+    else: variant_encodings[enc_name] = data
+
+  # Build sets of ops by their vdst type from operand metadata
+  sdst_opcodes = {}  # ops where vdst is OPR_SREG (writes to SGPR)
+  for fmt, ops in enums.items():
+    for op, name in ops.items():
+      op_types = types.get((name, fmt), {})
+      vdst_type = op_types.get("vdst", (None, None, None))[2]
+      if vdst_type == "OPR_SREG": sdst_opcodes.setdefault(fmt, set()).add(op)
+
+  lines = ["# autogenerated from AMD ISA XML - do not edit", "# ruff: noqa: F401,F403",
+           "from extra.assembly.amd.dsl import *", f"from extra.assembly.amd.autogen.{arch}.enum import *", "import functools", ""]
+
+  def fmt_allowed(op_enum: str, ops: set[int]) -> str:
+    """Format allowed ops as {EnumName.MEMBER, ...}."""
+    names = [f"{op_enum}.{enums[op_enum.removesuffix('Op')][op]}" for op in sorted(ops)]
+    return "{" + ", ".join(names) + "}"
+
+  # Generate base classes first
+  for enc_name, (fields, enc_bits) in sorted(base_encodings.items()):
+    all_ops = set(enums.get(enc_name, {}).keys())
+    # Get suffix-only ops for this format (these can't be used in base class)
+    base_suffix_ops = set().union(*(d.get(enc_name, set()) for d in suffix_only_ops.values()))
+    # Exclude SDST ops from base class (they need VOP1_SDST/VOP3_SDST/VOP3B)
+    base_allowed = all_ops - base_suffix_ops - sdst_opcodes.get(enc_name, set())
+    # RDNA3 FLAT/GLOBAL/SCRATCH share encoding bits, differentiated by seg field
+    # RDNA4 VFLAT/VGLOBAL/VSCRATCH have distinct encoding bits, no seg field needed
+    has_seg_field = any(fn == "seg" for fn, _, _ in fields)
+    if enc_name in ("FLAT", "VFLAT") and has_seg_field:
+      prefix = "V" if enc_name == "VFLAT" else ""
+      for cls, seg, op_enum in [(f"{prefix}FLAT", 0, f"{prefix}FLATOp"), (f"{prefix}GLOBAL", 2, f"{prefix}GLOBALOp"), (f"{prefix}SCRATCH", 1, f"{prefix}SCRATCHOp")]:
+        cls_ops = set(enums.get(cls, {}).keys())
+        lines.append(f"class {cls}(Inst):")
+        for fn, hi, lo in sort_fields(fields):
+          if fn == "seg": lines.append(f"  seg = FixedBitField({hi}, {lo}, {seg})")
+          elif fn == "op": lines.append(f"  op = EnumBitField({hi}, {lo}, {op_enum}, {fmt_allowed(op_enum, cls_ops)})")
+          else: lines.append(f"  {fn} = {field_def(fn, hi, lo, cls, enc_bits)}")
+        lines.append("")
+    elif enc_name not in ("FLAT_GLOBAL", "FLAT_SCRATCH", "FLAT_GLBL", "DPP", "SDWA"):
+      lines.append(f"class {enc_name}(Inst):")
+      for fn, hi, lo in sort_fields(fields):
+        if fn == "op":
+          base_fmt = get_base_fmt(enc_name)
+          lines.append(f"  op = EnumBitField({hi}, {lo}, {base_fmt}Op, {fmt_allowed(f'{base_fmt}Op', base_allowed)})")
+        else:
+          lines.append(f"  {fn} = {field_def(fn, hi, lo, enc_name, enc_bits if fn == 'encoding' else None)}")
+      lines.append("")
+
+  # Generate variant classes that inherit from base (only add extra fields)
+  for enc_name, (fields, enc_bits) in sorted(variant_encodings.items()):
+    base = get_base_fmt(enc_name)
+    if base not in base_encodings: continue  # skip if no base class
+    base_fields = {f[0] for f in base_encodings[base][0]}
+    extra_fields = [(fn, hi, lo) for fn, hi, lo in fields if fn not in base_fields]
+    # Check if this is a suffix-only variant
+    variant_suffix = next((sfx for sfx in _VARIANT_SUFFIXES if enc_name.endswith(sfx)), None)
+    is_suffix_variant = variant_suffix in suffix_only_ops
+    all_ops = set(enums.get(base, {}).keys())
+    if extra_fields or is_suffix_variant:
+      lines.append(f"class {enc_name}({base}):")
+      op_field = next((f for f in base_encodings[base][0] if f[0] == "op"), None)
+      # _LIT classes: override op to allow all opcodes (base excludes lit-only ops)
+      # other classes override op to only suffix-only opcodes
+      if op_field and is_suffix_variant:
+        _, hi, lo = op_field
+        allowed_ops = all_ops if variant_suffix == "_LIT" else suffix_only_ops[variant_suffix][base]
+        lines.append(f"  op = EnumBitField({hi}, {lo}, {base}Op, {fmt_allowed(f'{base}Op', allowed_ops)})")
+      for fn, hi, lo in sort_fields(extra_fields):
+        lines.append(f"  {fn} = {field_def(fn, hi, lo, enc_name)}")
+      lines.append("")
+
+  # SDST variants (special case - redefine vdst field type, restrict to SDST ops)
+  for base, field_hi, field_lo in [("VOP1", 24, 17), ("VOP3", 7, 0)]:
+    if base not in base_encodings: continue
+    sdst_ops = sdst_opcodes.get(base, set())
+    if not sdst_ops: continue
+    # For VOP3, all ops < 256 (compare/cmpx ops) use SDST encoding
+    all_base_ops = set(enums.get(base, {}).keys())
+    if base == "VOP3": sdst_ops = sdst_ops | {op for op in all_base_ops if op < 256}
+    op_field = next((f for f in base_encodings[base][0] if f[0] == "op"), None)
+    lines.append(f"class {base}_SDST({base}):")
+    if op_field:
+      _, hi, lo = op_field
+      lines.append(f"  op = EnumBitField({hi}, {lo}, {base}Op, {fmt_allowed(f'{base}Op', sdst_ops)})")
+    lines.append(f"  vdst = SSrcField({field_hi}, {field_lo})")
+    lines.append("")
+    # SDST_LIT class (for literals with SDST destination) - same ops, just adds literal field
+    lit_enc = variant_encodings.get(f"{base}_LIT")
+    if lit_enc:
+      lit_field = next((f for f in lit_enc[0] if f[0] == "literal"), None)
+      if lit_field:
+        lines.append(f"class {base}_SDST_LIT({base}_SDST):")
+        lines.append(f"  literal = BitField({lit_field[1]}, {lit_field[2]})")
+        lines.append("")
+
+  # Instruction helpers
+  lines.append("# instruction helpers")
+  for fmt, ops in sorted(enums.items()):
+    if fmt not in base_encodings and fmt not in ("GLOBAL", "SCRATCH", "VGLOBAL", "VSCRATCH"): continue
+    suffix = "_E32" if fmt in ("VOP1", "VOP2", "VOPC") else "_E64" if fmt == "VOP3" else ""
+    op_to_suffix = {op:suffix for suffix,ops in suffix_only_ops.items() for op in ops.get(fmt, set())}
+    fmt_sdst_ops = sdst_opcodes.get(fmt, set())
+    for op, name in sorted(ops.items()):
+      msuf = suffix if fmt != "VOP3" or op < 512 else ""
+      # Determine class: SDST variants, suffix-specific variants (e.g., _MFMA, _LIT), or base
+      if fmt == "VOP1" and op in fmt_sdst_ops: cls = "VOP1_SDST"
+      elif fmt == "VOP3" and (op in fmt_sdst_ops or op < 256): cls = "VOP3_SDST"
+      elif op_to_suffix.get(op): cls = f"{fmt}{op_to_suffix[op]}"
+      else: cls = fmt
+      lines.append(f"{name.lower()}{msuf.lower()} = functools.partial({cls}, {fmt}Op.{name}{msuf})")
+  with open(path, "w") as f: f.write("\n".join(lines))
+
+def write_operands(types, enums, arch, path):
+  valid = {(name, fmt) for fmt, ops in enums.items() for name in ops.values()}
+  lines = ["# autogenerated from AMD ISA XML - do not edit",
+           "from extra.assembly.amd.autogen.common import Fmt, OpType",
+           f"from extra.assembly.amd.autogen.{arch}.enum import *", ""]
+  lines.append("# instruction operand info: {Op: {field: (Fmt, size_bits, OpType)}}")
+  lines.append("OPERANDS = {")
+  def fmt_val(v):
+    fmt, size, otype = v
+    return f"({f'Fmt.{fmt}' if fmt else 'None'}, {size}, {f'OpType.{otype}' if otype else 'None'})"
+  for (name, enc_base), fields in sorted(types.items()):
+    if (name, enc_base) not in valid: continue
+    fstr = ", ".join(f'"{k}": {fmt_val(v)}' for k, v in sorted(fields.items()))
+    lines.append(f'  {enc_base}Op.{name}: {{{fstr}}},')
+  lines.append("}")
+  with open(path, "w") as f: f.write("\n".join(lines))
+
+def write_pcode(pcode: dict[tuple[str, int], str], enums: dict[str, dict[int, str]], arch: str, path: str):
+  """Write str_pcode.py file from extracted pseudocode."""
+  entries: list[tuple[str, str, int, str]] = []
+  for fmt_name, ops in enums.items():
+    member_suffix = "_E32" if fmt_name in ("VOP1", "VOP2", "VOPC") else "_E64" if fmt_name == "VOP3" else ""
+    for opcode, name in ops.items():
+      if (name, opcode) in pcode:
+        msuf = member_suffix if fmt_name != "VOP3" or opcode < 512 else ""
+        entries.append((f"{fmt_name}Op", f"{name}{msuf}", opcode, pcode[(name, opcode)]))
+  enum_names = sorted(set(e[0] for e in entries))
+  lines = ["# autogenerated from AMD ISA PDF - do not edit", "# ruff: noqa: E501",
+           f"from extra.assembly.amd.autogen.{arch}.enum import {', '.join(enum_names)}", "", "PCODE = {"]
+  for enum_name, name, opcode, code in sorted(entries, key=lambda x: (x[0], x[2])):
+    lines.append(f"  {enum_name}.{name}: {code!r},")
+  lines.append("}")
+  with open(path, "w") as f: f.write("\n".join(lines))
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# Main
+# ═══════════════════════════════════════════════════════════════════════════════
+
+if __name__ == "__main__":
+  import pathlib
+  all_fmts, all_op_types, arch_data = {}, set(), {}
+  # First pass: parse XML for all architectures
+  for arch, cfg in ARCHS.items():
+    print(f"Parsing XML: {cfg['xml']} -> {arch}")
+    encodings, enums, types, fmts, op_types_set, suffix_only_ops = parse_xml(cfg["xml"])
+    for fmt, ops in FIXES.get(arch, {}).items(): enums.setdefault(fmt, {}).update(ops)
+    for fmt, fields in FIELD_FIXES.get(arch, {}).items():
+      if fmt in encodings: encodings[fmt] = (encodings[fmt][0] + fields, encodings[fmt][1])
+    arch_data[arch] = {"encodings": encodings, "enums": enums, "types": types, "suffix_only_ops": suffix_only_ops}
+    for fmt, bits in fmts.items():
+      assert fmt not in all_fmts or all_fmts[fmt] == bits, f"FMT_BITS mismatch for {fmt}: {all_fmts[fmt]} vs {bits}"
+      all_fmts[fmt] = bits
+    all_op_types.update(op_types_set)
+  # Write common.py
+  common_path = pathlib.Path(__file__).parent / "autogen" / "common.py"
+  write_common(all_fmts, all_op_types, common_path)
+  print(f"Wrote common.py: {len(all_fmts)} formats, {len(all_op_types)} op types")
+  # Write per-arch files from XML
+  for arch, data in arch_data.items():
+    base = pathlib.Path(__file__).parent / "autogen" / arch
+    write_enum(data["enums"], base / "enum.py")
+    write_ins(data["encodings"], data["enums"], data["suffix_only_ops"], data["types"], arch, base / "ins.py")
+    write_operands(data["types"], data["enums"], arch, base / "operands.py")
+    print(f"  {arch}: {len(data['encodings'])} encodings, {sum(len(v) for v in data['enums'].values())} instructions")
+  # Second pass: parse PDFs and write pcode
+  for arch, cfg in ARCHS.items():
+    print(f"Parsing PDF: {arch}...")
+    pages = extract_pdf_text(cfg["pdf"])
+    name_to_op = {name: op for ops in arch_data[arch]["enums"].values() for op, name in ops.items()}
+    pcode = extract_pcode(pages, name_to_op)
+    base = pathlib.Path(__file__).parent / "autogen" / arch
+    write_pcode(pcode, arch_data[arch]["enums"], arch, base / "str_pcode.py")
+    print(f"  {arch}: {len(pcode)} pcode entries")
@@ -1,319 +0,0 @@
-# Generic PDF text extractor - no external dependencies
-import re, zlib
-from tinygrad.helpers import fetch, merge_dicts
-
-PDF_URLS = {
-  "rdna3": "https://docs.amd.com/api/khub/documents/UVVZM22UN7tMUeiW_4ShTQ/content",
-  "rdna4": "https://docs.amd.com/api/khub/documents/uQpkEvk3pv~kfAb2x~j4uw/content",
-  "cdna": "https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf",
-}
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# Generic PDF extraction tools
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def extract(url: str) -> list[list[tuple[float, float, str, str]]]:
-  """Extract positioned text from PDF. Returns list of text elements (x, y, text, font) per page."""
-  data = fetch(url).read_bytes()
-
-  # Parse xref table to locate objects
-  xref: dict[int, int] = {}
-  pos = int(re.search(rb'startxref\s+(\d+)', data).group(1)) + 4
-  while data[pos:pos+7] != b'trailer':
-    while data[pos:pos+1] in b' \r\n': pos += 1
-    line_end = data.find(b'\n', pos)
-    start_obj, count = map(int, data[pos:line_end].split()[:2])
-    pos = line_end + 1
-    for i in range(count):
-      if data[pos+17:pos+18] == b'n' and (off := int(data[pos:pos+10])) > 0: xref[start_obj + i] = off
-      pos += 20
-
-  def get_stream(n: int) -> bytes:
-    obj = data[xref[n]:data.find(b'endobj', xref[n])]
-    raw = obj[obj.find(b'stream\n') + 7:obj.find(b'\nendstream')]
-    return zlib.decompress(raw) if b'/FlateDecode' in obj else raw
-
-  # Find page content streams and extract text
-  pages = []
-  for n in sorted(xref):
-    if b'/Type /Page' not in data[xref[n]:xref[n]+500]: continue
-    if not (m := re.search(rb'/Contents (\d+) 0 R', data[xref[n]:xref[n]+500])): continue
-    stream = get_stream(int(m.group(1))).decode('latin-1')
-    elements, font = [], ''
-    for bt in re.finditer(r'BT(.*?)ET', stream, re.S):
-      x, y = 0.0, 0.0
-      for m in re.finditer(r'(/F[\d.]+) [\d.]+ Tf|([\d.+-]+) ([\d.+-]+) Td|[\d.+-]+ [\d.+-]+ [\d.+-]+ [\d.+-]+ ([\d.+-]+) ([\d.+-]+) Tm|<([0-9A-Fa-f]+)>.*?Tj|\[([^\]]+)\] TJ', bt.group(1)):
-        if m.group(1): font = m.group(1)
-        elif m.group(2): x, y = x + float(m.group(2)), y + float(m.group(3))
-        elif m.group(4): x, y = float(m.group(4)), float(m.group(5))
-        elif m.group(6) and (t := bytes.fromhex(m.group(6)).decode('latin-1')).strip(): elements.append((x, y, t, font))
-        elif m.group(7) and (t := ''.join(bytes.fromhex(h).decode('latin-1') for h in re.findall(r'<([0-9A-Fa-f]+)>', m.group(7)))).strip(): elements.append((x, y, t, font))
-    pages.append(sorted(elements, key=lambda e: (-e[1], e[0])))
-  return pages
-
-def extract_tables(pages: list[list[tuple[float, float, str, str]]]) -> dict[int, tuple[str, list[list[str]]]]:
-  """Extract numbered tables from PDF pages. Returns {table_num: (title, rows)} where rows is list of cells per row."""
-  def group_by_y(texts, key=lambda y: round(y)):
-    by_y: dict[int, list[tuple[float, float, str]]] = {}
-    for x, y, t, _ in texts:
-      by_y.setdefault(key(y), []).append((x, y, t))
-    return by_y
-
-  # Find all table headers by merging text on same line
-  table_positions = []
-  for page_idx, texts in enumerate(pages):
-    for items in group_by_y(texts).values():
-      line = ''.join(t for _, t in sorted((x, t) for x, _, t in items))
-      if m := re.search(r'Table (\d+)\. (.+)', line):
-        table_positions.append((int(m.group(1)), m.group(2).strip(), page_idx, items[0][1]))
-  table_positions.sort(key=lambda t: (t[2], -t[3]))
-
-  # For each table, find rows with matching X positions
-  result: dict[int, tuple[str, list[list[str]]]] = {}
-  for num, title, start_page, header_y in table_positions:
-    rows, col_xs = [], None
-    for page_idx in range(start_page, len(pages)):
-      page_texts = [(x, y, t) for x, y, t, _ in pages[page_idx] if 30 < y < 760 and (page_idx > start_page or y < header_y)]
-      for items in sorted(group_by_y([(x, y, t, '') for x, y, t in page_texts], key=lambda y: round(y / 5)).values(), key=lambda items: -items[0][1]):
-        xs = tuple(sorted(round(x) for x, _, _ in items))
-        if col_xs is None:
-          if len(xs) < 2: continue  # Skip single-column rows before table starts
-          col_xs = xs
-        elif len(xs) == 1 and xs[0] in col_xs: continue  # Skip continuation rows at known column positions
-        elif not any(c in xs for c in col_xs[:2]): break  # Row missing first columns = end of table
-        rows.append([t for _, t in sorted((x, t) for x, _, t in items)])
-      else: continue
-      break
-    if rows: result[num] = (title, rows)
-  return result
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# AMD specific extraction
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def extract_enums(tables: dict[int, tuple[str, list[list[str]]]]) -> dict[str, dict[int, str]]:
-  """Extract all enums from tables. Returns {enum_name: {value: name}}."""
-  enums: dict[str, dict[int, str]] = {}
-  for num, (title, rows) in tables.items():
-    # Opcode enums from "XXX Opcodes" tables
-    if m := re.match(r'(\w+) (?:Y-)?Opcodes', title):
-      fmt_name = 'VOPD' if 'Y-Opcodes' in title else m.group(1)
-      ops: dict[int, str] = {}
-      for row in rows:
-        for i in range(0, len(row) - 1, 2):
-          if row[i].isdigit() and re.match(r'^[A-Z][A-Z0-9_]+$', row[i + 1]):
-            ops[int(row[i])] = row[i + 1]
-      if ops: enums[fmt_name] = ops
-    # BufFmt from "Data Format" tables
-    if 'Data Format' in title:
-      for row in rows:
-        for i in range(0, len(row) - 1, 2):
-          if row[i].isdigit() and re.match(r'^[\dA-Z_]+$', row[i + 1]) and 'INVALID' not in row[i + 1]:
-            enums.setdefault('BufFmt', {})[int(row[i])] = row[i + 1]
-  return enums
-
-def extract_ins(tables: dict[int, tuple[str, list[list[str]]]]) -> tuple[dict[str, list[tuple[str, int, int]]], dict[str, str]]:
-  """Extract formats and encodings from 'XXX Fields' tables. Returns (formats, encodings)."""
-  formats: dict[str, list[tuple[str, int, int]]] = {}
-  encodings: dict[str, str] = {}
-  for num, (title, rows) in tables.items():
-    if not (m := re.match(r'(\w+) Fields$', title)): continue
-    fmt_name = m.group(1)
-    fields = []
-    for row in rows:
-      if len(row) < 2: continue
-      if (bits := re.match(r'\[?(\d+):(\d+)\]?$', row[1])) or (bits := re.match(r'\[(\d+)\]$', row[1])):
-        field_name = row[0].lower()
-        hi, lo = int(bits.group(1)), int(bits.group(2)) if bits.lastindex >= 2 else int(bits.group(1))
-        if field_name == 'encoding' and len(row) >= 3:
-          enc_bits = None
-          if "'b" in row[2]: enc_bits = row[2].split("'b")[-1].replace('_', '')
-          elif (enc := re.search(r':\s*([01_]+)', row[2])): enc_bits = enc.group(1).replace('_', '')
-          if enc_bits:
-            # If encoding bits exceed field width, extend field to match (AMD docs sometimes have this)
-            declared_width, actual_width = hi - lo + 1, len(enc_bits)
-            if actual_width > declared_width: lo = hi - actual_width + 1
-            encodings[fmt_name] = enc_bits
-        fields.append((field_name, hi, lo))
-    if fields: formats[fmt_name] = fields
-  return formats, encodings
-
-def extract_pcode(pages: list[list[tuple[float, float, str, str]]], enums: dict[str, dict[int, str]]) -> dict[tuple[str, int], str]:
-  """Extract pseudocode for instructions. Returns {(name, opcode): pseudocode}."""
-  # Build lookup from instruction name to opcode
-  name_to_op = {name: op for ops in enums.values() for op, name in ops.items()}
-
-  # First pass: find all instruction headers across all pages
-  all_instructions: list[tuple[int, float, str, int]] = []  # (page_idx, y, name, opcode)
-  for page_idx, page in enumerate(pages):
-    by_y: dict[int, list[tuple[float, str]]] = {}
-    for x, y, t, _ in page:
-      by_y.setdefault(round(y), []).append((x, t))
-    for y, items in sorted(by_y.items(), reverse=True):
-      left = [(x, t) for x, t in items if 55 < x < 65]
-      right = [(x, t) for x, t in items if 535 < x < 550]
-      if left and right and left[0][1] in name_to_op and right[0][1].isdigit():
-        all_instructions.append((page_idx, y, left[0][1], int(right[0][1])))
-
-  # Second pass: extract pseudocode between consecutive instructions
-  pcode: dict[tuple[str, int], str] = {}
-  for i, (page_idx, y, name, opcode) in enumerate(all_instructions):
-    # Get end boundary from next instruction
-    if i + 1 < len(all_instructions):
-      next_page, next_y = all_instructions[i + 1][0], all_instructions[i + 1][1]
-    else:
-      next_page, next_y = page_idx, 0
-    # Collect F6 text from current position to next instruction (pseudocode is at x ≈ 69)
-    lines = []
-    for p in range(page_idx, next_page + 1):
-      start_y = y if p == page_idx else 800
-      end_y = next_y if p == next_page else 0
-      lines.extend((p, y2, t) for x, y2, t, f in pages[p] if f in ('/F6.0', '/F7.0') and end_y < y2 < start_y and 60 < x < 80)
-    if lines:
-      # Sort by page first, then by y descending within each page (higher y = earlier text in PDF)
-      sorted_lines = sorted(lines, key=lambda x: (x[0], -x[1]))
-      # Stop at large Y gaps (>30) - indicates section break (Notes, examples, etc)
-      filtered = [sorted_lines[0]]
-      for j in range(1, len(sorted_lines)):
-        prev_page, prev_y, _ = sorted_lines[j-1]
-        curr_page, curr_y, _ = sorted_lines[j]
-        if curr_page == prev_page and prev_y - curr_y > 30: break
-        if curr_page != prev_page and prev_y > 60 and curr_y < 730: break  # examples spilled to next page (not at very top)
-        filtered.append(sorted_lines[j])
-      pcode_lines = [t.replace('Ê', '').strip() for _, _, t in filtered]
-      if pcode_lines: pcode[(name, opcode)] = '\n'.join(pcode_lines)
-  return pcode
-
-# ═══════════════════════════════════════════════════════════════════════════════
-# Write autogen files
-# ═══════════════════════════════════════════════════════════════════════════════
-
-def write_enums(enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write enum.py file from extracted enums."""
-  lines = ["# autogenerated from AMD ISA PDF by pdf.py - do not edit", "from enum import IntEnum", ""]
-  for name, values in sorted(enums.items()):
-    suffix = "Op" if name not in ('Src', 'BufFmt') else ("Enum" if name == 'Src' else "")
-    prefix = "BUF_FMT_" if name == 'BufFmt' else ""
-    lines.append(f"class {name}{suffix}(IntEnum):")
-    for val, member in sorted(values.items()):
-      lines.append(f"  {prefix}{member} = {val}")
-    lines.append("")
-  with open(path, "w") as f:
-    f.write("\n".join(lines))
-
-def write_ins(formats: dict[str, list[tuple[str, int, int]]], encodings: dict[str, str], enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write ins.py file from extracted formats and enums."""
-  # Field types and ordering
-  def field_type(name, fmt):
-    if name == 'op' and fmt in enums: return f'Annotated[BitField, {fmt}Op]'
-    if name in ('opx', 'opy'): return 'Annotated[BitField, VOPDOp]'
-    if name == 'vdsty': return 'VDSTYEnc'
-    if name in ('vdst', 'vsrc1', 'vaddr', 'vdata', 'data', 'data0', 'data1', 'addr', 'vsrc0', 'vsrc2', 'vsrc3'): return 'VGPRField'
-    if name in ('sdst', 'sbase', 'sdata', 'srsrc', 'ssamp'): return 'SGPRField'
-    if name.startswith('ssrc') or name in ('saddr', 'soffset'): return 'SSrc'
-    if name in ('src0', 'srcx0', 'srcy0') or name.startswith('src') and name[3:].isdigit(): return 'Src'
-    if name.startswith('simm'): return 'SImm'
-    if name == 'offset' or name.startswith('imm'): return 'Imm'
-    return None
-  field_priority = ['encoding', 'op', 'opx', 'opy', 'vdst', 'vdstx', 'vdsty', 'sdst', 'vdata', 'sdata', 'addr', 'vaddr', 'data', 'data0', 'data1',
-                    'src0', 'srcx0', 'srcy0', 'vsrc0', 'ssrc0', 'src1', 'vsrc1', 'vsrcx1', 'vsrcy1', 'ssrc1', 'src2', 'vsrc2', 'src3', 'vsrc3',
-                    'saddr', 'sbase', 'srsrc', 'ssamp', 'soffset', 'offset', 'simm16', 'en', 'target', 'attr', 'attr_chan',
-                    'omod', 'neg', 'neg_hi', 'abs', 'clmp', 'opsel', 'opsel_hi', 'waitexp', 'wait_va',
-                    'dmask', 'dim', 'seg', 'format', 'offen', 'idxen', 'glc', 'dlc', 'slc', 'tfe', 'unrm', 'done', 'row']
-  def sort_fields(fields):
-    order = {name: i for i, name in enumerate(field_priority)}
-    return sorted(fields, key=lambda f: (order.get(f[0], 1000), f[2]))
-
-  # Generate format classes
-  lines = ["# autogenerated from AMD ISA PDF by pdf.py - do not edit", "# ruff: noqa: F401,F403",
-           "from typing import Annotated",
-           "from extra.assembly.amd.dsl import *",
-           f"from extra.assembly.amd.autogen.{arch}.enum import *", "import functools", ""]
-  for fmt_name, fields in sorted(formats.items()):
-    lines.append(f"class {fmt_name}(Inst):")
-    for name, hi, lo in sort_fields(fields):
-      bits_str = f"bits[{hi}:{lo}]" if hi != lo else f"bits[{hi}]"
-      if name == 'encoding' and fmt_name in encodings: lines.append(f"  encoding = {bits_str} == 0b{encodings[fmt_name]}")
-      else:
-        ftype = field_type(name, fmt_name)
-        lines.append(f"  {name}{f':{ftype}' if ftype else ''} = {bits_str}")
-    lines.append("")
-
-  # Generate instruction helpers
-  lines.append("# instruction helpers")
-  for fmt_name, ops in sorted(enums.items()):
-    seg = {"GLOBAL": ", seg=2", "SCRATCH": ", seg=1"}.get(fmt_name, "")
-    tgt = {"GLOBAL": "FLAT, GLOBALOp", "SCRATCH": "FLAT, SCRATCHOp"}.get(fmt_name, f"{fmt_name}, {fmt_name}Op")
-    suffix = "_e32" if fmt_name in ("VOP1", "VOP2", "VOPC") else "_e64" if fmt_name == "VOP3" and len(ops) > 0 else ""
-    if fmt_name in formats or fmt_name in ("GLOBAL", "SCRATCH"):
-      for op_val, name in sorted(ops.items()):
-        fn_suffix = suffix if fmt_name != "VOP3" or op_val < 512 else ""
-        lines.append(f"{name.lower()}{fn_suffix} = functools.partial({tgt}.{name}{seg})")
-
-  with open(path, "w") as f:
-    f.write("\n".join(lines))
-
-def write_pcode(pcode: dict[tuple[str, int], str], enums: dict[str, dict[int, str]], arch: str, path: str):
-  """Write str_pcode.py file from extracted pseudocode."""
-  # Group pseudocode by enum class
-  by_enum: dict[str, list[tuple[str, int, str]]] = {}
-  for fmt_name, ops in enums.items():
-    for opcode, name in ops.items():
-      if (name, opcode) in pcode: by_enum.setdefault(f"{fmt_name}Op", []).append((name, opcode, pcode[(name, opcode)]))
-  # Generate file
-  enum_names = sorted(by_enum.keys())
-  lines = [f"# autogenerated by pdf.py - do not edit", f"# to regenerate: python -m extra.assembly.amd.pdf",
-           "# ruff: noqa: E501", f"from extra.assembly.amd.autogen.{arch}.enum import {', '.join(enum_names)}", ""]
-  for enum_name in enum_names:
-    lines.append(f"{enum_name}_PCODE = {{")
-    for name, opcode, code in sorted(by_enum[enum_name], key=lambda x: x[1]):
-      lines.append(f"  {enum_name}.{name}: {code!r},")
-    lines.append("}\n")
-  lines.append(f"PSEUDOCODE_STRINGS = {{{', '.join(f'{e}: {e}_PCODE' for e in enum_names)}}}")
-  with open(path, "w") as f:
-    f.write("\n".join(lines))
-
-if __name__ == "__main__":
-  import pathlib
-  for arch, url in PDF_URLS.items():
-    print(f"Processing {arch}...")
-    pages = extract(url)
-    tables = extract_tables(pages)
-    enums = extract_enums(tables)
-    formats, encodings = extract_ins(tables)
-    pcode = extract_pcode(pages, enums)
-    # Fix known PDF errors
-    if arch == 'rdna3':
-      fixes = {'SOPP': {8: 'S_WAITCNT_DEPCTR', 58: 'S_TTRACEDATA', 59: 'S_TTRACEDATA_IMM'},
-               'SOPK': {22: 'S_SUBVECTOR_LOOP_BEGIN', 23: 'S_SUBVECTOR_LOOP_END'},
-               'SMEM': {34: 'S_ATC_PROBE', 35: 'S_ATC_PROBE_BUFFER'},
-               'DS': {24: 'DS_GWS_SEMA_RELEASE_ALL', 25: 'DS_GWS_INIT', 26: 'DS_GWS_SEMA_V', 27: 'DS_GWS_SEMA_BR', 28: 'DS_GWS_SEMA_P', 29: 'DS_GWS_BARRIER'},
-               'FLAT': {40: 'GLOBAL_LOAD_ADDTID_B32', 41: 'GLOBAL_STORE_ADDTID_B32', 55: 'FLAT_ATOMIC_CSUB_U32'}}
-      for fmt, ops in fixes.items(): enums[fmt] = merge_dicts([enums[fmt], ops])
-    if arch == 'rdna4':
-      fixes = {'SMEM': {34: 'S_ATC_PROBE', 35: 'S_ATC_PROBE_BUFFER'},
-               'SOP1': {81: 'S_BARRIER_INIT', 82: 'S_BARRIER_JOIN'},
-               'SOPP': {21: 'S_BARRIER_LEAVE', 58: 'S_TTRACEDATA', 59: 'S_TTRACEDATA_IMM'}}
-      for fmt, ops in fixes.items(): enums[fmt] = merge_dicts([enums[fmt], ops])
-    if arch in ('rdna3', 'rdna4'):
-      # RDNA SMEM: PDF says DLC=[14], GLC=[16] but hardware uses DLC=[13], GLC=[14]
-      if 'SMEM' in formats:
-        formats['SMEM'] = [(n, 13 if n == 'dlc' else 14 if n == 'glc' else h, 13 if n == 'dlc' else 14 if n == 'glc' else l)
-                           for n, h, l in formats['SMEM']]
-    if arch == 'cdna':
-      # CDNA DS: PDF is missing the GDS field (bit 16)
-      if 'DS' in formats and not any(n == 'gds' for n, _, _ in formats['DS']):
-        formats['DS'].append(('gds', 16, 16))
-      # CDNA DPP/SDWA: PDF only documents modifier fields (bits[63:32]), need to add VOP overlay fields (bits[31:0])
-      vop_overlay = [('encoding', 8, 0), ('vop_op', 16, 9), ('vdst', 24, 17), ('vop2_op', 31, 25)]
-      if 'DPP' in formats and not any(n == 'encoding' for n, _, _ in formats['DPP']):
-        formats['DPP'] = vop_overlay + [('bc' if n == 'bound_ctrl' else n, h, l) for n, h, l in formats['DPP']]
-        encodings['DPP'] = '11111010'
-      if 'SDWA' in formats and not any(n == 'encoding' for n, _, _ in formats['SDWA']):
-        formats['SDWA'] = vop_overlay + [(n, h, l) for n, h, l in formats['SDWA']]
-        encodings['SDWA'] = '11111001'
-    base = pathlib.Path(__file__).parent / "autogen" / arch
-    write_enums(enums, arch, base / "enum.py")
-    write_ins(formats, encodings, enums, arch, base / "ins.py")
-    write_pcode(pcode, enums, arch, base / "str_pcode.py")
-    print(f"  {len(tables)} tables, {len(pcode)} pcode -> {base}")
@@ -5,28 +5,28 @@ The format is nibble-based with variable-width packets determined by a state mac
 Uses BitField infrastructure from dsl.py, similar to GPU instruction encoding.
 """
 from __future__ import annotations
-from enum import IntEnum
-from typing import get_type_hints
-from extra.assembly.amd.dsl import BitField, bits
+from typing import Iterator
+from enum import Enum
+from extra.assembly.amd.dsl import BitField, FixedBitField, bits

 # ═══════════════════════════════════════════════════════════════════════════════
 # FIELD ENUMS
 # ═══════════════════════════════════════════════════════════════════════════════

-class MemSrc(IntEnum):
+class MemSrc(Enum):
  LDS = 0
  LDS_ALT = 1
  VMEM = 2
  VMEM_ALT = 3

-class AluSrc(IntEnum):
+class AluSrc(Enum):
  NONE = 0
  SALU = 1
  VALU = 2
-  VALU_ALT = 3
+  VALU_SALU = 3

-class InstOp(IntEnum):
-  """SQTT instruction operation types.
+class InstOp(Enum):
+  """SQTT instruction operation types for RDNA3 (gfx1100).

  Memory ops appear in two ranges depending on which SIMD executes them:
  - 0x1x-0x2x range: ops on traced SIMD
@@ -95,50 +95,101 @@ class InstOp(IntEnum):
  SALU_SAVEEXEC = 0x72    # s_*_saveexec_b32/b64
  VALU_CMPX = 0x73        # v_cmpx_*

+class InstOpL4(Enum):
+  """SQTT instruction operation types for RDNA4 (gfx1200). Different encoding from RDNA3."""
+  # TODO: we need to do discovery of all of these from instructions
+  SALU = 0x0
+  SMEM = 0x1
+  UNK_02 = 0x2
+  JUMP_NO = 0x4
+  UNK_06 = 0x6
+  VMEM = 0x10
+  UNK_11 = 0x11
+  VINTERP = 0x12
+  UNK_14 = 0x14
+  OTHER_VMEM = 0x5e
+  UNK_60 = 0x60
+
 # ═══════════════════════════════════════════════════════════════════════════════
 # PACKET TYPE BASE CLASS
 # ═══════════════════════════════════════════════════════════════════════════════

 class PacketType:
  """Base class for SQTT packet types."""
-  _encoding: tuple[BitField, int] | None = None
-  _field_types: dict[str, type] = {}
-  _values: dict[str, int]
+  encoding: FixedBitField
  _raw: int
  _time: int

  def __init_subclass__(cls, **kwargs):
    super().__init_subclass__(**kwargs)
-    if 'encoding' in cls.__dict__ and isinstance(cls.__dict__['encoding'], tuple):
-      cls._encoding = cls.__dict__['encoding']
-    # Cache field type annotations for enum conversion
-    try: cls._field_types = {k: v for k, v in get_type_hints(cls).items() if isinstance(v, type) and issubclass(v, IntEnum)}
-    except Exception: cls._field_types = {}
-    # Cache fields and precompute extraction info: (name, lo, mask, enum_type)
-    cls._fields = {k: v for k, v in cls.__dict__.items() if isinstance(v, BitField) and k != 'encoding'}
-    cls._extract_info = [(name, bf.lo, bf.mask(), cls._field_types.get(name)) for name, bf in cls._fields.items()]
+    cls._fields = {k: v for k, v in cls.__dict__.items() if isinstance(v, BitField)}
    cls._size_nibbles = ((max((f.hi for f in cls._fields.values()), default=0) + 4) // 4)

  @classmethod
  def from_raw(cls, raw: int, time: int = 0):
    inst = object.__new__(cls)
-    inst._raw, inst._time, inst._values = raw, time, {}
-    for name, lo, mask, enum_type in cls._extract_info:
-      val = (raw >> lo) & mask
-      if enum_type is not None:
-        try: val = enum_type(val)
-        except ValueError: pass
-      inst._values[name] = val
+    inst._raw, inst._time = raw, time
    return inst

-  def __getattr__(self, name: str):
-    if name.startswith('_'): raise AttributeError(name)
-    return self._values.get(name, 0)
-
  def __repr__(self) -> str:
-    fields_str = ", ".join(f"{k}={v}" for k, v in self._values.items() if not k.startswith('_'))
+    fields_str = ", ".join(f"{k}={getattr(self, k)}" for k in self._fields if not k.startswith('_') and k != 'encoding')
    return f"{self.__class__.__name__}({fields_str})"

+# ═══════════════════════════════════════════════════════════════════════════════
+# TS PACKET TYPE DEFINITIONS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+class TS_DELTA_S8_W3(PacketType):
+  encoding = bits[6:0] == 0b0100001
+  delta = bits[10:8]
+  _padding = bits[63:11]
+
+class TS_DELTA_S8_W3_L4(PacketType):  # Layout 4: 64->72 bits
+  encoding = bits[6:0] == 0b0100001
+  delta = bits[10:8]
+  _padding = bits[71:11]
+
+class TS_DELTA_S5_W3(PacketType):
+  encoding = bits[4:0] == 0b00110
+  delta = bits[7:5]
+  _padding = bits[51:8]
+
+class TS_DELTA_S5_W3_L4(PacketType):  # Layout 4: 52->56 bits
+  encoding = bits[4:0] == 0b00110
+  delta = bits[9:7]
+  _padding = bits[55:10]
+
+class TS_DELTA_SHORT(PacketType):
+  encoding = bits[3:0] == 0b1000
+  delta = bits[7:4]
+
+class TS_DELTA_OR_MARK(PacketType):
+  encoding = bits[6:0] == 0b0000001
+  delta = bits[47:12]
+  bit8 = bits[8:8]
+  bit9 = bits[9:9]
+  @property
+  def is_marker(self) -> bool: return bool(self.bit9 and not self.bit8)
+
+class TS_DELTA_OR_MARK_L4(PacketType):  # Layout 4: 48->64 bits
+  encoding = bits[6:0] == 0b0000001
+  delta = bits[63:12]
+  bit7 = bits[7:7]
+  bit8 = bits[8:8]
+  bit9 = bits[9:9]
+  @property
+  def is_marker(self) -> bool: return bool((self.bit9 and not self.bit8) or self.bit7)
+
+class TS_DELTA_S5_W2(PacketType):
+  encoding = bits[4:0] == 0b11100
+  delta = bits[6:5]
+  _padding = bits[47:7]
+
+class TS_DELTA_S5_W2_L4(PacketType):  # Layout 4: 48->40 bits
+  encoding = bits[4:0] == 0b11100
+  delta = bits[6:5]
+  _padding = bits[39:7]
+
 # ═══════════════════════════════════════════════════════════════════════════════
 # PACKET TYPE DEFINITIONS
 # ═══════════════════════════════════════════════════════════════════════════════
@@ -152,12 +203,12 @@ class VALUINST(PacketType):  # exclude: 1 << 2
 class VMEMEXEC(PacketType):  # exclude: 1 << 0
  encoding = bits[3:0] == 0b1111
  delta = bits[5:4]
-  src: MemSrc = bits[7:6]
+  src = bits[7:6].enum(MemSrc)

 class ALUEXEC(PacketType):  # exclude: 1 << 1
  encoding = bits[3:0] == 0b1110
  delta = bits[5:4]
-  src: AluSrc = bits[7:6]
+  src = bits[7:6].enum(AluSrc)

 class IMMEDIATE(PacketType):  # exclude: 1 << 5
  encoding = bits[3:0] == 0b1101
@@ -174,11 +225,6 @@ class WAVERDY(PacketType):  # exclude: 1 << 3
  delta = bits[7:5]
  mask = bits[23:8]

-class TS_DELTA_S8_W3(PacketType):
-  encoding = bits[6:0] == 0b0100001
-  delta = bits[10:8]
-  _padding = bits[63:11]
-
 class WAVEEND(PacketType):  # exclude: 1 << 4
  encoding = bits[4:0] == 0b10101
  delta = bits[7:5]
@@ -200,29 +246,36 @@ class WAVESTART(PacketType):  # exclude: 1 << 4
  @property
  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)

-class TS_DELTA_S5_W2(PacketType):
-  encoding = bits[4:0] == 0b11100
+class WAVESTART_L4(PacketType):  # Layout 4 has wave field at different position
+  encoding = bits[4:0] == 0b01100
  delta = bits[6:5]
-  _padding = bits[47:7]
+  flag7 = bits[7:7]
+  simd = bits[9:8]
+  cu_lo = bits[12:10]
+  wave = bits[19:15]
+  id7 = bits[31:20]
+  @property
+  def cu(self) -> int: return self.cu_lo | (self.flag7 << 3)

 class WAVEALLOC(PacketType):  # exclude: 1 << 10
  encoding = bits[4:0] == 0b00101
  delta = bits[7:5]
  _padding = bits[19:8]

-class TS_DELTA_S5_W3(PacketType):
-  encoding = bits[4:0] == 0b00110
+class WAVEALLOC_L4(PacketType):  # Layout 4: 20->24 bits
+  encoding = bits[4:0] == 0b00101
  delta = bits[7:5]
-  _padding = bits[51:8]
+  _padding = bits[23:8]

 class PERF(PacketType):  # exclude: 1 << 11
  encoding = bits[4:0] == 0b10110
  delta = bits[7:5]
  arg = bits[27:8]

-class TS_DELTA_SHORT(PacketType):
-  encoding = bits[3:0] == 0b1000
-  delta = bits[7:4]
+class PERF_L4(PacketType):  # Layout 4: 28->32 bits
+  encoding = bits[4:0] == 0b10110
+  delta = bits[9:7]
+  arg = bits[31:10]

 class NOP(PacketType):
  encoding = bits[3:0] == 0b0000
@@ -263,14 +316,6 @@ class SNAPSHOT(PacketType):
  delta = bits[9:7]
  snap = bits[63:10]

-class TS_DELTA_OR_MARK(PacketType):
-  encoding = bits[6:0] == 0b0000001
-  delta = bits[47:12]
-  bit8 = bits[8:8]
-  bit9 = bits[9:9]
-  @property
-  def is_marker(self) -> bool: return bool(self.bit9 and not self.bit8)
-
 class LAYOUT_HEADER(PacketType):
  encoding = bits[6:0] == 0b0010001
  delta = None  # type: ignore
@@ -288,94 +333,126 @@ class INST(PacketType):
  flag1 = bits[3:3]
  flag2 = bits[7:7]
  wave = bits[12:8]
-  op: InstOp = bits[19:13]
+  op = bits[19:13].enum(InstOp)
+
+class INST_L4(PacketType):  # Layout 4: different delta position and InstOp encoding
+  encoding = bits[2:0] == 0b010
+  delta = bits[5:3]
+  flag1 = bits[6:6]
+  flag2 = bits[7:7]
+  wave = bits[12:8]
+  op = bits[19:13].enum(InstOpL4)

 class UTILCTR(PacketType):
  encoding = bits[6:0] == 0b0110001
  delta = bits[8:7]
  ctr = bits[47:9]

-# All packet types in encoding priority order (more specific masks first, NOP last as fallback)
-PACKET_TYPES: list[type[PacketType]] = [
-  EVENT, EVENT_BIG,
-  TS_DELTA_S8_W3, TS_WAVE_STATE, SNAPSHOT, TS_DELTA_OR_MARK, LAYOUT_HEADER, UTILCTR,
-  IMMEDIATE_MASK, WAVERDY, WAVEEND, WAVESTART, TS_DELTA_S5_W2, WAVEALLOC, TS_DELTA_S5_W3, PERF,
-  VMEMEXEC, ALUEXEC, IMMEDIATE, TS_DELTA_SHORT, REG,
-  VALUINST, INST,
-  NOP,
-]
+# Packet types with rocprof type IDs as keys
+PACKET_TYPES_L3: dict[int, type[PacketType]] = {
+  1: VALUINST, 2: VMEMEXEC, 3: ALUEXEC, 4: IMMEDIATE, 5: IMMEDIATE_MASK, 6: WAVERDY, 7: TS_DELTA_S8_W3, 8: WAVEEND,
+  9: WAVESTART, 10: TS_DELTA_S5_W2, 11: WAVEALLOC, 12: TS_DELTA_S5_W3, 13: PERF, 14: UTILCTR, 15: TS_DELTA_SHORT,
+  16: NOP, 17: TS_WAVE_STATE, 18: EVENT, 19: EVENT_BIG, 20: REG, 21: SNAPSHOT, 22: TS_DELTA_OR_MARK, 23: LAYOUT_HEADER, 24: INST,
+}
+PACKET_TYPES_L4: dict[int, type[PacketType]] = {
+  **PACKET_TYPES_L3,
+  7: TS_DELTA_S8_W3_L4, 9: WAVESTART_L4, 10: TS_DELTA_S5_W2_L4, 11: WAVEALLOC_L4,
+  12: TS_DELTA_S5_W3_L4, 13: PERF_L4, 22: TS_DELTA_OR_MARK_L4, 24: INST_L4,
+}
+def _build_decode_tables(packet_types: dict[int, type[PacketType]]) -> tuple[dict[int, tuple], bytes]:
+  # Build state table: byte -> opcode. Sort by mask specificity (more bits first), NOP last
+  sorted_types = sorted(packet_types.items(), key=lambda x: (-bin(x[1].encoding.mask).count('1'), x[0] == 16))
+  state_table = bytes(next((op for op, cls in sorted_types if (b & cls.encoding.mask) == cls.encoding.default), 16) for b in range(256))
+  # Build decode info: opcode -> (pkt_cls, nib_count, delta_lo, delta_mask, special_case)
+  # special_case: 0=none, 1=TS_DELTA_OR_MARK (check is_marker), 2=TS_DELTA_SHORT (add 8)
+  decode_info = {}
+  for opcode, pkt_cls in packet_types.items():
+    delta_field = getattr(pkt_cls, 'delta', None)
+    special = {22: 1, 15: 2}.get(opcode, 0)  # TS_DELTA_OR_MARK=22, TS_DELTA_SHORT=15
+    decode_info[opcode] = (pkt_cls, pkt_cls._size_nibbles, delta_field.lo if delta_field else 0, delta_field.mask if delta_field else 0, special)
+  return decode_info, state_table

-def _build_state_table() -> tuple[bytes, dict[int, type[PacketType]]]:
-  table = [len(PACKET_TYPES) - 1] * 256  # default to NOP
-  opcode_to_class: dict[int, type[PacketType]] = {i: cls for i, cls in enumerate(PACKET_TYPES)}
-
-  for byte_val in range(256):
-    for opcode, pkt_cls in enumerate(PACKET_TYPES):
-      if pkt_cls._encoding is None: continue
-      mask_bf, pattern = pkt_cls._encoding
-      if (byte_val & mask_bf.mask()) == pattern:
-        table[byte_val] = opcode
-        break
-
-  return bytes(table), opcode_to_class
-
-STATE_TO_OPCODE, OPCODE_TO_CLASS = _build_state_table()
-
-# Precompute special case opcodes
-_TS_DELTA_OR_MARK_OPCODE = next(op for op, cls in OPCODE_TO_CLASS.items() if cls is TS_DELTA_OR_MARK)
-_TS_DELTA_SHORT_OPCODE = next(op for op, cls in OPCODE_TO_CLASS.items() if cls is TS_DELTA_SHORT)
-_TS_DELTA_OR_MARK_BIT8 = (TS_DELTA_OR_MARK.bit8.lo, TS_DELTA_OR_MARK.bit8.mask())
-_TS_DELTA_OR_MARK_BIT9 = (TS_DELTA_OR_MARK.bit9.lo, TS_DELTA_OR_MARK.bit9.mask())
-
-# Combined lookup: opcode -> (pkt_cls, nib_count, delta_lo, delta_mask, special_case)
-# special_case: 0=none, 1=TS_DELTA_OR_MARK, 2=TS_DELTA_SHORT
-_DECODE_INFO: dict[int, tuple] = {}
-for _opcode, _pkt_cls in OPCODE_TO_CLASS.items():
-  _delta_field = getattr(_pkt_cls, 'delta', None)
-  _delta_lo = _delta_field.lo if _delta_field else 0
-  _delta_mask = _delta_field.mask() if _delta_field else 0
-  _special = 1 if _opcode == _TS_DELTA_OR_MARK_OPCODE else (2 if _opcode == _TS_DELTA_SHORT_OPCODE else 0)
-  _DECODE_INFO[_opcode] = (_pkt_cls, _pkt_cls._size_nibbles, _delta_lo, _delta_mask, _special)
+_DECODE_INFO_L3, _STATE_TABLE_L3 = _build_decode_tables(PACKET_TYPES_L3)
+_DECODE_INFO_L4, _STATE_TABLE_L4 = _build_decode_tables(PACKET_TYPES_L4)

 # ═══════════════════════════════════════════════════════════════════════════════
 # DECODER
 # ═══════════════════════════════════════════════════════════════════════════════

-def decode(data: bytes) -> list[PacketType]:
-  """Decode raw SQTT blob into list of packet instances."""
-  packets: list[PacketType] = []
-  packets_append = packets.append
-  n = len(data)
-  reg = 0
-  offset = 0
-  nib_count = 16
-  time = 0
-  state_to_opcode = STATE_TO_OPCODE
-  decode_info = _DECODE_INFO
-  mask64 = (1 << 64) - 1
+def decode(data: bytes) -> Iterator[PacketType]:
+  """Decode raw SQTT blob, yielding packet instances. Auto-detects layout from LAYOUT_HEADER."""
+  n, reg, pos, nib_off, nib_count, time = len(data), 0, 0, 0, 16, 0
+  decode_info, state_table = _DECODE_INFO_L3, _STATE_TABLE_L3  # default to layout 3, will update after seeing LAYOUT_HEADER

-  while (offset >> 3) < n:
-    target = offset + nib_count * 4
-    while offset < target and (offset >> 3) < n:
-      byte = data[offset >> 3]
-      nib = (byte >> (offset & 4)) & 0xF
-      reg = ((reg >> 4) | (nib << 60)) & mask64
-      offset += 4
-    if offset < target: break
+  while pos + ((nib_count + nib_off + 1) >> 1) <= n:
+    need = nib_count - nib_off
+    # 1. if unaligned, read high nibble to align
+    if nib_off: reg, pos = (reg >> 4) | ((data[pos] >> 4) << 60), pos + 1
+    # 2. read all full bytes at once
+    if (byte_count := need >> 1):
+      chunk = int.from_bytes(data[pos:pos + byte_count], 'little')
+      reg, pos = (reg >> (byte_count * 8)) | (chunk << (64 - byte_count * 8)), pos + byte_count
+    # 3. if odd, read low nibble
+    if (nib_off := need & 1): reg = (reg >> 4) | ((data[pos] & 0xF) << 60)

-    opcode = state_to_opcode[reg & 0xFF]
+    opcode = state_table[reg & 0xFF]
    pkt_cls, nib_count, delta_lo, delta_mask, special = decode_info[opcode]
-
    delta = (reg >> delta_lo) & delta_mask
-
    if special == 1:  # TS_DELTA_OR_MARK
-      bit8 = (reg >> _TS_DELTA_OR_MARK_BIT8[0]) & _TS_DELTA_OR_MARK_BIT8[1]
-      bit9 = (reg >> _TS_DELTA_OR_MARK_BIT9[0]) & _TS_DELTA_OR_MARK_BIT9[1]
-      if bit9 and not bit8: delta = 0
-    elif special == 2:  # TS_DELTA_SHORT
-      delta = delta + 8
-
+      pkt = pkt_cls.from_raw(reg, 0)  # create packet to check is_marker
+      if pkt.is_marker: delta = 0
+    elif special == 2: delta += 8  # TS_DELTA_SHORT
    time += delta
-    packets_append(pkt_cls.from_raw(reg, time))
+    pkt = pkt_cls.from_raw(reg, time)
+    # detect layout from first LAYOUT_HEADER and switch decode tables if needed
+    # NOTE: CDNA uses a completely different 16-bit header format, not nibbles - not supported here
+    if pkt_cls is LAYOUT_HEADER and pkt.layout == 4:
+      decode_info, state_table = _DECODE_INFO_L4, _STATE_TABLE_L4
+    yield pkt

-  return packets
+# ═══════════════════════════════════════════════════════════════════════════════
+# PRINTER
+# ═══════════════════════════════════════════════════════════════════════════════
+
+PACKET_COLORS = {
+  "INST": "WHITE", "VALUINST": "BLACK", "VMEMEXEC": "yellow", "ALUEXEC": "yellow",
+  "IMMEDIATE": "YELLOW", "IMMEDIATE_MASK": "YELLOW", "WAVERDY": "cyan", "WAVEALLOC": "cyan",
+  "WAVEEND": "blue", "WAVESTART": "blue", "PERF": "magenta", "EVENT": "red", "EVENT_BIG": "red",
+  "REG": "green", "LAYOUT_HEADER": "white", "SNAPSHOT": "white", "UTILCTR": "green",
+}
+
+def format_packet(p) -> str:
+  from tinygrad.helpers import colored
+  name = type(p).__name__
+  if isinstance(p, (INST, INST_L4)):
+    op_name = p.op.name if isinstance(p.op, (InstOp, InstOpL4)) else f"0x{p.op:02x}"
+    fields = f"wave={p.wave} op={op_name}" + (" flag1" if p.flag1 else "") + (" flag2" if p.flag2 else "")
+  elif isinstance(p, VALUINST): fields = f"wave={p.wave}" + (" flag" if p.flag else "")
+  elif isinstance(p, ALUEXEC): fields = f"src={p.src.name if isinstance(p.src, AluSrc) else p.src}"
+  elif isinstance(p, VMEMEXEC): fields = f"src={p.src.name if isinstance(p.src, MemSrc) else p.src}"
+  elif isinstance(p, (WAVESTART, WAVESTART_L4, WAVEEND)): fields = f"wave={p.wave} simd={p.simd} cu={p.cu}"
+  elif hasattr(p, '_fields'):
+    filt = {'delta', 'encoding'} if not isinstance(p, (TS_DELTA_OR_MARK, TS_DELTA_OR_MARK_L4)) else {'encoding'}
+    fields = " ".join(f"{k}=0x{getattr(p, k):x}" if k in {'snap', 'val32'} else f"{k}={getattr(p, k)}"
+                      for k in p._fields if not k.startswith('_') and k not in filt)
+  else: fields = ""
+  return f"{p._time:8}: {colored(f'{name:18}', PACKET_COLORS.get(name.replace('_L4', ''), 'white'))} {fields}"
+
+def print_packets(packets) -> None:
+  from tinygrad.helpers import getenv
+  skip = {"NOP", "TS_DELTA_SHORT", "TS_WAVE_STATE", "TS_DELTA_OR_MARK",
+          "TS_DELTA_S5_W2", "TS_DELTA_S5_W3", "TS_DELTA_S8_W3", "REG", "EVENT"} if not getenv("NOSKIP") else {"NOP"}
+  for p in packets:
+    if type(p).__name__.replace("_L4", "") not in skip: print(format_packet(p))
+
+if __name__ == "__main__":
+  import sys, pickle
+  if len(sys.argv) < 2:
+    print("Usage: python sqtt.py <pkl_file>")
+    sys.exit(1)
+  with open(sys.argv[1], "rb") as f:
+    data = pickle.load(f)
+  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
+  for i, event in enumerate(sqtt_events):
+    print(f"\n=== event {i} ===")
+    print_packets(decode(event.blob))
@@ -0,0 +1,161 @@
+"""SQTT (SQ Thread Trace) packet decoder for CDNA/MI300 GPUs.
+
+CDNA uses a completely different 16-bit header format from RDNA's nibble-based encoding.
+"""
+from __future__ import annotations
+from typing import Iterator
+from extra.assembly.amd.dsl import bits
+from extra.assembly.amd.sqtt import PacketType
+
+# CDNA pkt_fmt -> size in bytes (extracted from rocprof hash table)
+CDNA_PKT_SIZES = {0: 2, 1: 8, 2: 8, 3: 4, 4: 2, 5: 6, 6: 2, 7: 2, 8: 2, 9: 2, 10: 2, 11: 8, 12: 6, 13: 4, 14: 8, 15: 6}
+
+class CDNA_DELTA(PacketType):
+  """pkt_fmt=0: 16-bit timestamp delta packet"""
+  encoding = bits[3:0] == 0
+  delta = bits[11:4]      # (data >> 4) & 0xff
+  unk_0 = bits[12:12]     # (data >> 0xc) & 1
+  unk_1 = bits[15:13]     # (data >> 0xd)
+
+class CDNA_TIMESTAMP(PacketType):
+  """pkt_fmt=1: 64-bit timestamp packet (case 0x0)"""
+  encoding = bits[3:0] == 1
+  unk_0 = bits[15:4]
+  timestamp = bits[63:16]   # stored as (data_word >> 0x10) in low 46 bits of local_58
+
+class CDNA_PKT_2(PacketType):
+  """pkt_fmt=2: 64-bit packet (case 0x4)"""
+  encoding = bits[3:0] == 2
+  unk_0 = bits[6:5]       # (data >> 5) & 3
+  unk_1 = bits[7:7]       # (data >> 7) + 1 & 1
+  unk_padding = bits[63:8]
+
+class CDNA_WAVESTART(PacketType):
+  """pkt_fmt=3: 32-bit WAVESTART packet (case 0x8)"""
+  encoding = bits[3:0] == 3
+  unk_0 = bits[5:5]       # (data >> 5) & 1
+  unk_1 = bits[9:6]       # (data >> 6) & 0xf
+  wave = bits[13:10]      # (data >> 10) & 0xf
+  simd = bits[15:14]      # (data >> 0xe) & 3
+  cu = bits[17:16]        # (data >> 0x10) & 3
+  unk_5 = bits[19:18]     # (data >> 0x12) & 3
+  unk_6 = bits[28:22]     # (data >> 0x16) & 0x7f
+  unk_padding = bits[31:29]
+
+class CDNA_PKT_4(PacketType):
+  """pkt_fmt=4: 16-bit packet (case 0xc, same as 0x8/0x14)"""
+  encoding = bits[3:0] == 4
+  unk_0 = bits[5:5]       # (data_word >> 5) & 1
+  unk_1 = bits[9:6]       # (data_word >> 6) & 0xf
+  unk_2 = bits[13:10]     # (data_word >> 10) & 0xf
+  unk_3 = bits[15:14]     # (data_word >> 0xe)
+
+class CDNA_PKT_5(PacketType):
+  """pkt_fmt=5: 48-bit packet (case 0x10)"""
+  encoding = bits[3:0] == 5
+  unk_0 = bits[6:5]       # (data >> 5) & 3
+  unk_1 = bits[7:7]       # (data >> 7) + 1 & 1
+  unk_2 = bits[15:9]      # (data >> 9) & 0x7f
+  unk_padding = bits[47:16]
+
+class CDNA_WAVEEND(PacketType):
+  """pkt_fmt=6: 16-bit WAVEEND packet (case 0x14, same as 0x8/0xc)"""
+  encoding = bits[3:0] == 6
+  unk_0 = bits[5:5]       # (data_word >> 5) & 1
+  unk_1 = bits[9:6]       # (data_word >> 6) & 0xf
+  wave = bits[13:10]      # (data_word >> 10) & 0xf
+  simd = bits[15:14]      # (data_word >> 0xe)
+
+class CDNA_EXEC(PacketType):
+  """pkt_fmt=10: 16-bit EXEC packet (case 0x24)"""
+  encoding = bits[3:0] == 10
+  unk_0 = bits[8:5]       # (data_word >> 5) & 0xf
+  unk_1 = bits[10:9]      # (data_word >> 9) & 3
+  unk_2 = bits[15:11]     # (data_word >> 0xb)
+
+class CDNA_PKT_11(PacketType):
+  """pkt_fmt=11: 64-bit packet (case 0x28)"""
+  encoding = bits[3:0] == 11
+  unk_0 = bits[8:5]       # (data_word >> 5) & 0xf
+  unk_1 = bits[10:9]      # (data_word >> 9) & 3
+  unk_2 = bits[15:15]     # (data_word >> 0xf) & 1
+  unk_padding = bits[63:16]
+
+class CDNA_INST(PacketType):
+  """pkt_fmt=13: 32-bit INST packet (case 0x30)"""
+  encoding = bits[3:0] == 13
+  unk_0 = bits[6:5]       # (data >> 5) & 3
+  unk_1 = bits[9:8]       # (data >> 8) & 3
+  unk_2 = bits[11:10]     # (data >> 10) & 3
+  unk_3 = bits[13:12]     # (data >> 0xc) & 3
+  unk_4 = bits[15:14]     # (data >> 0xe) & 3
+  unk_5 = bits[19:18]     # (data >> 0x12) & 3
+  unk_6 = bits[21:20]     # (data >> 0x14) & 3
+  unk_7 = bits[23:22]     # (data >> 0x16) & 3
+  unk_8 = bits[25:24]     # (data >> 0x18) & 3
+  unk_9 = bits[27:26]     # (data >> 0x1a) & 3
+  unk_padding = bits[31:28]
+
+class CDNA_PKT_14(PacketType):
+  """pkt_fmt=14: 64-bit packet (case 0x34)"""
+  encoding = bits[3:0] == 14
+  unk_0 = bits[5:5]       # (data >> 5) & 1
+  unk_1 = bits[9:6]       # (data >> 6) & 0xf
+  unk_2 = bits[11:10]     # (data >> 10) & 3
+  unk_3 = bits[24:12]     # (data >> 0xc) & 0x1fff
+  unk_4 = bits[37:25]     # (data >> 0x19) & 0x1fff
+  unk_5 = bits[50:38]     # (data >> 0x26) & 0x1fff
+  unk_6 = bits[51:51]     # (data >> 0x33) & 1
+  unk_padding = bits[63:52]
+
+class CDNA_PKT_15(PacketType):
+  """pkt_fmt=15: 48-bit packet (case 0x38, same as 0x10)"""
+  encoding = bits[3:0] == 15
+  unk_0 = bits[6:5]       # (data >> 5) & 3
+  unk_1 = bits[7:7]       # (data >> 7) + 1 & 1
+  unk_2 = bits[15:9]      # (data >> 9) & 0x7f
+  unk_padding = bits[47:16]
+
+CDNA_PKT_TYPES: dict[int, type[PacketType]] = {
+  0: CDNA_DELTA, 1: CDNA_TIMESTAMP, 2: CDNA_PKT_2, 3: CDNA_WAVESTART, 4: CDNA_PKT_4,
+  5: CDNA_PKT_5, 6: CDNA_WAVEEND, 10: CDNA_EXEC, 11: CDNA_PKT_11, 13: CDNA_INST, 14: CDNA_PKT_14, 15: CDNA_PKT_15,
+}
+
+# Validate CDNA packet definitions
+for pkt_fmt, pkt_cls in CDNA_PKT_TYPES.items():
+  assert pkt_cls.encoding.default == pkt_fmt, f"{pkt_cls.__name__} encoding {pkt_cls.encoding.default} != pkt_fmt {pkt_fmt}"
+  assert CDNA_PKT_SIZES[pkt_fmt] * 2 == pkt_cls._size_nibbles, f"{pkt_cls.__name__} size {pkt_cls._size_nibbles//2} != {CDNA_PKT_SIZES[pkt_fmt]}"
+
+def decode(data: bytes) -> Iterator[PacketType]:
+  """Decode CDNA SQTT blob using 16-bit header format."""
+  pos, time, ts_offset = 0, 0, None
+  while pos + 2 <= len(data):
+    header = int.from_bytes(data[pos:pos+2], 'little')
+    pkt_fmt = header & 0xf
+    pkt_size = CDNA_PKT_SIZES[pkt_fmt]
+    if pos + pkt_size > len(data): break
+
+    raw = int.from_bytes(data[pos:pos+pkt_size], 'little')
+    # pkt_fmt=0 has delta in bits[11:4], accumulate it
+    if pkt_fmt == 0: time += ((raw >> 4) & 0xff) * 4
+    # pkt_fmt=1 with unk_0=0 is absolute timestamp - use it to anchor time
+    if pkt_fmt == 1 and ((raw >> 4) & 0xfff) == 0:
+      abs_ts = raw >> 16
+      if ts_offset is None: ts_offset = abs_ts - time  # first timestamp: save offset
+      else: time = ((abs_ts - ts_offset) & ~3) - 4     # subsequent: compute time, align to 4, subtract 4
+    pkt_cls = CDNA_PKT_TYPES[pkt_fmt]
+    yield pkt_cls.from_raw(raw, time)
+    pos += pkt_size
+
+if __name__ == "__main__":
+  import sys, pickle
+  if len(sys.argv) < 2:
+    print("Usage: python sqtt_cdna.py <pkl_file>")
+    sys.exit(1)
+  with open(sys.argv[1], "rb") as f:
+    data = pickle.load(f)
+  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
+  for i, event in enumerate(sqtt_events):
+    print(f"\n=== event {i} ===")
+    for pkt in decode(event.blob):
+      print(f"{pkt._time:8}: {pkt}")
@@ -0,0 +1,122 @@
+# maps SQTT trace packets to instructions.
+from dataclasses import dataclass
+from typing import Iterator
+
+from extra.assembly.amd.sqtt import decode, print_packets, INST, VALUINST, IMMEDIATE, WAVESTART, WAVEEND, InstOp, PacketType, IMMEDIATE_MASK
+from extra.assembly.amd.dsl import Inst
+from extra.assembly.amd.autogen.rdna3.ins import SOPP, s_endpgm
+from extra.assembly.amd.autogen.rdna3.enum import SOPPOp
+
+@dataclass(frozen=True)
+class InstructionInfo:
+  pc: int
+  wave: int
+  inst: Inst
+
+def map_insts(data:bytes, lib:bytes, target:int) -> Iterator[tuple[PacketType, InstructionInfo|None]]:
+  """maps SQTT packets to instructions, yields (packet, instruction_info or None)"""
+  # map pcs to insts
+  from tinygrad.viz.serve import amd_decode
+  pc_map = amd_decode(lib, target)
+
+  wave_pc:dict[int, int] = {}
+  # only processing packets on one [CU, SIMD] unit
+  def simd_select(p) -> bool: return getattr(p, "cu", 0) == 0 and getattr(p, "simd", 0) == 0
+  for p in decode(data):
+    if not simd_select(p): continue
+    if isinstance(p, WAVESTART):
+      assert p.wave not in wave_pc, "only one inflight wave per unit"
+      wave_pc[p.wave] = next(iter(pc_map))
+      continue
+    if isinstance(p, WAVEEND):
+      pc = wave_pc.pop(p.wave)
+      yield (p, InstructionInfo(pc, p.wave, s_endpgm()))
+      continue
+    # skip OTHER_ instructions, they don't belong to this unit
+    if isinstance(p, INST) and p.op.name.startswith("OTHER_"): continue
+    if isinstance(p, IMMEDIATE_MASK):
+      # immediate mask may yield multiple times per packet
+      for wave in range(16):
+        if p.mask & (1 << wave):
+          inst = pc_map[pc:=wave_pc[wave]]
+          # can this assert be more strict?
+          assert isinstance(inst, SOPP), f"IMMEDIATE_MASK packet must map to SOPP, got {inst}"
+          wave_pc[wave] += inst.size()
+          yield (p, InstructionInfo(pc, wave, inst))
+      continue
+    if isinstance(p, (VALUINST, INST, IMMEDIATE)):
+      inst = pc_map[pc:=wave_pc[p.wave]]
+      # s_delay_alu doesn't get a packet?
+      if isinstance(inst, SOPP) and inst.op in {SOPPOp.S_DELAY_ALU}:
+        wave_pc[p.wave] += inst.size()
+        inst = pc_map[pc:=wave_pc[p.wave]]
+      # identify a branch instruction, only used for asserts
+      is_branch = isinstance(inst, SOPP) and "BRANCH" in inst.op_name
+      if is_branch: assert isinstance(p, INST) and p.op in {InstOp.JUMP_NO, InstOp.JUMP}, f"branch can only be folowed by jump packets, got {p}"
+      # JUMP handling
+      if isinstance(p, INST) and p.op is InstOp.JUMP:
+        assert is_branch, f"JUMP packet must map to a branch instruction, got {inst}"
+        x = inst.simm16 & 0xffff
+        wave_pc[p.wave] += inst.size() + (x - 0x10000 if x & 0x8000 else x)*4
+      else:
+        if is_branch: assert inst.op != SOPPOp.S_BRANCH, f"S_BRANCH must have a JUMP packet, got {p}"
+        wave_pc[p.wave] += inst.size()
+      yield (p, InstructionInfo(pc, p.wave, inst))
+      continue
+    # for all other packets (VMEMEXEC, ALUEXEC, etc.), yield with None
+    yield (p, None)
+
+# test to compare every packet with the rocprof decoder
+
+def test_rocprof_inst_traces_match(sqtt, prg, target):
+  from tinygrad.viz.serve import amd_decode
+  from extra.sqtt.roc import decode as roc_decode, InstExec
+  addr_table = amd_decode(prg.lib, target)
+  disasm = {addr+prg.base:(inst.disasm(), inst.size()) for addr,inst in addr_table.items()}
+  rctx = roc_decode([sqtt], {prg.tag:disasm})
+  rwaves = rctx.inst_execs.get((sqtt.kern, sqtt.exec_tag), [])
+  rwaves_iter:dict[int, list[Iterator[InstExec]]] = {} # wave unit (0-15) -> list of inst trace iterators for all executions on that unit
+  for w in rwaves: rwaves_iter.setdefault(w.wave_id, []).append(w.unpack_insts())
+
+  passed_insts = 0
+  for pkt, info in map_insts(sqtt.blob, prg.lib, target):
+    if DEBUG >= 2: print_packets([pkt])
+    if info is None: continue
+    if DEBUG >= 2: print(f"{' '*29}{info.inst.disasm()}")
+    rocprof_inst = next(rwaves_iter[info.wave][0])
+    ref_pc = rocprof_inst.pc-prg.base
+    # always check pc matches
+    assert ref_pc == info.pc, f"pc mismatch {ref_pc}:{disasm[rocprof_inst.pc][0]} != {info.pc}:{info.inst.disasm()}"
+    # special handling for s_endpgm, it marks the wave completion.
+    if info.inst == s_endpgm():
+      completed_wave = list(rwaves_iter[info.wave].pop(0))
+      assert len(completed_wave) == 0, f"incomplete instructions in wave {info.wave}"
+    # otherwise the packet timestamp is time + "stall"
+    else:
+      assert pkt._time == rocprof_inst.time+rocprof_inst.stall
+    passed_insts += 1
+
+  for k,v in rwaves_iter.items():
+    assert len(v) == 0, f"incomplete wave {k}"
+
+  if len(rwaves):
+    print(f"passed for {passed_insts} instructions across {len(rwaves)} waves scheduled on {len(rwaves_iter)} wave units")
+
+if __name__ == "__main__":
+  import argparse, pickle, pathlib
+  from tinygrad.helpers import temp, DEBUG
+  parser = argparse.ArgumentParser()
+  parser.add_argument('--profile', type=pathlib.Path, metavar="PATH", help='Path to profile (optional file, default: latest profile)',
+                      default=pathlib.Path(temp("profile.pkl", append_user=True)))
+  parser.add_argument('--kernel', type=str, default=None, metavar="NAME", help='Kernel to focus on (optional name, default: all kernels)')
+  args = parser.parse_args()
+  with open(args.profile, "rb") as f:
+    data = pickle.load(f)
+  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
+  kern_events = {e.tag:e for e in data if type(e).__name__ == "ProfileProgramEvent"}
+  target = next((e for e in data if type(e).__name__ == "ProfileDeviceEvent" and e.device.startswith("AMD"))).props["gfx_target_version"]
+  for e in sqtt_events:
+    if args.kernel is not None and args.kernel != e.kern: continue
+    if not e.itrace: continue
+    print(f"==== {e.kern}")
+    test_rocprof_inst_traces_match(e, kern_events[e.kern], target)
@@ -6,7 +6,9 @@ from pathlib import Path
 # Set AMD=1 before importing tinygrad
 os.environ["AMD"] = "1"

-from extra.assembly.amd.emu import run_asm as python_run_asm, set_valid_mem_ranges, decode_program
+from extra.assembly.amd.emu import run_asm as python_run_asm, decode_program
+from extra.assembly.amd import decode_inst
+from extra.assembly.amd.autogen.rdna3.ins import SOPP, SOPPOp

 REMU_PATH = Path(__file__).parents[3] / "remu/target/release/libremu.so"
 if not REMU_PATH.exists():
@@ -64,6 +66,55 @@ def benchmark_emulator(name: str, run_fn, kernel: bytes, global_size, local_size

  return sum(times) / len(times)

+def profile_instructions(kernel: bytes):
+  """Profile individual instruction compile times."""
+  from extra.assembly.amd.emu import _get_runner, _canonical_runner_cache
+  from tinygrad.helpers import Context
+  _get_runner.cache_clear()
+  _canonical_runner_cache.clear()
+
+  results = []
+  i = 0
+  while i < len(kernel):
+    inst = decode_inst(kernel[i:])
+    if isinstance(inst, SOPP) and inst.op == SOPPOp.S_CODE_END: break
+    inst_bytes = bytes(kernel[i:i + inst.size() + 4])
+    try: inst_str = repr(inst)
+    except Exception: inst_str = f"<{type(inst).__name__}>"
+
+    # Time the full compile (sink + render + compile)
+    start = time.perf_counter()
+    with Context(CCACHE=0):
+      runner, is_new = _get_runner(inst_bytes)
+    compile_time = time.perf_counter() - start
+
+    results.append({
+      'inst_str': inst_str + ('' if is_new else ' [CACHED]'),
+      'compile_ms': compile_time * 1000 if is_new else 0,
+    })
+    i += inst.size()
+
+  return sorted(results, key=lambda x: x['compile_ms'], reverse=True)
+
+def benchmark_python_split(kernel: bytes, global_size, local_size, args_ptr, rsrc2: int, iterations: int = 5):
+  """Benchmark Python emulator with compile and execution times."""
+  from extra.assembly.amd.emu import _get_runner, _canonical_runner_cache
+  from tinygrad.helpers import Context
+  _get_runner.cache_clear()
+  _canonical_runner_cache.clear()
+  decode_program.cache_clear()
+
+  # Measure compile time (decode_program builds sinks, renders, and compiles)
+  compile_start = time.perf_counter()
+  with Context(CCACHE=0):
+    program = decode_program(kernel)
+  compile_time = time.perf_counter() - compile_start
+  n_compiled = len(_canonical_runner_cache)
+
+  # Execution time
+  exec_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, rsrc2, iterations)
+  return compile_time, exec_time, len(program), n_compiled
+
 def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], dict[int, bytes], int] | None:
  """Get a real tinygrad kernel by operation name. Returns (code, global_size, local_size, buf_sizes, buf_data, rsrc2)."""
  try:
@@ -119,14 +170,36 @@ def get_tinygrad_kernel(op_name: str) -> tuple[bytes, tuple, tuple, list[int], d
    print(f"  Error getting kernel: {e}")
    return None

-TINYGRAD_TESTS = ["add", "mul", "reduce_sum", "softmax", "exp", "gelu", "matmul_small"]
+TINYGRAD_TESTS = ["add", "mul", "reduce_sum", "softmax", "exp", "sin", "gelu", "matmul_small"]

 def main():
  import argparse
  parser = argparse.ArgumentParser(description="Benchmark RDNA3 emulators")
  parser.add_argument("--iterations", type=int, default=3, help="Number of iterations per benchmark")
+  parser.add_argument("--profile", type=str, default=None, help="Profile instructions for a specific kernel (e.g. 'sin')")
+  parser.add_argument("--top", type=int, default=20, help="Number of top instructions to show in profile")
  args = parser.parse_args()

+  # Profile mode: show individual instruction timing
+  if args.profile:
+    kernel_info = get_tinygrad_kernel(args.profile)
+    if kernel_info is None:
+      print(f"Failed to get kernel for '{args.profile}'")
+      return
+    kernel = kernel_info[0]
+    print(f"Profiling instructions for '{args.profile}' kernel...")
+    print("=" * 110)
+    results = profile_instructions(kernel)
+    print(f"{'Instruction':<90} {'Compile(ms)':>12}")
+    print("-" * 110)
+    for r in results[:args.top]:
+      inst = r['inst_str'][:87] + "..." if len(r['inst_str']) > 90 else r['inst_str']
+      print(f"{inst:<90} {r['compile_ms']:>12.3f}")
+    print("-" * 110)
+    total = sum(r['compile_ms'] for r in results)
+    print(f"{'TOTAL':<90} {total:>12.3f}")
+    return
+
  rust_remu = get_rust_remu()
  if rust_remu is None:
    print("Rust libremu not found. Build with: cargo build --release --manifest-path extra/remu/Cargo.toml")
@@ -149,44 +222,45 @@ def main():
      continue

    kernel, global_size, local_size, buf_sizes, buf_data, rsrc2 = kernel_info
-    n_insts = count_instructions(kernel)
+    buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes, buf_data)
+
+    # Benchmark Python emulator (must be first to measure compile time before cache is populated)
+    py_compile, py_exec, n_insts, n_compiled = benchmark_python_split(kernel, global_size, local_size, args_ptr, rsrc2, args.iterations)
+
    n_workgroups = global_size[0] * global_size[1] * global_size[2]
    n_threads = local_size[0] * local_size[1] * local_size[2]
    total_work = n_insts * n_workgroups * n_threads

-    print(f"{n_insts} insts × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")
-
-    buffers, args_arr, args_ptr, ranges = setup_buffers(buf_sizes, buf_data)
-    set_valid_mem_ranges(ranges)
-
-    py_time = benchmark_emulator("Python", python_run_asm, kernel, global_size, local_size, args_ptr, rsrc2, args.iterations)
+    print(f"{n_insts} insts ({n_compiled} unique) × {n_workgroups} WGs × {n_threads} threads = {total_work:,} ops")
    rust_time = benchmark_emulator("Rust", rust_remu.run_asm, kernel, global_size, local_size, args_ptr, rsrc2, args.iterations) if rust_remu else None

-    if py_time:
-      py_rate = total_work / py_time / 1e6
-      print(f"  Python: {py_time*1000:8.3f} ms  ({py_rate:7.2f} M ops/s)")
+    if py_compile is not None:
+      py_exec_rate = total_work / py_exec / 1e6
+      print(f"  Compile:        {py_compile*1000:8.3f} ms  ({n_compiled} unique)")
+      print(f"  Exec:           {py_exec*1000:8.3f} ms  ({py_exec_rate:7.2f} M ops/s)")
    if rust_time:
      rust_rate = total_work / rust_time / 1e6
-      speedup = py_time / rust_time if py_time else 0
-      print(f"  Rust:   {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")
+      speedup = py_exec / rust_time if py_exec else 0
+      print(f"  Rust:           {rust_time*1000:8.3f} ms  ({rust_rate:7.2f} M ops/s)  [{speedup:.1f}x faster]")

-    results.append((op_name, n_insts, n_workgroups, py_time, rust_time))
+    results.append((op_name, n_insts, n_compiled, n_workgroups, py_compile, py_exec, rust_time))

  # Summary table
-  print("\n" + "=" * 90)
+  print("\n" + "=" * 110)
  print("SUMMARY")
-  print("=" * 90)
-  print(f"{'Name':<25} {'Insts':<8} {'WGs':<6} {'Python (ms)':<14} {'Rust (ms)':<14} {'Speedup':<10}")
-  print("-" * 90)
+  print("=" * 110)
+  print(f"{'Name':<16} {'Insts':<6} {'Unique':<6} {'WGs':<5} {'Compile (ms)':<14} {'Exec (ms)':<12} {'Rust (ms)':<12} {'Speedup':<10}")
+  print("-" * 110)

-  for name, n_insts, n_wgs, py_time, rust_time in results:
-    py_ms = f"{py_time*1000:.3f}" if py_time else "error"
+  for name, n_insts, n_compiled, n_wgs, py_compile, py_exec, rust_time in results:
+    compile_ms = f"{py_compile*1000:.3f}" if py_compile else "error"
+    exec_ms = f"{py_exec*1000:.3f}" if py_exec else "error"
    if rust_time:
      rust_ms = f"{rust_time*1000:.3f}"
-      speedup = f"{py_time/rust_time:.1f}x" if py_time else "N/A"
+      speedup = f"{py_exec/rust_time:.1f}x" if py_exec else "N/A"
    else:
      rust_ms, speedup = "N/A", "N/A"
-    print(f"{name:<25} {n_insts:<8} {n_wgs:<6} {py_ms:<14} {rust_ms:<14} {speedup:<10}")
+    print(f"{name:<16} {n_insts:<6} {n_compiled:<6} {n_wgs:<5} {compile_ms:<14} {exec_ms:<12} {rust_ms:<12} {speedup:<10}")

 if __name__ == "__main__":
  main()
@@ -1,196 +0,0 @@
-# Usability tests for the RDNA3 ASM DSL
-# These tests demonstrate how the DSL *should* work for a good user experience
-# Currently many of these tests fail - they document desired behavior
-
-import unittest
-from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.dsl import Inst, RawImm, SGPR, VGPR
-
-class TestRegisterSliceSyntax(unittest.TestCase):
-  """
-  Issue: Register slice syntax should use AMD assembly convention (inclusive end).
-
-  In AMD assembly, s[4:7] means registers s4, s5, s6, s7 (4 registers, inclusive).
-  The DSL should match this convention so that:
-  - s[4:7] gives 4 registers
-  - Disassembler output can be copied directly back into DSL code
-
-  Fix: Change _RegFactory.__getitem__ to use inclusive end:
-    key.stop - key.start + 1  (instead of key.stop - key.start)
-  """
-  def test_register_slice_count(self):
-    # s[4:7] should give 4 registers: s4, s5, s6, s7 (AMD convention, inclusive)
-    reg = s[4:7]
-    self.assertEqual(reg.count, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")
-
-  def test_register_slice_roundtrip(self):
-    # Round-trip: DSL -> disasm -> DSL should preserve register count
-    reg = s[4:7]  # 4 registers in AMD convention
-    inst = s_load_b128(reg, s[0:1], NULL, 0)
-    disasm = inst.disasm()
-    # Disasm shows s[4:7] - user should be able to copy this back
-    self.assertIn("s[4:7]", disasm)
-    # And s[4:7] in DSL should give the same 4 registers
-    reg_from_disasm = s[4:7]
-    self.assertEqual(reg_from_disasm.count, 4, "s[4:7] from disasm should give 4 registers")
-
-
-class TestReprReadability(unittest.TestCase):
-  """
-  Issue: repr() leaks internal RawImm type and omits zero-valued fields.
-
-  When you create v_mov_b32_e32(v[0], v[1]), the repr shows:
-    VOP1(op=1, src0=RawImm(257))
-
-  Problems:
-  1. vdst=v[0] is omitted because 0 is treated as "default"
-  2. src0 shows RawImm(257) instead of v[1]
-  3. User sees encoded values (257 = 256 + 1) instead of register names
-
-  Expected repr: VOP1(op=1, vdst=v[0], src0=v[1])
-  """
-  def test_repr_shows_registers_not_raw_imm(self):
-    inst = v_mov_b32_e32(v[0], v[1])
-    # Should show v[1], not RawImm(257)
-    self.assertNotIn("RawImm", repr(inst), "repr should not expose RawImm internal type")
-    self.assertIn("v[1]", repr(inst), "repr should show register name")
-
-  def test_repr_includes_zero_dst(self):
-    inst = v_mov_b32_e32(v[0], v[1])
-    # v[0] is a valid destination register, should be shown
-    self.assertIn("vdst", repr(inst), "repr should include vdst even when 0")
-
-  def test_repr_roundtrip(self):
-    # repr should produce something that can be eval'd back
-    inst = v_mov_b32_e32(v[0], v[1])
-    # This would require repr to output valid Python, e.g.:
-    # "VOP1(op=VOP1Op.V_MOV_B32, vdst=v[0], src0=v[1])"
-    r = repr(inst)
-    # At minimum, it should be human-readable
-    self.assertIn("v[", r, "repr should show register syntax")
-
-
-class TestInstructionEquality(unittest.TestCase):
-  """
-  Issue: No __eq__ method - instruction comparison requires repr() workaround.
-
-  Two identical instructions should compare equal with ==, but currently:
-    inst1 == inst2 returns False
-
-  The test_handwritten.py works around this with:
-    self.assertEqual(repr(self.inst), repr(reasm))
-  """
-  def test_identical_instructions_equal(self):
-    inst1 = v_mov_b32_e32(v[0], v[1])
-    inst2 = v_mov_b32_e32(v[0], v[1])
-    self.assertEqual(inst1, inst2, "identical instructions should be equal")
-
-  def test_different_instructions_not_equal(self):
-    inst1 = v_mov_b32_e32(v[0], v[1])
-    inst2 = v_mov_b32_e32(v[0], v[2])
-    self.assertNotEqual(inst1, inst2, "different instructions should not be equal")
-
-
-class TestVOPDHelperSignature(unittest.TestCase):
-  """
-  Issue: VOPD helper functions have confusing semantics.
-
-  v_dual_mul_f32 is defined as:
-    v_dual_mul_f32 = functools.partial(VOPD, VOPDOp.V_DUAL_MUL_F32)
-
-  This binds VOPDOp.V_DUAL_MUL_F32 to the FIRST positional arg of VOPD.__init__,
-  which is 'opx'. So v_dual_mul_f32 sets the X operation.
-
-  But then test_dual_mul in test_handwritten.py does:
-    v_dual_mul_f32(VOPDOp.V_DUAL_MUL_F32, vdstx=v[0], ...)
-
-  This passes V_DUAL_MUL_F32 as the SECOND positional arg (opy), making both
-  X and Y operations the same. This is confusing because:
-  1. The function name suggests it handles the X operation
-  2. But you still pass an opcode as the first arg (which becomes opy)
-
-  Expected: Either make the helper fully specify both ops, or make the
-  signature clearer about what the positional arg means.
-  """
-  def test_vopd_helper_opy_should_be_required(self):
-    # Using only keyword args "works" but opy silently defaults to 0
-    inst = v_dual_mul_f32(vdstx=v[0], vdsty=v[1], srcx0=v[2], vsrcx1=v[3], srcy0=v[4], vsrcy1=v[5])
-    self.assertEqual(inst.opx, VOPDOp.V_DUAL_MUL_F32)
-    # Bug: opy defaults to 0 (V_DUAL_FMAC_F32) silently - should require explicit opy
-    # This test documents the bug - it should fail once fixed
-    self.assertNotEqual(inst.opy, VOPDOp.V_DUAL_FMAC_F32, "opy should not silently default to FMAC")
-
-  def test_vopd_helper_positional_arg_is_opy(self):
-    # The first positional arg after the partial becomes opy, not a second opx
-    inst = v_dual_mul_f32(VOPDOp.V_DUAL_MOV_B32, vdstx=v[0], vdsty=v[1], srcx0=v[2], vsrcx1=v[3], srcy0=v[4], vsrcy1=v[5])
-    self.assertEqual(inst.opx, VOPDOp.V_DUAL_MUL_F32)  # From partial
-    self.assertEqual(inst.opy, VOPDOp.V_DUAL_MOV_B32)  # From first positional arg
-
-
-class TestFieldAccessPreservesType(unittest.TestCase):
-  """
-  Issue: Field access loses type information.
-
-  After creating an instruction, accessing fields returns encoded int values:
-    inst = v_mov_b32_e32(v[0], v[1])
-    inst.vdst  # returns 0, not VGPR(0)
-
-  This makes it impossible to round-trip register types through field access.
-  """
-  def test_vdst_returns_register(self):
-    inst = v_mov_b32_e32(v[5], v[1])
-    vdst = inst.vdst
-    # Should return a VGPR, not an int
-    self.assertIsInstance(vdst, (VGPR, int), "vdst should return VGPR or at least be usable")
-    # Ideally: self.assertIsInstance(vdst, VGPR)
-
-  def test_src_returns_register_for_vgpr_source(self):
-    inst = v_mov_b32_e32(v[0], v[1])
-    # src0 is encoded as 257 (256 + 1 for v1)
-    # Ideally it should decode back to v[1]
-    src0_raw = inst._values.get('src0')
-    # Currently returns RawImm(257), should return VGPR(1) or similar
-    self.assertNotIsInstance(src0_raw, RawImm, "source should not be RawImm internally")
-
-
-class TestArgumentDiscoverability(unittest.TestCase):
-  """
-  Issue: No clear signature for positional arguments.
-
-  inspect.signature(s_load_b128) shows: (*args, literal=None, **kwargs)
-
-  Users have no way to know the argument order without reading source code.
-  The order is implicitly defined by the class field definition order.
-
-  Possible fixes:
-  1. Add explicit parameter names to functools.partial
-  2. Generate type stubs with proper signatures
-  3. Add docstrings listing the expected arguments
-  """
-  def test_signature_has_named_params(self):
-    import inspect
-    sig = inspect.signature(s_load_b128)
-    params = list(sig.parameters.keys())
-    # Currently: ['args', 'literal', 'kwargs'] (from *args, literal=None, **kwargs)
-    # Expected: something like ['sdata', 'sbase', 'soffset', 'offset', 'literal']
-    self.assertIn('sdata', params, "signature should show field names")
-
-
-class TestSpecialConstants(unittest.TestCase):
-  """
-  Issue: NULL and other constants are IntEnum values that might be confusing.
-
-  NULL = SrcEnum.NULL = 124, but users might expect NULL to be a special object
-  that clearly represents "no register" rather than a magic number.
-  """
-  def test_null_has_clear_repr(self):
-    # NULL should have a clear string representation
-    self.assertIn("NULL", str(NULL) or repr(NULL), "NULL should be clearly identifiable")
-
-  def test_null_is_distinguishable_from_int(self):
-    # NULL should be distinguishable from the raw integer 124
-    self.assertNotEqual(type(NULL), int, "NULL should not be plain int")
-
-
-if __name__ == "__main__":
-  unittest.main()
@@ -5,6 +5,7 @@ from dataclasses import dataclass
@dataclass
 class KernelInfo:
  code: bytes
+  src: str
  global_size: tuple[int, int, int]
  local_size: tuple[int, int, int]
  buf_idxs: list[int]  # indices into shared buffer pool
@@ -23,44 +24,15 @@ def get_llvm_objdump():
    if shutil.which(p): return p
  raise FileNotFoundError("llvm-objdump not found")

-# ═══════════════════════════════════════════════════════════════════════════════
-# EXECUTION CONTEXT (for testing compiled pseudocode)
-# ═══════════════════════════════════════════════════════════════════════════════
+ARCH_TO_TARGET:dict[str, list[str]] = {
+  "rdna3":["gfx1100"],
+  "rdna4":["gfx1200"],
+  "cdna":["gfx950", "gfx942"],
+}

-class ExecContext:
-  """Context for running compiled pseudocode in tests."""
-  def __init__(self, s0=0, s1=0, s2=0, d0=0, scc=0, vcc=0, lane=0, exec_mask=0xffffffff, literal=0, vgprs=None, src0_idx=0, vdst_idx=0):
-    from extra.assembly.amd.pcode import Reg, MASK32, MASK64, TypedView
-    self._Reg, self._MASK64, self._TypedView = Reg, MASK64, TypedView
-    self.S0, self.S1, self.S2 = Reg(s0), Reg(s1), Reg(s2)
-    self.D0, self.D1 = Reg(d0), Reg(0)
-    self.SCC, self.VCC, self.EXEC = Reg(scc), Reg(vcc), Reg(exec_mask)
-    self.tmp, self.saveexec = Reg(0), Reg(exec_mask)
-    self.lane, self.laneId, self.literal = lane, lane, literal
-    self.SIMM16, self.SIMM32 = Reg(literal), Reg(literal)
-    self.VGPR = vgprs if vgprs is not None else {}
-    self.SRC0, self.VDST = Reg(src0_idx), Reg(vdst_idx)
+TARGET_TO_ARCH:dict[str, str] = {t:arch for arch,targets in ARCH_TO_TARGET.items() for t in targets}

-  def run(self, code: str):
-    """Execute compiled code."""
-    import extra.assembly.amd.pcode as pcode
-    ns = {k: getattr(pcode, k) for k in dir(pcode) if not k.startswith('_')}
-    # Also include underscore-prefixed helpers that compiled pseudocode uses
-    for k in ['_pack', '_pack32']:
-      if hasattr(pcode, k): ns[k] = getattr(pcode, k)
-    ns.update({
-      'S0': self.S0, 'S1': self.S1, 'S2': self.S2, 'D0': self.D0, 'D1': self.D1,
-      'SCC': self.SCC, 'VCC': self.VCC, 'EXEC': self.EXEC,
-      'EXEC_LO': self._TypedView(self.EXEC, 31, 0), 'EXEC_HI': self._TypedView(self.EXEC, 63, 32),
-      'tmp': self.tmp, 'saveexec': self.saveexec,
-      'lane': self.lane, 'laneId': self.laneId, 'literal': self.literal,
-      'SIMM16': self.SIMM16, 'SIMM32': self.SIMM32, 'VGPR': self.VGPR, 'SRC0': self.SRC0, 'VDST': self.VDST,
-    })
-    exec(code, ns)
-    def _sync(ctx_reg, ns_val):
-      if isinstance(ns_val, self._Reg): ctx_reg._val = ns_val._val
-      else: ctx_reg._val = int(ns_val) & self._MASK64
-    for name in ('SCC', 'VCC', 'EXEC', 'D0', 'D1', 'tmp', 'saveexec'):
-      if ns.get(name) is not getattr(self, name): _sync(getattr(self, name), ns[name])
+def get_target(arch:str) -> str: return ARCH_TO_TARGET[arch][0]

-  def result(self) -> dict: return {"d0": self.D0._val, "scc": self.SCC._val & 1}
+def get_mattr(arch:str) -> str:
+  return {"rdna3":"+real-true16,+wavefrontsize32", "rdna4":"+real-true16,+wavefrontsize32", "cdna":"+wavefrontsize64"}[arch]
@@ -1,23 +1,70 @@
 """Test infrastructure for hardware-validated RDNA3 emulator tests.

 Uses run_asm() with memory output, so tests can run on both emulator and real hardware.
-Set USE_HW=1 to run on both emulator and real hardware, comparing results.
+Set USE_HW=1 to run on both emulator and hardware, comparing results.
 """
-import ctypes, os, struct
+import ctypes, math, os, struct
 from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.dsl import RawImm
-from extra.assembly.amd.emu import WaveState, run_asm, set_valid_mem_ranges
-from extra.assembly.amd.pcode import _i32, _f32

-VCC = SrcEnum.VCC_LO  # For VOP3SD sdst field
+from extra.assembly.amd.emu import run_asm
+from extra.assembly.amd.dsl import NULL, SCC, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, M0
+
+def _i32(f: float) -> int: return struct.unpack('<I', struct.pack('<f', f))[0]
+def _f32(i: int) -> float: return struct.unpack('<f', struct.pack('<I', i & 0xFFFFFFFF))[0]
+
+# f16 conversion helpers
+def f16(i: int) -> float: return struct.unpack('<e', struct.pack('<H', i & 0xFFFF))[0]
+def f32_to_f16(f: float) -> int:
+  f = float(f)
+  if math.isnan(f): return 0x7e00
+  if math.isinf(f): return 0x7c00 if f > 0 else 0xfc00
+  try: return struct.unpack('<H', struct.pack('<e', f))[0]
+  except OverflowError: return 0x7c00 if f > 0 else 0xfc00
+
+# For backwards compatibility with tests using SrcEnum.NULL etc.
+class SrcEnum:
+  NULL = NULL
+  VCC_LO = VCC_LO
+  VCC_HI = VCC_HI
+  EXEC_LO = EXEC_LO
+  EXEC_HI = EXEC_HI
+  SCC = SCC
+  M0 = M0
+  POS_HALF = 0.5
+  NEG_HALF = -0.5
+  POS_ONE = 1.0
+  NEG_ONE = -1.0
+  POS_TWO = 2.0
+  NEG_TWO = -2.0
+  POS_FOUR = 4.0
+  NEG_FOUR = -4.0
+
+VCC = VCC_LO  # For VOP3SD sdst field (VCC_LO is exported from dsl)
 USE_HW = os.environ.get("USE_HW", "0") == "1"
 FLOAT_TOLERANCE = 1e-5

-# Output buffer layout: vgpr[16][32], sgpr[16], vcc, scc
+def get_gpu_target() -> tuple[int, int, int]:
+  """Get the GPU target as (major, minor, stepping) tuple."""
+  if not USE_HW: return (0, 0, 0)
+  from tinygrad.device import Device
+  return Device["AMD"].target
+
+def skip_unless_gfx(min_major: int, min_minor: int = 0, reason: str = ""):
+  """Skip test if GPU target is below the minimum required version."""
+  import unittest
+  def decorator(test_func):
+    if not USE_HW: return test_func
+    target = get_gpu_target()
+    if target[0] < min_major or (target[0] == min_major and target[1] < min_minor):
+      return unittest.skip(reason or f"requires gfx{min_major}{min_minor}0+")(test_func)
+    return test_func
+  return decorator
+
+# Output buffer layout: vgpr[16][32], sgpr[16], vcc, scc, exec
 N_VGPRS, N_SGPRS, WAVE_SIZE = 16, 16, 32
 VGPR_BYTES = N_VGPRS * WAVE_SIZE * 4  # 16 regs * 32 lanes * 4 bytes = 2048
 SGPR_BYTES = N_SGPRS * 4  # 16 regs * 4 bytes = 64
-OUT_BYTES = VGPR_BYTES + SGPR_BYTES + 8  # + vcc + scc
+OUT_BYTES = VGPR_BYTES + SGPR_BYTES + 12  # + vcc + scc + exec

 # Float conversion helpers
 def f2i(f: float) -> int: return _i32(f)
@@ -28,6 +75,14 @@ def i642f(i: int) -> float: return struct.unpack('<d', struct.pack('<Q', i))[0]
 def assemble(instructions: list) -> bytes:
  return b''.join(inst.to_bytes() for inst in instructions)

+# Simple WaveState class for test output parsing (mirrors emu.py interface for tests)
+class WaveState:
+  def __init__(self):
+    self.vgpr = [[0] * 256 for _ in range(32)]  # vgpr[lane][reg]
+    self.sgpr = [0] * 128
+    self.vcc = 0
+    self.scc = 0
+
 def get_prologue_epilogue(n_lanes: int) -> tuple[list, list]:
  """Generate prologue and epilogue instructions for state capture."""
  prologue = [
@@ -39,29 +94,36 @@ def get_prologue_epilogue(n_lanes: int) -> tuple[list, list]:
    prologue.append(v_mov_b32_e32(v[i], 0))
  for i in range(N_SGPRS):
    prologue.append(s_mov_b32(s[i], 0))
-  prologue.append(s_mov_b32(s[SrcEnum.VCC_LO - 128], 0))
+  prologue.append(s_mov_b32(VCC_LO, 0))

  epilogue = [
-    s_mov_b32(s[90], SrcEnum.VCC_LO),
+    s_mov_b32(s[90], VCC_LO),
    s_cselect_b32(s[91], 1, 0),
-    s_load_b64(s[92:93], s[80], 0, soffset=SrcEnum.NULL),
-    s_waitcnt(lgkmcnt=0),
+    # Save EXEC early (before we modify it for VGPR stores)
+    s_mov_b32(s[95], EXEC_LO),
+    # Restore EXEC to all active lanes for VGPR stores (test may have modified EXEC)
+    s_mov_b32(EXEC_LO, (1 << n_lanes) - 1),
+    s_load_b64(s[92:93], s[80:81], 0, soffset=NULL),
+    s_waitcnt(0),  # simm16=0 waits for all
    v_lshlrev_b32_e32(v[240], 2, v[255]),
  ]
  for i in range(N_VGPRS):
-    epilogue.append(global_store_b32(addr=v[240], data=v[i], saddr=s[92], offset=i * WAVE_SIZE * 4))
+    epilogue.append(global_store_b32(addr=v[240], data=v[i], saddr=s[92:93], offset=i * WAVE_SIZE * 4))
  epilogue.append(v_mov_b32_e32(v[241], 0))
  epilogue.append(v_cmp_eq_u32_e32(v[255], v[241]))
-  epilogue.append(s_and_saveexec_b32(s[94], SrcEnum.VCC_LO))
+  epilogue.append(s_and_saveexec_b32(s[94], VCC_LO))
  epilogue.append(v_mov_b32_e32(v[240], 0))
  for i in range(N_SGPRS):
    epilogue.append(v_mov_b32_e32(v[243], s[i]))
-    epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92], offset=VGPR_BYTES + i * 4))
+    epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + i * 4))
  epilogue.append(v_mov_b32_e32(v[243], s[90]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92], offset=VGPR_BYTES + SGPR_BYTES))
+  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + SGPR_BYTES))
  epilogue.append(v_mov_b32_e32(v[243], s[91]))
-  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92], offset=VGPR_BYTES + SGPR_BYTES + 4))
-  epilogue.append(s_mov_b32(s[SrcEnum.EXEC_LO - 128], s[94]))
+  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + SGPR_BYTES + 4))
+  # Store EXEC (saved earlier in s[95])
+  epilogue.append(v_mov_b32_e32(v[243], s[95]))
+  epilogue.append(global_store_b32(addr=v[240], data=v[243], saddr=s[92:93], offset=VGPR_BYTES + SGPR_BYTES + 8))
+  epilogue.append(s_mov_b32(EXEC_LO, s[94]))
  epilogue.append(s_endpgm())
  return prologue, epilogue

@@ -76,6 +138,8 @@ def parse_output(out_buf: bytes, n_lanes: int) -> WaveState:
    st.sgpr[i] = struct.unpack_from('<I', out_buf, VGPR_BYTES + i * 4)[0]
  st.vcc = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES)[0]
  st.scc = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES + 4)[0]
+  # Store EXEC in its proper location (index 126)
+  st.sgpr[EXEC_LO.offset] = struct.unpack_from('<I', out_buf, VGPR_BYTES + SGPR_BYTES + 8)[0]
  return st

 def run_program_emu(instructions: list, n_lanes: int = 1) -> WaveState:
@@ -91,10 +155,10 @@ def run_program_emu(instructions: list, n_lanes: int = 1) -> WaveState:
  kernel_buf = (ctypes.c_char * len(code)).from_buffer_copy(code)
  lib_ptr = ctypes.addressof(kernel_buf)

-  set_valid_mem_ranges({(out_addr, OUT_BYTES), (args_ptr, 8)})
  # rsrc2: USER_SGPR_COUNT=2, ENABLE_SGPR_WORKGROUP_ID_X/Y/Z=1, LDS_SIZE=128 (64KB)
  rsrc2 = 0x19c | (128 << 15)
-  result = run_asm(lib_ptr, len(code), 1, 1, 1, n_lanes, 1, 1, args_ptr, rsrc2)
+  scratch_size = 0x10000  # 64KB per lane, matches .amdhsa_private_segment_fixed_size in run_program_hw
+  result = run_asm(lib_ptr, len(code), 1, 1, 1, n_lanes, 1, 1, args_ptr, rsrc2, scratch_size)
  assert result == 0, f"run_asm failed with {result}"

  return parse_output(bytes(out_buf), n_lanes)
@@ -129,6 +193,8 @@ test:
  .amdhsa_user_sgpr_kernarg_segment_ptr 1
  .amdhsa_kernarg_size 8
  .amdhsa_group_segment_fixed_size 65536
+  .amdhsa_private_segment_fixed_size 65536
+  .amdhsa_enable_private_segment 1
 .end_amdhsa_kernel

 .amdgpu_metadata
@@ -141,7 +207,7 @@ amdhsa.kernels:
    .symbol: test.kd
    .kernarg_segment_size: 8
    .group_segment_fixed_size: 65536
-    .private_segment_fixed_size: 0
+    .private_segment_fixed_size: 65536
    .kernarg_segment_align: 8
    .wavefront_size: 32
    .sgpr_count: 96
@@ -155,6 +221,7 @@ amdhsa.kernels:
  prg = AMDProgram(dev, "test", lib)

  out_gpu = dev.allocator.alloc(OUT_BYTES)
+  assert out_gpu.va_addr % 16 == 0, f"buffer not 16-byte aligned: 0x{out_gpu.va_addr:x}"
  prg(out_gpu, global_size=(1, 1, 1), local_size=(n_lanes, 1, 1), wait=True)

  out_buf = bytearray(OUT_BYTES)
@@ -162,8 +229,12 @@ amdhsa.kernels:

  return parse_output(bytes(out_buf), n_lanes)

-def compare_wave_states(emu_st: WaveState, hw_st: WaveState, n_lanes: int, n_vgprs: int = N_VGPRS) -> list[str]:
-  """Compare two WaveStates and return list of differences."""
+def compare_wave_states(emu_st: WaveState, hw_st: WaveState, n_lanes: int, n_vgprs: int = N_VGPRS, ulp_tolerance: int = 0) -> list[str]:
+  """Compare two WaveStates and return list of differences.
+
+  Args:
+    ulp_tolerance: Allow up to this many ULPs difference for float comparisons (0 = exact match required)
+  """
  import math
  diffs = []
  for i in range(n_vgprs):
@@ -174,6 +245,11 @@ def compare_wave_states(emu_st: WaveState, hw_st: WaveState, n_lanes: int, n_vgp
        emu_f, hw_f = _f32(emu_val), _f32(hw_val)
        if math.isnan(emu_f) and math.isnan(hw_f):
          continue
+        # Check ULP difference for floats (only for same-sign values)
+        if ulp_tolerance > 0 and (emu_val < 0x80000000) == (hw_val < 0x80000000):
+          ulp_diff = abs(int(emu_val) - int(hw_val))
+          if ulp_diff <= ulp_tolerance:
+            continue
        diffs.append(f"v[{i}] lane {lane}: emu=0x{emu_val:08x} ({emu_f:.6g}) hw=0x{hw_val:08x} ({hw_f:.6g})")
  for i in range(N_SGPRS):
    emu_val = emu_st.sgpr[i]
@@ -186,16 +262,19 @@ def compare_wave_states(emu_st: WaveState, hw_st: WaveState, n_lanes: int, n_vgp
    diffs.append(f"scc: emu={emu_st.scc} hw={hw_st.scc}")
  return diffs

-def run_program(instructions: list, n_lanes: int = 1) -> WaveState:
+def run_program(instructions: list, n_lanes: int = 1, ulp_tolerance: int = 0) -> WaveState:
  """Run instructions and return WaveState.

  If USE_HW=1, runs on both emulator and hardware, compares results, and raises if they differ.
  Otherwise, runs only on emulator.
+
+  Args:
+    ulp_tolerance: Allow up to this many ULPs difference for float comparisons (0 = exact match required)
  """
  emu_st = run_program_emu(instructions, n_lanes)
  if USE_HW:
    hw_st = run_program_hw(instructions, n_lanes)
-    diffs = compare_wave_states(emu_st, hw_st, n_lanes)
+    diffs = compare_wave_states(emu_st, hw_st, n_lanes, ulp_tolerance=ulp_tolerance)
    if diffs:
      raise AssertionError(f"Emulator vs Hardware mismatch:\n" + "\n".join(diffs))
    return hw_st
@@ -20,7 +20,7 @@ class TestDS2Addr(unittest.TestCase):
      v_mov_b32_e32(v[1], s[0]),
      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=0, offset1=1),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2], offset0=0, offset1=1),
+      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2:3], offset0=0, offset1=1),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -39,9 +39,9 @@ class TestDS2Addr(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0x9ABCDEF0),
      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_B64, addr=v[10], data0=v[0], data1=v[2], vdst=v[0], offset0=0, offset1=2),
+      DS(DSOp.DS_STORE_2ADDR_B64, addr=v[10], data0=v[0:1], data1=v[2:3], vdst=v[0], offset0=0, offset1=2),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4], offset0=0, offset1=2),
+      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4:7], offset0=0, offset1=2),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -64,7 +64,7 @@ class TestDS2AddrMore(unittest.TestCase):
      v_mov_b32_e32(v[1], s[2]),
      DS(DSOp.DS_STORE_2ADDR_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=2, offset1=5),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2], offset0=2, offset1=5),
+      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2:3], offset0=2, offset1=5),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -88,7 +88,7 @@ class TestDS2AddrMore(unittest.TestCase):
      v_mov_b32_e32(v[0], s[2]),
      ds_store_b32(addr=v[10], data0=v[0], offset0=12),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4], offset0=0, offset1=1),
+      DS(DSOp.DS_LOAD_2ADDR_B64, addr=v[10], vdst=v[4:7], offset0=0, offset1=1),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -109,7 +109,7 @@ class TestDS2AddrMore(unittest.TestCase):
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[2], 0xDEADBEEF),
      v_mov_b32_e32(v[4], s[2]),  # Sentinel
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2], offset0=0, offset1=1),
+      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[2:3], offset0=0, offset1=1),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -125,11 +125,11 @@ class TestDS2AddrMore(unittest.TestCase):
      v_mov_b32_e32(v[0], s[2]),
      s_mov_b32(s[2], 0xCAFEBABE),
      v_mov_b32_e32(v[1], s[2]),
-      ds_store_b64(addr=v[10], data0=v[0], offset0=0),
+      ds_store_b64(addr=v[10], data0=v[0:1], offset0=0),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[2], 0x12345678),
      v_mov_b32_e32(v[4], s[2]),  # Sentinel
-      ds_load_b64(addr=v[10], vdst=v[2], offset0=0),
+      ds_load_b64(addr=v[10], vdst=v[2:3], offset0=0),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -138,6 +138,100 @@ class TestDS2AddrMore(unittest.TestCase):
    self.assertEqual(st.vgpr[0][4], 0x12345678, "v4 should be untouched")


+class TestDSB96(unittest.TestCase):
+  """Tests for DS_STORE_B96 and DS_LOAD_B96 (96-bit / 3 dwords)."""
+
+  def test_ds_store_load_b96(self):
+    """DS_STORE_B96 stores 3 VGPRs, DS_LOAD_B96 loads them back."""
+    instructions = [
+      v_mov_b32_e32(v[10], 0),
+      s_mov_b32(s[0], 0x11111111),
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[0], 0x22222222),
+      v_mov_b32_e32(v[1], s[0]),
+      s_mov_b32(s[0], 0x33333333),
+      v_mov_b32_e32(v[2], s[0]),
+      ds_store_b96(addr=v[10], data0=v[0:2]),
+      s_waitcnt(lgkmcnt=0),
+      ds_load_b96(addr=v[10], vdst=v[4:6]),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have first dword")
+    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have second dword")
+    self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should have third dword")
+
+  def test_ds_store_b96_with_offset(self):
+    """DS_STORE_B96 with non-zero offset."""
+    instructions = [
+      v_mov_b32_e32(v[10], 0),
+      s_mov_b32(s[0], 0xAAAAAAAA),
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[0], 0xBBBBBBBB),
+      v_mov_b32_e32(v[1], s[0]),
+      s_mov_b32(s[0], 0xCCCCCCCC),
+      v_mov_b32_e32(v[2], s[0]),
+      DS(DSOp.DS_STORE_B96, addr=v[10], data0=v[0:2], offset0=12),
+      s_waitcnt(lgkmcnt=0),
+      DS(DSOp.DS_LOAD_B96, addr=v[10], vdst=v[4:6], offset0=12),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
+    self.assertEqual(st.vgpr[0][5], 0xBBBBBBBB)
+    self.assertEqual(st.vgpr[0][6], 0xCCCCCCCC)
+
+
+class TestDSB128(unittest.TestCase):
+  """Tests for DS_STORE_B128 and DS_LOAD_B128 (128-bit / 4 dwords)."""
+
+  def test_ds_store_load_b128(self):
+    """DS_STORE_B128 stores 4 VGPRs, DS_LOAD_B128 loads them back."""
+    instructions = [
+      v_mov_b32_e32(v[10], 0),
+      s_mov_b32(s[0], 0x11111111),
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[0], 0x22222222),
+      v_mov_b32_e32(v[1], s[0]),
+      s_mov_b32(s[0], 0x33333333),
+      v_mov_b32_e32(v[2], s[0]),
+      s_mov_b32(s[0], 0x44444444),
+      v_mov_b32_e32(v[3], s[0]),
+      ds_store_b128(addr=v[10], data0=v[0:3]),
+      s_waitcnt(lgkmcnt=0),
+      ds_load_b128(addr=v[10], vdst=v[4:7]),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][4], 0x11111111, "v4 should have first dword")
+    self.assertEqual(st.vgpr[0][5], 0x22222222, "v5 should have second dword")
+    self.assertEqual(st.vgpr[0][6], 0x33333333, "v6 should have third dword")
+    self.assertEqual(st.vgpr[0][7], 0x44444444, "v7 should have fourth dword")
+
+  def test_ds_store_b128_with_offset(self):
+    """DS_STORE_B128 with non-zero offset."""
+    instructions = [
+      v_mov_b32_e32(v[10], 0),
+      s_mov_b32(s[0], 0xAAAAAAAA),
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[0], 0xBBBBBBBB),
+      v_mov_b32_e32(v[1], s[0]),
+      s_mov_b32(s[0], 0xCCCCCCCC),
+      v_mov_b32_e32(v[2], s[0]),
+      s_mov_b32(s[0], 0xDDDDDDDD),
+      v_mov_b32_e32(v[3], s[0]),
+      DS(DSOp.DS_STORE_B128, addr=v[10], data0=v[0:3], offset0=16),
+      s_waitcnt(lgkmcnt=0),
+      DS(DSOp.DS_LOAD_B128, addr=v[10], vdst=v[4:7], offset0=16),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
+    self.assertEqual(st.vgpr[0][5], 0xBBBBBBBB)
+    self.assertEqual(st.vgpr[0][6], 0xCCCCCCCC)
+    self.assertEqual(st.vgpr[0][7], 0xDDDDDDDD)
+
+
 class TestDSAtomic(unittest.TestCase):
  """Tests for DS atomic operations."""

@@ -452,7 +546,7 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[1], s[0]),
      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B32, addr=v[10], data0=v[0], data1=v[1], vdst=v[0], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[2], offset0=1, offset1=2),
+      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[2:3], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -471,9 +565,9 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0x9ABCDEF0),
      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0], data1=v[2], vdst=v[0], offset0=1, offset1=2),
+      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0:1], data1=v[2:3], vdst=v[0], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[4], offset0=1, offset1=2),
+      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[4:7], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -496,9 +590,9 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0xBBBBBBBB),
      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4], offset0=0, offset1=1),
+      DS(DSOp.DS_STOREXCHG_2ADDR_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4:5], offset0=0, offset1=1),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[6], offset0=0, offset1=1),
+      DS(DSOp.DS_LOAD_2ADDR_B32, addr=v[10], vdst=v[6:7], offset0=0, offset1=1),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -516,15 +610,15 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[0], s[0]),   # initial low
      s_mov_b32(s[0], 0xCAFEBABE),
      v_mov_b32_e32(v[1], s[0]),   # initial high
-      DS(DSOp.DS_STORE_B64, addr=v[10], data0=v[0], vdst=v[0], offset0=0),
+      DS(DSOp.DS_STORE_B64, addr=v[10], data0=v[0:1], vdst=v[0], offset0=0),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[0], 0x12345678),
      v_mov_b32_e32(v[2], s[0]),   # new low
      s_mov_b32(s[0], 0x9ABCDEF0),
      v_mov_b32_e32(v[3], s[0]),   # new high
-      DS(DSOp.DS_STOREXCHG_RTN_B64, addr=v[10], data0=v[2], vdst=v[4], offset0=0),
+      DS(DSOp.DS_STOREXCHG_RTN_B64, addr=v[10], data0=v[2:3], vdst=v[4:5], offset0=0),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_B64, addr=v[10], vdst=v[6], offset0=0),
+      DS(DSOp.DS_LOAD_B64, addr=v[10], vdst=v[6:7], offset0=0),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -541,9 +635,9 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[0], s[0]),
      s_mov_b32(s[0], 0x22222222),
      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0], data1=v[0], vdst=v[0], offset0=1, offset1=2),
+      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0:1], data1=v[0:1], vdst=v[0], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[2], offset0=1, offset1=2),
+      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B64, addr=v[10], vdst=v[2:5], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -566,9 +660,9 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0xBBBBBBBB),
      v_mov_b32_e32(v[3], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4], offset0=1, offset1=2),
+      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B32, addr=v[10], data0=v[2], data1=v[3], vdst=v[4:5], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
-      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[6], offset0=1, offset1=2),
+      DS(DSOp.DS_LOAD_2ADDR_STRIDE64_B32, addr=v[10], vdst=v[6:7], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -585,13 +679,13 @@ class TestDS2AddrStride64(unittest.TestCase):
      v_mov_b32_e32(v[0], s[0]),
      s_mov_b32(s[0], 0x22222222),
      v_mov_b32_e32(v[1], s[0]),
-      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0], data1=v[0], vdst=v[0], offset0=1, offset1=2),
+      DS(DSOp.DS_STORE_2ADDR_STRIDE64_B64, addr=v[10], data0=v[0:1], data1=v[0:1], vdst=v[0], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[0], 0xAAAAAAAA),
      v_mov_b32_e32(v[6], s[0]),
      s_mov_b32(s[0], 0xBBBBBBBB),
      v_mov_b32_e32(v[7], s[0]),
-      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64, addr=v[10], data0=v[6], data1=v[6], vdst=v[8], offset0=1, offset1=2),
+      DS(DSOp.DS_STOREXCHG_2ADDR_STRIDE64_RTN_B64, addr=v[10], data0=v[6:7], data1=v[6:7], vdst=v[8:11], offset0=1, offset1=2),
      s_waitcnt(lgkmcnt=0),
    ]
    st = run_program(instructions, n_lanes=1)
@@ -625,5 +719,47 @@ class TestAtomicOrdering(unittest.TestCase):
    self.assertEqual(st.vgpr[0][4], 150, "Final value should be 150")


+class TestDsPermute(unittest.TestCase):
+  """Tests for DS_PERMUTE_B32 and DS_BPERMUTE_B32 instructions."""
+
+  def test_ds_permute_b32_identity(self):
+    """DS_PERMUTE_B32 with identity permutation (lane 0 sends to lane 0)."""
+    # For simplicity, test with single lane
+    instructions = [
+      v_mov_b32_e32(v[0], 0),  # addr = 0 (lane 0)
+      v_mov_b32_e32(v[1], 0xDEADBEEF),  # data
+      ds_permute_b32(v[2], v[0], v[1]),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Lane 0 sends to lane 0, so lane 0 gets 0xDEADBEEF
+    self.assertEqual(st.vgpr[0][2], 0xDEADBEEF)
+
+  def test_ds_bpermute_b32_identity(self):
+    """DS_BPERMUTE_B32 with identity permutation (each lane reads from itself)."""
+    instructions = [
+      v_mov_b32_e32(v[0], 0),  # addr = 0 (read from lane 0)
+      v_mov_b32_e32(v[1], 0xCAFEBABE),  # data in lane 0
+      ds_bpermute_b32(v[2], v[0], v[1]),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Lane 0 reads from lane 0's v[1]
+    self.assertEqual(st.vgpr[0][2], 0xCAFEBABE)
+
+  def test_ds_permute_b32_broadcast(self):
+    """DS_PERMUTE_B32 broadcast - all lanes send to lane 0."""
+    # With 4 lanes, all sending to lane 0, highest lane wins
+    instructions = [
+      v_mov_b32_e32(v[0], 0),  # All lanes send to addr 0 (lane 0)
+      v_mov_b32_e32(v[1], 0x11111111),  # All lanes send same data
+      ds_permute_b32(v[2], v[0], v[1]),
+      s_waitcnt(lgkmcnt=0),
+    ]
+    st = run_program(instructions, n_lanes=4)
+    # Lane 0 receives data (highest numbered active lane wins)
+    self.assertEqual(st.vgpr[0][2], 0x11111111)
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -11,7 +11,7 @@ class TestFlatAtomic(unittest.TestCase):
  def _make_test(self, setup_instrs, atomic_instr, check_fn, test_offset=2000):
    """Helper to create atomic test instructions."""
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -30,12 +30,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 100),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 50),
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 100)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -46,12 +46,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 0xAAAAAAAA),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0xBBBBBBBB),
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -62,12 +62,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 0xFF00FF00),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0xFFFF0000),
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_AND_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_AND_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 0xFF00FF00)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -78,12 +78,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 0x00FF0000),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0x0000FF00),
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_OR_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_OR_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 0x00FF0000)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -94,12 +94,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 10),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 100),  # threshold
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 10)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -110,12 +110,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 10),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 100),
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_DEC_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_DEC_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 10)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -126,12 +126,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 100),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 30),
      v_mov_b32_e32(v[3], s[0]),  # sub 30
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SUB_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_SUB_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 100, "v4 should have old value (100)")
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -142,12 +142,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 0xAAAAAAAA),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0xFFFFFFFF),
      v_mov_b32_e32(v[3], s[0]),  # XOR mask
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_XOR_B32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_XOR_B32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 0xAAAAAAAA, "v4 should have old value")
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -158,12 +158,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 100),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 50),
      v_mov_b32_e32(v[3], s[0]),  # compare value (smaller)
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_MIN_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_MIN_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 100, "v4 should have old value (100)")
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -174,12 +174,12 @@ class TestFlatAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 50),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 100),
      v_mov_b32_e32(v[3], s[0]),  # compare value (larger)
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_MAX_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_MAX_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 50, "v4 should have old value (50)")
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -193,14 +193,14 @@ class TestFlatAtomic(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0xCAFEBABE),
      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      # Threshold: 0xFFFFFFFF_FFFFFFFF
      s_mov_b32(s[0], 0xFFFFFFFF),
      v_mov_b32_e32(v[4], s[0]),
      v_mov_b32_e32(v[5], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_INC_U64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][6], 0xDEADBEEF, "v6 should have old value low dword")
      self.assertEqual(st.vgpr[0][7], 0xCAFEBABE, "v7 should have old value high dword")
@@ -214,14 +214,14 @@ class TestFlatAtomic(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0x22222222),
      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0x00000001),  # add 1
      v_mov_b32_e32(v[4], s[0]),
      s_mov_b32(s[0], 0x00000000),
      v_mov_b32_e32(v[5], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_ADD_U64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][6], 0x11111111, "v6 should have old value low")
      self.assertEqual(st.vgpr[0][7], 0x22222222, "v7 should have old value high")
@@ -235,14 +235,14 @@ class TestFlatAtomic(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0xBBBBBBBB),
      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0xCCCCCCCC),
      v_mov_b32_e32(v[4], s[0]),
      s_mov_b32(s[0], 0xDDDDDDDD),
      v_mov_b32_e32(v[5], s[0]),
    ]
-    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
+    atomic = FLAT(FLATOp.FLAT_ATOMIC_SWAP_B64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][6], 0xAAAAAAAA, "v6 should have old value low")
      self.assertEqual(st.vgpr[0][7], 0xBBBBBBBB, "v7 should have old value high")
@@ -256,15 +256,15 @@ class TestFlatLoad(unittest.TestCase):
    """FLAT_LOAD_B32 loads 32-bit value correctly."""
    TEST_OFFSET = 2000
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
      s_mov_b32(s[0], 0xDEADBEEF),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B32, addr=v[0], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      FLAT(FLATOp.FLAT_LOAD_B32, addr=v[0:1], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], 0),
      v_mov_b32_e32(v[1], 0),
@@ -278,7 +278,7 @@ class TestFlatLoad(unittest.TestCase):
    """FLAT_LOAD_B64 loads 64-bit value correctly."""
    TEST_OFFSET = 2000
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -286,9 +286,9 @@ class TestFlatLoad(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0xCAFEBABE),
      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B64, addr=v[0], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      FLAT(FLATOp.FLAT_LOAD_B64, addr=v[0:1], vdst=v[4:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], 0),
      v_mov_b32_e32(v[1], 0),
@@ -303,7 +303,7 @@ class TestFlatLoad(unittest.TestCase):
    """FLAT_LOAD_B96 loads 96-bit (3 dword) value correctly."""
    TEST_OFFSET = 2000
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -313,9 +313,9 @@ class TestFlatLoad(unittest.TestCase):
      v_mov_b32_e32(v[3], s[0]),
      s_mov_b32(s[0], 0x33333333),
      v_mov_b32_e32(v[4], s[0]),
-      global_store_b96(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b96(addr=v[0:1], data=v[2:4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B96, addr=v[0], vdst=v[5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      FLAT(FLATOp.FLAT_LOAD_B96, addr=v[0:1], vdst=v[5:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], 0),
      v_mov_b32_e32(v[1], 0),
@@ -331,7 +331,7 @@ class TestFlatLoad(unittest.TestCase):
    """FLAT_LOAD_B128 loads 128-bit value correctly."""
    TEST_OFFSET = 2000
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -343,9 +343,9 @@ class TestFlatLoad(unittest.TestCase):
      v_mov_b32_e32(v[4], s[0]),
      s_mov_b32(s[0], 0x44444444),
      v_mov_b32_e32(v[5], s[0]),
-      global_store_b128(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b128(addr=v[0:1], data=v[2:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(FLATOp.FLAT_LOAD_B128, addr=v[0], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      FLAT(FLATOp.FLAT_LOAD_B128, addr=v[0:1], vdst=v[6:9], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], 0),
      v_mov_b32_e32(v[1], 0),
@@ -11,7 +11,7 @@ class TestGlobalAtomic(unittest.TestCase):
  def _make_test(self, setup_instrs, atomic_instr, check_fn, test_offset=2000):
    """Helper to create atomic test instructions."""
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -30,12 +30,12 @@ class TestGlobalAtomic(unittest.TestCase):
    setup = [
      s_mov_b32(s[0], 100),
      v_mov_b32_e32(v[2], s[0]),
-      global_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 50),
      v_mov_b32_e32(v[3], s[0]),
    ]
-    atomic = FLAT(GLOBALOp.GLOBAL_ATOMIC_ADD_U32, addr=v[0], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1, seg=2)
+    atomic = GLOBAL(GLOBALOp.GLOBAL_ATOMIC_ADD_U32, addr=v[0:1], data=v[3], vdst=v[4], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][4], 100)
    self._make_test(setup, atomic, check, TEST_OFFSET)
@@ -48,14 +48,14 @@ class TestGlobalAtomic(unittest.TestCase):
      v_mov_b32_e32(v[2], s[0]),
      s_mov_b32(s[0], 0x00000000),
      v_mov_b32_e32(v[3], s[0]),
-      global_store_b64(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b64(addr=v[0:1], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[0], 0x00000001),
      v_mov_b32_e32(v[4], s[0]),
      s_mov_b32(s[0], 0x00000000),
      v_mov_b32_e32(v[5], s[0]),
    ]
-    atomic = FLAT(GLOBALOp.GLOBAL_ATOMIC_ADD_U64, addr=v[0], data=v[4], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1, seg=2)
+    atomic = GLOBAL(GLOBALOp.GLOBAL_ATOMIC_ADD_U64, addr=v[0:1], data=v[4:5], vdst=v[6:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET, glc=1)
    def check(st):
      self.assertEqual(st.vgpr[0][6], 0xFFFFFFFF)
      self.assertEqual(st.vgpr[0][7], 0x00000000)
@@ -69,7 +69,7 @@ class TestGlobalLoad(unittest.TestCase):
    """GLOBAL_LOAD_B96 loads 96-bit value correctly."""
    TEST_OFFSET = 2000
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -79,9 +79,9 @@ class TestGlobalLoad(unittest.TestCase):
      v_mov_b32_e32(v[3], s[0]),
      s_mov_b32(s[0], 0xCCCCCCCC),
      v_mov_b32_e32(v[4], s[0]),
-      global_store_b96(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b96(addr=v[0:1], data=v[2:4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_B96, addr=v[0], vdst=v[5], saddr=SrcEnum.NULL, offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B96, addr=v[0:1], vdst=v[5:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], 0),
      v_mov_b32_e32(v[1], 0),
@@ -97,7 +97,7 @@ class TestGlobalLoad(unittest.TestCase):
    """GLOBAL_LOAD_B128 loads 128-bit value correctly."""
    TEST_OFFSET = 2000
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
@@ -109,9 +109,9 @@ class TestGlobalLoad(unittest.TestCase):
      v_mov_b32_e32(v[4], s[0]),
      s_mov_b32(s[0], 0x9ABCDEF0),
      v_mov_b32_e32(v[5], s[0]),
-      global_store_b128(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b128(addr=v[0:1], data=v[2:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_B128, addr=v[0], vdst=v[6], saddr=SrcEnum.NULL, offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B128, addr=v[0:1], vdst=v[6:9], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], 0),
      v_mov_b32_e32(v[1], 0),
@@ -128,20 +128,183 @@ class TestGlobalLoad(unittest.TestCase):
 class TestGlobalStore(unittest.TestCase):
  """Tests for GLOBAL store instructions."""

+  def test_global_store_b8_basic(self):
+    """GLOBAL_STORE_B8 stores a single byte from VDATA[7:0]."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      # First store 0xDEADBEEF to memory
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Now store single byte 0x42 to same address (should only change byte 0)
+      v_mov_b32_e32(v[2], 0x42),
+      global_store_b8(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Read back and check
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Only byte 0 should change from 0xEF to 0x42
+    self.assertEqual(st.vgpr[0][0], 0xDEADBE42, "Only byte 0 should be modified")
+
+  def test_global_store_b8_byte1(self):
+    """GLOBAL_STORE_B8 at offset+1 stores to byte 1."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[2], 0x42),
+      global_store_b8(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+1),
+      s_waitcnt(vmcnt=0),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xDEAD42EF, "Only byte 1 should be modified")
+
+  def test_global_store_b16_basic(self):
+    """GLOBAL_STORE_B16 stores a 16-bit value from VDATA[15:0]."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      s_mov_b32(s[4], 0xCAFE),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xDEADCAFE, "Only lower 16 bits should be modified")
+
+  def test_global_store_b16_high_half(self):
+    """GLOBAL_STORE_B16 at offset+2 stores to high 16 bits."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      s_mov_b32(s[4], 0xCAFE),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+2),
+      s_waitcnt(vmcnt=0),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xCAFEBEEF, "Only upper 16 bits should be modified")
+
+  def test_global_store_b16_byte_offset_1(self):
+    """GLOBAL_STORE_B16 at byte offset 1 stores bytes 1-2 within the same word."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDDCCBBAA),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Store 0xBEEF at byte offset 1 (bytes 1-2)
+      s_mov_b32(s[4], 0xBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+1),
+      s_waitcnt(vmcnt=0),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Bytes 1-2 should be 0xBEEF (0xEF at byte 1, 0xBE at byte 2)
+    # Original: 0xDDCCBBAA -> bytes [AA, BB, CC, DD]
+    # After:    0xDDBEEFAA -> bytes [AA, EF, BE, DD]
+    self.assertEqual(st.vgpr[0][0], 0xDDBEEFAA, "Bytes 1-2 should be 0xBEEF")
+
+  def test_global_store_b16_cross_word_boundary(self):
+    """GLOBAL_STORE_B16 at byte offset 3 crosses word boundary (byte 3 of word N, byte 0 of word N+1)."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Initialize two consecutive words
+      s_mov_b32(s[4], 0xDDCCBBAA),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_mov_b32(s[4], 0x44332211),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      # Store 0xBEEF at byte offset 3 (crosses word boundary)
+      # Low byte (0xEF) goes to byte 3 of first word
+      # High byte (0xBE) goes to byte 0 of second word
+      s_mov_b32(s[4], 0xBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b16(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+3),
+      s_waitcnt(vmcnt=0),
+      # Load back both words
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[4], data=v[4], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      v_mov_b32_e32(v[1], v[4]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # First word: 0xDDCCBBAA -> 0xEFCCBBAA (byte 3 becomes 0xEF)
+    # Second word: 0x44332211 -> 0x443322BE (byte 0 becomes 0xBE)
+    self.assertEqual(st.vgpr[0][0], 0xEFCCBBAA, "Byte 3 of first word should be 0xEF")
+    self.assertEqual(st.vgpr[0][1], 0x443322BE, "Byte 0 of second word should be 0xBE")
+
  def test_global_store_b64_basic(self):
    """GLOBAL_STORE_B64 stores 8 bytes from v[n:n+1] to memory."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0xDEADBEEF),
      s_mov_b32(s[5], 0xCAFEBABE),
      v_mov_b32_e32(v[2], s[4]),
      v_mov_b32_e32(v[3], s[5]),
      v_mov_b32_e32(v[0], 0),
-      global_store_b64(addr=v[0], data=v[2], saddr=s[2], offset=TEST_OFFSET),
+      global_store_b64(addr=v[0], data=v[2:3], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_B64, addr=v[0], vdst=v[4], data=v[4], saddr=s[2], offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B64, addr=v[0], vdst=v[4:5], data=v[4:5], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[4]),
      v_mov_b32_e32(v[1], v[5]),
@@ -160,17 +323,17 @@ class TestD16HiLoads(unittest.TestCase):
    """GLOBAL_LOAD_D16_HI_B16 must preserve low 16 bits of destination."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      v_mov_b32_e32(v[0], s[2]),
      v_mov_b32_e32(v[1], s[3]),
      s_mov_b32(s[4], 0xCAFE),
      v_mov_b32_e32(v[2], s[4]),
-      global_store_b16(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      global_store_b16(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[4], 0x0000BEEF),
      v_mov_b32_e32(v[3], s[4]),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[0], vdst=v[3], data=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[0:1], vdst=v[3], data=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[3]),
      v_mov_b32_e32(v[1], 0),
@@ -185,17 +348,17 @@ class TestD16HiLoads(unittest.TestCase):
    """GLOBAL_LOAD_D16_HI_B16 where data field differs from vdst."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0xCAFE),
      v_mov_b32_e32(v[2], s[4]),
      v_mov_b32_e32(v[3], 0),
-      global_store_b16(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
+      global_store_b16(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[4], 0x0000DEAD),
      v_mov_b32_e32(v[0], s[4]),  # data field - should NOT affect result
      v_mov_b32_e32(v[1], 0),     # vdst - low bits should be preserved
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2], offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[1]),
      s_mov_b32(s[2], 0),
@@ -209,19 +372,19 @@ class TestD16HiLoads(unittest.TestCase):
    """GLOBAL_LOAD_D16_HI_U8 where data field differs from vdst."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0xAB),
      v_mov_b32_e32(v[2], s[4]),
      v_mov_b32_e32(v[3], 0),
-      global_store_b8(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
+      global_store_b8(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[4], 0x0000DEAD),
      v_mov_b32_e32(v[4], s[4]),  # data field
      s_mov_b32(s[4], 0x0000BEEF),
      v_mov_b32_e32(v[5], s[4]),  # vdst
      v_mov_b32_e32(v[3], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_U8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2], offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_U8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[5]),
      s_mov_b32(s[2], 0),
@@ -235,15 +398,15 @@ class TestD16HiLoads(unittest.TestCase):
    """GLOBAL_LOAD_D16_HI_B16 with same register for addr and vdst, addr value=0."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0xCAFE),
      v_mov_b32_e32(v[2], s[4]),
      v_mov_b32_e32(v[3], 0),
-      global_store_b16(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
+      global_store_b16(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[1], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2], offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[1]),
      s_mov_b32(s[2], 0),
@@ -257,13 +420,13 @@ class TestD16HiLoads(unittest.TestCase):
    """Exact pattern from tril() failure: data=v0 differs from vdst=v1."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0x01010101),
      v_mov_b32_e32(v[10], s[4]),
      v_mov_b32_e32(v[3], 0),
-      global_store_b32(addr=v[3], data=v[10], saddr=s[2], offset=TEST_OFFSET),
-      global_store_b32(addr=v[3], data=v[10], saddr=s[2], offset=TEST_OFFSET+4),
+      global_store_b32(addr=v[3], data=v[10], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b32(addr=v[3], data=v[10], saddr=s[2:3], offset=TEST_OFFSET+4),
      s_waitcnt(vmcnt=0),
      # Set v[0] to 0x0101 (simulating prior u16 load result)
      s_mov_b32(s[4], 0x0101),
@@ -271,7 +434,7 @@ class TestD16HiLoads(unittest.TestCase):
      # Set v[1] to 0
      v_mov_b32_e32(v[1], 0),
      # Load using v[1] as addr AND vdst, but v[0] as data
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2], offset=TEST_OFFSET+6, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[0], saddr=s[2:3], offset=TEST_OFFSET+6),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[1]),
      s_mov_b32(s[2], 0),
@@ -286,19 +449,19 @@ class TestD16HiLoads(unittest.TestCase):
    """GLOBAL_LOAD_D16_HI_I8 where data field differs from vdst."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0x80),  # negative signed byte = -128
      v_mov_b32_e32(v[2], s[4]),
      v_mov_b32_e32(v[3], 0),
-      global_store_b8(addr=v[3], data=v[2], saddr=s[2], offset=TEST_OFFSET),
+      global_store_b8(addr=v[3], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      s_mov_b32(s[4], 0x0000DEAD),
      v_mov_b32_e32(v[4], s[4]),  # data field
      s_mov_b32(s[4], 0x0000BEEF),
      v_mov_b32_e32(v[5], s[4]),  # vdst
      v_mov_b32_e32(v[3], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_I8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2], offset=TEST_OFFSET, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_I8, addr=v[3], vdst=v[5], data=v[4], saddr=s[2:3], offset=TEST_OFFSET),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[5]),
      s_mov_b32(s[2], 0),
@@ -313,7 +476,7 @@ class TestD16HiLoads(unittest.TestCase):
    """Test the exact pattern from tril() kernel that was failing."""
    TEST_OFFSET = 256
    instructions = [
-      s_load_b64(s[2:3], s[80], 0, soffset=SrcEnum.NULL),
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
      s_waitcnt(lgkmcnt=0),
      s_mov_b32(s[4], 0x01010101),
      v_mov_b32_e32(v[10], s[4]),
@@ -321,16 +484,16 @@ class TestD16HiLoads(unittest.TestCase):
      s_mov_b32(s[4], 0x01),
      v_mov_b32_e32(v[12], s[4]),
      v_mov_b32_e32(v[0], 0),
-      global_store_b64(addr=v[0], data=v[10], saddr=s[2], offset=TEST_OFFSET),
-      global_store_b8(addr=v[0], data=v[12], saddr=s[2], offset=TEST_OFFSET+8),
+      global_store_b64(addr=v[0], data=v[10:11], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b8(addr=v[0], data=v[12], saddr=s[2:3], offset=TEST_OFFSET+8),
      s_waitcnt(vmcnt=0),

      v_mov_b32_e32(v[2], 0),
      v_mov_b32_e32(v[1], 0),
-      FLAT(GLOBALOp.GLOBAL_LOAD_U16, addr=v[2], vdst=v[0], data=v[0], saddr=s[2], offset=TEST_OFFSET+3, seg=2),
-      FLAT(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2], offset=TEST_OFFSET+6, seg=2),
-      FLAT(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[3], data=v[3], saddr=s[2], offset=TEST_OFFSET, seg=2),
-      FLAT(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[4], data=v[4], saddr=s[2], offset=TEST_OFFSET+8, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_U16, addr=v[2], vdst=v[0], data=v[0], saddr=s[2:3], offset=TEST_OFFSET+3),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_D16_HI_B16, addr=v[1], vdst=v[1], data=v[1], saddr=s[2:3], offset=TEST_OFFSET+6),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[3], data=v[3], saddr=s[2:3], offset=TEST_OFFSET),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_U8, addr=v[2], vdst=v[4], data=v[4], saddr=s[2:3], offset=TEST_OFFSET+8),
      s_waitcnt(vmcnt=0),

      v_and_b32_e32(v[5], 0xffff, v[0]),
@@ -339,10 +502,10 @@ class TestD16HiLoads(unittest.TestCase):
      v_or_b32_e32(v[0], v[3], v[0]),
      v_or_b32_e32(v[1], v[5], v[1]),

-      global_store_b64(addr=v[2], data=v[0], saddr=s[2], offset=TEST_OFFSET+16),
+      global_store_b64(addr=v[2], data=v[0:1], saddr=s[2:3], offset=TEST_OFFSET+16),
      s_waitcnt(vmcnt=0),

-      FLAT(GLOBALOp.GLOBAL_LOAD_B64, addr=v[2], vdst=v[6], data=v[6], saddr=s[2], offset=TEST_OFFSET+16, seg=2),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B64, addr=v[2], vdst=v[6:7], data=v[6:7], saddr=s[2:3], offset=TEST_OFFSET+16),
      s_waitcnt(vmcnt=0),
      v_mov_b32_e32(v[0], v[6]),
      v_mov_b32_e32(v[1], v[7]),
@@ -360,5 +523,157 @@ class TestD16HiLoads(unittest.TestCase):
    self.assertEqual(byte5, 0x00, f"byte5: expected 0x00, got 0x{byte5:02x}")


+class TestGlobalOffset(unittest.TestCase):
+  """Tests for GLOBAL instructions with different offsets.
+
+  These tests verify that instruction deduplication correctly handles different offset values.
+  If offset is made dynamic incorrectly, instructions with different offsets may load/store wrong data.
+  """
+
+  def test_global_load_different_offsets(self):
+    """Load from two different offsets and verify correct values."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+      # Store 0xAAAAAAAA at offset 100
+      s_mov_b32(s[0], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=100),
+      # Store 0xBBBBBBBB at offset 200
+      s_mov_b32(s[0], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=200),
+      s_waitcnt(vmcnt=0),
+      # Load from offset 100 -> should get 0xAAAAAAAA
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[3], saddr=SrcEnum.NULL, offset=100),
+      # Load from offset 200 -> should get 0xBBBBBBBB
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[4], saddr=SrcEnum.NULL, offset=200),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      v_mov_b32_e32(v[1], v[4]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, f"offset 100: expected 0xAAAAAAAA, got 0x{st.vgpr[0][0]:08x}")
+    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB, f"offset 200: expected 0xBBBBBBBB, got 0x{st.vgpr[0][1]:08x}")
+
+  def test_global_store_different_offsets(self):
+    """Store to two different offsets and verify correct values."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+      # Store 0x11111111 at offset 300
+      s_mov_b32(s[0], 0x11111111),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=300),
+      # Store 0x22222222 at offset 400
+      s_mov_b32(s[0], 0x22222222),
+      v_mov_b32_e32(v[3], s[0]),
+      global_store_b32(addr=v[0:1], data=v[3], saddr=SrcEnum.NULL, offset=400),
+      s_waitcnt(vmcnt=0),
+      # Load back to verify
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[4], saddr=SrcEnum.NULL, offset=300),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0:1], vdst=v[5], saddr=SrcEnum.NULL, offset=400),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[4]),
+      v_mov_b32_e32(v[1], v[5]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x11111111, f"offset 300: expected 0x11111111, got 0x{st.vgpr[0][0]:08x}")
+    self.assertEqual(st.vgpr[0][1], 0x22222222, f"offset 400: expected 0x22222222, got 0x{st.vgpr[0][1]:08x}")
+
+  def test_global_negative_offset_no_saddr(self):
+    """Test negative offset without saddr (VGPR pair for address).
+    Store 0xAAAA at offset 100, 0xBBBB at offset 200.
+    Load with offset -100 from vaddr pointing to base+200 -> should get 0xAAAA (at 100).
+    Load with offset -100 from vaddr pointing to base+300 -> should get 0xBBBB (at 200)."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+      # Store 0xAAAAAAAA at offset 100, 0xBBBBBBBB at offset 200
+      s_mov_b32(s[0], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=100),
+      s_mov_b32(s[0], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=SrcEnum.NULL, offset=200),
+      s_waitcnt(vmcnt=0),
+      # vaddr = base+200, load with offset -100 -> should get value at 100
+      s_add_u32(s[4], s[2], 200),
+      s_addc_u32(s[5], s[3], 0),
+      v_mov_b32_e32(v[4], s[4]),
+      v_mov_b32_e32(v[5], s[5]),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[4:5], vdst=v[6], saddr=SrcEnum.NULL, offset=-100),
+      # vaddr = base+300, load with offset -100 -> should get value at 200
+      s_add_u32(s[4], s[2], 300),
+      s_addc_u32(s[5], s[3], 0),
+      v_mov_b32_e32(v[4], s[4]),
+      v_mov_b32_e32(v[5], s[5]),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[4:5], vdst=v[7], saddr=SrcEnum.NULL, offset=-100),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[6]),
+      v_mov_b32_e32(v[1], v[7]),
+      v_mov_b32_e32(v[4], 0),
+      v_mov_b32_e32(v[5], 0),
+      v_mov_b32_e32(v[6], 0),
+      v_mov_b32_e32(v[7], 0),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+      s_mov_b32(s[4], 0),
+      s_mov_b32(s[5], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, f"offset 200-100=100: expected 0xAAAAAAAA, got 0x{st.vgpr[0][0]:08x}")
+    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB, f"offset 300-100=200: expected 0xBBBBBBBB, got 0x{st.vgpr[0][1]:08x}")
+
+  def test_global_negative_offset_with_saddr(self):
+    """Test negative offset with saddr (SGPR pair for base address).
+    Store 0xAAAA at offset 100, 0xBBBB at offset 200.
+    Load with offset -100 from saddr pointing to base+200 -> should get 0xAAAA (at 100).
+    Load with offset -100 from saddr pointing to base+300 -> should get 0xBBBB (at 200)."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      # Store 0xAAAAAAAA at offset 100, 0xBBBBBBBB at offset 200
+      s_mov_b32(s[0], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=100),
+      s_mov_b32(s[0], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[0]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=200),
+      s_waitcnt(vmcnt=0),
+      # saddr = base+200, load with offset -100 -> should get value at 100
+      s_add_u32(s[4], s[2], 200),
+      s_addc_u32(s[5], s[3], 0),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[6], saddr=s[4:5], offset=-100),
+      # saddr = base+300, load with offset -100 -> should get value at 200
+      s_add_u32(s[4], s[2], 300),
+      s_addc_u32(s[5], s[3], 0),
+      GLOBAL(GLOBALOp.GLOBAL_LOAD_B32, addr=v[0], vdst=v[7], saddr=s[4:5], offset=-100),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[6]),
+      v_mov_b32_e32(v[1], v[7]),
+      v_mov_b32_e32(v[6], 0),
+      v_mov_b32_e32(v[7], 0),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+      s_mov_b32(s[4], 0),
+      s_mov_b32(s[5], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, f"offset 200-100=100: expected 0xAAAAAAAA, got 0x{st.vgpr[0][0]:08x}")
+    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB, f"offset 300-100=200: expected 0xBBBBBBBB, got 0x{st.vgpr[0][1]:08x}")
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -0,0 +1,355 @@
+"""Tests for SCRATCH instructions - scratch (private) memory operations.
+
+Includes: scratch_load_*, scratch_store_*
+"""
+import unittest
+from extra.assembly.amd.test.hw.helpers import *
+
+class TestScratchStore(unittest.TestCase):
+  """Tests for SCRATCH store instructions."""
+
+  def test_scratch_store_b32_basic(self):
+    """SCRATCH_STORE_B32 stores 32-bit value to scratch memory."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      # Store via scratch
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Load back via scratch
+      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
+
+  def test_scratch_store_b64_basic(self):
+    """SCRATCH_STORE_B64 stores 64-bit value to scratch memory."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      s_mov_b32(s[5], 0xCAFEBABE),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[3], s[5]),
+      v_mov_b32_e32(v[0], 0),
+      scratch_store_b64(addr=v[0], data=v[2:3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_b64(addr=v[0], vdst=v[4:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[4]),
+      v_mov_b32_e32(v[1], v[5]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
+    self.assertEqual(st.vgpr[0][1], 0xCAFEBABE)
+
+  def test_scratch_store_b8_basic(self):
+    """SCRATCH_STORE_B8 stores single byte to scratch memory."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      # First store full word
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Store single byte
+      v_mov_b32_e32(v[2], 0x42),
+      scratch_store_b8(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Load back
+      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Only byte 0 should change from 0xEF to 0x42
+    self.assertEqual(st.vgpr[0][0], 0xDEADBE42)
+
+  def test_scratch_store_b16_basic(self):
+    """SCRATCH_STORE_B16 stores 16-bit value to scratch memory."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[0], 0),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      s_mov_b32(s[4], 0xCAFE),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b16(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xDEADCAFE)
+
+
+class TestScratchLoad(unittest.TestCase):
+  """Tests for SCRATCH load instructions."""
+
+  def test_scratch_load_b96(self):
+    """SCRATCH_LOAD_B96 loads 96-bit value correctly."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[4]),
+      s_mov_b32(s[4], 0xBBBBBBBB),
+      v_mov_b32_e32(v[3], s[4]),
+      s_mov_b32(s[4], 0xCCCCCCCC),
+      v_mov_b32_e32(v[4], s[4]),
+      scratch_store_b96(addr=v[0], data=v[2:4], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_b96(addr=v[0], vdst=v[5:7], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[5]),
+      v_mov_b32_e32(v[1], v[6]),
+      v_mov_b32_e32(v[2], v[7]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA)
+    self.assertEqual(st.vgpr[0][1], 0xBBBBBBBB)
+    self.assertEqual(st.vgpr[0][2], 0xCCCCCCCC)
+
+  def test_scratch_load_b128(self):
+    """SCRATCH_LOAD_B128 loads 128-bit value correctly."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[4]),
+      s_mov_b32(s[4], 0xCAFEBABE),
+      v_mov_b32_e32(v[3], s[4]),
+      s_mov_b32(s[4], 0x12345678),
+      v_mov_b32_e32(v[4], s[4]),
+      s_mov_b32(s[4], 0x9ABCDEF0),
+      v_mov_b32_e32(v[5], s[4]),
+      scratch_store_b128(addr=v[0], data=v[2:5], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_b128(addr=v[0], vdst=v[6:9], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[6]),
+      v_mov_b32_e32(v[1], v[7]),
+      v_mov_b32_e32(v[2], v[8]),
+      v_mov_b32_e32(v[3], v[9]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xDEADBEEF)
+    self.assertEqual(st.vgpr[0][1], 0xCAFEBABE)
+    self.assertEqual(st.vgpr[0][2], 0x12345678)
+    self.assertEqual(st.vgpr[0][3], 0x9ABCDEF0)
+
+  def test_scratch_load_u8(self):
+    """SCRATCH_LOAD_U8 loads unsigned byte with zero extension."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0xDEADBEAB),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_u8(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xAB)
+
+  def test_scratch_load_i8(self):
+    """SCRATCH_LOAD_I8 loads signed byte with sign extension."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0x80),  # -128 as signed byte
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b8(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_i8(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFF80)
+
+  def test_scratch_load_u16(self):
+    """SCRATCH_LOAD_U16 loads unsigned 16-bit with zero extension."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0xDEADCAFE),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_u16(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xCAFE)
+
+  def test_scratch_load_i16(self):
+    """SCRATCH_LOAD_I16 loads signed 16-bit with sign extension."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0x8000),  # -32768 as signed 16-bit
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b16(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      scratch_load_i16(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFF8000)
+
+
+class TestScratchSVE(unittest.TestCase):
+  """Tests for SCRATCH SVE (Scratch VGPR Enable) bit behavior."""
+
+  def test_scratch_sve_zero_ignores_vaddr(self):
+    """With SVE=0, VADDR should be ignored in address calculation."""
+    TEST_OFFSET = 256
+    # Store a marker value at offset 256 (where SVE=0 should go)
+    # Then set v[0] to a non-zero value (100) and store via scratch with SVE=0
+    # If SVE=0 is handled correctly, the VADDR (100) should be IGNORED,
+    # and the store should go to offset 256, not 256+100=356
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      # First, store 0xAAAAAAAA at offset 256 with v[0]=0
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=0),
+      s_waitcnt(vmcnt=0),
+      # Now set v[0] to 100 (non-zero) and store 0xBBBBBBBB with SVE=0
+      # With SVE=0, v[0] should be IGNORED, so this should overwrite offset 256
+      v_mov_b32_e32(v[0], 100),
+      s_mov_b32(s[4], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=0),
+      s_waitcnt(vmcnt=0),
+      # Load back from offset 256 (with v[0]=0) - should get 0xBBBBBBBB
+      v_mov_b32_e32(v[0], 0),
+      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=0),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # If SVE=0 works correctly, v[0] should be 0xBBBBBBBB (the second store overwrote the first)
+    # If SVE=0 is wrong (VADDR used), v[0] would be 0xAAAAAAAA (stores went to different locations)
+    self.assertEqual(st.vgpr[0][0], 0xBBBBBBBB, "SVE=0 should ignore VADDR, both stores should go to same location")
+
+  def test_scratch_sve_one_uses_vaddr(self):
+    """With SVE=1, VADDR should be used as offset in address calculation."""
+    TEST_OFFSET = 256
+    # Store at offset 256 with v[0]=0, then store at offset 256 with v[0]=100 and SVE=1
+    # With SVE=1, the second store should go to 256+100=356, not 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      # First, store 0xAAAAAAAA at offset 256 with v[0]=0
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[4], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=1),
+      s_waitcnt(vmcnt=0),
+      # Now set v[0] to 100 and store 0xBBBBBBBB with SVE=1
+      # With SVE=1, v[0] IS used, so this should go to offset 256+100=356
+      v_mov_b32_e32(v[0], 100),
+      s_mov_b32(s[4], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[4]),
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=1),
+      s_waitcnt(vmcnt=0),
+      # Load back from offset 256 (with v[0]=0) - should still be 0xAAAAAAAA
+      v_mov_b32_e32(v[0], 0),
+      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET, sve=1),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # If SVE=1 works correctly, v[0] should be 0xAAAAAAAA (stores went to different locations)
+    self.assertEqual(st.vgpr[0][0], 0xAAAAAAAA, "SVE=1 should use VADDR, stores should go to different locations")
+
+
+class TestScratchMultiLane(unittest.TestCase):
+  """Tests for SCRATCH operations with multiple lanes."""
+
+  def test_scratch_store_load_multi_lane(self):
+    """SCRATCH store/load works correctly with multiple lanes (private per-lane memory)."""
+    TEST_OFFSET = 256
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=SrcEnum.NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Each lane stores its lane ID
+      v_mov_b32_e32(v[0], 0),
+      v_mov_b32_e32(v[2], v[255]),  # v[255] has packed workitem IDs, low 10 bits = x
+      v_and_b32_e32(v[2], 0x3FF, v[2]),  # extract lane ID
+      scratch_store_b32(addr=v[0], data=v[2], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      # Load back
+      scratch_load_b32(addr=v[0], vdst=v[3], saddr=SrcEnum.NULL, offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      v_mov_b32_e32(v[0], v[3]),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=4)
+    # Each lane should have loaded its own lane ID
+    for lane in range(4):
+      self.assertEqual(st.vgpr[lane][0], lane, f"Lane {lane} should have value {lane}")
+
+
+if __name__ == '__main__':
+  unittest.main()
@@ -0,0 +1,448 @@
+"""Tests for SMEM instructions - scalar memory operations.
+
+Includes: s_load_b32, s_load_b64, s_load_b128, s_load_b256, s_load_b512
+Tests both immediate and register offset addressing modes.
+"""
+import unittest
+from extra.assembly.amd.test.hw.helpers import *
+
+# Use offset into output buffer for test data (output buffer is 2124 bytes)
+TEST_OFFSET = 2000
+
+# Cache invalidation sequence for scalar loads after vector stores
+# s_wait_idle waits for all outstanding memory operations including cache flushes
+CACHE_INV = [s_gl1_inv(), s_dcache_inv(), s_wait_idle()]
+
+class TestSLoadRegisterOffset(unittest.TestCase):
+  """Tests for s_load with register offset (soffset field).
+
+  Bug: s_load_b32(s[dst], s[base:base+1], s[off]) ignores the register offset
+  and only uses the immediate offset field. This causes incorrect memory loads
+  when the offset comes from a register.
+  """
+
+  def test_s_load_b32_register_offset_basic(self):
+    """s_load_b32 with register offset should load from base + reg_offset."""
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test values to output buffer: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
+      s_mov_b32(s[4], 0xAAAAAAAA),
+      s_mov_b32(s[5], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[3], s[5]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Now test s_load with register offset
+      # Put offset value in s[4]: offset = 4 bytes (1 dword)
+      s_mov_b32(s[4], 4),
+      # Load from out_ptr + TEST_OFFSET + s[4] (should load 0xBBBBBBBB)
+      s_load_b32(s[5], s[2:3], s[4], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[5], 0xBBBBBBBB,
+      f"s_load with reg offset 4 should load 0xBBBBBBBB: s[5]=0x{st.sgpr[5]:08x}")
+
+  def test_s_load_b32_register_offset_different_from_immediate(self):
+    """s_load_b32 with register offset loads different data than immediate offset 0."""
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test values: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
+      s_mov_b32(s[4], 0xAAAAAAAA),
+      s_mov_b32(s[5], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[4]),
+      v_mov_b32_e32(v[3], s[5]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load with immediate offset 0
+      s_load_b32(s[5], s[2:3], NULL, offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Load with register offset 4
+      s_mov_b32(s[4], 4),
+      s_load_b32(s[6], s[2:3], s[4], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # s[5] has dword at offset 0 (0xAAAAAAAA), s[6] has dword at offset 4 (0xBBBBBBBB)
+    self.assertEqual(st.sgpr[5], 0xAAAAAAAA)
+    self.assertEqual(st.sgpr[6], 0xBBBBBBBB)
+    self.assertNotEqual(st.sgpr[5], st.sgpr[6],
+      f"s_load with reg offset 4 should load different value than offset 0: "
+      f"s[5]=0x{st.sgpr[5]:08x}, s[6]=0x{st.sgpr[6]:08x}")
+
+  def test_s_load_b32_register_offset_same_as_dst(self):
+    """s_load_b32 where soffset register is same as destination.
+
+    This is the exact pattern that exposes the bug:
+    s_load_b32(s[8], s[2:3], s[8])
+    The offset should be read BEFORE the destination is overwritten.
+    """
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test values: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
+      s_mov_b32(s[6], 0xAAAAAAAA),
+      s_mov_b32(s[7], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[6]),
+      v_mov_b32_e32(v[3], s[7]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Set up s[4] = 4 (offset in bytes)
+      s_mov_b32(s[4], 4),
+      # Load using s[4] as both offset and destination
+      # Should load from base + 4, then store result in s[4]
+      s_load_b32(s[4], s[2:3], s[4], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Also load with immediate offset 4 for comparison
+      s_load_b32(s[5], s[2:3], NULL, offset=TEST_OFFSET+4),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # s[4] and s[5] should have the same value (both loaded from offset 4 = 0xBBBBBBBB)
+    self.assertEqual(st.sgpr[4], 0xBBBBBBBB)
+    self.assertEqual(st.sgpr[4], st.sgpr[5],
+      f"s_load with reg offset s[4]=4 should match immediate offset=4: "
+      f"s[4]=0x{st.sgpr[4]:08x}, s[5]=0x{st.sgpr[5]:08x}")
+
+  def test_s_load_b32_register_offset_zero(self):
+    """s_load_b32 with register offset = 0 should be same as immediate offset 0."""
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test value: 0xDEADBEEF at offset
+      s_mov_b32(s[7], 0xDEADBEEF),
+      v_mov_b32_e32(v[2], s[7]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load with register offset 0
+      s_mov_b32(s[4], 0),
+      s_load_b32(s[5], s[2:3], s[4], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Load with immediate offset 0
+      s_load_b32(s[6], s[2:3], NULL, offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[5], 0xDEADBEEF)
+    self.assertEqual(st.sgpr[5], st.sgpr[6],
+      f"s_load with reg offset 0 should match immediate offset 0: "
+      f"s[5]=0x{st.sgpr[5]:08x}, s[6]=0x{st.sgpr[6]:08x}")
+
+  def test_s_load_b32_register_plus_immediate_offset(self):
+    """s_load_b32 with both register and immediate offset should add them."""
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test values: 0xAAAAAAAA at offset, 0xBBBBBBBB at offset+4
+      s_mov_b32(s[8], 0xAAAAAAAA),
+      s_mov_b32(s[9], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[8]),
+      v_mov_b32_e32(v[3], s[9]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # reg offset = 4, imm offset = 0 -> total offset = 4
+      s_mov_b32(s[4], 4),
+      s_load_b32(s[5], s[2:3], s[4], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # reg offset = 0, imm offset = 4 -> total offset = 4
+      s_mov_b32(s[6], 0),
+      s_load_b32(s[7], s[2:3], s[6], offset=TEST_OFFSET+4),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Both should load from offset 4 (0xBBBBBBBB)
+    self.assertEqual(st.sgpr[5], 0xBBBBBBBB)
+    self.assertEqual(st.sgpr[7], 0xBBBBBBBB)
+    self.assertEqual(st.sgpr[5], st.sgpr[7],
+      f"reg_off=4 + imm_off=0 should equal reg_off=0 + imm_off=4: "
+      f"s[5]=0x{st.sgpr[5]:08x}, s[7]=0x{st.sgpr[7]:08x}")
+
+
+class TestSLoadMultiDword(unittest.TestCase):
+  """Tests for multi-dword s_load with register offset."""
+
+  def test_s_load_b64_register_offset(self):
+    """s_load_b64 with register offset should load 2 dwords from base + reg_offset."""
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test values: 0xAAAAAAAA, 0xBBBBBBBB at offset
+      s_mov_b32(s[10], 0xAAAAAAAA),
+      s_mov_b32(s[11], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[10]),
+      v_mov_b32_e32(v[3], s[11]),
+      v_mov_b32_e32(v[0], 0),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      global_store_b32(addr=v[0], data=v[3], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load with register offset 0
+      s_mov_b32(s[4], 0),
+      s_load_b64(s[6:7], s[2:3], s[4], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Compare with immediate offset
+      s_load_b64(s[8:9], s[2:3], NULL, offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[6], 0xAAAAAAAA)
+    self.assertEqual(st.sgpr[7], 0xBBBBBBBB)
+    self.assertEqual(st.sgpr[6], st.sgpr[8])
+    self.assertEqual(st.sgpr[7], st.sgpr[9])
+
+  def test_s_load_b128_register_offset(self):
+    """s_load_b128 with register offset should load 4 dwords from base + reg_offset."""
+    instructions = [
+      # Load output buffer pointer from args
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      # Store test values: 0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD at offset
+      v_mov_b32_e32(v[0], 0),
+      s_mov_b32(s[14], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[14]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_mov_b32(s[14], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[14]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_mov_b32(s[14], 0xCCCCCCCC),
+      v_mov_b32_e32(v[2], s[14]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+8),
+      s_mov_b32(s[14], 0xDDDDDDDD),
+      v_mov_b32_e32(v[2], s[14]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+12),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load with register offset 0 (s_load_b128 requires 4-aligned dest: s[4], s[8], s[12], ...)
+      s_mov_b32(s[15], 0),
+      s_load_b128(s[4:7], s[2:3], s[15], offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Compare with immediate offset
+      s_load_b128(s[8:11], s[2:3], NULL, offset=TEST_OFFSET),
+      s_waitcnt(0),
+      # Zero out pointer regs (different addresses in emu vs hw)
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[4], 0xAAAAAAAA)
+    self.assertEqual(st.sgpr[5], 0xBBBBBBBB)
+    self.assertEqual(st.sgpr[6], 0xCCCCCCCC)
+    self.assertEqual(st.sgpr[7], 0xDDDDDDDD)
+    self.assertEqual(st.sgpr[4], st.sgpr[8])
+    self.assertEqual(st.sgpr[5], st.sgpr[9])
+
+
+class TestSLoadLarge(unittest.TestCase):
+  """Tests for large s_load operations (s_load_b256, s_load_b512)."""
+
+  def test_s_load_b256_basic(self):
+    """s_load_b256 loads 8 consecutive dwords."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      # Store 8 test values
+      s_mov_b32(s[20], 0x11111111),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET),
+      s_mov_b32(s[20], 0x22222222),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+4),
+      s_mov_b32(s[20], 0x33333333),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+8),
+      s_mov_b32(s[20], 0x44444444),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+12),
+      s_mov_b32(s[20], 0x55555555),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+16),
+      s_mov_b32(s[20], 0x66666666),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+20),
+      s_mov_b32(s[20], 0x77777777),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+24),
+      s_mov_b32(s[20], 0x88888888),
+      v_mov_b32_e32(v[2], s[20]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET+28),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load all 8 dwords with s_load_b256
+      s_load_b256(s[4:11], s[2:3], NULL, offset=TEST_OFFSET),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[4], 0x11111111)
+    self.assertEqual(st.sgpr[5], 0x22222222)
+    self.assertEqual(st.sgpr[6], 0x33333333)
+    self.assertEqual(st.sgpr[7], 0x44444444)
+    self.assertEqual(st.sgpr[8], 0x55555555)
+    self.assertEqual(st.sgpr[9], 0x66666666)
+    self.assertEqual(st.sgpr[10], 0x77777777)
+    self.assertEqual(st.sgpr[11], 0x88888888)
+
+  def test_s_load_b512_basic(self):
+    """s_load_b512 loads 16 consecutive dwords."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      # Store 16 test values (use a pattern: 0x10, 0x20, ..., 0x100)
+      *[instr for i in range(16) for instr in [
+        s_mov_b32(s[20], (i + 1) * 0x11111111),
+        v_mov_b32_e32(v[2], s[20]),
+        global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET + i * 4),
+      ]],
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load all 16 dwords with s_load_b512
+      s_load_b512(s[64:79], s[2:3], NULL, offset=TEST_OFFSET),
+      s_waitcnt(lgkmcnt=0),
+      # Copy results to lower regs for verification (since st.sgpr only has 16 regs in test)
+      s_mov_b32(s[4], s[64]),
+      s_mov_b32(s[5], s[65]),
+      s_mov_b32(s[6], s[78]),
+      s_mov_b32(s[7], s[79]),
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[4], 0x11111111, "first dword")
+    self.assertEqual(st.sgpr[5], 0x22222222, "second dword")
+    self.assertEqual(st.sgpr[6], 0xFFFFFFFF & (15 * 0x11111111), "15th dword")
+    self.assertEqual(st.sgpr[7], 0xFFFFFFFF & (16 * 0x11111111), "16th dword")
+
+  def test_s_load_b256_with_register_offset(self):
+    """s_load_b256 with register offset should add reg offset to address."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      # Store pattern at TEST_OFFSET+8: skip first 2 dwords
+      *[instr for i in range(8) for instr in [
+        s_mov_b32(s[20], (i + 1) * 0x11111111),
+        v_mov_b32_e32(v[2], s[20]),
+        global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=TEST_OFFSET + 8 + i * 4),
+      ]],
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load with register offset 8
+      s_mov_b32(s[20], 8),
+      s_load_b256(s[4:11], s[2:3], s[20], offset=TEST_OFFSET),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[4], 0x11111111, "first dword at offset+8")
+    self.assertEqual(st.sgpr[5], 0x22222222, "second dword at offset+8")
+    self.assertEqual(st.sgpr[11], 0x88888888, "last dword at offset+8")
+
+
+class TestSLoadOffset(unittest.TestCase):
+  """Tests for s_load with different immediate offsets.
+
+  These tests verify that instruction deduplication correctly handles different offset values.
+  If offset is made dynamic incorrectly, instructions with different offsets may load wrong data.
+  """
+
+  def test_s_load_different_offsets(self):
+    """Load from two different offsets and verify correct values."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      # Store 0xAAAAAAAA at offset 100
+      s_mov_b32(s[4], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=100),
+      # Store 0xBBBBBBBB at offset 200
+      s_mov_b32(s[4], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[4]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=200),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # Load from offset 100 -> should get 0xAAAAAAAA
+      s_load_b32(s[4], s[2:3], NULL, offset=100),
+      # Load from offset 200 -> should get 0xBBBBBBBB
+      s_load_b32(s[5], s[2:3], NULL, offset=200),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[2], 0), s_mov_b32(s[3], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[4], 0xAAAAAAAA, f"offset 100: expected 0xAAAAAAAA, got 0x{st.sgpr[4]:08x}")
+    self.assertEqual(st.sgpr[5], 0xBBBBBBBB, f"offset 200: expected 0xBBBBBBBB, got 0x{st.sgpr[5]:08x}")
+
+  def test_s_load_negative_offset(self):
+    """Test negative offset (21-bit signed).
+    Store 0xAAAA at offset 100, 0xBBBB at offset 200.
+    Load with offset -100 from base+200 -> should get 0xAAAA.
+    Load with offset -100 from base+300 -> should get 0xBBBB."""
+    instructions = [
+      s_load_b64(s[2:3], s[80:81], 0, soffset=NULL),
+      s_waitcnt(lgkmcnt=0),
+      v_mov_b32_e32(v[0], 0),
+      # Store 0xAAAAAAAA at offset 100, 0xBBBBBBBB at offset 200
+      s_mov_b32(s[8], 0xAAAAAAAA),
+      v_mov_b32_e32(v[2], s[8]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=100),
+      s_mov_b32(s[8], 0xBBBBBBBB),
+      v_mov_b32_e32(v[2], s[8]),
+      global_store_b32(addr=v[0], data=v[2], saddr=s[2:3], offset=200),
+      s_waitcnt(vmcnt=0),
+      *CACHE_INV,
+      # base+200, load with offset -100 -> should get value at 100
+      s_add_u32(s[6], s[2], 200),
+      s_addc_u32(s[7], s[3], 0),
+      s_load_b32(s[4], s[6:7], NULL, offset=-100),
+      # base+300, load with offset -100 -> should get value at 200
+      s_add_u32(s[6], s[2], 300),
+      s_addc_u32(s[7], s[3], 0),
+      s_load_b32(s[5], s[6:7], NULL, offset=-100),
+      s_waitcnt(lgkmcnt=0),
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 0),
+      s_mov_b32(s[6], 0),
+      s_mov_b32(s[7], 0),
+      s_mov_b32(s[8], 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[4], 0xAAAAAAAA, f"offset 200-100=100: expected 0xAAAAAAAA, got 0x{st.sgpr[4]:08x}")
+    self.assertEqual(st.sgpr[5], 0xBBBBBBBB, f"offset 300-100=200: expected 0xBBBBBBBB, got 0x{st.sgpr[5]:08x}")
+
+
+if __name__ == '__main__':
+  unittest.main()
@@ -62,6 +62,74 @@ class TestBasicScalar(unittest.TestCase):
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.sgpr[1], 0x80000000)

+  @skip_unless_gfx(11, 5, "SALU FP ops require gfx1150+")
+  def test_s_fmamk_f32(self):
+    """S_FMAMK_F32: D = S0 * literal + S1."""
+    # 2.0 * 3.0 + 1.0 = 7.0
+    instructions = [
+      s_mov_b32(s[0], f2i(2.0)),
+      s_mov_b32(s[1], f2i(1.0)),
+      s_fmamk_f32(s[2], s[0], s[1], literal=f2i(3.0)),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], f2i(7.0))
+
+  @skip_unless_gfx(11, 5, "SALU FP ops require gfx1150+")
+  def test_s_fmamk_f32_negative(self):
+    """S_FMAMK_F32 with negative values."""
+    # -2.0 * 4.0 + 10.0 = 2.0
+    instructions = [
+      s_mov_b32(s[0], f2i(-2.0)),
+      s_mov_b32(s[1], f2i(10.0)),
+      s_fmamk_f32(s[2], s[0], s[1], literal=f2i(4.0)),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], f2i(2.0))
+
+
+class TestPack(unittest.TestCase):
+  """Tests for S_PACK instructions."""
+
+  def test_s_pack_ll_b32_b16(self):
+    """S_PACK_LL_B32_B16 packs low 16 bits of two sources into one 32-bit result."""
+    instructions = [
+      s_mov_b32(s[0], 0xDEADAAAA),
+      s_mov_b32(s[1], 0xDEADBBBB),
+      s_pack_ll_b32_b16(s[2], s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xBBBBAAAA)
+
+  def test_s_pack_lh_b32_b16(self):
+    """S_PACK_LH_B32_B16: D0 = { S1[31:16], S0[15:0] }."""
+    instructions = [
+      s_mov_b32(s[0], 0xDEADAAAA),
+      s_mov_b32(s[1], 0xDEADBBBB),
+      s_pack_lh_b32_b16(s[2], s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xDEADAAAA)
+
+  def test_s_pack_hh_b32_b16(self):
+    """S_PACK_HH_B32_B16: D0 = { S1[31:16], S0[31:16] }."""
+    instructions = [
+      s_mov_b32(s[0], 0xDEADAAAA),
+      s_mov_b32(s[1], 0xDEADBBBB),
+      s_pack_hh_b32_b16(s[2], s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xDEADDEAD)
+
+  def test_s_pack_hl_b32_b16(self):
+    """S_PACK_HL_B32_B16: D0 = { S1[15:0], S0[31:16] }."""
+    instructions = [
+      s_mov_b32(s[0], 0xDEADAAAA),
+      s_mov_b32(s[1], 0xDEADBBBB),
+      s_pack_hl_b32_b16(s[2], s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xBBBBDEAD)
+

 class TestQuadmaskWqm(unittest.TestCase):
  """Tests for S_QUADMASK_B32 and S_WQM_B32."""
@@ -142,8 +210,8 @@ class TestBranch(unittest.TestCase):
    """S_CBRANCH_VCCNZ should only check VCC_LO in wave32."""
    instructions = [
      # Set VCC_LO = 0, VCC_HI = 1
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 0),
-      s_mov_b32(s[SrcEnum.VCC_HI - 128], 1),
+      s_mov_b32(VCC_LO, 0),
+      s_mov_b32(VCC_HI, 1),
      v_mov_b32_e32(v[0], 0),
      # If VCC_HI is incorrectly used, branch will be taken
      s_cbranch_vccnz(1),  # Skip next instruction if VCC != 0
@@ -156,8 +224,8 @@ class TestBranch(unittest.TestCase):
    """S_CBRANCH_VCCZ should only check VCC_LO in wave32."""
    instructions = [
      # Set VCC_LO = 1, VCC_HI = 0
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 1),
-      s_mov_b32(s[SrcEnum.VCC_HI - 128], 0),
+      s_mov_b32(VCC_LO, 1),
+      s_mov_b32(VCC_HI, 0),
      v_mov_b32_e32(v[0], 0),
      # If VCC_HI is incorrectly used, branch will be taken
      s_cbranch_vccz(1),  # Skip next instruction if VCC == 0
@@ -169,7 +237,7 @@ class TestBranch(unittest.TestCase):
  def test_cbranch_vccnz_branches_on_vcc_lo(self):
    """S_CBRANCH_VCCNZ branches when VCC_LO is non-zero."""
    instructions = [
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 1),
+      s_mov_b32(VCC_LO, 1),
      v_mov_b32_e32(v[0], 0),
      s_cbranch_vccnz(1),  # Skip next instruction if VCC != 0
      v_mov_b32_e32(v[0], 42),  # This should be skipped
@@ -195,15 +263,6 @@ class Test64BitLiterals(unittest.TestCase):
    result = i642f(st.vgpr[0][0] | (st.vgpr[0][1] << 32))
    self.assertAlmostEqual(result, -4294967296.0, places=5)

-  def test_64bit_literal_positive_encoding(self):
-    """64-bit instruction encodes large positive literals correctly."""
-    large_val = 0x12345678
-    inst = v_add_f64(v[2], v[0], large_val)
-    self.assertIsNotNone(inst._literal, "Literal should be set")
-    actual_lit = (inst._literal >> 32) & 0xffffffff
-    self.assertEqual(actual_lit, large_val, f"Literal should be {large_val:#x}, got {actual_lit:#x}")
-
-
 class TestSCCBehavior(unittest.TestCase):
  """Tests for SCC condition code behavior."""

@@ -307,6 +366,56 @@ class TestSignedArithmetic(unittest.TestCase):
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.sgpr[2], 2)

+  def test_s_mul_hi_u32_max(self):
+    """S_MUL_HI_U32: 0xFFFFFFFF * 0xFFFFFFFF."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),
+      s_mov_b32(s[1], 0xFFFFFFFF),
+      s_mul_hi_u32(s[2], s[0], s[1]),  # (0xFFFFFFFF * 0xFFFFFFFF) >> 32 = 0xFFFFFFFE
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xFFFFFFFE)
+
+  def test_s_mul_hi_i32_positive(self):
+    """S_MUL_HI_I32: positive * positive."""
+    instructions = [
+      s_mov_b32(s[0], 0x40000000),  # 2^30
+      s_mov_b32(s[1], 4),
+      s_mul_hi_i32(s[2], s[0], s[1]),  # (2^30 * 4) >> 32 = 1
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 1)
+
+  def test_s_mul_hi_i32_neg_times_neg(self):
+    """S_MUL_HI_I32: (-1) * (-1) = 1, high bits = 0."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),  # -1
+      s_mov_b32(s[1], 0xFFFFFFFF),  # -1
+      s_mul_hi_i32(s[2], s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0)
+
+  def test_s_mul_hi_i32_neg_times_pos(self):
+    """S_MUL_HI_I32: (-1) * 2 = -2, high bits = -1 (sign extension)."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),  # -1
+      s_mov_b32(s[1], 2),
+      s_mul_hi_i32(s[2], s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xFFFFFFFF)  # -1 sign extends
+
+  def test_s_mul_hi_i32_min_int(self):
+    """S_MUL_HI_I32: MIN_INT * 2 = -2^32, high = -1."""
+    instructions = [
+      s_mov_b32(s[0], 0x80000000),  # -2^31 (MIN_INT)
+      s_mov_b32(s[1], 2),
+      s_mul_hi_i32(s[2], s[0], s[1]),  # (-2^31 * 2) >> 32 = -1
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0xFFFFFFFF)
+
  def test_s_mul_i32(self):
    """S_MUL_I32: signed multiply low 32 bits."""
    instructions = [
@@ -338,5 +447,490 @@ class TestSignedArithmetic(unittest.TestCase):
    self.assertEqual(st.sgpr[7], ((dividend * 2) + 1) & 0xFFFFFFFF)


+class TestBitSet(unittest.TestCase):
+  """Tests for S_BITSET0_B32 and S_BITSET1_B32 instructions."""
+
+  def test_s_bitset1_b32_set_bit0(self):
+    """S_BITSET1_B32: set bit 0 in destination."""
+    instructions = [
+      s_mov_b32(s[0], 0),     # start with 0
+      s_mov_b32(s[1], 0),     # bit position = 0
+      s_bitset1_b32(s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 1, "Bit 0 should be set")
+
+  def test_s_bitset1_b32_set_bit31(self):
+    """S_BITSET1_B32: set bit 31 in destination."""
+    instructions = [
+      s_mov_b32(s[0], 0),     # start with 0
+      s_mov_b32(s[1], 31),    # bit position = 31
+      s_bitset1_b32(s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0x80000000, "Bit 31 should be set")
+
+  def test_s_bitset1_b32_preserves_other_bits(self):
+    """S_BITSET1_B32: preserves bits not being set."""
+    instructions = [
+      s_mov_b32(s[0], 0xFF00FF00),  # existing pattern
+      s_mov_b32(s[1], 0),            # bit position = 0
+      s_bitset1_b32(s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0xFF00FF01, "Should set bit 0 while preserving others")
+
+  def test_s_bitset0_b32_clear_bit0(self):
+    """S_BITSET0_B32: clear bit 0 in destination."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),  # start with all bits set
+      s_mov_b32(s[1], 0),            # bit position = 0
+      s_bitset0_b32(s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0xFFFFFFFE, "Bit 0 should be cleared")
+
+  def test_s_bitset0_b32_clear_bit31(self):
+    """S_BITSET0_B32: clear bit 31 in destination."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),  # start with all bits set
+      s_mov_b32(s[1], 31),           # bit position = 31
+      s_bitset0_b32(s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0x7FFFFFFF, "Bit 31 should be cleared")
+
+  def test_s_bitset1_b32_uses_low5_bits(self):
+    """S_BITSET1_B32: only uses low 5 bits of position (mod 32)."""
+    instructions = [
+      s_mov_b32(s[0], 0),
+      s_mov_b32(s[1], 32 + 5),   # position = 37, but mod 32 = 5
+      s_bitset1_b32(s[0], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0x20, "Bit 5 should be set (37 mod 32 = 5)")
+
+
+class TestBfeI64(unittest.TestCase):
+  """Tests for S_BFE_I64 - 64-bit bit field extract with sign extension.
+
+  Regression tests for sign extension bug where 32-bit masks were incorrectly
+  used for 64-bit operations, causing the high 32 bits to not be sign-extended.
+  """
+
+  def test_s_bfe_i64_positive_no_sign_extend(self):
+    """S_BFE_I64: positive value (1) in 16 bits should not sign extend."""
+    # S1 encodes: [22:16] = width, [5:0] = offset
+    # width=16, offset=0 -> S1 = (16 << 16) | 0 = 0x100000
+    instructions = [
+      s_mov_b32(s[0], 1),         # S0 lo = 1
+      s_mov_b32(s[1], 0),         # S0 hi = 0
+      s_mov_b32(s[2], 0x100000),  # width=16, offset=0
+      s_bfe_i64(s[4:5], s[0:1], s[2]),
+      v_mov_b32_e32(v[0], s[4]),
+      v_mov_b32_e32(v[1], s[5]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 1, "lo should be 1")
+    self.assertEqual(st.vgpr[0][1], 0, "hi should be 0 (no sign extend)")
+
+  def test_s_bfe_i64_negative_sign_extend(self):
+    """S_BFE_I64: 0xFFFF (-1 in 16 bits) should sign extend to 64 bits.
+
+    This is the main regression test - before the fix, hi was 0 instead of 0xFFFFFFFF.
+    """
+    instructions = [
+      s_mov_b32(s[0], 0xFFFF),    # S0 lo = -1 in 16 bits
+      s_mov_b32(s[1], 0),         # S0 hi = 0
+      s_mov_b32(s[2], 0x100000),  # width=16, offset=0
+      s_bfe_i64(s[4:5], s[0:1], s[2]),
+      v_mov_b32_e32(v[0], s[4]),
+      v_mov_b32_e32(v[1], s[5]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF, "lo should be 0xFFFFFFFF")
+    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
+
+  def test_s_bfe_i64_8bit_negative_sign_extend(self):
+    """S_BFE_I64: 0xFF (-1 in 8 bits) should sign extend to 64 bits."""
+    # width=8, offset=0 -> S1 = (8 << 16) | 0 = 0x80000
+    instructions = [
+      s_mov_b32(s[0], 0xFF),      # S0 lo = -1 in 8 bits
+      s_mov_b32(s[1], 0),         # S0 hi = 0
+      s_mov_b32(s[2], 0x80000),   # width=8, offset=0
+      s_bfe_i64(s[4:5], s[0:1], s[2]),
+      v_mov_b32_e32(v[0], s[4]),
+      v_mov_b32_e32(v[1], s[5]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF, "lo should be 0xFFFFFFFF")
+    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
+
+  def test_s_bfe_i64_8bit_positive(self):
+    """S_BFE_I64: 0x7F (127 in 8 bits) should not sign extend."""
+    # width=8, offset=0 -> S1 = (8 << 16) | 0 = 0x80000
+    instructions = [
+      s_mov_b32(s[0], 0x7F),      # S0 lo = 127 in 8 bits (MSB=0)
+      s_mov_b32(s[1], 0),         # S0 hi = 0
+      s_mov_b32(s[2], 0x80000),   # width=8, offset=0
+      s_bfe_i64(s[4:5], s[0:1], s[2]),
+      v_mov_b32_e32(v[0], s[4]),
+      v_mov_b32_e32(v[1], s[5]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x7F, "lo should be 0x7F")
+    self.assertEqual(st.vgpr[0][1], 0, "hi should be 0 (no sign extend)")
+
+  def test_s_bfe_i64_with_offset(self):
+    """S_BFE_I64: extract from non-zero bit offset with sign extension."""
+    # Extract 16 bits starting at bit 8: value 0xFF00 >> 8 = 0xFF = -1 in 8 bits? No wait...
+    # Let's put 0x8000FF00: extract 16 bits at offset 8 = 0x00FF (positive)
+    # Put 0xFF00_0000: extract 16 bits at offset 16 = 0xFF00 = -256 in signed 16-bit
+    instructions = [
+      s_mov_b32(s[0], 0xFF000000),  # bits [31:24] = 0xFF, [23:16] = 0x00
+      s_mov_b32(s[1], 0),
+      # width=16, offset=16 -> S1 = (16 << 16) | 16 = 0x100010
+      s_mov_b32(s[2], 0x100010),
+      s_bfe_i64(s[4:5], s[0:1], s[2]),
+      v_mov_b32_e32(v[0], s[4]),
+      v_mov_b32_e32(v[1], s[5]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Extract bits [31:16] = 0xFF00, sign bit is bit 15 of extracted = bit 31 of original = 1
+    # So result should be sign-extended 0xFF00 -> 0xFFFFFF00 in lo, 0xFFFFFFFF in hi
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFF00, "lo should be sign-extended 0xFF00")
+    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
+
+  def test_s_bfe_i64_32bit_negative(self):
+    """S_BFE_I64: extract 32 bits with sign extension."""
+    # width=32, offset=0 -> S1 = (32 << 16) | 0 = 0x200000
+    instructions = [
+      s_mov_b32(s[0], 0x80000000),  # MIN_INT32 = -2^31
+      s_mov_b32(s[1], 0),
+      s_mov_b32(s[2], 0x200000),    # width=32, offset=0
+      s_bfe_i64(s[4:5], s[0:1], s[2]),
+      v_mov_b32_e32(v[0], s[4]),
+      v_mov_b32_e32(v[1], s[5]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x80000000, "lo should be 0x80000000")
+    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF, "hi should be 0xFFFFFFFF (sign extended)")
+
+
+class Test64BitCompare(unittest.TestCase):
+  """Tests for 64-bit scalar compare instructions."""
+
+  def test_s_cmp_eq_u64_equal(self):
+    """S_CMP_EQ_U64: comparing equal 64-bit values sets SCC=1."""
+    val = 0x123456789ABCDEF0
+    instructions = [
+      s_mov_b32(s[0], val & 0xFFFFFFFF),
+      s_mov_b32(s[1], val >> 32),
+      s_mov_b32(s[2], val & 0xFFFFFFFF),
+      s_mov_b32(s[3], val >> 32),
+      s_cmp_eq_u64(s[0:1], s[2:3]),
+      s_cselect_b32(s[4], 1, 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.scc, 1)
+    self.assertEqual(st.sgpr[4], 1)
+
+  def test_s_cmp_eq_u64_different_upper_bits(self):
+    """S_CMP_EQ_U64: values differing only in upper 32 bits are not equal."""
+    # This is the bug case - if only lower 32 bits are compared, these would be equal
+    instructions = [
+      s_mov_b32(s[0], 0),  # lower 32 bits of value 0
+      s_mov_b32(s[1], 0),  # upper 32 bits of value 0
+      s_mov_b32(s[2], 0),  # lower 32 bits of 0x100000000
+      s_mov_b32(s[3], 1),  # upper 32 bits of 0x100000000
+      s_cmp_eq_u64(s[0:1], s[2:3]),
+      s_cselect_b32(s[4], 1, 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.scc, 0, "0 != 0x100000000, SCC should be 0")
+    self.assertEqual(st.sgpr[4], 0)
+
+  def test_s_cmp_lg_u64_different(self):
+    """S_CMP_LG_U64: different 64-bit values sets SCC=1."""
+    instructions = [
+      s_mov_b32(s[0], 0),
+      s_mov_b32(s[1], 0),  # s[0:1] = 0
+      s_mov_b32(s[2], 0),
+      s_mov_b32(s[3], 1),  # s[2:3] = 0x100000000
+      s_cmp_lg_u64(s[0:1], s[2:3]),
+      s_cselect_b32(s[4], 1, 0),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.scc, 1, "0 != 0x100000000, SCC should be 1")
+    self.assertEqual(st.sgpr[4], 1)
+
+
+class TestSOPPNop(unittest.TestCase):
+  """Tests for S_NOP and other SOPP instructions with expression-based for loops.
+
+  S_NOP's pcode uses 'for i in 0U : SIMM16.u16[3 : 0].u32 do' which requires
+  the parser to handle non-constant loop bounds.
+  """
+
+  def test_s_nop_basic(self):
+    """S_NOP executes without side effects."""
+    # S_NOP with immediate 0 should just do nothing
+    instructions = [
+      s_mov_b32(s[0], 42),
+      s_nop(0),  # nop with simm16=0
+      s_mov_b32(s[1], 100),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 42)
+    self.assertEqual(st.sgpr[1], 100)
+
+  def test_s_nop_with_count(self):
+    """S_NOP with count parameter executes multiple nops."""
+    # S_NOP with immediate 3 should execute 4 nops (0:3 inclusive)
+    instructions = [
+      s_mov_b32(s[0], 1),
+      s_nop(3),  # nop with simm16=3 -> 4 iterations
+      s_add_u32(s[0], s[0], 1),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 2)
+
+
+class TestNullRegister(unittest.TestCase):
+  """Tests for NULL register (124) behavior - writes should be discarded, reads return 0."""
+
+  def test_s_mov_b32_from_null(self):
+    """S_MOV_B32 from NULL should read as 0."""
+    instructions = [
+      s_mov_b32(s[0], 0xDEADBEEF),  # Set s[0] to sentinel
+      s_mov_b32(s[0], NULL),  # Read from NULL - should be 0
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0)
+
+  def test_s_add_u32_with_null_src(self):
+    """S_ADD_U32 with NULL as source should use 0."""
+    instructions = [
+      s_mov_b32(s[0], 100),
+      s_add_u32(s[1], s[0], NULL),  # 100 + 0 = 100
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[1], 100)
+
+  def test_s_mov_b32_to_null(self):
+    """S_MOV_B32 to NULL (sdst=124) should discard the write."""
+    instructions = [
+      s_mov_b32(s[0], 0xDEADBEEF),  # Set s[0] to sentinel
+      s_mov_b32(NULL, 42),  # Write to NULL - should be discarded
+      # s[0] should still be 0xDEADBEEF since NULL write doesn't affect it
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[0], 0xDEADBEEF)
+
+  def test_s_add_u32_to_null(self):
+    """S_ADD_U32 with sdst=NULL should discard result but still set SCC."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),
+      s_mov_b32(s[1], 1),
+      s_add_u32(NULL, s[0], s[1]),  # overflow, write to NULL
+      s_cselect_b32(s[2], 1, 0),  # capture SCC
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # SCC should still be set from overflow even though result was discarded
+    self.assertEqual(st.sgpr[2], 1)
+    self.assertEqual(st.scc, 1)
+
+  def test_s_and_b32_to_null(self):
+    """S_AND_B32 with sdst=NULL should discard result but still set SCC."""
+    instructions = [
+      s_mov_b32(s[0], 0xFF00FF00),
+      s_mov_b32(s[1], 0x0F0F0F0F),
+      s_and_b32(NULL, s[0], s[1]),  # result=0x0F000F00, non-zero so SCC=1
+      s_cselect_b32(s[2], 1, 0),  # capture SCC
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 1)  # SCC=1 because result was non-zero
+    self.assertEqual(st.scc, 1)
+
+  def test_s_or_b32_to_null_zero_result(self):
+    """S_OR_B32 with sdst=NULL and zero result should set SCC=0."""
+    instructions = [
+      s_mov_b32(s[0], 0),
+      s_mov_b32(s[1], 0),
+      s_or_b32(NULL, s[0], s[1]),  # result=0, so SCC=0
+      s_cselect_b32(s[2], 1, 0),  # capture SCC
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.sgpr[2], 0)  # SCC=0 because result was zero
+    self.assertEqual(st.scc, 0)
+
+
+class Test64BitSOP1InlineConstants(unittest.TestCase):
+  """Tests for 64-bit SOP1 instructions with inline constants.
+
+  Regression tests for bug where rsrc_dyn didn't properly handle 64-bit
+  inline constants, incorrectly duplicating lo bits to hi instead of
+  zero/sign-extending.
+  """
+
+  def test_s_mov_b64_inline_0(self):
+    """S_MOV_B64 with inline constant 0."""
+    instructions = [
+      s_mov_b64(s[0:1], 0),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_mov_b64_inline_16(self):
+    """S_MOV_B64 with inline constant 16 should set lo=16, hi=0."""
+    instructions = [
+      s_mov_b64(s[0:1], 16),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 16)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_mov_b64_inline_64(self):
+    """S_MOV_B64 with inline constant 64 (max positive)."""
+    instructions = [
+      s_mov_b64(s[0:1], 64),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 64)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_mov_b64_inline_neg1(self):
+    """S_MOV_B64 with inline constant -1 should sign-extend."""
+    instructions = [
+      s_mov_b64(s[0:1], -1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF)
+    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF)
+
+  def test_s_mov_b64_inline_neg16(self):
+    """S_MOV_B64 with inline constant -16 should sign-extend."""
+    instructions = [
+      s_mov_b64(s[0:1], -16),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFFF0)
+    self.assertEqual(st.vgpr[0][1], 0xFFFFFFFF)
+
+  def test_s_mov_b64_float_const_1_0(self):
+    """S_MOV_B64 with float inline constant 1.0 - casts F32 to F64."""
+    instructions = [
+      s_mov_b64(s[0:1], 1.0),  # inline constant 242 (1.0f)
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Hardware casts F32 to F64: 1.0f64 = 0x3FF0000000000000
+    self.assertEqual(st.vgpr[0][0], 0x00000000)  # lo
+    self.assertEqual(st.vgpr[0][1], 0x3FF00000)  # hi
+
+  def test_s_or_b64_inline_constant(self):
+    """S_OR_B64 with 64-bit inline constant."""
+    instructions = [
+      s_mov_b64(s[0:1], 0),
+      s_or_b64(s[2:3], s[0:1], 16),
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 16)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_and_b64_inline_constant(self):
+    """S_AND_B64 with 64-bit inline constant."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),
+      s_mov_b32(s[1], 0xFFFFFFFF),
+      s_and_b64(s[2:3], s[0:1], 16),
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 16)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+
+class Test64BitSOPLiterals(unittest.TestCase):
+  """Tests for 64-bit SOP instructions with 32-bit literals.
+
+  Tests the behavior when a 64-bit SOP instruction uses a 32-bit literal
+  (offset 255 in instruction encoding). The literal is zero-extended to 64 bits.
+  """
+
+  def test_s_mov_b64_literal(self):
+    """S_MOV_B64 with 32-bit literal value - zero-extended to 64 bits."""
+    instructions = [
+      s_mov_b64(s[0:1], 0x12345678),  # literal > 64, uses literal encoding
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x12345678)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_or_b64_literal(self):
+    """S_OR_B64 with 32-bit literal value - zero-extended to 64 bits."""
+    instructions = [
+      s_mov_b64(s[0:1], 0),
+      s_or_b64(s[2:3], s[0:1], 0x12345678),  # literal
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x12345678)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_and_b64_literal(self):
+    """S_AND_B64 with 32-bit literal value - zero-extended to 64 bits."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),
+      s_mov_b32(s[1], 0xFFFFFFFF),
+      s_and_b64(s[2:3], s[0:1], 0x12345678),  # literal
+      v_mov_b32_e32(v[0], s[2]),
+      v_mov_b32_e32(v[1], s[3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x12345678)
+    self.assertEqual(st.vgpr[0][1], 0)
+
+  def test_s_mov_b64_literal_negative(self):
+    """S_MOV_B64 with 0xFFFFFFFF literal - zero-extended (not sign-extended)."""
+    instructions = [
+      s_mov_b64(s[0:1], 0xFFFFFFFF),  # -1 as 32-bit, but zero-extended to 64-bit
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF)
+    self.assertEqual(st.vgpr[0][1], 0)  # zero-extended, not sign-extended
+
+  def test_s_mov_b64_literal_high_bit(self):
+    """S_MOV_B64 with 0x80000000 literal - zero-extended (not sign-extended)."""
+    instructions = [
+      s_mov_b64(s[0:1], 0x80000000),  # high bit set, but zero-extended
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0x80000000)
+    self.assertEqual(st.vgpr[0][1], 0)  # zero-extended, not sign-extended
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -255,7 +255,6 @@ class TestF16Conversions(unittest.TestCase):

  def test_v_cvt_f16_f32_small(self):
    """V_CVT_F16_F32 converts small f32 value."""
-    from extra.assembly.amd.pcode import f32_to_f16
    instructions = [
      v_mov_b32_e32(v[0], 0.5),
      v_cvt_f16_f32_e32(v[1], v[0]),
@@ -293,7 +292,6 @@ class TestF16Conversions(unittest.TestCase):

  def test_v_cvt_f16_f32_reads_full_32bit_source(self):
    """V_CVT_F16_F32 must read full 32-bit f32 source."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x3fc00000),  # f32 1.5
      v_mov_b32_e32(v[0], s[0]),
@@ -302,7 +300,7 @@ class TestF16Conversions(unittest.TestCase):
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][1]
    lo_bits = result & 0xffff
-    self.assertEqual(lo_bits, 0x3e00, f"Expected f16(1.5)=0x3e00, got 0x{lo_bits:04x} ({_f16(lo_bits)})")
+    self.assertEqual(lo_bits, 0x3e00, f"Expected f16(1.5)=0x3e00, got 0x{lo_bits:04x} ({f16(lo_bits)})")

  def test_v_cvt_i16_f16_zero(self):
    """V_CVT_I16_F16 converts f16 zero to i16 zero."""
@@ -348,6 +346,142 @@ class TestF16Conversions(unittest.TestCase):
    self.assertEqual(result, 1, f"Expected 1 from high bits, got {result}")


+class TestF64Conversions(unittest.TestCase):
+  """Tests for f64 conversion instructions. Regression tests for f32_to_f64/f64_to_f32."""
+
+  def test_v_cvt_f64_f32_one(self):
+    """V_CVT_F64_F32 converts f32 1.0 to f64."""
+    instructions = [
+      s_mov_b32(s[0], f2i(1.0)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_f64_f32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertAlmostEqual(result, 1.0, places=10)
+
+  def test_v_cvt_f64_f32_negative(self):
+    """V_CVT_F64_F32 converts f32 -2.5 to f64."""
+    instructions = [
+      s_mov_b32(s[0], f2i(-2.5)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_f64_f32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertAlmostEqual(result, -2.5, places=10)
+
+  def test_v_cvt_f64_f32_pi(self):
+    """V_CVT_F64_F32 converts f32 pi to f64."""
+    import math
+    instructions = [
+      s_mov_b32(s[0], f2i(3.14159265)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_f64_f32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertAlmostEqual(result, 3.14159265, places=5)
+
+  def test_v_cvt_f64_f32_zero(self):
+    """V_CVT_F64_F32 converts f32 0.0 to f64."""
+    instructions = [
+      v_mov_b32_e32(v[0], 0),
+      v_cvt_f64_f32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertEqual(result, 0.0)
+
+  def test_v_cvt_f32_f64_one(self):
+    """V_CVT_F32_F64 converts f64 1.0 to f32."""
+    f64_bits = f2i64(1.0)
+    lo, hi = f64_bits & 0xFFFFFFFF, (f64_bits >> 32) & 0xFFFFFFFF
+    instructions = [
+      s_mov_b32(s[0], lo),
+      s_mov_b32(s[1], hi),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_cvt_f32_f64_e32(v[2], v[0:1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][2])
+    self.assertAlmostEqual(result, 1.0, places=5)
+
+  def test_v_cvt_f32_f64_negative(self):
+    """V_CVT_F32_F64 converts f64 -3.5 to f32."""
+    f64_bits = f2i64(-3.5)
+    lo, hi = f64_bits & 0xFFFFFFFF, (f64_bits >> 32) & 0xFFFFFFFF
+    instructions = [
+      s_mov_b32(s[0], lo),
+      s_mov_b32(s[1], hi),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_cvt_f32_f64_e32(v[2], v[0:1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][2])
+    self.assertAlmostEqual(result, -3.5, places=5)
+
+  def test_v_cvt_f32_f64_large(self):
+    """V_CVT_F32_F64 converts large f64 to f32."""
+    f64_bits = f2i64(123456.789)
+    lo, hi = f64_bits & 0xFFFFFFFF, (f64_bits >> 32) & 0xFFFFFFFF
+    instructions = [
+      s_mov_b32(s[0], lo),
+      s_mov_b32(s[1], hi),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_cvt_f32_f64_e32(v[2], v[0:1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][2])
+    self.assertAlmostEqual(result, 123456.789, places=0)
+
+  def test_v_cvt_f64_i32_positive(self):
+    """V_CVT_F64_I32 converts positive i32 to f64."""
+    instructions = [
+      s_mov_b32(s[0], 42),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_f64_i32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertAlmostEqual(result, 42.0, places=10)
+
+  def test_v_cvt_f64_i32_negative(self):
+    """V_CVT_F64_I32 converts negative i32 to f64."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),  # -1 as i32
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_f64_i32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertAlmostEqual(result, -1.0, places=10)
+
+  def test_v_cvt_f64_u32_large(self):
+    """V_CVT_F64_U32 converts large u32 to f64."""
+    instructions = [
+      s_mov_b32(s[0], 0xFFFFFFFF),  # max u32
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_f64_u32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertAlmostEqual(result, 4294967295.0, places=0)
+
+  def test_v_cvt_f64_u32_zero(self):
+    """V_CVT_F64_U32 converts 0 to f64."""
+    instructions = [
+      v_mov_b32_e32(v[0], 0),
+      v_cvt_f64_u32_e32(v[2:3], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i642f((st.vgpr[0][3] << 32) | st.vgpr[0][2])
+    self.assertEqual(result, 0.0)
+
+
 class TestClz(unittest.TestCase):
  """Tests for V_CLZ_I32_U32 - count leading zeros."""

@@ -526,16 +660,16 @@ class TestExp(unittest.TestCase):
 class TestReadFirstLane(unittest.TestCase):
  """Tests for V_READFIRSTLANE_B32."""

-  def _readfirstlane(self, sdst_idx, vsrc):
+  def _readfirstlane(self, sdst, vsrc):
    """Helper to create V_READFIRSTLANE_B32 with SGPR destination."""
-    return VOP1(VOP1Op.V_READFIRSTLANE_B32, vdst=RawImm(sdst_idx), src0=vsrc)
+    return v_readfirstlane_b32_e32(sdst, vsrc)

  def test_v_readfirstlane_b32_basic(self):
    """V_READFIRSTLANE_B32 reads from the first active lane."""
    instructions = [
      v_lshlrev_b32_e32(v[0], 2, v[255]),
      v_add_nc_u32_e32(v[0], 1000, v[0]),
-      self._readfirstlane(0, v[0]),
+      self._readfirstlane(s[0], v[0]),
      v_mov_b32_e32(v[1], s[0]),
    ]
    st = run_program(instructions, n_lanes=4)
@@ -547,7 +681,7 @@ class TestReadFirstLane(unittest.TestCase):
    instructions = [
      v_lshlrev_b32_e32(v[7], 5, v[255]),
      v_add_nc_u32_e32(v[7], 200, v[7]),
-      self._readfirstlane(0, v[7]),
+      self._readfirstlane(s[0], v[7]),
      v_mov_b32_e32(v[8], s[0]),
    ]
    st = run_program(instructions, n_lanes=4)
@@ -560,7 +694,6 @@ class TestCvtF16Modifiers(unittest.TestCase):

  def test_v_cvt_f32_f16_abs_negative(self):
    """V_CVT_F32_F16 with |abs| on negative value."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_neg1 = f32_to_f16(-1.0)  # 0xbc00
    instructions = [
      s_mov_b32(s[0], f16_neg1),
@@ -573,7 +706,6 @@ class TestCvtF16Modifiers(unittest.TestCase):

  def test_v_cvt_f32_f16_abs_positive(self):
    """V_CVT_F32_F16 with |abs| on positive value (should stay positive)."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_2 = f32_to_f16(2.0)  # 0x4000
    instructions = [
      s_mov_b32(s[0], f16_2),
@@ -586,7 +718,6 @@ class TestCvtF16Modifiers(unittest.TestCase):

  def test_v_cvt_f32_f16_neg_positive(self):
    """V_CVT_F32_F16 with neg on positive value."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_2 = f32_to_f16(2.0)  # 0x4000
    instructions = [
      s_mov_b32(s[0], f16_2),
@@ -599,7 +730,6 @@ class TestCvtF16Modifiers(unittest.TestCase):

  def test_v_cvt_f32_f16_neg_negative(self):
    """V_CVT_F32_F16 with neg on negative value (double negative)."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_neg2 = f32_to_f16(-2.0)  # 0xc000
    instructions = [
      s_mov_b32(s[0], f16_neg2),
@@ -612,7 +742,6 @@ class TestCvtF16Modifiers(unittest.TestCase):

  def test_v_cvt_f16_f32_then_pack_for_wmma(self):
    """CVT F32->F16 followed by pack (common WMMA pattern)."""
-    from extra.assembly.amd.pcode import _f16
    f32_val = 3.5
    instructions = [
      s_mov_b32(s[0], f2i(f32_val)),
@@ -621,8 +750,8 @@ class TestCvtF16Modifiers(unittest.TestCase):
      v_pack_b32_f16(v[2], v[1], v[1]),  # Pack same value
    ]
    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][2] & 0xffff)
-    hi = _f16((st.vgpr[0][2] >> 16) & 0xffff)
+    lo = f16(st.vgpr[0][2] & 0xffff)
+    hi = f16((st.vgpr[0][2] >> 16) & 0xffff)
    self.assertAlmostEqual(lo, f32_val, places=1)
    self.assertAlmostEqual(hi, f32_val, places=1)

@@ -668,7 +797,6 @@ class TestConversionRounding(unittest.TestCase):

  def test_f16_to_f32_precision(self):
    """F16 to F32 conversion precision."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_val = f32_to_f16(1.5)
    instructions = [
      s_mov_b32(s[0], f16_val),
@@ -680,7 +808,6 @@ class TestConversionRounding(unittest.TestCase):

  def test_f16_denormal_to_f32(self):
    """F16 denormal converts to small positive f32."""
-    from extra.assembly.amd.pcode import _f16
    f16_denorm = 0x0001  # Smallest positive f16 denormal
    instructions = [
      v_mov_b32_e32(v[0], f16_denorm),
@@ -1238,5 +1365,220 @@ class TestFloorEdgeCases(unittest.TestCase):
    self.assertAlmostEqual(i2f(st.vgpr[0][1]), -1.0, places=5)


+class TestVop1F16HiHalf(unittest.TestCase):
+  """Regression tests for VOP1 f16 hi-half source operand handling.
+
+  For 16-bit VOP1 operations, when src0 is in the range v[128]+ (offset >= 384),
+  the hardware reads from the high 16 bits of v[src0-128]. The emulator must
+  extract bits [31:16] from the actual VGPR.
+  """
+
+  def test_v_cvt_f32_f16_src_hi_half(self):
+    """V_CVT_F32_F16 with source from hi-half (v[128]+).
+
+    When src0 >= v[128], it reads from the high 16 bits of v[src0-128].
+    This is critical for global_load_d16_hi_b16 + v_cvt_f32_f16 patterns.
+
+    Regression test for: VOP1 f16 src0 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0x40003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # v_cvt_f32_f16 v[1], v[128] (reads hi half of v[0])
+      # Should convert f16(2.0) to f32(2.0)
+      v_cvt_f32_f16_e32(v[1], v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][1])
+    self.assertAlmostEqual(result, 2.0, places=5, msg=f"Expected f32(2.0), got {result}")
+
+  def test_v_cvt_f32_f16_src_lo_vs_hi(self):
+    """V_CVT_F32_F16 comparing lo and hi half reads.
+
+    v[0] has different values in lo and hi halves.
+    v_cvt_f32_f16 v[1], v[0] should read lo (1.0)
+    v_cvt_f32_f16 v[2], v[128] should read hi (2.0)
+
+    Regression test for: VOP1 f16 src0 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0x40003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # Read from lo half
+      v_cvt_f32_f16_e32(v[1], v[0]),
+      # Read from hi half
+      v_cvt_f32_f16_e32(v[2], v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result_lo = i2f(st.vgpr[0][1])
+    result_hi = i2f(st.vgpr[0][2])
+    self.assertAlmostEqual(result_lo, 1.0, places=5, msg=f"Expected f32(1.0) from lo, got {result_lo}")
+    self.assertAlmostEqual(result_hi, 2.0, places=5, msg=f"Expected f32(2.0) from hi, got {result_hi}")
+
+  def test_v_cvt_i16_f16_src_hi_half(self):
+    """V_CVT_I16_F16 with source from hi-half.
+
+    Regression test for: VOP1 f16 src0 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0xc000_3c00: hi=f16(-2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0xc0003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # v_cvt_i16_f16 v[1], v[128] (reads hi half of v[0])
+      # Should convert f16(-2.0) to i16(-2)
+      v_cvt_i16_f16_e32(v[1], v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    expected = (-2) & 0xffff
+    self.assertEqual(result, expected, f"Expected i16(-2)=0x{expected:04x}, got 0x{result:04x}")
+
+  def test_v_mov_b16_src_hi_half(self):
+    """V_MOV_B16 with source from hi-half.
+
+    Regression test for: VOP1 f16 src0 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0xBEEF_DEAD: hi=0xBEEF, lo=0xDEAD
+      s_mov_b32(s[0], 0xBEEFDEAD),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = 0x0000_0000 initially
+      v_mov_b32_e32(v[1], 0),
+      # v_mov_b16 v[1], v[128] (reads hi half of v[0])
+      # Should move 0xBEEF to v[1].lo
+      v_mov_b16_e32(v[1], v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    self.assertEqual(result, 0xBEEF, f"Expected 0xBEEF from hi half, got 0x{result:04x}")
+
+
+class TestReciprocalF16(unittest.TestCase):
+  """Tests for V_RCP_F16 - reciprocal in half precision.
+
+  The pcode uses a 16-bit float literal: D0.f16 = 16'1.0 / S0.f16
+  This tests that the sized float literal (16'1.0) is correctly parsed.
+  """
+
+  def test_v_rcp_f16_one(self):
+    """V_RCP_F16: 1/1.0 = 1.0"""
+    import struct
+    def f16_to_bits(f): return struct.unpack('<H', struct.pack('<e', f))[0]
+    def bits_to_f16(b): return struct.unpack('<e', struct.pack('<H', b))[0]
+    instructions = [
+      # Load f16 1.0 into low 16 bits of v[0]
+      v_mov_b32_e32(v[0], f16_to_bits(1.0)),
+      v_rcp_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = bits_to_f16(st.vgpr[0][1] & 0xFFFF)
+    self.assertAlmostEqual(result, 1.0, places=2, msg="1/1.0 should be 1.0")
+
+  def test_v_rcp_f16_two(self):
+    """V_RCP_F16: 1/2.0 = 0.5"""
+    import struct
+    def f16_to_bits(f): return struct.unpack('<H', struct.pack('<e', f))[0]
+    def bits_to_f16(b): return struct.unpack('<e', struct.pack('<H', b))[0]
+    instructions = [
+      v_mov_b32_e32(v[0], f16_to_bits(2.0)),
+      v_rcp_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = bits_to_f16(st.vgpr[0][1] & 0xFFFF)
+    self.assertAlmostEqual(result, 0.5, places=2, msg="1/2.0 should be 0.5")
+
+  def test_v_rcp_f16_four(self):
+    """V_RCP_F16: 1/4.0 = 0.25"""
+    import struct
+    def f16_to_bits(f): return struct.unpack('<H', struct.pack('<e', f))[0]
+    def bits_to_f16(b): return struct.unpack('<e', struct.pack('<H', b))[0]
+    instructions = [
+      v_mov_b32_e32(v[0], f16_to_bits(4.0)),
+      v_rcp_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = bits_to_f16(st.vgpr[0][1] & 0xFFFF)
+    self.assertAlmostEqual(result, 0.25, places=2, msg="1/4.0 should be 0.25")
+
+
+class TestCvtNormF16(unittest.TestCase):
+  """Tests for V_CVT_NORM_I16_F16 and V_CVT_NORM_U16_F16."""
+
+  def test_cvt_norm_i16_f16_positive(self):
+    """V_CVT_NORM_I16_F16: f16 1.0 -> i16 max (32767)."""
+    instructions = [
+      s_mov_b32(s[0], f32_to_f16(1.0)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_norm_i16_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    self.assertEqual(result, 32767)
+
+  def test_cvt_norm_i16_f16_negative(self):
+    """V_CVT_NORM_I16_F16: f16 -1.0 -> i16 -32767 (0x8001)."""
+    instructions = [
+      s_mov_b32(s[0], f32_to_f16(-1.0)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_norm_i16_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    self.assertEqual(result, 0x8001)  # -32767, hardware uses symmetric range
+
+  def test_cvt_norm_i16_f16_zero(self):
+    """V_CVT_NORM_I16_F16: f16 0.0 -> i16 0."""
+    instructions = [
+      v_mov_b32_e32(v[0], 0),
+      v_cvt_norm_i16_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    self.assertEqual(result, 0)
+
+  def test_cvt_norm_u16_f16_one(self):
+    """V_CVT_NORM_U16_F16: f16 1.0 -> u16 max (65535)."""
+    instructions = [
+      s_mov_b32(s[0], f32_to_f16(1.0)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_norm_u16_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    self.assertEqual(result, 65535)
+
+  def test_cvt_norm_u16_f16_half(self):
+    """V_CVT_NORM_U16_F16: f16 0.5 -> u16 ~32768."""
+    instructions = [
+      s_mov_b32(s[0], f32_to_f16(0.5)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_cvt_norm_u16_f16_e32(v[1], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    self.assertAlmostEqual(result, 32768, delta=1)
+
+
+class TestPermlane64(unittest.TestCase):
+  """Tests for V_PERMLANE64_B32 instruction (wave64 cross-half swap)."""
+
+  def test_v_permlane64_b32_is_nop_in_wave32(self):
+    """V_PERMLANE64_B32 is a NOP in wave32 mode.
+
+    Per AMD pcode: "if WAVE32 then s_nop(...) else ... endif"
+    The emulator runs in wave32 mode, so this instruction should not modify registers.
+    """
+    instructions = [
+      v_mov_b32_e32(v[0], 0xCAFEBABE),  # source
+      v_mov_b32_e32(v[1], 0x12345678),  # dest (should be preserved)
+      v_permlane64_b32_e32(v[1], v[0]),  # NOP in wave32
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # Dest register should be unchanged (NOP behavior in wave32)
+    self.assertEqual(st.vgpr[0][1], 0x12345678)
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -46,7 +46,7 @@ class TestBasicArithmetic(unittest.TestCase):
    instructions = [
      v_mov_b32_e32(v[0], 2.0),
      v_mov_b32_e32(v[1], 4.0),
-      v_fmaak_f32_e32(v[2], v[0], v[1], 0x3f800000),
+      v_fmaak_f32_e32(v[2], v[0], v[1], literal=0x3f800000),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
@@ -56,7 +56,7 @@ class TestBasicArithmetic(unittest.TestCase):
    instructions = [
      v_mov_b32_e32(v[0], 2.0),
      v_mov_b32_e32(v[1], 1.0),
-      v_fmamk_f32_e32(v[2], v[0], 0x40800000, v[1]),
+      v_fmamk_f32_e32(v[2], v[0], v[1], literal=0x40800000),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 9.0, places=5)
@@ -66,7 +66,7 @@ class TestBasicArithmetic(unittest.TestCase):
    instructions = [
      v_mov_b32_e32(v[0], 4.0),
      v_mov_b32_e32(v[1], 1.0),
-      v_fmamk_f32_e32(v[2], v[0], f2i(0.5), v[1]),
+      v_fmamk_f32_e32(v[2], v[0], v[1], literal=f2i(0.5)),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 3.0, places=5)
@@ -237,6 +237,32 @@ class TestF16Ops(unittest.TestCase):
    # 2.0 * 3.0 + 1.0 = 7.0, f16 7.0 = 0x4700
    self.assertEqual(result, 0x4700, f"Expected 0x4700 (f16 7.0), got 0x{result:04x}")

+  def test_v_max_f16_basic(self):
+    """V_MAX_F16 returns the maximum of two f16 values."""
+    instructions = [
+      s_mov_b32(s[0], 0x3c00),  # f16 1.0
+      s_mov_b32(s[1], 0x4000),  # f16 2.0
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_max_f16_e32(v[2], v[0], v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][2] & 0xffff
+    self.assertEqual(result, 0x4000, f"Expected 0x4000 (f16 2.0), got 0x{result:04x}")
+
+  def test_v_min_f16_basic(self):
+    """V_MIN_F16 returns the minimum of two f16 values."""
+    instructions = [
+      s_mov_b32(s[0], 0x3c00),  # f16 1.0
+      s_mov_b32(s[1], 0x4000),  # f16 2.0
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_min_f16_e32(v[2], v[0], v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][2] & 0xffff
+    self.assertEqual(result, 0x3c00, f"Expected 0x3c00 (f16 1.0), got 0x{result:04x}")
+
  def test_v_fmaak_f16_basic(self):
    """V_FMAAK_F16: d = a * b + K."""
    instructions = [
@@ -244,7 +270,7 @@ class TestF16Ops(unittest.TestCase):
      s_mov_b32(s[1], 0x4200),  # f16 3.0
      v_mov_b32_e32(v[0], s[0]),
      v_mov_b32_e32(v[1], s[1]),
-      v_fmaak_f16_e32(v[2], v[0], v[1], 0x3c00),  # + f16 1.0
+      v_fmaak_f16_e32(v[2], v[0], v[1], literal=0x3c00),  # + f16 1.0
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2] & 0xffff
@@ -341,13 +367,300 @@ class TestHiHalfOps(unittest.TestCase):
      self.assertEqual(result, 0x4200, f"Lane {lane}: expected 0x4200, got 0x{result:04x}")


+class TestVop2F16HiHalf(unittest.TestCase):
+  """Regression tests for VOP2 f16 hi-half operand handling.
+
+  These test the bugs where:
+  1. VOP2 vsrc1 >= 384 (v[128]+) wasn't extracting hi 16 bits
+  2. VOP2 vdst >= 384 (v[128]+) wasn't preserving lo 16 bits
+  """
+
+  def test_v_add_f16_e32_vsrc1_hi_half(self):
+    """V_ADD_F16_E32 with vsrc1 from hi-half (v[128]+).
+
+    When vsrc1 >= 384 (representing v[128]+), the hardware reads from the hi 16 bits
+    of v[vsrc1-128]. The emulator must extract bits [31:16] from the actual VGPR.
+
+    Regression test for: VOP2 f16 vsrc1 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0x40003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # v_add_f16_e32 v[1], v[0], v[128]  (vsrc1=v[128] reads hi of v[0])
+      # In VOP2 encoding, vsrc1=384 means v[128], which maps to v[0].hi
+      # v[1] = v[0].lo + v[0].hi = 1.0 + 2.0 = 3.0
+      VOP2(VOP2Op.V_ADD_F16, vdst=v[1], src0=v[0], vsrc1=v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    # 1.0 + 2.0 = 3.0, f16 3.0 = 0x4200
+    self.assertEqual(result, 0x4200, f"Expected f16(3.0)=0x4200, got 0x{result:04x}")
+
+  def test_v_mul_f16_e32_vsrc1_hi_half(self):
+    """V_MUL_F16_E32 with vsrc1 from hi-half.
+
+    Regression test for: VOP2 f16 vsrc1 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4200_4000: hi=f16(3.0), lo=f16(2.0)
+      s_mov_b32(s[0], 0x42004000),
+      v_mov_b32_e32(v[0], s[0]),
+      # v_mul_f16_e32 v[1], v[0], v[128]  (vsrc1=v[128] reads hi of v[0])
+      # v[1] = v[0].lo * v[0].hi = 2.0 * 3.0 = 6.0
+      VOP2(VOP2Op.V_MUL_F16, vdst=v[1], src0=v[0], vsrc1=v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    # 2.0 * 3.0 = 6.0, f16 6.0 = 0x4600
+    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
+
+  def test_v_add_f16_e32_vdst_hi_half(self):
+    """V_ADD_F16_E32 writing to hi-half destination (v[128]+).
+
+    When vdst >= 384 (representing v[128]+), the hardware writes to bits [31:16]
+    of v[vdst-128] while preserving bits [15:0]. The emulator must merge the result.
+
+    Regression test for: VOP2 f16 vdst hi-half write bug.
+    """
+    instructions = [
+      # v[0] = 0x0000_BEEF: lo has marker value
+      s_mov_b32(s[0], 0x0000BEEF),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = f16(1.0), v[2] = f16(2.0)
+      s_mov_b32(s[1], 0x3c00),
+      s_mov_b32(s[2], 0x4000),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], s[2]),
+      # v_add_f16_e32 v[128], v[1], v[2]  (vdst=v[128] writes hi of v[0])
+      # v[0].hi = 1.0 + 2.0 = 3.0, v[0].lo preserved = 0xBEEF
+      VOP2(VOP2Op.V_ADD_F16, vdst=v[128], src0=v[1], vsrc1=v[2]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    hi = (st.vgpr[0][0] >> 16) & 0xffff
+    lo = st.vgpr[0][0] & 0xffff
+    # hi = 3.0 = 0x4200, lo preserved = 0xBEEF
+    self.assertEqual(hi, 0x4200, f"Expected hi=f16(3.0)=0x4200, got 0x{hi:04x}")
+    self.assertEqual(lo, 0xBEEF, f"Expected lo preserved=0xBEEF, got 0x{lo:04x}")
+
+  def test_v_mul_f16_e32_vdst_hi_half(self):
+    """V_MUL_F16_E32 writing to hi-half destination.
+
+    Regression test for: VOP2 f16 vdst hi-half write bug.
+    """
+    instructions = [
+      # v[0] = 0x0000_DEAD: lo has marker value
+      s_mov_b32(s[0], 0x0000DEAD),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = f16(2.0), v[2] = f16(4.0)
+      s_mov_b32(s[1], 0x4000),
+      s_mov_b32(s[2], 0x4400),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], s[2]),
+      # v_mul_f16_e32 v[128], v[1], v[2]  (vdst=v[128] writes hi of v[0])
+      # v[0].hi = 2.0 * 4.0 = 8.0, v[0].lo preserved = 0xDEAD
+      VOP2(VOP2Op.V_MUL_F16, vdst=v[128], src0=v[1], vsrc1=v[2]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    hi = (st.vgpr[0][0] >> 16) & 0xffff
+    lo = st.vgpr[0][0] & 0xffff
+    # hi = 8.0 = 0x4800, lo preserved = 0xDEAD
+    self.assertEqual(hi, 0x4800, f"Expected hi=f16(8.0)=0x4800, got 0x{hi:04x}")
+    self.assertEqual(lo, 0xDEAD, f"Expected lo preserved=0xDEAD, got 0x{lo:04x}")
+
+  def test_v_add_f16_e32_both_hi_half(self):
+    """V_ADD_F16_E32 with both vsrc1 and vdst as hi-half (different underlying regs).
+
+    Tests the combination of both fixes: reading vsrc1 from hi-half AND
+    writing result to hi-half destination, using different underlying VGPRs.
+
+    Regression test for: VOP2 f16 hi-half bugs (combined).
+    """
+    instructions = [
+      # v[0] = 0x4000_xxxx: hi=f16(2.0) for vsrc1
+      s_mov_b32(s[0], 0x40000000),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = 0x0000_3c00: lo=f16(1.0) for src0
+      s_mov_b32(s[1], 0x00003c00),
+      v_mov_b32_e32(v[1], s[1]),
+      # v[2] = 0x0000_CAFE: lo=marker for vdst preservation
+      s_mov_b32(s[2], 0x0000CAFE),
+      v_mov_b32_e32(v[2], s[2]),
+      # v_add_f16_e32 v[130], v[1], v[128]
+      # src0 = v[1].lo = 1.0
+      # vsrc1 = v[128] reads v[0].hi = 2.0
+      # result = 1.0 + 2.0 = 3.0
+      # vdst = v[130] writes to v[2].hi, preserving v[2].lo
+      VOP2(VOP2Op.V_ADD_F16, vdst=v[130], src0=v[1], vsrc1=v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    hi = (st.vgpr[0][2] >> 16) & 0xffff
+    lo = st.vgpr[0][2] & 0xffff
+    # hi = 3.0 = 0x4200, lo preserved = 0xCAFE
+    self.assertEqual(hi, 0x4200, f"Expected hi=f16(3.0)=0x4200, got 0x{hi:04x}")
+    self.assertEqual(lo, 0xCAFE, f"Expected lo preserved=0xCAFE, got 0x{lo:04x}")
+
+  def test_v_fmac_f16_e32_vsrc1_hi_half(self):
+    """V_FMAC_F16_E32 with vsrc1 from hi-half.
+
+    V_FMAC_F16: vdst = vdst + src0 * vsrc1
+
+    Regression test for: VOP2 f16 vsrc1 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0x40003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = f16(3.0) = 0x4200
+      s_mov_b32(s[1], 0x4200),
+      v_mov_b32_e32(v[1], s[1]),
+      # v_fmac_f16_e32 v[1], v[0], v[128]
+      # vdst = v[1] = 3.0 + v[0].lo * v[0].hi = 3.0 + 1.0 * 2.0 = 5.0
+      VOP2(VOP2Op.V_FMAC_F16, vdst=v[1], src0=v[0], vsrc1=v[128]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xffff
+    # 3.0 + 1.0 * 2.0 = 5.0, f16 5.0 = 0x4500
+    self.assertEqual(result, 0x4500, f"Expected f16(5.0)=0x4500, got 0x{result:04x}")
+
+  def test_v_fmac_f16_e32_vdst_hi_half(self):
+    """V_FMAC_F16_E32 writing to hi-half destination.
+
+    V_FMAC_F16: vdst.h = vdst.h + src0 * vsrc1
+
+    When vdst is v[128]+, the accumulator D0 must also read from the hi-half.
+    This tests the bug where D0 was read from lo-half instead of hi-half.
+
+    Regression test for: VOP2 FMAC hi-half D0 accumulator read bug.
+    """
+    instructions = [
+      # v[0] = 0x3800_DEAD: hi=f16(0.5), lo=marker (0xDEAD)
+      s_mov_b32(s[0], 0x3800DEAD),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = f16(2.0) = 0x4000
+      s_mov_b32(s[1], 0x4000),
+      v_mov_b32_e32(v[1], s[1]),
+      # v[2] = f16(3.0) = 0x4200
+      s_mov_b32(s[2], 0x4200),
+      v_mov_b32_e32(v[2], s[2]),
+      # v_fmac_f16_e32 v[128], v[1], v[2]
+      # vdst = v[128] means v[0].hi
+      # D0 = v[0].hi = 0.5
+      # result = D0 + src0 * vsrc1 = 0.5 + 2.0 * 3.0 = 6.5
+      # v[0].hi = 6.5, v[0].lo preserved = 0xDEAD
+      VOP2(VOP2Op.V_FMAC_F16, vdst=v[128], src0=v[1], vsrc1=v[2]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    hi = (st.vgpr[0][0] >> 16) & 0xffff
+    lo = st.vgpr[0][0] & 0xffff
+    # hi = 6.5 = 0x4680, lo preserved = 0xDEAD
+    self.assertEqual(hi, 0x4680, f"Expected hi=f16(6.5)=0x4680, got 0x{hi:04x}")
+    self.assertEqual(lo, 0xDEAD, f"Expected lo preserved=0xDEAD, got 0x{lo:04x}")
+
+  def test_v_mul_f16_e32_src0_hi_half(self):
+    """V_MUL_F16_E32 with src0 from hi-half (src0 >= v[128]).
+
+    When src0 >= 384 (representing v[128]+), the hardware reads from the hi 16 bits
+    of v[src0-128]. The emulator must extract bits [31:16] from the actual VGPR.
+
+    Regression test for: VOP2 f16 src0 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0x40003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = f16(3.0) = 0x4200
+      s_mov_b32(s[1], 0x4200),
+      v_mov_b32_e32(v[1], s[1]),
+      # v_mul_f16_e32 v[2], v[128], v[1]
+      # src0 = v[128] reads from v[0].hi = 2.0
+      # result = 2.0 * 3.0 = 6.0
+      VOP2(VOP2Op.V_MUL_F16, vdst=v[2], src0=v[128], vsrc1=v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][2] & 0xffff
+    # 2.0 * 3.0 = 6.0, f16 6.0 = 0x4600
+    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
+
+  def test_v_add_f16_e32_src0_hi_half(self):
+    """V_ADD_F16_E32 with src0 from hi-half (src0 >= v[128]).
+
+    Regression test for: VOP2 f16 src0 hi-half extraction bug.
+    """
+    instructions = [
+      # v[0] = 0x4000_3c00: hi=f16(2.0), lo=f16(1.0)
+      s_mov_b32(s[0], 0x40003c00),
+      v_mov_b32_e32(v[0], s[0]),
+      # v[1] = f16(5.0) = 0x4500
+      s_mov_b32(s[1], 0x4500),
+      v_mov_b32_e32(v[1], s[1]),
+      # v_add_f16_e32 v[2], v[128], v[1]
+      # src0 = v[128] reads from v[0].hi = 2.0
+      # result = 2.0 + 5.0 = 7.0
+      VOP2(VOP2Op.V_ADD_F16, vdst=v[2], src0=v[128], vsrc1=v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][2] & 0xffff
+    # 2.0 + 5.0 = 7.0, f16 7.0 = 0x4700
+    self.assertEqual(result, 0x4700, f"Expected f16(7.0)=0x4700, got 0x{result:04x}")
+
+
+class TestF16InlineConstants(unittest.TestCase):
+  """Regression tests for VOP2 F16 inline float constants.
+
+  For 16-bit VOP2 operations (v_add_f16, v_mul_f16, etc.), inline float constants
+  like 1.0, 2.0 must use F16 encoding (0x3c00, 0x4000) not F32 encoding (0x3f800000).
+
+  The emulator's rsrc() function needs bits=16 to select F16_INLINE constants.
+
+  Regression test for: VOP2 16-bit inline constant using F32 instead of F16.
+  """
+
+  def test_v_add_f16_inline_constant_1_0(self):
+    """V_ADD_F16_E32 with inline constant 1.0 should use F16 encoding."""
+    instructions = [
+      s_mov_b32(s[0], 0x3c00),  # f16 1.0
+      v_mov_b32_e32(v[0], s[0]),
+      # v_add_f16_e32 v[1], 1.0, v[0]  -- 1.0 must be F16 0x3c00, not F32 0x3f800000
+      v_add_f16_e32(v[1], 1.0, v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xFFFF
+    # 1.0 + 1.0 = 2.0, f16 2.0 = 0x4000
+    self.assertEqual(result, 0x4000, f"Expected f16(2.0)=0x4000, got 0x{result:04x}")
+
+  def test_v_add_f16_inline_constant_2_0(self):
+    """V_ADD_F16_E32 with inline constant 2.0."""
+    instructions = [
+      s_mov_b32(s[0], 0x4200),  # f16 3.0
+      v_mov_b32_e32(v[0], s[0]),
+      v_add_f16_e32(v[1], 2.0, v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xFFFF
+    # 2.0 + 3.0 = 5.0, f16 5.0 = 0x4500
+    self.assertEqual(result, 0x4500, f"Expected f16(5.0)=0x4500, got 0x{result:04x}")
+
+  def test_v_mul_f16_inline_constant(self):
+    """V_MUL_F16_E32 with inline constant 2.0."""
+    instructions = [
+      s_mov_b32(s[0], 0x4200),  # f16 3.0
+      v_mov_b32_e32(v[0], s[0]),
+      v_mul_f16_e32(v[1], 2.0, v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1] & 0xFFFF
+    # 2.0 * 3.0 = 6.0, f16 6.0 = 0x4600
+    self.assertEqual(result, 0x4600, f"Expected f16(6.0)=0x4600, got 0x{result:04x}")
+
+
 class TestCndmask(unittest.TestCase):
  """Tests for V_CNDMASK_B32 and V_CNDMASK_B16."""

  def test_v_cndmask_b16_select_src0(self):
    """V_CNDMASK_B16 selects src0 when VCC bit is 0."""
    instructions = [
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 0),  # VCC = 0
+      s_mov_b32(VCC_LO, 0),  # VCC = 0
      s_mov_b32(s[0], 0x3c00),  # f16 1.0
      s_mov_b32(s[1], 0x4000),  # f16 2.0
      v_mov_b32_e32(v[0], s[0]),
@@ -361,7 +674,7 @@ class TestCndmask(unittest.TestCase):
  def test_v_cndmask_b16_select_src1(self):
    """V_CNDMASK_B16 selects src1 when VCC bit is 1."""
    instructions = [
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 1),  # VCC = 1
+      s_mov_b32(VCC_LO, 1),  # VCC = 1
      s_mov_b32(s[0], 0x3c00),  # f16 1.0
      s_mov_b32(s[1], 0x4000),  # f16 2.0
      v_mov_b32_e32(v[0], s[0]),
@@ -381,7 +694,7 @@ class TestCndmask(unittest.TestCase):
      v_mov_b32_e32(v[1], s[1]),
      s_mov_b32(s[2], 0xDEAD0000),  # v2 initial: hi=0xDEAD, lo=0
      v_mov_b32_e32(v[2], s[2]),
-      s_mov_b32(s[SrcEnum.VCC_LO - 128], 0),  # vcc = 0, select src0
+      s_mov_b32(VCC_LO, 0),  # vcc = 0, select src0
      # opsel=0b1011: bit0=src0 hi, bit1=src1 hi, bit3=dst hi
      VOP3(VOP3Op.V_CNDMASK_B16, vdst=v[2], src0=v[0], src1=v[1], src2=SrcEnum.VCC_LO, opsel=0b1011),
    ]
@@ -447,5 +760,224 @@ class TestSpecialFloatValues(unittest.TestCase):
    self.assertEqual(st.vgpr[0][1], 0x00000000)


+class TestCarryOps(unittest.TestCase):
+  """Tests for VOP2 carry instructions (v_add_co_ci_u32, v_sub_co_ci_u32, v_subrev_co_ci_u32)."""
+
+  def test_v_subrev_co_ci_u32_no_borrow(self):
+    """V_SUBREV_CO_CI_U32: D0 = S1 - S0 - VCC_IN, when VCC_IN=0."""
+    instructions = [
+      s_mov_b32(VCC_LO, 0),  # VCC = 0 (no borrow in)
+      v_mov_b32_e32(v[0], 5),  # S0 = 5
+      v_mov_b32_e32(v[1], 10),  # S1 = 10
+      v_subrev_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 10 - 5 - 0 = 5
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 5)
+    self.assertEqual(st.vcc, 0)  # No borrow out
+
+  def test_v_subrev_co_ci_u32_with_borrow(self):
+    """V_SUBREV_CO_CI_U32: D0 = S1 - S0 - VCC_IN, when VCC_IN=1."""
+    instructions = [
+      s_mov_b32(VCC_LO, 1),  # VCC = 1 (borrow in)
+      v_mov_b32_e32(v[0], 5),  # S0 = 5
+      v_mov_b32_e32(v[1], 10),  # S1 = 10
+      v_subrev_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 10 - 5 - 1 = 4
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 4)
+    self.assertEqual(st.vcc, 0)  # No borrow out
+
+  def test_v_subrev_co_ci_u32_generates_borrow(self):
+    """V_SUBREV_CO_CI_U32: generates borrow when S0 + VCC_IN > S1."""
+    instructions = [
+      s_mov_b32(VCC_LO, 0),  # VCC = 0
+      v_mov_b32_e32(v[0], 10),  # S0 = 10
+      v_mov_b32_e32(v[1], 5),  # S1 = 5
+      v_subrev_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 5 - 10 - 0 = -5 (underflow)
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 0xFFFFFFFB)  # -5 as unsigned
+    self.assertEqual(st.vcc, 1)  # Borrow out
+
+  def test_v_add_co_ci_u32_no_carry(self):
+    """V_ADD_CO_CI_U32: D0 = S0 + S1 + VCC_IN, when VCC_IN=0."""
+    instructions = [
+      s_mov_b32(VCC_LO, 0),  # VCC = 0 (no carry in)
+      v_mov_b32_e32(v[0], 5),  # S0 = 5
+      v_mov_b32_e32(v[1], 10),  # S1 = 10
+      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 5 + 10 + 0 = 15
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 15)
+    self.assertEqual(st.vcc, 0)  # No carry out
+
+  def test_v_add_co_ci_u32_with_carry(self):
+    """V_ADD_CO_CI_U32: D0 = S0 + S1 + VCC_IN, when VCC_IN=1."""
+    instructions = [
+      s_mov_b32(VCC_LO, 1),  # VCC = 1 (carry in)
+      v_mov_b32_e32(v[0], 5),  # S0 = 5
+      v_mov_b32_e32(v[1], 10),  # S1 = 10
+      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 5 + 10 + 1 = 16
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 16)
+    self.assertEqual(st.vcc, 0)  # No carry out
+
+  def test_v_add_co_ci_u32_generates_carry(self):
+    """V_ADD_CO_CI_U32: generates carry when overflow occurs."""
+    instructions = [
+      s_mov_b32(VCC_LO, 1),  # VCC = 1 (carry in)
+      s_mov_b32(s[0], 0xFFFFFFFF),  # max u32
+      v_mov_b32_e32(v[0], s[0]),  # S0 = 0xFFFFFFFF
+      v_mov_b32_e32(v[1], 0),  # S1 = 0
+      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 0xFFFFFFFF + 0 + 1 = 0 (overflow)
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 0)  # Overflowed to 0
+    self.assertEqual(st.vcc, 1)  # Carry out
+
+  def test_v_add_co_ci_u32_clears_carry(self):
+    """V_ADD_CO_CI_U32: VCC must be updated even when no carry is generated.
+
+    This tests the case where VCC=1 going in (carry-in consumed) but the addition
+    does not overflow, so VCC must be cleared to 0.
+
+    Regression test for: VCC not being written by v_add_co_ci_u32_e32.
+    """
+    instructions = [
+      s_mov_b32(VCC_LO, 1),  # VCC = 1 (carry in)
+      v_mov_b32_e32(v[0], 1),  # S0 = 1
+      v_mov_b32_e32(v[1], 1),  # S1 = 1
+      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 1 + 1 + 1 = 3 (no overflow)
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 3)  # 1 + 1 + 1 = 3
+    self.assertEqual(st.vcc, 0)  # No carry out - VCC must be cleared
+
+  def test_v_add_co_ci_u32_multilane_clears_vcc(self):
+    """V_ADD_CO_CI_U32 with multiple lanes: VCC bits must be updated per-lane.
+
+    When VCC has multiple bits set (one per active lane), and the addition doesn't
+    overflow for any lane, all VCC bits must be cleared.
+
+    Regression test for: VCC not being written by v_add_co_ci_u32_e32 in multi-lane case.
+    """
+    instructions = [
+      s_mov_b32(VCC_LO, 0b11),  # VCC = 0b11 (lanes 0,1 have carry-in)
+      v_mov_b32_e32(v[0], 1),  # S0 = 1 for all lanes
+      v_mov_b32_e32(v[1], 1),  # S1 = 1 for all lanes
+      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 1 + 1 + 1 = 3 (no overflow)
+    ]
+    st = run_program(instructions, n_lanes=2)
+    self.assertEqual(st.vgpr[0][2], 3)  # lane 0: 1 + 1 + 1 = 3
+    self.assertEqual(st.vgpr[1][2], 3)  # lane 1: 1 + 1 + 1 = 3
+    self.assertEqual(st.vcc, 0)  # No carry out for any lane - all VCC bits must be cleared
+
+  def test_v_add_co_ci_u32_preserves_inactive_vcc_bits(self):
+    """V_ADD_CO_CI_U32: VCC carry-out overwrites entire VCC register.
+
+    VOP2 carry instructions write ALL VCC bits based on carry-out, clearing
+    bits for lanes that don't overflow regardless of EXEC mask.
+
+    Note: This differs from VOPC which only writes active lane bits.
+    """
+    instructions = [
+      s_mov_b32(VCC_LO, 0x00010000),  # VCC bit 16 set
+      v_mov_b32_e32(v[0], 1),  # S0 = 1
+      v_mov_b32_e32(v[1], 1),  # S1 = 1
+      v_add_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 1 + 1 + 0 = 2 (no carry)
+    ]
+    st = run_program(instructions, n_lanes=4)
+    self.assertEqual(st.vgpr[0][2], 2)  # lane 0: 1 + 1 + 0 = 2
+    # VCC should be completely cleared (all lanes have no carry-out)
+    self.assertEqual(st.vcc, 0)
+
+  def test_v_add_co_ci_u32_all_lanes_same_result(self):
+    """V_ADD_CO_CI_U32: all active lanes should produce the same result.
+
+    When the same constant inputs are used across all lanes, each lane should
+    compute the same result and write to its own VGPR slot.
+
+    Regression test for: VGPR writes not happening for all lanes.
+    """
+    instructions = [
+      s_mov_b32(VCC_LO, 0),  # No carry-in
+      v_mov_b32_e32(v[0], 3),  # inline constant 3
+      v_mov_b32_e32(v[1], 5),  # value 5
+      v_add_co_ci_u32_e32(v[1], 3, v[1]),  # v[1] = 3 + v[1] + 0 = 3 + 5 = 8
+    ]
+    st = run_program(instructions, n_lanes=4)
+    # All 4 lanes should have v[1] = 8
+    for lane in range(4):
+      self.assertEqual(st.vgpr[lane][1], 8, f"lane {lane} should have v[1]=8")
+
+  def test_v_sub_co_ci_u32_no_borrow(self):
+    """V_SUB_CO_CI_U32: D0 = S0 - S1 - VCC_IN, when VCC_IN=0."""
+    instructions = [
+      s_mov_b32(VCC_LO, 0),  # VCC = 0 (no borrow in)
+      v_mov_b32_e32(v[0], 10),  # S0 = 10
+      v_mov_b32_e32(v[1], 5),  # S1 = 5
+      v_sub_co_ci_u32_e32(v[2], v[0], v[1]),  # D0 = 10 - 5 - 0 = 5
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 5)
+    self.assertEqual(st.vcc, 0)  # No borrow out
+
+  def test_v_sub_co_ci_u32_vop3sd_separate_carry_regs(self):
+    """VOP3SD V_SUB_CO_CI_U32: carry-in from src2, carry-out to sdst (separate registers).
+
+    This tests the VOP3SD encoding where src2 specifies the carry-in register
+    independently from sdst (carry-out). The bug was reading carry-in from sdst
+    instead of src2.
+
+    Computation: D0 = S0 - S1 - carry_in = 0 - 0 - 1 = -1 = 0xFFFFFFFF
+    """
+    instructions = [
+      s_mov_b32(s[6], 1),  # carry-in = 1 (in s[6])
+      s_mov_b32(s[10], 0),  # carry-out dest = 0 initially (in s[10])
+      # VOP3SD: v_sub_co_ci_u32(vdst, sdst, src0, src1, src2)
+      # src2 is carry-in (s[6]=1), sdst is carry-out (s[10])
+      v_sub_co_ci_u32(v[0], s[10], 0, 0, s[6]),  # D0 = 0 - 0 - 1 = -1
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0xFFFFFFFF)  # -1 as unsigned
+    self.assertEqual(st.sgpr[10], 1)  # Borrow out to s[10]
+
+  def test_v_add_co_ci_u32_vop3sd_separate_carry_regs(self):
+    """VOP3SD V_ADD_CO_CI_U32: carry-in from src2, carry-out to sdst (separate registers).
+
+    This tests the VOP3SD encoding where src2 specifies the carry-in register
+    independently from sdst (carry-out).
+
+    Computation: D0 = S0 + S1 + carry_in = 5 + 10 + 1 = 16
+    """
+    instructions = [
+      s_mov_b32(s[6], 1),  # carry-in = 1 (in s[6])
+      s_mov_b32(s[10], 0),  # carry-out dest = 0 initially (in s[10])
+      # VOP3SD: v_add_co_ci_u32(vdst, sdst, src0, src1, src2)
+      v_add_co_ci_u32(v[0], s[10], 5, 10, s[6]),  # D0 = 5 + 10 + 1 = 16
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 16)
+    self.assertEqual(st.sgpr[10], 0)  # No carry out
+
+  def test_v_add_co_ci_u32_vop3sd_null_sdst(self):
+    """VOP3SD V_ADD_CO_CI_U32 with sdst=NULL: carry output is discarded.
+
+    When sdst=NULL (register 124), the carry-out should NOT be written anywhere.
+    We verify this by checking that VCC (which we set to a sentinel value) is unchanged.
+    """
+    instructions = [
+      s_mov_b32(VCC_LO, 0xDEADBEEF),  # Sentinel value in VCC
+      s_mov_b32(s[6], 0),  # carry-in = 0
+      # VOP3SD with NULL sdst: carry-out should be discarded
+      # Uses 0xFFFFFFFF + 1 + 0 = 0 with carry-out=1, but carry should not be written
+      v_add_co_ci_u32(v[0], NULL, 0xFFFFFFFF, 1, s[6]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][0], 0)  # 0xFFFFFFFF + 1 + 0 = 0 (overflow)
+    self.assertEqual(st.vcc, 0xDEADBEEF)  # VCC unchanged - carry was discarded
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -23,14 +23,12 @@ class TestPackInstructions(unittest.TestCase):

  def test_v_pack_b32_f16_opsel_hi_hi(self):
    """V_PACK_B32_F16 with opsel to read high halves."""
-    inst = v_pack_b32_f16(v[2], v[0], v[1])
-    inst._values['opsel'] = 0b0011
    instructions = [
      s_mov_b32(s[0], 0x40003c00),  # hi=2.0, lo=1.0
      s_mov_b32(s[1], 0x44004200),  # hi=4.0, lo=3.0
      v_mov_b32_e32(v[0], s[0]),
      v_mov_b32_e32(v[1], s[1]),
-      inst,
+      v_pack_b32_f16(v[2], v[0], v[1], opsel=0b0011),
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2]
@@ -83,14 +81,12 @@ class TestPackMore(unittest.TestCase):

  def test_v_pack_b32_f16_opsel_lo_hi(self):
    """V_PACK_B32_F16 with opsel=0b0010 to read lo from src0, hi from src1."""
-    inst = v_pack_b32_f16(v[2], v[0], v[1])
-    inst._values['opsel'] = 0b0010
    instructions = [
      s_mov_b32(s[0], 0x40003c00),
      s_mov_b32(s[1], 0x44004200),
      v_mov_b32_e32(v[0], s[0]),
      v_mov_b32_e32(v[1], s[1]),
-      inst,
+      v_pack_b32_f16(v[2], v[0], v[1], opsel=0b0010),
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2]
@@ -98,14 +94,12 @@ class TestPackMore(unittest.TestCase):

  def test_v_pack_b32_f16_opsel_hi_lo(self):
    """V_PACK_B32_F16 with opsel=0b0001 to read hi from src0, lo from src1."""
-    inst = v_pack_b32_f16(v[2], v[0], v[1])
-    inst._values['opsel'] = 0b0001
    instructions = [
      s_mov_b32(s[0], 0x40003c00),
      s_mov_b32(s[1], 0x44004200),
      v_mov_b32_e32(v[0], s[0]),
      v_mov_b32_e32(v[1], s[1]),
-      inst,
+      v_pack_b32_f16(v[2], v[0], v[1], opsel=0b0001),
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2]
@@ -155,7 +149,6 @@ class TestFmaMix(unittest.TestCase):

  def test_v_fma_mix_f32_src2_f16_lo(self):
    """V_FMA_MIX_F32 with src2 as f16 from lo bits."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_2 = f32_to_f16(2.0)
    instructions = [
      s_mov_b32(s[0], f2i(1.0)),
@@ -172,7 +165,6 @@ class TestFmaMix(unittest.TestCase):

  def test_v_fma_mix_f32_src2_f16_hi(self):
    """V_FMA_MIX_F32 with src2 as f16 from hi bits."""
-    from extra.assembly.amd.pcode import f32_to_f16
    f16_2 = f32_to_f16(2.0)
    val = (f16_2 << 16) | 0
    instructions = [
@@ -203,9 +195,60 @@ class TestFmaMix(unittest.TestCase):
    result = i2f(st.vgpr[0][3])
    self.assertAlmostEqual(result, 7.0, places=5)

+  def test_v_fma_mix_f32_with_abs_f16_src2_lo(self):
+    """V_FMA_MIX_F32 with abs modifier on f16 src2 (lo half). Regression test for sin(1.0) bug."""
+    f16_neg1 = f32_to_f16(-1.0)  # 0xbc00
+    instructions = [
+      s_mov_b32(s[0], f2i(0.0)),  # src0 = 0.0 (f32)
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[1], f2i(1.0)),  # src1 = 1.0 (f32)
+      v_mov_b32_e32(v[1], s[1]),
+      s_mov_b32(s[2], f16_neg1),  # src2 = -1.0 (f16 in lo)
+      v_mov_b32_e32(v[2], s[2]),
+      # 0*1 + abs(-1.0) = 1.0; neg_hi=4 means abs on src2, opsel_hi2=1 means src2 is f16
+      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=1, neg_hi=4),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][3])
+    self.assertAlmostEqual(result, 1.0, places=5)
+
+  def test_v_fma_mix_f32_with_neg_f16_src2_lo(self):
+    """V_FMA_MIX_F32 with neg modifier on f16 src2 (lo half)."""
+    f16_1 = f32_to_f16(1.0)  # 0x3c00
+    instructions = [
+      s_mov_b32(s[0], f2i(0.0)),  # src0 = 0.0 (f32)
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[1], f2i(1.0)),  # src1 = 1.0 (f32)
+      v_mov_b32_e32(v[1], s[1]),
+      s_mov_b32(s[2], f16_1),  # src2 = 1.0 (f16 in lo)
+      v_mov_b32_e32(v[2], s[2]),
+      # 0*1 + neg(1.0) = -1.0; neg=4 means neg on src2, opsel_hi2=1 means src2 is f16
+      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=1, neg=4),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][3])
+    self.assertAlmostEqual(result, -1.0, places=5)
+
+  def test_v_fma_mix_f32_with_abs_f16_src2_hi(self):
+    """V_FMA_MIX_F32 with abs modifier on f16 src2 (hi half)."""
+    f16_neg1 = f32_to_f16(-1.0)  # 0xbc00
+    val = (f16_neg1 << 16) | 0  # -1.0 in hi, 0 in lo
+    instructions = [
+      s_mov_b32(s[0], f2i(0.0)),
+      v_mov_b32_e32(v[0], s[0]),
+      s_mov_b32(s[1], f2i(1.0)),
+      v_mov_b32_e32(v[1], s[1]),
+      s_mov_b32(s[2], val),
+      v_mov_b32_e32(v[2], s[2]),
+      # opsel=4 selects hi half of src2; neg_hi=4 means abs on src2
+      VOP3P(VOP3POp.V_FMA_MIX_F32, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=4, opsel_hi=0, opsel_hi2=1, neg_hi=4),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][3])
+    self.assertAlmostEqual(result, 1.0, places=5)
+
  def test_v_fma_mixlo_f16(self):
    """V_FMA_MIXLO_F16 writes to low 16 bits of destination."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], f2i(2.0)),
      v_mov_b32_e32(v[0], s[0]),
@@ -218,14 +261,13 @@ class TestFmaMix(unittest.TestCase):
      VOP3P(VOP3POp.V_FMA_MIXLO_F16, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=0),
    ]
    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][3] & 0xffff)
+    lo = f16(st.vgpr[0][3] & 0xffff)
    hi = (st.vgpr[0][3] >> 16) & 0xffff
    self.assertAlmostEqual(lo, 7.0, places=1)
    self.assertEqual(hi, 0xdead, f"hi should be preserved, got 0x{hi:04x}")

  def test_v_fma_mixlo_f16_all_f32_sources(self):
    """V_FMA_MIXLO_F16 with all f32 sources."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], f2i(1.0)),
      v_mov_b32_e32(v[0], s[0]),
@@ -237,13 +279,12 @@ class TestFmaMix(unittest.TestCase):
      VOP3P(VOP3POp.V_FMA_MIXLO_F16, vdst=v[3], src0=v[0], src1=v[1], src2=v[2], opsel=0, opsel_hi=0, opsel_hi2=0),
    ]
    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][3] & 0xffff)
+    lo = f16(st.vgpr[0][3] & 0xffff)
    # 1*2+3 = 5
    self.assertAlmostEqual(lo, 5.0, places=1)

  def test_v_fma_mixlo_f16_sin_case(self):
    """V_FMA_MIXLO_F16 case from sin kernel."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x3f800000),  # f32 1.0
      v_mov_b32_e32(v[3], s[0]),
@@ -256,7 +297,7 @@ class TestFmaMix(unittest.TestCase):
      VOP3P(VOP3POp.V_FMA_MIXLO_F16, vdst=v[3], src0=v[3], src1=s[6], src2=v[5], opsel=0, opsel_hi=0, opsel_hi2=0),
    ]
    st = run_program(instructions, n_lanes=1)
-    lo = _f16(st.vgpr[0][3] & 0xffff)
+    lo = f16(st.vgpr[0][3] & 0xffff)
    self.assertAlmostEqual(lo, -3.14159, delta=0.01)


@@ -265,7 +306,6 @@ class TestVOP3P(unittest.TestCase):

  def test_v_pk_add_f16_basic(self):
    """V_PK_ADD_F16 adds two packed f16 values."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x40003c00),  # hi=2.0, lo=1.0
      s_mov_b32(s[1], 0x44004200),  # hi=4.0, lo=3.0
@@ -275,14 +315,13 @@ class TestVOP3P(unittest.TestCase):
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
    self.assertAlmostEqual(lo, 4.0, places=2)
    self.assertAlmostEqual(hi, 6.0, places=2)

  def test_v_pk_mul_f16_basic(self):
    """V_PK_MUL_F16 multiplies two packed f16 values."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x42004000),  # hi=3.0, lo=2.0
      s_mov_b32(s[1], 0x45004400),  # hi=5.0, lo=4.0
@@ -292,14 +331,13 @@ class TestVOP3P(unittest.TestCase):
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
    self.assertAlmostEqual(lo, 8.0, places=1)
    self.assertAlmostEqual(hi, 15.0, places=1)

  def test_v_pk_fma_f16_basic(self):
    """V_PK_FMA_F16: D = A * B + C for packed f16."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x42004000),  # A: hi=3.0, lo=2.0
      s_mov_b32(s[1], 0x45004400),  # B: hi=5.0, lo=4.0
@@ -311,8 +349,8 @@ class TestVOP3P(unittest.TestCase):
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][3]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
    self.assertAlmostEqual(lo, 9.0, places=1)   # 2*4+1
    self.assertAlmostEqual(hi, 16.0, places=0)  # 3*5+1

@@ -321,7 +359,6 @@ class TestVOP3P(unittest.TestCase):
    Inline constants for VOP3P are f16 values in the low 16 bits only.
    hi half of inline constant is 0, so hi result = v0.hi + 0 = 1.0.
    """
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x3c003c00),  # packed f16: hi=1.0, lo=1.0
      v_mov_b32_e32(v[0], s[0]),
@@ -329,8 +366,8 @@ class TestVOP3P(unittest.TestCase):
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][1]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
    # lo = 1.0 + 1.0 = 2.0, hi = 1.0 + 0.0 = 1.0 (inline const hi half is 0)
    self.assertAlmostEqual(lo, 2.0, places=2)
    self.assertAlmostEqual(hi, 1.0, places=2)
@@ -339,7 +376,6 @@ class TestVOP3P(unittest.TestCase):
    """V_PK_MUL_F16 with inline constant POS_TWO (2.0).
    Inline constant has value only in low 16 bits, hi is 0.
    """
-    from extra.assembly.amd.pcode import _f16
    # v0 = packed (3.0, 4.0), multiply by POS_TWO
    # lo = 3.0 * 2.0 = 6.0, hi = 4.0 * 0.0 = 0.0 (inline const hi is 0)
    instructions = [
@@ -349,14 +385,120 @@ class TestVOP3P(unittest.TestCase):
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][1]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
    self.assertAlmostEqual(lo, 6.0, places=1)
    self.assertAlmostEqual(hi, 0.0, places=1)

+  def test_v_pk_add_u16_float_inline_const_opsel(self):
+    """V_PK_ADD_U16 with float inline constant 2.0
+    Regression test: for integer packed ops, do not perform the f32->f16 conversion.
+    """
+    # src1 = inline float constant 2.0
+    instructions = [
+      s_mov_b32(s[0], 0x00030005),  # packed u16: hi=3, lo=5
+      v_mov_b32_e32(v[0], s[0]),
+      v_pk_add_u16(v[1], v[0], SrcEnum.POS_TWO, opsel_hi=3, opsel_hi2=1),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][1]
+    lo = result & 0xffff
+    hi = (result >> 16) & 0xffff
+    # lo = 5 + 0x0000 = 0x0005, hi = 3 + 0x4000 = 0x4003
+    self.assertEqual(lo, 0x0005, f"lo: expected 0x0005, got 0x{lo:04x}")
+    self.assertEqual(hi, 0x4003, f"hi: expected 0x4003, got 0x{hi:04x}")
+
+
+class TestWMMAF16(unittest.TestCase):
+  """Tests for WMMA F16 output variant (V_WMMA_F16_16X16X16_F16).
+
+  Note: RDNA3 WMMA F16 uses 8 VGPRs for accumulator/output (same as F32 variant),
+  but values are packed as f16. This differs from RDNA4 which uses 4 VGPRs.
+  """
+
+  def test_v_wmma_f16_16x16x16_f16_all_ones(self):
+    """V_WMMA_F16_16X16X16_F16 with all ones produces 16.0 in f16."""
+    instructions = []
+    instructions.append(s_mov_b32(s[0], 0x3c003c00))  # packed f16 1.0
+    # Initialize A matrix in v[16:23] (8 regs)
+    for i in range(16, 24):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize B matrix in v[24:31] (8 regs)
+    for i in range(24, 32):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize C (accumulator) in v[0:7] to zero (8 regs for RDNA3 WMMA F16)
+    for i in range(8):
+      instructions.append(v_mov_b32_e32(v[i], 0))
+    # WMMA F16: D = A @ B + C
+    instructions.append(v_wmma_f16_16x16x16_f16(v[0:7], v[16:23], v[24:31], v[0:7]))
+    st = run_program(instructions, n_lanes=32)
+    # Result should be 16.0 in f16, stored in lo 16 bits of each VGPR (hi bits are 0)
+    for lane in range(32):
+      for reg in range(8):
+        result = st.vgpr[lane][reg]
+        lo = f16(result & 0xffff)
+        self.assertAlmostEqual(lo, 16.0, places=1, msg=f"v[{reg}] lane {lane}: expected 16.0, got {lo}")
+        self.assertEqual(result >> 16, 0, msg=f"v[{reg}] lane {lane}: hi bits should be 0")
+
+  def test_v_wmma_f16_16x16x16_f16_with_accumulator(self):
+    """V_WMMA_F16_16X16X16_F16 with non-zero accumulator."""
+    instructions = []
+    instructions.append(s_mov_b32(s[0], 0x3c003c00))  # packed f16 1.0
+    instructions.append(s_mov_b32(s[1], 0x4500))  # f16 5.0 in lo bits only
+    # Initialize A matrix in v[16:23] (8 regs)
+    for i in range(16, 24):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize B matrix in v[24:31] (8 regs)
+    for i in range(24, 32):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize C (accumulator) in v[0:7] to 5.0 in lo bits (8 regs for RDNA3 WMMA F16)
+    for i in range(8):
+      instructions.append(v_mov_b32_e32(v[i], s[1]))
+    # WMMA F16: D = A @ B + C
+    instructions.append(v_wmma_f16_16x16x16_f16(v[0:7], v[16:23], v[24:31], v[0:7]))
+    st = run_program(instructions, n_lanes=32)
+    # Result should be 16.0 + 5.0 = 21.0 in f16, stored in lo 16 bits (hi bits are 0)
+    for lane in range(32):
+      for reg in range(8):
+        result = st.vgpr[lane][reg]
+        lo = f16(result & 0xffff)
+        self.assertAlmostEqual(lo, 21.0, places=0, msg=f"v[{reg}] lane {lane}: expected 21.0, got {lo}")
+        self.assertEqual(result >> 16, 0, msg=f"v[{reg}] lane {lane}: hi bits should be 0")
+
+  def test_v_wmma_f16_16x16x16_f16_high_registers(self):
+    """V_WMMA_F16_16X16X16_F16 with high register indices.
+
+    Regression test: WMMA was using static register indices instead of dynamic.
+    This test uses v[64:71] for A, v[80:87] for B, v[96:103] for C/D.
+    """
+    instructions = []
+    instructions.append(s_mov_b32(s[0], 0x3c003c00))  # packed f16 1.0
+    # Initialize A matrix in v[64:71] (8 regs)
+    for i in range(64, 72):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize B matrix in v[80:87] (8 regs)
+    for i in range(80, 88):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize C (accumulator) in v[96:103] to zero (8 regs for RDNA3 WMMA F16)
+    for i in range(96, 104):
+      instructions.append(v_mov_b32_e32(v[i], 0))
+    # WMMA F16: D = A @ B + C, result in v[96:103]
+    instructions.append(v_wmma_f16_16x16x16_f16(v[96:103], v[64:71], v[80:87], v[96:103]))
+    # Copy results to v[0:7] for checking
+    for i in range(8):
+      instructions.append(v_mov_b32_e32(v[i], v[96+i]))
+    st = run_program(instructions, n_lanes=32)
+    # Result should be 16.0 in f16, stored in lo 16 bits (hi bits are 0)
+    for lane in range(32):
+      for reg in range(8):
+        result = st.vgpr[lane][reg]
+        lo = f16(result & 0xffff)
+        self.assertAlmostEqual(lo, 16.0, places=1, msg=f"v[{reg}] lane {lane}: expected 16.0, got {lo}")
+        self.assertEqual(result >> 16, 0, msg=f"v[{reg}] lane {lane}: hi bits should be 0")
+

 class TestWMMA(unittest.TestCase):
-  """Tests for WMMA (Wave Matrix Multiply-Accumulate) instructions."""
+  """Tests for WMMA (Wave Matrix Multiply-Accumulate) instructions with F32 output."""

  def test_v_wmma_f32_16x16x16_f16_all_ones(self):
    """V_WMMA_F32_16X16X16_F16 with all ones produces 16.0."""
@@ -366,7 +508,7 @@ class TestWMMA(unittest.TestCase):
      instructions.append(v_mov_b32_e32(v[i], s[0]))
    for i in range(8):
      instructions.append(v_mov_b32_e32(v[i], 0))
-    instructions.append(v_wmma_f32_16x16x16_f16(v[0], v[16], v[24], v[0]))
+    instructions.append(v_wmma_f32_16x16x16_f16(v[0:7], v[16:23], v[24:31], v[0:7]))
    st = run_program(instructions, n_lanes=32)
    expected = f2i(16.0)
    for lane in range(32):
@@ -383,7 +525,76 @@ class TestWMMA(unittest.TestCase):
      instructions.append(v_mov_b32_e32(v[i], s[0]))
    for i in range(8):
      instructions.append(v_mov_b32_e32(v[i], s[1]))
-    instructions.append(v_wmma_f32_16x16x16_f16(v[0], v[16], v[24], v[0]))
+    instructions.append(v_wmma_f32_16x16x16_f16(v[0:7], v[16:23], v[24:31], v[0:7]))
+    st = run_program(instructions, n_lanes=32)
+    expected = f2i(21.0)  # 16 + 5
+    for lane in range(32):
+      for reg in range(8):
+        result = st.vgpr[lane][reg]
+        self.assertEqual(result, expected, f"v[{reg}] lane {lane}: expected 21.0, got {i2f(result)}")
+
+  def test_v_wmma_f32_16x16x16_f16_high_registers(self):
+    """V_WMMA_F32_16X16X16_F16 with high register indices.
+
+    Regression test: WMMA was using static register indices instead of dynamic,
+    causing incorrect results when registers weren't at the default positions.
+    This test uses v[64:71] for A, v[80:87] for B, v[96:103] for C/D.
+    """
+    instructions = []
+    instructions.append(s_mov_b32(s[0], 0x3c003c00))  # packed f16 1.0
+    # Initialize A matrix in v[64:71]
+    for i in range(64, 72):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize B matrix in v[80:87]
+    for i in range(80, 88):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    # Initialize C (accumulator) in v[96:103] to zero
+    for i in range(96, 104):
+      instructions.append(v_mov_b32_e32(v[i], 0))
+    # WMMA: D = A @ B + C, result in v[96:103]
+    instructions.append(v_wmma_f32_16x16x16_f16(v[96:103], v[64:71], v[80:87], v[96:103]))
+    # Copy results to v[0:7] for checking
+    for i in range(8):
+      instructions.append(v_mov_b32_e32(v[i], v[96+i]))
+    st = run_program(instructions, n_lanes=32)
+    expected = f2i(16.0)
+    for lane in range(32):
+      for reg in range(8):
+        result = st.vgpr[lane][reg]
+        self.assertEqual(result, expected, f"v[{reg}] lane {lane}: expected 16.0, got {i2f(result)}")
+
+
+class TestWMMABF16(unittest.TestCase):
+  """Tests for WMMA BF16 instructions."""
+
+  def test_v_wmma_f32_16x16x16_bf16_all_ones(self):
+    """V_WMMA_F32_16X16X16_BF16 with all ones produces 16.0."""
+    instructions = []
+    # BF16 1.0 = 0x3f80, packed = 0x3f803f80
+    instructions.append(s_mov_b32(s[0], 0x3f803f80))
+    for i in range(16, 32):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    for i in range(8):
+      instructions.append(v_mov_b32_e32(v[i], 0))
+    instructions.append(v_wmma_f32_16x16x16_bf16(v[0:7], v[16:23], v[24:31], v[0:7]))
+    st = run_program(instructions, n_lanes=32)
+    expected = f2i(16.0)
+    for lane in range(32):
+      for reg in range(8):
+        result = st.vgpr[lane][reg]
+        self.assertEqual(result, expected, f"v[{reg}] lane {lane}: expected 16.0, got {i2f(result)}")
+
+  def test_v_wmma_f32_16x16x16_bf16_with_accumulator(self):
+    """V_WMMA_F32_16X16X16_BF16 with non-zero accumulator."""
+    instructions = []
+    # BF16 1.0 = 0x3f80, packed = 0x3f803f80
+    instructions.append(s_mov_b32(s[0], 0x3f803f80))
+    instructions.append(s_mov_b32(s[1], f2i(5.0)))
+    for i in range(16, 32):
+      instructions.append(v_mov_b32_e32(v[i], s[0]))
+    for i in range(8):
+      instructions.append(v_mov_b32_e32(v[i], s[1]))
+    instructions.append(v_wmma_f32_16x16x16_bf16(v[0:7], v[16:23], v[24:31], v[0:7]))
    st = run_program(instructions, n_lanes=32)
    expected = f2i(21.0)  # 16 + 5
    for lane in range(32):
@@ -504,7 +715,6 @@ class TestPackedMixedSigns(unittest.TestCase):

  def test_pk_add_f16_mixed_signs(self):
    """V_PK_ADD_F16 with mixed positive/negative values."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0xc0003c00),  # packed: hi=-2.0, lo=1.0
      s_mov_b32(s[1], 0x3c003c00),  # packed: hi=1.0, lo=1.0
@@ -514,14 +724,13 @@ class TestPackedMixedSigns(unittest.TestCase):
    ]
    st = run_program(instructions, n_lanes=1)
    result = st.vgpr[0][2]
-    lo = _f16(result & 0xffff)
-    hi = _f16((result >> 16) & 0xffff)
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
    self.assertAlmostEqual(lo, 2.0, places=2)   # 1.0 + 1.0
    self.assertAlmostEqual(hi, -1.0, places=2)  # -2.0 + 1.0

  def test_pk_mul_f16_zero(self):
    """V_PK_MUL_F16 with zero."""
-    from extra.assembly.amd.pcode import _f16
    instructions = [
      s_mov_b32(s[0], 0x40004000),  # packed: 2.0, 2.0
      s_mov_b32(s[1], 0x00000000),  # packed: 0.0, 0.0
@@ -534,5 +743,277 @@ class TestPackedMixedSigns(unittest.TestCase):
    self.assertEqual(result, 0x00000000, "2.0 * 0.0 should be 0.0")


+class TestDot2F32F16(unittest.TestCase):
+  """Tests for V_DOT2_F32_F16 - dot product of f16 pairs producing f32."""
+
+  def test_v_dot2_f32_f16_basic(self):
+    """V_DOT2_F32_F16: dot product of two packed f16 pairs -> f32."""
+    # src0 = {hi=2.0, lo=1.0}, src1 = {hi=4.0, lo=3.0}
+    # result = 1.0*3.0 + 2.0*4.0 + 0 = 3 + 8 = 11.0
+    src0 = (f32_to_f16(2.0) << 16) | f32_to_f16(1.0)
+    src1 = (f32_to_f16(4.0) << 16) | f32_to_f16(3.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot2_f32_f16(v[3], v[0], v[1], v[2], opsel_hi=3, opsel_hi2=1),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][3])
+    self.assertAlmostEqual(result, 11.0, places=2)
+
+  def test_v_dot2_f32_f16_with_accumulator(self):
+    """V_DOT2_F32_F16 with non-zero f32 accumulator."""
+    # src0 = {hi=1.0, lo=1.0}, src1 = {hi=1.0, lo=1.0}, acc = 5.0
+    # result = 1.0*1.0 + 1.0*1.0 + 5.0 = 7.0
+    src0 = (f32_to_f16(1.0) << 16) | f32_to_f16(1.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], f2i(5.0)),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[0]),  # same as src0
+      v_mov_b32_e32(v[2], s[1]),
+      v_dot2_f32_f16(v[3], v[0], v[1], v[2], opsel_hi=3, opsel_hi2=1),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = i2f(st.vgpr[0][3])
+    self.assertAlmostEqual(result, 7.0, places=2)
+
+  def test_v_dot2_f32_f16_negative_values(self):
+    """V_DOT2_F32_F16 with negative f16 values."""
+    # src0 = {hi=-2.0, lo=3.0}, src1 = {hi=1.0, lo=2.0}
+    # result = 3.0*2.0 + (-2.0)*1.0 + 0 = 6 - 2 = 4.0
+    # NOTE: Hardware DOT2 may have up to 1 ULP difference due to internal implementation
+    src0 = (f32_to_f16(-2.0) << 16) | f32_to_f16(3.0)
+    src1 = (f32_to_f16(1.0) << 16) | f32_to_f16(2.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot2_f32_f16(v[3], v[0], v[1], v[2], opsel_hi=3, opsel_hi2=1),
+    ]
+    st = run_program(instructions, n_lanes=1, ulp_tolerance=1)
+    result = i2f(st.vgpr[0][3])
+    self.assertAlmostEqual(result, 4.0, places=2)
+
+
+class TestDot2F16F16(unittest.TestCase):
+  """Tests for V_DOT2_F16_F16 - dot product of f16 pairs producing f16."""
+
+  def test_v_dot2_f16_f16_basic(self):
+    """V_DOT2_F16_F16: dot product of two packed f16 pairs -> f16."""
+    # src0 = {hi=2.0, lo=1.0}, src1 = {hi=3.0, lo=2.0}
+    # result = 1.0*2.0 + 2.0*3.0 + 0 = 2 + 6 = 8.0 (f16)
+    src0 = (f32_to_f16(2.0) << 16) | f32_to_f16(1.0)
+    src1 = (f32_to_f16(3.0) << 16) | f32_to_f16(2.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot2_f16_f16(v[3], v[0], v[1], v[2]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = f16(st.vgpr[0][3] & 0xffff)
+    self.assertAlmostEqual(result, 8.0, places=1)
+
+  def test_v_dot2_f16_f16_with_accumulator(self):
+    """V_DOT2_F16_F16 with non-zero f16 accumulator."""
+    # src0 = {hi=1.0, lo=1.0}, src1 = {hi=1.0, lo=1.0}, acc = 3.0 (f16)
+    # result = 1.0*1.0 + 1.0*1.0 + 3.0 = 5.0 (f16)
+    src0 = (f32_to_f16(1.0) << 16) | f32_to_f16(1.0)
+    acc = f32_to_f16(3.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[2], acc),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[0]),  # same as src0
+      v_mov_b32_e32(v[2], s[2]),
+      v_dot2_f16_f16(v[3], v[0], v[1], v[2]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = f16(st.vgpr[0][3] & 0xffff)
+    self.assertAlmostEqual(result, 5.0, places=1)
+
+
+class TestSignedDotProducts(unittest.TestCase):
+  """Tests for V_DOT4_I32_IU8 and V_DOT8_I32_IU4 with signed inputs."""
+
+  def test_v_dot4_i32_iu8_signed_both(self):
+    """V_DOT4_I32_IU8 with both inputs signed (neg=0b011)."""
+    # src0 = {-1, -2, 3, 4} as i8 = {0xff, 0xfe, 0x03, 0x04}
+    # src1 = {1, 1, 1, 1} as i8
+    # result = (-1)*1 + (-2)*1 + 3*1 + 4*1 = -1 - 2 + 3 + 4 = 4
+    src0 = (0xff << 24) | (0xfe << 16) | (0x03 << 8) | 0x04  # -1, -2, 3, 4
+    src1 = 0x01010101  # 1, 1, 1, 1
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot4_i32_iu8(v[3], v[0], v[1], v[2], neg=0b011),  # both signed
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][3]
+    # Result is i32, interpret as signed
+    if result >= 0x80000000:
+      result = result - 0x100000000
+    self.assertEqual(result, 4)
+
+  def test_v_dot4_i32_iu8_src0_signed(self):
+    """V_DOT4_I32_IU8 with only src0 signed (neg=0b001)."""
+    # src0 = {-1, -1, -1, -1} as i8 = {0xff, 0xff, 0xff, 0xff}
+    # src1 = {2, 2, 2, 2} as u8
+    # result = (-1)*2 + (-1)*2 + (-1)*2 + (-1)*2 = -8
+    src0 = 0xffffffff  # -1, -1, -1, -1 (as i8)
+    src1 = 0x02020202  # 2, 2, 2, 2 (as u8)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot4_i32_iu8(v[3], v[0], v[1], v[2], neg=0b001),  # src0 signed
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][3]
+    if result >= 0x80000000:
+      result = result - 0x100000000
+    self.assertEqual(result, -8)
+
+  def test_v_dot4_i32_iu8_src1_signed(self):
+    """V_DOT4_I32_IU8 with only src1 signed (neg=0b010)."""
+    # src0 = {2, 2, 2, 2} as u8
+    # src1 = {-1, -1, -1, -1} as i8 = {0xff, 0xff, 0xff, 0xff}
+    # result = 2*(-1) + 2*(-1) + 2*(-1) + 2*(-1) = -8
+    src0 = 0x02020202  # 2, 2, 2, 2 (as u8)
+    src1 = 0xffffffff  # -1, -1, -1, -1 (as i8)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot4_i32_iu8(v[3], v[0], v[1], v[2], neg=0b010),  # src1 signed
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][3]
+    if result >= 0x80000000:
+      result = result - 0x100000000
+    self.assertEqual(result, -8)
+
+  def test_v_dot4_i32_iu8_unsigned_as_reference(self):
+    """V_DOT4_I32_IU8 with both unsigned (neg=0) - same as V_DOT4_U32_U8."""
+    # src0 = {0xff, 0xff, 0xff, 0xff} = 255 each as u8
+    # src1 = {1, 1, 1, 1}
+    # result = 255*1 + 255*1 + 255*1 + 255*1 = 1020
+    src0 = 0xffffffff
+    src1 = 0x01010101
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot4_i32_iu8(v[3], v[0], v[1], v[2], neg=0),  # both unsigned
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][3], 1020)
+
+  def test_v_dot8_i32_iu4_signed_both(self):
+    """V_DOT8_I32_IU4 with both inputs signed (neg=0b011)."""
+    # src0 = 8 nibbles: {-1, -2, 3, 4, -1, -2, 3, 4} as i4
+    # i4 -1 = 0xf, -2 = 0xe, 3 = 0x3, 4 = 0x4
+    # src0 = 0xfe34fe34
+    # src1 = {1, 1, 1, 1, 1, 1, 1, 1} as i4 = 0x11111111
+    # result = 2 * ((-1)*1 + (-2)*1 + 3*1 + 4*1) = 2 * 4 = 8
+    src0 = 0xfe34fe34
+    src1 = 0x11111111
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot8_i32_iu4(v[3], v[0], v[1], v[2], neg=0b011),  # both signed
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][3]
+    if result >= 0x80000000:
+      result = result - 0x100000000
+    self.assertEqual(result, 8)
+
+  def test_v_dot8_i32_iu4_all_negative(self):
+    """V_DOT8_I32_IU4 with all negative signed values."""
+    # src0 = 8 nibbles all -1 (0xf) = 0xffffffff
+    # src1 = 8 nibbles all 1 = 0x11111111
+    # result = 8 * ((-1)*1) = -8
+    src0 = 0xffffffff  # all -1 as i4
+    src1 = 0x11111111  # all 1
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], 0),
+      v_dot8_i32_iu4(v[3], v[0], v[1], v[2], neg=0b011),  # both signed
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][3]
+    if result >= 0x80000000:
+      result = result - 0x100000000
+    self.assertEqual(result, -8)
+
+
+class TestPkMinMaxF16(unittest.TestCase):
+  """Tests for V_PK_MIN_F16 and V_PK_MAX_F16."""
+
+  def test_v_pk_min_f16_basic(self):
+    """V_PK_MIN_F16: packed min of two f16 pairs."""
+    # src0 = {hi=3.0, lo=1.0}, src1 = {hi=2.0, lo=4.0}
+    # result = {min(3,2)=2, min(1,4)=1}
+    src0 = (f32_to_f16(3.0) << 16) | f32_to_f16(1.0)
+    src1 = (f32_to_f16(2.0) << 16) | f32_to_f16(4.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_pk_min_f16(v[2], v[0], v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][2]
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
+    self.assertAlmostEqual(lo, 1.0, delta=0.01)
+    self.assertAlmostEqual(hi, 2.0, delta=0.01)
+
+  def test_v_pk_max_f16_basic(self):
+    """V_PK_MAX_F16: packed max of two f16 pairs."""
+    # src0 = {hi=3.0, lo=1.0}, src1 = {hi=2.0, lo=4.0}
+    # result = {max(3,2)=3, max(1,4)=4}
+    src0 = (f32_to_f16(3.0) << 16) | f32_to_f16(1.0)
+    src1 = (f32_to_f16(2.0) << 16) | f32_to_f16(4.0)
+    instructions = [
+      s_mov_b32(s[0], src0),
+      s_mov_b32(s[1], src1),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[1]),
+      v_pk_max_f16(v[2], v[0], v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    result = st.vgpr[0][2]
+    lo = f16(result & 0xffff)
+    hi = f16((result >> 16) & 0xffff)
+    self.assertAlmostEqual(lo, 4.0, delta=0.01)
+    self.assertAlmostEqual(hi, 3.0, delta=0.01)
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -271,7 +271,7 @@ class TestCmpClassF16(unittest.TestCase):
    instructions = [
      v_mov_b32_e32(v[0], 0),         # f16 +0.0
      s_mov_b32(s[0], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[0]),
+      v_cmp_class_f16_e64(VCC_LO, v[0], s[0]),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +zero with VOP3 encoding")
@@ -282,7 +282,7 @@ class TestCmpClassF16(unittest.TestCase):
      s_mov_b32(s[0], 0x3c00),        # f16 +1.0
      v_mov_b32_e32(v[0], s[0]),
      s_mov_b32(s[1], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[1]),
+      v_cmp_class_f16_e64(VCC_LO, v[0], s[1]),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.vcc & 1, 1, "VCC should be 1 for +1.0 (normal) with mask 0x1f8")
@@ -293,7 +293,7 @@ class TestCmpClassF16(unittest.TestCase):
      s_mov_b32(s[0], 0x7e00),        # f16 quiet NaN
      v_mov_b32_e32(v[0], s[0]),
      s_mov_b32(s[1], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[1]),
+      v_cmp_class_f16_e64(VCC_LO, v[0], s[1]),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.vcc & 1, 0, "VCC should be 0 for NaN with mask 0x1f8 (no NaN bits)")
@@ -304,7 +304,7 @@ class TestCmpClassF16(unittest.TestCase):
      s_mov_b32(s[0], 0x7c00),        # f16 +inf
      v_mov_b32_e32(v[0], s[0]),
      s_mov_b32(s[1], 0x1f8),         # class mask
-      VOP3(VOP3Op.V_CMP_CLASS_F16, vdst=RawImm(VCC), src0=v[0], src1=s[1]),
+      v_cmp_class_f16_e64(VCC_LO, v[0], s[1]),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.vcc & 1, 0, "VCC should be 0 for +inf with mask 0x1f8 (no inf bits)")
@@ -324,6 +324,29 @@ class TestCmpInt(unittest.TestCase):
    st = run_program(instructions, n_lanes=4)
    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should match")

+  def test_v_cmp_ne_u32_with_zero(self):
+    """V_CMP_NE_U32: compare with zero, used for int->bool cast."""
+    instructions = [
+      v_mov_b32_e32(v[1], 0),
+      v_cmp_eq_u32_e32(1, v[255]),  # vcc = (lane == 1)
+      v_cndmask_b32_e64(v[1], v[1], 1, VCC_LO),  # v1[lane1] = 1
+      v_cmp_ne_u32_e32(0, v[1]),  # vcc = (0 != v1)
+      v_cndmask_b32_e64(v[0], 0, 1, VCC_LO),  # v0 = vcc ? 1 : 0
+    ]
+    st = run_program(instructions, n_lanes=2)
+    self.assertEqual(st.vgpr[0][0], 0, "lane 0: 0 != 0 should be false")
+    self.assertEqual(st.vgpr[1][0], 1, "lane 1: 0 != 1 should be true")
+    self.assertEqual(st.vcc & 0x3, 0x2, "VCC should be 0b10")
+
+  def test_v_cmp_ne_u32_all_nonzero(self):
+    """V_CMP_NE_U32: all lanes have nonzero values."""
+    instructions = [
+      v_mov_b32_e32(v[1], 5),
+      v_cmp_ne_u32_e32(0, v[1]),
+    ]
+    st = run_program(instructions, n_lanes=4)
+    self.assertEqual(st.vcc & 0xf, 0xf, "All lanes should be != 0")
+
  def test_cmp_eq_u16_opsel_lo_lo(self):
    """V_CMP_EQ_U16 comparing lo halves."""
    instructions = [
@@ -337,21 +360,15 @@ class TestCmpInt(unittest.TestCase):
    self.assertEqual(st.vcc & 1, 1, "Lo halves should be equal")

  def test_cmp_eq_u16_opsel_hi_hi(self):
-    """V_CMP_EQ_U16 comparing hi halves with VOP3 opsel.
-
-    VOPC doesn't have opsel, so we use VOP3 form for hi-half comparisons.
-    VOP3 compares write result to SGPR via vdst field.
-    """
+    """V_CMP_EQ_U16 comparing hi halves with VOP3 opsel."""
    instructions = [
      s_mov_b32(s[2], 0x00051234),  # hi=5, lo=0x1234
      v_mov_b32_e32(v[0], s[2]),
      s_mov_b32(s[2], 0x0005ABCD),  # hi=5, lo=0xABCD
      v_mov_b32_e32(v[1], s[2]),
-      # opsel=3 means compare hi halves, vdst=v[0] actually writes to s[0]
-      VOP3(VOP3Op.V_CMP_EQ_U16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
+      v_cmp_eq_u16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
    ]
    st = run_program(instructions, n_lanes=1)
-    # Result is in sgpr[0], not vcc
    self.assertEqual(st.sgpr[0] & 1, 1, "Hi halves should be equal: 5==5")

  def test_cmp_eq_u16_opsel_hi_hi_equal(self):
@@ -361,7 +378,7 @@ class TestCmpInt(unittest.TestCase):
      v_mov_b32_e32(v[0], s[2]),
      s_mov_b32(s[2], 0x12340009),  # lo=9, hi=0x1234
      v_mov_b32_e32(v[1], s[2]),
-      VOP3(VOP3Op.V_CMP_EQ_U16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
+      v_cmp_eq_u16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.sgpr[0] & 1, 1, "hi==hi should be true: 0x1234==0x1234")
@@ -373,7 +390,7 @@ class TestCmpInt(unittest.TestCase):
      v_mov_b32_e32(v[0], s[2]),
      s_mov_b32(s[2], 0x12340005),  # lo=5, hi=0x1234
      v_mov_b32_e32(v[1], s[2]),
-      VOP3(VOP3Op.V_CMP_GT_U16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
+      v_cmp_gt_u16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
    ]
    st = run_program(instructions, n_lanes=1)
    self.assertEqual(st.sgpr[0] & 1, 1, "hi>hi should be true: 0x9999>0x1234")
@@ -389,11 +406,9 @@ class TestCmpFloat(unittest.TestCase):
      v_mov_b32_e32(v[0], s[2]),
      s_mov_b32(s[2], 0x40000000),  # hi=2.0 (f16), lo=0
      v_mov_b32_e32(v[1], s[2]),
-      # opsel=3 means read hi halves for both src0 and src1
-      VOP3(VOP3Op.V_CMP_LT_F16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
+      v_cmp_lt_f16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
    ]
    st = run_program(instructions, n_lanes=1)
-    # Result is in sgpr[0]
    self.assertEqual(st.sgpr[0] & 1, 1, "1.0 < 2.0 should be true")

  def test_v_cmp_gt_f16_vsrc1_hi(self):
@@ -403,11 +418,9 @@ class TestCmpFloat(unittest.TestCase):
      v_mov_b32_e32(v[0], s[2]),
      s_mov_b32(s[2], 0x3c000000),  # hi=1.0 (f16), lo=0
      v_mov_b32_e32(v[1], s[2]),
-      # opsel=3 means read hi halves for both src0 and src1
-      VOP3(VOP3Op.V_CMP_GT_F16, vdst=v[0], src0=v[0], src1=v[1], opsel=3),
+      v_cmp_gt_f16_e64(vdst=s[0], src0=v[0], src1=v[1], opsel=3),
    ]
    st = run_program(instructions, n_lanes=1)
-    # Result is in sgpr[0]
    self.assertEqual(st.sgpr[0] & 1, 1, "2.0 > 1.0 should be true")

  def test_v_cmp_eq_f16_vsrc1_hi_equal(self):
@@ -458,6 +471,242 @@ class TestCmpFloat(unittest.TestCase):
    self.assertEqual((st.vcc >> 1) & 1, 0, "Lane 1: expected vcc=0 (2.0 < 1.0)")


+class TestVOP3VOPCModifiers(unittest.TestCase):
+  """Tests for VOP3 VOPC with abs/neg modifiers."""
+
+  def test_v_cmp_ge_f32_abs_both(self):
+    """v_cmp_ge_f32 with abs on both sources: abs(0.0) >= abs(-1.0) = false.
+
+    Regression test: int16 mod operation uses v_cmp_ge_f32 with abs modifiers.
+    """
+    instructions = [
+      v_mov_b32_e32(v[0], 0.0),
+      v_mov_b32_e32(v[1], -1.0),
+      # abs=0b11 means abs(src0) and abs(src1)
+      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "abs(0.0) >= abs(-1.0) should be false")
+
+  def test_v_cmp_ge_f32_abs_negative_divisor(self):
+    """v_cmp_ge_f32 with abs: remainder check for negative divisor.
+
+    Tests the exact comparison used in int16 mod: abs(rem_f) >= abs(div_f).
+    For 1 % -1: rem_f = 0.0, div_f = -1.0, so abs(0.0) >= abs(-1.0) = false.
+    """
+    instructions = [
+      v_mov_b32_e32(v[0], 0.0),    # remainder as float
+      v_mov_b32_e32(v[1], -1.0),   # divisor as float
+      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "abs(0.0) >= abs(-1.0) should be false")
+
+  def test_v_cmp_ge_f32_abs_small_remainder(self):
+    """v_cmp_ge_f32 with abs: abs(-0.5) >= abs(-3.0) = false."""
+    instructions = [
+      v_mov_b32_e32(v[0], -0.5),
+      v_mov_b32_e32(v[1], -3.0),
+      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "abs(-0.5) >= abs(-3.0) should be false")
+
+  def test_v_cmp_ge_f32_abs_equal(self):
+    """v_cmp_ge_f32 with abs: abs(-1.0) >= abs(1.0) = true."""
+    instructions = [
+      v_mov_b32_e32(v[0], -1.0),
+      v_mov_b32_e32(v[1], 1.0),
+      v_cmp_ge_f32_e64(VCC_LO, v[0], v[1], abs=0b11),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "abs(-1.0) >= abs(1.0) should be true")
+
+
+class TestVOP3VOPC64Bit(unittest.TestCase):
+  """Tests for VOP3 VOPC with 64-bit operands."""
+
+  def test_v_cmp_lt_f64_basic(self):
+    """v_cmp_lt_f64: 0.0 < 1.0 = true."""
+    zero_f64 = f2i64(0.0)
+    one_f64 = f2i64(1.0)
+    instructions = [
+      s_mov_b32(s[0], zero_f64 & 0xffffffff),
+      s_mov_b32(s[1], zero_f64 >> 32),
+      s_mov_b32(s[2], one_f64 & 0xffffffff),
+      s_mov_b32(s[3], one_f64 >> 32),
+      v_cmp_lt_f64_e64(VCC_LO, s[0:1], s[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "0.0 < 1.0 should be true")
+
+  def test_v_cmp_lt_f64_negative(self):
+    """v_cmp_lt_f64: -1.0 < 0.0 = true."""
+    neg_one_f64 = f2i64(-1.0)
+    zero_f64 = f2i64(0.0)
+    instructions = [
+      s_mov_b32(s[0], neg_one_f64 & 0xffffffff),
+      s_mov_b32(s[1], neg_one_f64 >> 32),
+      s_mov_b32(s[2], zero_f64 & 0xffffffff),
+      s_mov_b32(s[3], zero_f64 >> 32),
+      v_cmp_lt_f64_e64(VCC_LO, s[0:1], s[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "-1.0 < 0.0 should be true")
+
+  def test_v_cmp_lt_i64_signed(self):
+    """v_cmp_lt_i64: 0 < -1 (signed) = false."""
+    instructions = [
+      s_mov_b32(s[0], 0),
+      s_mov_b32(s[1], 0),              # s[0:1] = 0
+      s_mov_b32(s[2], 0xffffffff),
+      s_mov_b32(s[3], 0xffffffff),     # s[2:3] = -1
+      v_cmp_lt_i64_e64(VCC_LO, s[0:1], s[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "0 < -1 (signed) should be false")
+
+  def test_v_cmp_lt_u64_unsigned(self):
+    """v_cmp_lt_u64: 0 < 0xFFFFFFFFFFFFFFFF (unsigned) = true."""
+    instructions = [
+      s_mov_b32(s[0], 0),
+      s_mov_b32(s[1], 0),              # s[0:1] = 0
+      s_mov_b32(s[2], 0xffffffff),
+      s_mov_b32(s[3], 0xffffffff),     # s[2:3] = max uint64
+      v_cmp_lt_u64_e64(VCC_LO, s[0:1], s[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "0 < max_uint64 should be true")
+
+
+class TestVOPCF64(unittest.TestCase):
+  """Tests for VOPC (E32 encoding) with 64-bit float operands. Regression test for f64 compare bug."""
+
+  def test_v_cmp_lt_f64_e32_true(self):
+    """v_cmp_lt_f64_e32: 2.0 < 3.0 = true."""
+    lo0, hi0 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
+    lo1, hi1 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
+    instructions = [
+      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
+      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
+      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
+      v_cmp_lt_f64_e32(v[0:1], v[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "2.0 < 3.0 should be true")
+
+  def test_v_cmp_lt_f64_e32_false(self):
+    """v_cmp_lt_f64_e32: 3.0 < 2.0 = false."""
+    lo0, hi0 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
+    lo1, hi1 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
+    instructions = [
+      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
+      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
+      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
+      v_cmp_lt_f64_e32(v[0:1], v[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "3.0 < 2.0 should be false")
+
+  def test_v_cmp_nlt_f64_e32_true(self):
+    """v_cmp_nlt_f64_e32: !(3.0 < 2.0) = true."""
+    lo0, hi0 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
+    lo1, hi1 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
+    instructions = [
+      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
+      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
+      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
+      v_cmp_nlt_f64_e32(v[0:1], v[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "!(3.0 < 2.0) should be true")
+
+  def test_v_cmp_nlt_f64_e32_false(self):
+    """v_cmp_nlt_f64_e32: !(2.0 < 3.0) = false."""
+    lo0, hi0 = f2i64(2.0) & 0xffffffff, f2i64(2.0) >> 32
+    lo1, hi1 = f2i64(3.0) & 0xffffffff, f2i64(3.0) >> 32
+    instructions = [
+      s_mov_b32(s[0], lo0), s_mov_b32(s[1], hi0),
+      s_mov_b32(s[2], lo1), s_mov_b32(s[3], hi1),
+      v_mov_b32_e32(v[0], s[0]), v_mov_b32_e32(v[1], s[1]),
+      v_mov_b32_e32(v[2], s[2]), v_mov_b32_e32(v[3], s[3]),
+      v_cmp_nlt_f64_e32(v[0:1], v[2:3]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "!(2.0 < 3.0) should be false")
+
+
+class TestCmpxExec(unittest.TestCase):
+  """Tests for V_CMPX instructions that modify EXEC mask."""
+
+  def test_v_cmpx_ngt_f32_e64_all_true(self):
+    """V_CMPX_NGT_F32_E64: all lanes pass (literal <= all values)."""
+    # 131072.0 = 0x48000000
+    # All values > 131072, so !(131072 > val) = true for all
+    instructions = [
+      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
+      v_mov_b32_e32(v[0], f2i(200000.0)),  # lane 0
+      v_cmp_eq_u32_e32(1, v[255]),
+      v_cndmask_b32_e64(v[1], v[0], f2i(300000.0), VCC_LO),  # lane 1
+      v_cmp_eq_u32_e32(2, v[255]),
+      v_cndmask_b32_e64(v[1], v[1], f2i(400000.0), VCC_LO),  # lane 2
+      # Now v[1] has: lane0=200000, lane1=300000, lane2=400000
+      # Compare: !(131072.0 > v[1]) i.e., 131072.0 <= v[1]
+      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[1]),
+    ]
+    st = run_program(instructions, n_lanes=3)
+    # All values > 131072, so all lanes should remain active
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x7, "All 3 lanes should remain active")
+
+  def test_v_cmpx_ngt_f32_e64_some_false(self):
+    """V_CMPX_NGT_F32_E64: some lanes fail (literal > some values)."""
+    instructions = [
+      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
+      v_mov_b32_e32(v[0], f2i(100000.0)),  # lane 0: 131072 > 100000 = true, so !(true) = false
+      v_cmp_eq_u32_e32(1, v[255]),
+      v_cndmask_b32_e64(v[1], v[0], f2i(200000.0), VCC_LO),  # lane 1: 131072 > 200000 = false, so !(false) = true
+      v_cmp_eq_u32_e32(2, v[255]),
+      v_cndmask_b32_e64(v[1], v[1], f2i(150000.0), VCC_LO),  # lane 2: 131072 > 150000 = false, so !(false) = true
+      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[1]),
+    ]
+    st = run_program(instructions, n_lanes=3)
+    # lane 0: fail (100000 < 131072), lanes 1,2: pass
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x6, "Lanes 1,2 should be active, lane 0 inactive")
+
+  def test_v_cmpx_ngt_f32_e64_all_false(self):
+    """V_CMPX_NGT_F32_E64: all lanes fail (literal > all values)."""
+    instructions = [
+      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
+      v_mov_b32_e32(v[0], f2i(100.0)),  # all lanes have 100.0
+      # 131072 > 100 = true, so !(true) = false for all
+      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[0]),
+    ]
+    st = run_program(instructions, n_lanes=3)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x0, "All lanes should be inactive")
+
+  def test_v_cmpx_ngt_f32_e64_large_values(self):
+    """V_CMPX_NGT_F32_E64: test with values that trigger Payne-Hanek in sin().
+
+    This is a regression test for the sin(859240.0) bug.
+    Values 859240, 1000000, 100594688 should all pass !(131072 > val).
+    """
+    instructions = [
+      s_mov_b32(EXEC_LO, 0x7),  # 3 lanes active
+      v_mov_b32_e32(v[0], f2i(859240.0)),   # lane 0
+      v_cmp_eq_u32_e32(1, v[255]),
+      v_cndmask_b32_e64(v[1], v[0], f2i(1000000.0), VCC_LO),   # lane 1
+      v_cmp_eq_u32_e32(2, v[255]),
+      v_cndmask_b32_e64(v[1], v[1], f2i(100594688.0), VCC_LO), # lane 2
+      v_cmpx_ngt_f32_e64(EXEC_LO, f2i(131072.0), v[1]),
+    ]
+    st = run_program(instructions, n_lanes=3)
+    # All values > 131072, so !(131072 > val) = true for all
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0x7, 0x7, "All 3 lanes should remain active")
+
+
 class TestVCCBehavior(unittest.TestCase):
  """Tests for VCC condition code behavior."""

@@ -482,5 +731,206 @@ class TestVCCBehavior(unittest.TestCase):
    self.assertEqual(st.vcc >> 16, 0x0000, "Lanes 16-31 should be false")


+class TestCmpNge(unittest.TestCase):
+  """Tests for V_CMP_NGE (not-greater-or-equal) with NaN semantics.
+
+  NGE = !(a >= b). With NaN inputs:
+  - If either input is NaN, a >= b is false, so !(false) = true
+  - This differs from a < b which returns false for NaN inputs
+  """
+
+  def test_v_cmp_nge_f32_normal_values(self):
+    """v_cmp_nge_f32: basic comparison with normal floats."""
+    instructions = [
+      v_mov_b32_e32(v[0], f2i(1.0)),
+      v_mov_b32_e32(v[1], f2i(2.0)),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(1.0 >= 2.0) = !(false) = true
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "!(1.0 >= 2.0) should be true")
+
+  def test_v_cmp_nge_f32_equal_values(self):
+    """v_cmp_nge_f32: equal values should return false."""
+    instructions = [
+      v_mov_b32_e32(v[0], f2i(1.0)),
+      v_mov_b32_e32(v[1], f2i(1.0)),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(1.0 >= 1.0) = !(true) = false
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "!(1.0 >= 1.0) should be false")
+
+  def test_v_cmp_nge_f32_greater_value(self):
+    """v_cmp_nge_f32: greater value should return false."""
+    instructions = [
+      v_mov_b32_e32(v[0], f2i(2.0)),
+      v_mov_b32_e32(v[1], f2i(1.0)),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(2.0 >= 1.0) = !(true) = false
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 0, "!(2.0 >= 1.0) should be false")
+
+  def test_v_cmp_nge_f32_neg_inf(self):
+    """v_cmp_nge_f32: -inf compared to normal value."""
+    neg_inf = 0xff800000  # -inf
+    instructions = [
+      s_mov_b32(s[0], neg_inf),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], f2i(1.0)),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(-inf >= 1.0) = !(false) = true
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "!(-inf >= 1.0) should be true")
+
+  def test_v_cmp_nge_f32_clears_inactive_vcc_bits(self):
+    """v_cmp_nge_f32 with partial EXEC clears inactive VCC bits (hardware behavior)."""
+    neg_inf = 0xff800000  # -inf
+    instructions = [
+      # Set VCC to all 1s first
+      s_mov_b32(VCC_LO, 0xFFFFFFFF),
+      # Set EXEC to only lane 0
+      s_mov_b32(EXEC_LO, 0x00000001),
+      # v0 = 1.0 for lane 0
+      v_mov_b32_e32(v[0], f2i(1.0)),
+      # Compare: !(-inf >= 1.0) = true for lane 0
+      v_cmp_nge_f32_e32(neg_inf, v[0]),
+    ]
+    st = run_program(instructions, n_lanes=16)
+    # Hardware clears inactive lane bits, only active lane results remain
+    # Lane 0 result = 1 (true), lanes 1-15 = 0 (cleared)
+    self.assertEqual(st.vcc, 0x00000001, "VCC should only have active lane results")
+
+  def test_v_cmp_nge_f32_nan_src0(self):
+    """v_cmp_nge_f32: NaN in src0 should return true (NaN >= x is false)."""
+    quiet_nan = 0x7fc00000
+    instructions = [
+      s_mov_b32(s[0], quiet_nan),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], f2i(1.0)),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(NaN >= 1.0) = !(false) = true
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "!(NaN >= 1.0) should be true")
+
+  def test_v_cmp_nge_f32_nan_src1(self):
+    """v_cmp_nge_f32: NaN in src1 should return true (x >= NaN is false)."""
+    quiet_nan = 0x7fc00000
+    instructions = [
+      s_mov_b32(s[0], quiet_nan),
+      v_mov_b32_e32(v[0], f2i(1.0)),
+      v_mov_b32_e32(v[1], s[0]),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(1.0 >= NaN) = !(false) = true
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "!(1.0 >= NaN) should be true")
+
+  def test_v_cmp_nge_f32_both_nan(self):
+    """v_cmp_nge_f32: both NaN should return true."""
+    quiet_nan = 0x7fc00000
+    instructions = [
+      s_mov_b32(s[0], quiet_nan),
+      v_mov_b32_e32(v[0], s[0]),
+      v_mov_b32_e32(v[1], s[0]),
+      v_cmp_nge_f32_e32(v[0], v[1]),  # !(NaN >= NaN) = !(false) = true
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vcc & 1, 1, "!(NaN >= NaN) should be true")
+
+
+class TestCmpxPartialWavefront(unittest.TestCase):
+  """Tests for V_CMPX with partial wavefronts (fewer than 32 active lanes).
+
+  Regression tests for bug where v_cmpx incorrectly set EXEC bits for inactive
+  lanes when the wavefront had fewer than 32 lanes. This caused garbage data
+  from uninitialized lanes to corrupt memory writes.
+  """
+
+  def test_v_cmpx_eq_u32_partial_wave_3_lanes(self):
+    """V_CMPX_EQ_U32 with 3 active lanes should only affect those 3 lanes.
+
+    With n_lanes=3, initial EXEC=0x7. After v_cmpx comparing lane_id == 1,
+    only lane 1 should pass, so EXEC should become 0x2 (not have bits 3-31 set).
+    """
+    instructions = [
+      v_cmpx_eq_u32_e32(1, v[255]),  # EXEC = lanes where lane_id == 1
+    ]
+    st = run_program(instructions, n_lanes=3)
+    # Only lane 1 should be active (bit 1 set)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x2,
+                     "Only lane 1 should be active after v_cmpx_eq_u32 with 3 lanes")
+
+  def test_v_cmpx_eq_u32_partial_wave_5_lanes(self):
+    """V_CMPX_EQ_U32 with 5 active lanes."""
+    instructions = [
+      v_cmpx_eq_u32_e32(3, v[255]),  # EXEC = lanes where lane_id == 3
+    ]
+    st = run_program(instructions, n_lanes=5)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x8,
+                     "Only lane 3 should be active after v_cmpx_eq_u32 with 5 lanes")
+
+  def test_v_cmpx_lt_u32_partial_wave(self):
+    """V_CMPX_LT_U32 with partial wavefront."""
+    # VOPC: src0 < vsrc1, so we need v_cmpx_gt_u32 to get lane_id < 2
+    instructions = [
+      v_cmpx_gt_u32_e32(2, v[255]),  # EXEC = lanes where 2 > lane_id (i.e., lane_id < 2)
+    ]
+    st = run_program(instructions, n_lanes=4)
+    # Lanes 0,1 should be active (bits 0,1 set = 0x3)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x3,
+                     "Only lanes 0,1 should be active after v_cmpx_gt_u32(2, lane_id) with 4 lanes")
+
+  def test_v_cmpx_ge_u32_partial_wave(self):
+    """V_CMPX_GE_U32 with partial wavefront."""
+    # VOPC: src0 >= vsrc1, so v_cmpx_le_u32(1, lane_id) gives lane_id >= 2? No.
+    # v_cmpx_le_u32(src0, vsrc1) = src0 <= vsrc1 = 1 <= lane_id
+    instructions = [
+      v_cmpx_le_u32_e32(2, v[255]),  # EXEC = lanes where 2 <= lane_id (i.e., lane_id >= 2)
+    ]
+    st = run_program(instructions, n_lanes=4)
+    # Lanes 2,3 should be active (bits 2,3 set = 0xC)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0xC,
+                     "Only lanes 2,3 should be active after v_cmpx_le_u32(2, lane_id) with 4 lanes")
+
+  def test_v_cmpx_ne_u32_partial_wave_all_pass(self):
+    """V_CMPX_NE_U32 where all active lanes pass."""
+    instructions = [
+      v_cmpx_ne_u32_e32(99, v[255]),  # EXEC = lanes where lane_id != 99
+    ]
+    st = run_program(instructions, n_lanes=3)
+    # All 3 lanes should remain active (bits 0,1,2 set = 0x7)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x7,
+                     "All 3 lanes should remain active when all pass")
+
+  def test_v_cmpx_eq_u32_partial_wave_none_pass(self):
+    """V_CMPX_EQ_U32 where no active lanes pass."""
+    instructions = [
+      v_cmpx_eq_u32_e32(99, v[255]),  # EXEC = lanes where lane_id == 99
+    ]
+    st = run_program(instructions, n_lanes=3)
+    # No lanes should be active
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x0,
+                     "No lanes should be active when none pass")
+
+  def test_v_cmpx_f32_partial_wave(self):
+    """V_CMPX_GT_F32 with partial wavefront - float comparison."""
+    instructions = [
+      v_cvt_f32_u32_e32(v[0], v[255]),  # v[0] = float(lane_id)
+      v_mov_b32_e32(v[1], f2i(0.5)),    # v[1] = 0.5
+      v_cmpx_gt_f32_e32(v[0], v[1]),    # EXEC = lanes where v[0] > 0.5
+    ]
+    st = run_program(instructions, n_lanes=4)
+    # Lanes 1,2,3 have values > 0.5, lane 0 has 0.0
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0xE,
+                     "Lanes 1,2,3 should be active (float > 0.5)")
+
+  def test_v_cmpx_e64_partial_wave(self):
+    """V_CMPX_EQ_U32_E64 (VOP3 encoding) with partial wavefront."""
+    instructions = [
+      v_cmpx_eq_u32_e64(EXEC_LO, v[255], 2),  # EXEC = lanes where lane_id == 2
+    ]
+    st = run_program(instructions, n_lanes=4)
+    self.assertEqual(st.sgpr[EXEC_LO.offset] & 0xFFFFFFFF, 0x4,
+                     "Only lane 2 should be active after v_cmpx_eq_u32_e64")
+
+
 if __name__ == '__main__':
  unittest.main()
@@ -0,0 +1,161 @@
+"""Tests for VOPD instructions - dual-issue vector operations.
+
+VOPD executes two operations simultaneously. Key behavior:
+- Both ops read their sources BEFORE either writes (dual-issue semantics)
+- This means if X writes to a register that Y reads, Y sees the OLD value
+- Op X can use ops 0-15 (FMAC, MUL, ADD, MOV, etc.)
+- Op Y can use ops 0-18 (includes ADD_NC_U32, LSHLREV, AND)
+"""
+import unittest
+from extra.assembly.amd.test.hw.helpers import run_program, run_program_emu, run_program_hw, compare_wave_states, \
+  v, s, v_mov_b32_e32, s_mov_b32
+from extra.assembly.amd.autogen.rdna3.ins import VOPD, VOPD_LIT, VOPDOp
+
+class TestVOPDBasic(unittest.TestCase):
+  """Basic VOPD functionality tests."""
+
+  def test_vopd_dual_mov(self):
+    """VOPD with two MOV operations to different registers."""
+    instructions = [
+      v_mov_b32_e32(v[0], 0x12345678),
+      v_mov_b32_e32(v[1], 0xDEADBEEF),
+      # X: v[2] = v[0], Y: v[3] = v[1]
+      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[1], v[0], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 0x12345678)
+    self.assertEqual(st.vgpr[0][3], 0xDEADBEEF)
+
+  def test_vopd_mov_and_add(self):
+    """VOPD with MOV (X) and ADD_NC_U32 (Y) - ADD_NC_U32 can only be Y op."""
+    instructions = [
+      v_mov_b32_e32(v[0], 10),
+      v_mov_b32_e32(v[1], 5),
+      # X: v[2] = 100 (literal), Y: v[3] = v[0] + v[1] = 15
+      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[3], 100, v[0], v[0], v[1]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertEqual(st.vgpr[0][2], 100)
+    self.assertEqual(st.vgpr[0][3], 15)
+
+
+class TestVOPDReadBeforeWrite(unittest.TestCase):
+  """Tests for VOPD dual-issue read-before-write semantics.
+
+  In VOPD, both X and Y operations read their sources BEFORE either writes.
+  This is critical when X's destination is Y's source.
+  """
+
+  def test_vopd_x_writes_y_reads_same_reg(self):
+    """VOPD where X writes to a register that Y reads.
+
+    X: v[2] = 0 (overwrites v[2])
+    Y: v[1] = v[2] + v[0]  (srcy0=v[2], vsrcy1=v[0])
+
+    If reads happen before writes: v[1] = OLD_v[2] + v[0] = 0xFFFFFFFF + 1 = 0
+    If writes happen before reads: v[1] = 0 + v[0] = 0 + 1 = 1
+
+    Hardware does reads-before-writes, so v[1] should be 0.
+    """
+    instructions = [
+      v_mov_b32_e32(v[0], 1),          # v[0] = 1
+      v_mov_b32_e32(v[1], 0x99999999), # v[1] = placeholder (will be overwritten)
+      v_mov_b32_e32(v[2], 0xFFFFFFFF), # v[2] = 0xFFFFFFFF
+      # X: v[2] = 0 (literal), srcx0=0, vsrcx1=v[0] (unused for MOV)
+      # Y: v[1] = srcy0 + vsrcy1 = v[2] + v[0] (should read OLD v[2] = 0xFFFFFFFF)
+      # vdsty encoding: (vdsty << 1) | ((vdstx & 1) ^ 1) where vdsty field = 0, vdstx = v[2]
+      # So vdsty_reg = (0 << 1) | ((2 & 1) ^ 1) = 0 | 1 = 1 = v[1]
+      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 0, v[2], v[0], v[0]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # X should have written 0 to v[2]
+    self.assertEqual(st.vgpr[0][2], 0, "X should write 0 to v[2]")
+    # Y should have read OLD v[2] (0xFFFFFFFF) and added v[0] (1)
+    # 0xFFFFFFFF + 1 = 0 (wrap around)
+    self.assertEqual(st.vgpr[0][1], 0, "Y should read OLD v[2]=0xFFFFFFFF, compute 0xFFFFFFFF+1=0")
+
+  def test_vopd_x_writes_y_reads_same_reg_v2(self):
+    """VOPD where X writes to a register that Y reads - cleaner test case.
+
+    X: v[2] = 0 (MOV)
+    Y: v[1] = v[2] + v[2] (ADD_NC_U32 with both sources from v[2])
+
+    If reads happen before writes: v[1] = OLD_v[2] + OLD_v[2] = 100 + 100 = 200
+    If writes happen before reads: v[1] = 0 + 0 = 0
+
+    Hardware does reads-before-writes, so v[1] should be 200.
+    """
+    instructions = [
+      v_mov_b32_e32(v[0], 0x88888888), # v[0] = unused placeholder
+      v_mov_b32_e32(v[1], 0x99999999), # v[1] = placeholder (will be overwritten)
+      v_mov_b32_e32(v[2], 100),        # v[2] = 100
+      # X: v[2] = 0 (literal)
+      # Y: v[1] = srcy0 + vsrcy1 = v[2] + v[2] (should read OLD v[2] = 100)
+      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 0, v[2], v[0], v[2]),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    # X should have written 0 to v[2]
+    self.assertEqual(st.vgpr[0][2], 0, "X should write 0 to v[2]")
+    # Y should have read OLD v[2] (100) twice and added them
+    self.assertEqual(st.vgpr[0][1], 200, "Y should read OLD v[2]=100 twice, compute 100+100=200")
+
+
+class TestVOPDLiterals(unittest.TestCase):
+  """Tests for VOPD instructions that use SIMM32 literals (FMAAK, FMAMK)."""
+
+  def test_vopd_fmaak_f32(self):
+    """VOPD V_DUAL_FMAAK_F32: D = S0 * S1 + SIMM32 (literal addend).
+
+    Tests that the 32-bit literal (SIMM32) is correctly passed to the instruction.
+    fma(2.0, 3.0, 10.0) = 2*3 + 10 = 16.0
+    """
+    from extra.assembly.amd.test.hw.helpers import f2i, i2f
+    instructions = [
+      v_mov_b32_e32(v[0], f2i(2.0)),  # v[0] = 2.0
+      v_mov_b32_e32(v[1], f2i(3.0)),  # v[1] = 3.0
+      # VOPD args: opx, opy, vdstx, vdsty, srcx0, srcy0, vsrcx1, vsrcy1
+      # X: v[2] = fma(srcx0, vsrcx1, SIMM32) = v[0]*v[1]+10.0 = 2*3+10 = 16
+      # Y: v[3] = srcy0 (MOV) = v[0] = 2.0
+      VOPD_LIT(VOPDOp.V_DUAL_FMAAK_F32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[0], v[1], v[0], literal=f2i(10.0)),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 16.0, places=5, msg="fma(2.0, 3.0, 10.0) should be 16.0")
+
+  def test_vopd_fmamk_f32(self):
+    """VOPD V_DUAL_FMAMK_F32: D = S0 * SIMM32 + S1 (literal multiplier).
+
+    Tests that the 32-bit literal (SIMM32) is correctly used as the multiplier.
+    fma(2.0, 5.0, 3.0) = 2*5 + 3 = 13.0
+    """
+    from extra.assembly.amd.test.hw.helpers import f2i, i2f
+    instructions = [
+      v_mov_b32_e32(v[0], f2i(2.0)),  # v[0] = 2.0
+      v_mov_b32_e32(v[1], f2i(3.0)),  # v[1] = 3.0
+      # X: v[2] = fma(srcx0, SIMM32, vsrcx1) = v[0]*5.0+v[1] = 2*5+3 = 13
+      # Y: v[3] = srcy0 (MOV) = v[0] = 2.0
+      VOPD_LIT(VOPDOp.V_DUAL_FMAMK_F32, VOPDOp.V_DUAL_MOV_B32, v[2], v[3], v[0], v[0], v[1], v[0], literal=f2i(5.0)),
+    ]
+    st = run_program(instructions, n_lanes=1)
+    self.assertAlmostEqual(i2f(st.vgpr[0][2]), 13.0, places=5, msg="fma(2.0, 5.0, 3.0) should be 13.0")
+
+
+class TestVOPDMultilane(unittest.TestCase):
+  """Tests for VOPD with multiple lanes."""
+
+  def test_vopd_multilane_mov_add(self):
+    """VOPD MOV and ADD with multiple active lanes - no register conflict."""
+    instructions = [
+      v_mov_b32_e32(v[0], 5),
+      v_mov_b32_e32(v[1], 10),
+      # X: v[2] = 100 (constant), Y: v[1] = v[0] + v[1] = 5 + 10 = 15
+      # vdsty_reg = (vdsty << 1) | ((vdstx.offset & 1) ^ 1) = (0 << 1) | ((258 & 1) ^ 1) = 0 | 1 = 1
+      VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_ADD_NC_U32, v[2], v[0], 100, v[0], v[2], v[1]),
+    ]
+    st = run_program(instructions, n_lanes=4)
+    for lane in range(4):
+      self.assertEqual(st.vgpr[lane][2], 100, f"Lane {lane}: v[2] should be 100")
+      self.assertEqual(st.vgpr[lane][1], 15, f"Lane {lane}: v[1] should be 15 (5+10)")
+
+
+if __name__ == '__main__':
+  unittest.main()
@@ -1,18 +1,14 @@
 # Test to compare Python and Rust RDNA3 emulators by running real tinygrad kernels
-import unittest, ctypes, os
+import unittest, ctypes
 from dataclasses import dataclass
-from pathlib import Path

-# Set environment before any tinygrad imports to use MOCKGPU
-# This allows generating AMD GPU kernels without requiring real hardware
-os.environ["AMD"] = "1"
-os.environ["MOCKGPU"] = "1"
-os.environ["PYTHON_REMU"] = "1"
-
-from extra.assembly.amd.emu import WaveState, decode_program, WAVE_SIZE, set_valid_mem_ranges, LDSMem
+from extra.assembly.amd.emu import WaveState, decode_program, WAVE_SIZE, VCC_LO, EXEC_LO, SCC
+from extra.assembly.amd import decode_inst
 from extra.assembly.amd.test.helpers import KernelInfo
 from extra.assembly.amd.test.bench_emu import REMU_PATH

+def set_valid_mem_ranges(ranges): pass  # emu2 doesn't need this
+
 def _is_f32_nan(bits: int) -> bool:
  """Check if 32-bit value is a NaN (exponent all 1s, mantissa non-zero)."""
  return (bits & 0x7f800000) == 0x7f800000 and (bits & 0x007fffff) != 0
@@ -91,33 +87,61 @@ class PythonEmulator:
  def __init__(self):
    self.state: WaveState | None = None
    self.program: dict | None = None
+    self.vmem_buf = None
+    self.lds_buf = None
+    self.kernel_buf = None  # Keep kernel bytes alive
+    self.lib_addr = 0  # Base address of kernel code

  def create(self, kernel: bytes, n_lanes: int):
-    self.program = decode_program(kernel)
-    self.state = WaveState(LDSMem(bytearray(65536)), n_lanes)
-    self.state.exec_mask = (1 << n_lanes) - 1
+    import ctypes
+    from tinygrad.device import Buffer, BufferSpec
+    from tinygrad.dtype import dtypes
+    # Store kernel in a ctypes buffer so generic instructions can read from vmem at actual PC address
+    self.kernel_buf = (ctypes.c_char * len(kernel)).from_buffer_copy(kernel)
+    self.lib_addr = ctypes.addressof(self.kernel_buf)
+    # Remap program dict to use actual addresses (like run_asm does)
+    program_raw = decode_program(kernel)
+    self.program = {self.lib_addr + offset: val for offset, val in program_raw.items()}
+    self.state = WaveState(n_lanes)
+    self.state.pc = self.lib_addr  # Set PC to code base address
+    self.vmem_buf = Buffer('CPU', 1 << 40, dtypes.uint32, options=BufferSpec(external_ptr=0)).ensure_allocated()
+    self.lds_buf = Buffer('CPU', 65536 // 4, dtypes.uint32).ensure_allocated()

  def step(self) -> int:
+    import ctypes
    assert self.program is not None and self.state is not None
-    return self.program[self.state.pc]._dispatch(self.state, self.program[self.state.pc])
+    pc = self.state.pc
+    if pc == 0xFFFFFFFFFFFFFFFF or pc not in self.program: return -1
+    name, fxn, globals_list, _runner = self.program[pc]
+    if fxn is None: return 1  # unsupported instruction
+    buf_addrs = {0: self.state.sgpr_buf._buf.va_addr, 1: self.state.vgpr_buf._buf.va_addr,
+                 2: self.vmem_buf._buf.va_addr, 3: self.lds_buf._buf.va_addr}
+    # Direct ctypes call - bypasses HCQ overhead
+    fxn(*[ctypes.c_uint64(buf_addrs[g]) for g in globals_list], ctypes.c_int32(0))
+    return -1 if self.state.pc == 0xFFFFFFFFFFFFFFFF else 0
+
  def set_sgpr(self, idx: int, val: int):
    assert self.state is not None
-    self.state.sgpr[idx] = val & 0xffffffff
+    self.state._write_sgpr(idx, val)
  def set_vgpr(self, lane: int, idx: int, val: int):
    assert self.state is not None
-    self.state.vgpr[lane][idx] = val & 0xffffffff
+    self.state._write_vgpr(idx, lane, val)

  def get_snapshot(self) -> StateSnapshot:
    assert self.state is not None
-    return StateSnapshot(pc=self.state.pc, scc=self.state.scc, vcc=self.state.vcc & 0xffffffff,
-                         exec_mask=self.state.exec_mask & 0xffffffff, sgpr=list(self.state.sgpr),
-                         vgpr=[list(self.state.vgpr[i]) for i in range(WAVE_SIZE)])
+    sgpr = [self.state._read_sgpr(i) for i in range(128)]
+    vgpr = [[self.state._read_vgpr(reg, lane) for reg in range(256)] for lane in range(WAVE_SIZE)]
+    # Convert actual PC address to word offset for comparison with Rust emulator
+    pc_offset = (self.state.pc - self.lib_addr) // 4 if self.state.pc != 0xFFFFFFFFFFFFFFFF else 0xFFFFFFFFFFFFFFFF
+    return StateSnapshot(pc=pc_offset, scc=self.state._read_sgpr(SCC.offset), vcc=sgpr[VCC_LO.offset],
+                         exec_mask=sgpr[EXEC_LO.offset], sgpr=sgpr, vgpr=vgpr)

 def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: tuple[int, int, int],
-                      program, max_steps: int, debug: bool, trace_len: int, kernel_idx: int = 0,
-                      max_workgroups: int = 8) -> tuple[bool, str, int]:
+                      local_size: tuple[int, int, int], program, max_steps: int, debug: bool, trace_len: int,
+                      kernel_idx: int = 0, max_workgroups: int = 8) -> tuple[bool, str, int]:
  """Run a single kernel through both emulators. Returns (success, message, total_steps)."""
  gx, gy, gz = global_size
+  lx, ly, lz = local_size
  total_steps = 0
  wg_count = 0

@@ -140,28 +164,52 @@ def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: t
          emu.set_sgpr(13, gidx)
          emu.set_sgpr(14, gidy)
          emu.set_sgpr(15, gidz)
+          # Initialize v[0] with packed workitem IDs for each lane
+          for lane in range(n_lanes):
+            tid = lane
+            z, y, x = tid // (lx * ly), (tid // lx) % ly, tid % lx
+            emu.set_vgpr(lane, 0, (z << 20) | (y << 10) | x)

        step = 0
        trace: list[tuple[int, int, str, StateSnapshot, StateSnapshot]] = []
+        prev_sync_after = False  # Track if previous instruction had known Rust bugs
        try:
          while step < max_steps:
            rust_before = rust.get_snapshot()
            python_before = python.get_snapshot()

-            inst = program.get(python_before.pc)
-            inst_str = inst.disasm() if inst else f"unknown at PC={python_before.pc}"
+            inst_info = python.program.get(python.lib_addr + python_before.pc * 4)  # Convert word offset to actual address
+            inst_hex_name = inst_info[0] if inst_info else f"unknown at PC={python_before.pc}"
+            # Decode the instruction to get mnemonic for sync_after checks
+            try:
+              # Format is mnemonic_hexbytes, e.g. v_exp_f32_e32_014b027e -> hex is 014b027e
+              parts = inst_hex_name.rsplit('_', 1)
+              inst_bytes_hex = parts[1] if len(parts) == 2 else ""
+              inst_bytes = bytes.fromhex(inst_bytes_hex) if inst_bytes_hex else b''
+              decoded = decode_inst(inst_bytes) if inst_bytes else None
+              inst_mnemonic = repr(decoded).split('(')[0] if decoded else ""
+            except:
+              inst_mnemonic = ""
+            # For generic instructions, use function name for sync_after check
+            if not inst_mnemonic: inst_mnemonic = inst_hex_name
+            inst_str = inst_hex_name
            trace.append((step, python_before.pc, inst_str, rust_before, python_before))
            if len(trace) > trace_len: trace.pop(0)

            if debug: print(f"K{kernel_idx} WG({gidx},{gidy},{gidz}) Step {step}: PC={python_before.pc}, inst={inst_str}")

-            # Instructions with known Rust emulator bugs - sync Python to Rust after execution
+            # Instructions with known Rust emulator bugs or precision differences - sync Python to Rust after execution
            # v_div_scale/v_div_fixup: Rust has different VCC handling
            # v_cvt_f16_f32: Rust clears high 16 bits, but hardware (and Python) preserves them
            # s_add_i32/s_sub_i32: Rust has incorrect SCC overflow detection
-            sync_after = any(x in inst_str for x in ('v_div_scale_f32', 'v_div_scale_f64', 'v_div_fixup_f32', 'v_div_fixup_f64',
-                                                      'v_cvt_f16_f32', 's_add_i32', 's_sub_i32'))
-            diffs = rust_before.diff(python_before, n_lanes)
+            # v_exp_f32/v_log_f32/v_ldexp_f32: precision differences in transcendental functions
+            # s_delay_alu: Rust handles differently
+            # v_add_co_ci_u32/v_sub_co_ci_u32/v_subrev_co_ci_u32: Rust preserves inactive VCC bits, but hardware clears all bits
+            sync_after = any(x in inst_mnemonic.lower() for x in ('v_div_scale', 'v_div_fixup', 'v_cvt_f16_f32', 's_add_i32', 's_sub_i32',
+                                                                   'v_exp_f32', 'v_log_f32', 'v_ldexp_f32', 's_delay_alu',
+                                                                   'v_add_co_ci_u32', 'v_sub_co_ci_u32', 'v_subrev_co_ci_u32'))
+            # Skip comparison if previous instruction had known Rust bugs (states were synced but may still differ slightly)
+            diffs = rust_before.diff(python_before, n_lanes) if not prev_sync_after else []
            if diffs:
              trace_lines = []
              for idx, (s, pc, d, rb, pb) in enumerate(trace):
@@ -200,7 +248,12 @@ def run_single_kernel(kernel: bytes, n_lanes: int, args_ptr: int, global_size: t
              for lane in range(n_lanes):
                for i in range(256): python.set_vgpr(lane, i, rust_after.vgpr[lane][i])
              assert python.state is not None
-              python.state.pc, python.state.scc, python.state.vcc, python.state.exec_mask = rust_after.pc, rust_after.scc, rust_after.vcc, rust_after.exec_mask
+              # Convert Rust's word-based PC to Python's actual address
+              python.state.pc = python.lib_addr + rust_after.pc * 4
+              python.state._write_sgpr(SCC.offset, rust_after.scc)
+              python.state._write_sgpr(VCC_LO.offset, rust_after.vcc)
+              python.state._write_sgpr(EXEC_LO.offset, rust_after.exec_mask)
+            prev_sync_after = sync_after

            if rust_result == -1:
              total_steps += step + 1
@@ -254,7 +307,7 @@ def compare_emulators_multi_kernel(kernels: list[KernelInfo], buf_pool: dict[int

    ok, msg, steps = run_single_kernel(
      kernel.code, min(n_lanes, 32), args_ptr, kernel.global_size,
-      program, max_steps, debug, trace_len, ki
+      kernel.local_size, program, max_steps, debug, trace_len, ki
    )
    total_steps += steps
    if not ok:
@@ -281,7 +334,8 @@ def compare_emulators_with_memory(kernel: bytes, n_lanes: int, buf_sizes: list,
  set_valid_mem_ranges(ranges)

  program = decode_program(kernel)
-  ok, msg, _ = run_single_kernel(kernel, n_lanes, args_ptr, global_size, program, max_steps, debug, trace_len)
+  # Legacy wrapper assumes local_size = (n_lanes, 1, 1)
+  ok, msg, _ = run_single_kernel(kernel, n_lanes, args_ptr, global_size, (n_lanes, 1, 1), program, max_steps, debug, trace_len)
  return ok, msg

 def get_kernels_from_tinygrad(op_fn) -> tuple[list[KernelInfo], dict[int, int], dict[int, bytes]]:
@@ -324,6 +378,7 @@ def get_kernels_from_tinygrad(op_fn) -> tuple[list[KernelInfo], dict[int, int],
              buf_sizes.append(b.nbytes)
            kernels.append(KernelInfo(
              code=bytes(sec.content),
+              src=lowered.prg.p.src,
              global_size=tuple(lowered.prg.p.global_size),
              local_size=tuple(lowered.prg.p.local_size),
              buf_idxs=buf_idxs,
@@ -386,6 +441,7 @@ class TestTinygradKernels(unittest.TestCase):
    from tinygrad import dtypes
    self._test_kernel(lambda T: T.empty(4, 4)[T.arange(4).cast(dtypes.int64), :])
  def test_gelu(self): self._test_kernel(lambda T: T.empty(32, 32).gelu())
+  def test_exp(self): self._test_kernel(lambda T: T.empty(1024).exp())
  def test_cross_entropy(self):
    import numpy as np
    np.random.seed(0)
@@ -397,5 +453,55 @@ class TestTinygradKernels(unittest.TestCase):
    from tinygrad import dtypes
    self._test_kernel(lambda T: T([2.0], dtype=dtypes.float64).sin())

+  def test_sin_large_f32(self):
+    """Test sin with large values that trigger Payne-Hanek range reduction."""
+    # Values around 859240 trigger the Payne-Hanek algorithm
+    # This tests the integer multiply-high instructions used in range reduction
+    self._test_kernel(lambda T: T([859240.0, 1000000.0, 100594688.0]).sin())
+
+  def test_clip_zero_one(self):
+    """Test clip(0, 1) - regression for binary_crossentropy failure."""
+    import numpy as np
+    np.random.seed(0)
+    x_np = np.random.uniform(-2, 2, (32, 10)).astype(np.float32).tolist()
+    self._test_kernel(lambda T: T(x_np).clip(0, 1))
+
+  def test_mod_int64(self):
+    """Test int64 modulo, especially edge cases like 1 % -1."""
+    from tinygrad import dtypes
+    self._test_kernel(lambda T: T([1, 10, -10, 7], dtype=dtypes.int64) % T([-1, 3, 3, -3], dtype=dtypes.int64))
+
+  def test_expand_flatten_sum(self):
+    """Test flatten of expanded tensor followed by sum.
+
+    Bug: flatten() of an expanded tensor produces wrong results for certain sizes.
+    Sizes that are multiples of 32 work (32, 48, 64), but sizes like 33, 49, 50 fail.
+    This breaks masked_select and nonzero operations.
+    """
+    import numpy as np
+    np.random.seed(0)
+    x_np = np.random.uniform(-2, 2, (33,)).astype(np.float32)
+    self._test_kernel(lambda T: (T(x_np.tolist()) > 0.5).unsqueeze(-1).expand(33, 3).flatten().sum())
+
+  @unittest.skip("slow and broken with AMD_LLVM=1")
+  def test_nonzero(self):
+    """Test nonzero operation - counts and gathers indices of non-zero elements."""
+    import numpy as np
+    np.random.seed(42)
+    x_np = np.random.rand(10, 5, 3).astype(np.float32)
+    self._test_kernel(lambda T: (T(x_np.tolist()) > 0.5).nonzero())
+
+  @unittest.skip("Precision differences in v_exp/v_log accumulate across kernels, causing memory divergence")
+  def test_softmax_argmax_fused(self):
+    """Test fused softmax+argmax - tracks exp2 precision issue.
+
+    The fused kernel recomputes softmax inline and Python emulator's exp2 polynomial
+    has up to 1 ULP error vs native exp2f, causing accumulated differences.
+    """
+    import torch
+    torch.manual_seed(0)
+    x_np = torch.rand(4, 10).numpy()
+    self._test_kernel(lambda T: T(x_np.tolist()).softmax(1).argmax())
+
 if __name__ == "__main__":
  unittest.main()
@@ -0,0 +1,77 @@
+import unittest
+import functools
+from tinygrad import Tensor, Device, dtypes
+from tinygrad.uop.ops import UOp, Ops, KernelInfo
+from tinygrad.renderer import Estimates
+from tinygrad.runtime.support.compiler_amd import HIPCompiler
+
+from extra.assembly.amd.autogen.rdna3.ins import *
+from extra.assembly.amd.dsl import s, v, Inst
+
+def assemble_insts(insts:list[Inst], name:str, arch:str, kernarg_size:int=8) -> tuple[UOp, UOp]:
+  kd = {"kernarg_size":kernarg_size, "user_sgpr_kernarg_segment_ptr":1, "next_free_vgpr":8, "next_free_sgpr":8, "wavefront_size32":1}
+  disasm = "\n".join([inst.disasm() for inst in insts])
+  hsasrc = f".text\n.globl {name}\n.p2align 8\n.type fn_name,@function\n{name}:\n{disasm}\ns_code_end\n"
+  hsasrc += f".rodata\n.p2align 6\n.amdhsa_kernel {name}\n"+"\n".join([f".amdhsa_{k} {v}" for k,v in kd.items()])+"\n.end_amdhsa_kernel"
+  binary = HIPCompiler(arch).compile(hsasrc)
+  return UOp(Ops.SOURCE, arg=disasm), UOp(Ops.BINARY, arg=binary)
+
+def custom_add_one(A:UOp, arch:str) -> UOp:
+  A = A.flatten()
+  assert dtypes.is_float(A.dtype.base), f"buffer dtype must be float32, got {A.dtype}"
+  threads = UOp.special(A.size, "lidx0")
+  insts = [
+    s_load_b64(s[0:1], s[0:1], soffset=NULL),
+    s_waitcnt(lgkmcnt=0),
+    v_lshlrev_b32_e32(v[0], 2, v[0]), # element offset
+    global_load_b32(v[1], v[0], saddr=s[0:1]),
+    s_waitcnt(vmcnt=0),
+    v_mov_b32_e32(v[2], 1.0),
+    v_add_f32_e32(v[1], v[1], v[2]),
+    global_store_b32(addr=v[0], data=v[1], saddr=s[0:1]),
+    s_endpgm(),
+  ]
+  sink = UOp.sink(A.base, threads, arg=KernelInfo(name:=f"custom_add_one_{A.size}", estimates=Estimates(ops=A.size, mem=A.size*4*2)))
+  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg="AMD"), UOp(Ops.LINEAR, src=(*sink.src, sink)), *assemble_insts(insts, name, arch)))
+
+def custom_add_var(A:UOp, B:UOp, arch:str) -> UOp:
+  A,B = A.flatten(), B.flatten()
+  assert A.dtype.base == dtypes.uint32, f"buffer dtype must be uint32, got {A.dtype}"
+  threads = UOp.special(A.size, "lidx0")
+  var = UOp.variable("var", 0, 10)
+  insts = [
+    s_load_b128(s[4:7], s[0:1]),
+    s_load_b32(s[8], s[0:1], offset=0x10), # all threads load the same variable
+    s_waitcnt(lgkmcnt=0),
+    v_lshlrev_b32_e32(v[0], 2, v[0]), # element offset, different per thread
+    global_load_b32(v[1], v[0], saddr=s[6:7]),
+    s_waitcnt(vmcnt=0),
+    v_add_nc_u32_e32(v[1], s[8], v[1]),
+    global_store_b32(addr=v[0], data=v[1], saddr=s[4:5]),
+    s_endpgm(),
+  ]
+  sink = UOp.sink(A.base, B.base, var, threads, arg=KernelInfo(name:=f"custom_add_one_{A.size}"))
+  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg="AMD"), UOp(Ops.LINEAR, src=(*sink.src, sink)),
+                               *assemble_insts(insts, name, arch, kernarg_size=16)))
+
+class TestCustomKernel(unittest.TestCase):
+  def test_simple(self):
+    a = Tensor.full((16, 16), 1.).contiguous().realize()
+    a = Tensor.custom_kernel(a, fxn=functools.partial(custom_add_one, arch=Device[Device.DEFAULT].renderer.arch))[0]
+    ei = a.schedule()[-1].lower()
+    self.assertEqual(ei.prg.estimates.ops, a.numel())
+    self.assertEqual(ei.prg.estimates.mem, a.nbytes()*2)
+    ei.run()
+    self.assertTrue((a.numpy() == 2.).all())
+
+  def test_variable(self):
+    b = Tensor.full((16, 16), 1, dtype=dtypes.uint32).contiguous().realize()
+    a = Tensor.zeros_like(b).contiguous().realize()
+    a = Tensor.custom_kernel(a, b, fxn=functools.partial(custom_add_var, arch=Device[Device.DEFAULT].renderer.arch))[0]
+    ei = a.schedule()[-1].lower()
+    for i in range(4):
+      ei.run({"var":i})
+      self.assertTrue((a.numpy() == 1+i).all())
+
+if __name__ == "__main__":
+  unittest.main()
@@ -0,0 +1,170 @@
+import unittest
+from extra.assembly.amd.dsl import *
+from extra.assembly.amd.dsl import VDSTYField
+from extra.assembly.amd.autogen.rdna3.enum import VOP1Op, VOP2Op
+from extra.assembly.amd.autogen.rdna3.ins import VOP1
+
+class TestRegisters(unittest.TestCase):
+  def test_vgpr_single(self):
+    self.assertEqual(repr(v[5]), "v[5]")
+    self.assertEqual(v[5].offset, 261)  # 256 + 5
+    self.assertEqual(v[5].sz, 1)
+
+  def test_sgpr_single(self):
+    self.assertEqual(repr(s[10]), "s[10]")
+    self.assertEqual(s[10].offset, 10)
+
+  def test_vgpr_range(self):
+    self.assertEqual(repr(v[0:3]), "v[0:3]")
+    self.assertEqual(v[0:3].offset, 256)
+    self.assertEqual(v[0:3].sz, 4)
+
+  def test_sgpr_range(self):
+    self.assertEqual(repr(s[4:5]), "s[4:5]")
+    self.assertEqual(s[4:5].sz, 2)
+
+  def test_ttmp_reslice(self):
+    # ttmp is src[108:123], so ttmp[0] should be src[108]
+    self.assertEqual(ttmp[0].offset, 108)
+    self.assertEqual(ttmp[1].offset, 109)
+    # ttmp[0:1] is 2 elements (inclusive slicing)
+    self.assertEqual(ttmp[0:1].offset, 108)
+    self.assertEqual(ttmp[0:1].sz, 2)
+    # ttmp[0:1][0] should be src[108]
+    self.assertEqual(ttmp[0:1][0].offset, 108)
+
+  def test_special_regs(self):
+    self.assertEqual(NULL.offset, 124)
+    self.assertEqual(M0.offset, 125)
+    self.assertEqual(EXEC_LO.offset, 126)
+    self.assertEqual(EXEC_HI.offset, 127)
+    # Check repr round-trips
+    self.assertEqual(repr(NULL), "NULL")
+    self.assertEqual(repr(M0), "M0")
+    self.assertEqual(repr(EXEC_LO), "EXEC_LO")
+    self.assertEqual(repr(EXEC), "EXEC")
+
+  def test_vcc(self):
+    self.assertEqual(VCC.offset, 106)
+    self.assertEqual(VCC.sz, 2)
+    self.assertEqual(VCC_LO.offset, 106)
+    self.assertEqual(VCC_HI.offset, 107)
+    # Check repr round-trips
+    self.assertEqual(repr(VCC_LO), "VCC_LO")
+    self.assertEqual(repr(VCC_HI), "VCC_HI")
+    self.assertEqual(repr(VCC), "VCC")
+
+  def test_float_constants(self):
+    self.assertEqual(src[240].offset, 240)
+    self.assertEqual(repr(src[240]), "0.5")
+    self.assertEqual(repr(src[242]), "1.0")
+    self.assertEqual(repr(src[243]), "-1.0")
+
+  def test_int_constants(self):
+    self.assertEqual(repr(src[128]), "0")
+    self.assertEqual(repr(src[129]), "1")
+    self.assertEqual(repr(src[192]), "64")
+    self.assertEqual(repr(src[193]), "-1")
+    self.assertEqual(repr(src[208]), "-16")
+
+class TestEnumBitField(unittest.TestCase):
+  def test_enum_name(self):
+    self.assertEqual(VOP1Op.V_MOV_B32_E32.name, "V_MOV_B32_E32")
+
+  def test_enum_value(self):
+    self.assertEqual(VOP1Op.V_MOV_B32_E32.value, 1)
+
+  def test_enum_comparison(self):
+    self.assertEqual(VOP1Op.V_MOV_B32_E32, VOP1Op.V_MOV_B32_E32)
+    self.assertNotEqual(VOP1Op.V_NOP_E32, VOP1Op.V_MOV_B32_E32)
+
+  def test_enum_different_types(self):
+    # VOP1Op and VOP2Op are different enums, even if same value
+    self.assertNotEqual(VOP1Op.V_MOV_B32_E32, VOP2Op.V_CNDMASK_B32_E32)
+
+  def test_wrong_enum_type_raises(self):
+    # Passing VOP2Op to VOP1 should raise
+    with self.assertRaises(RuntimeError):
+      VOP1(VOP2Op.V_CNDMASK_B32_E32, v[5], v[6])
+
+class TestVOP1(unittest.TestCase):
+  def test_class_setup(self):
+    self.assertEqual(VOP1._size(), 4)
+    field_names = [n for n, _ in VOP1._fields]
+    self.assertIn('encoding', field_names)
+    self.assertIn('op', field_names)
+    self.assertIn('vdst', field_names)
+    self.assertIn('src0', field_names)
+
+  def test_encoding_vgpr_vgpr(self):
+    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
+    raw = i._raw
+    # Check each field
+    self.assertEqual((raw >> 25) & 0x7f, 0b0111111)  # encoding
+    self.assertEqual((raw >> 17) & 0xff, 5)          # vdst (just VGPR index)
+    self.assertEqual((raw >> 9) & 0xff, 1)           # op
+    self.assertEqual(raw & 0x1ff, 262)               # src0 (256 + 6)
+
+  def test_encoding_vgpr_sgpr(self):
+    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], s[10])
+    raw = i._raw
+    self.assertEqual((raw >> 17) & 0xff, 5)    # vdst (just VGPR index)
+    self.assertEqual(raw & 0x1ff, 10)          # src0 (SGPR encoded)
+
+  def test_to_bytes(self):
+    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
+    b = i.to_bytes()
+    self.assertEqual(len(b), 4)
+    self.assertEqual(int.from_bytes(b, 'little'), i._raw)
+
+  def test_from_bytes(self):
+    i1 = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
+    i2 = VOP1.from_bytes(i1.to_bytes())
+    self.assertEqual(i1._raw, i2._raw)
+
+  def test_repr(self):
+    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
+    self.assertEqual(repr(i), "v_mov_b32_e32(v[5], v[6])")
+
+  def test_repr_sgpr_src(self):
+    i = VOP1(VOP1Op.V_MOV_B32_E32, v[5], s[10])
+    self.assertEqual(repr(i), "v_mov_b32_e32(v[5], s[10])")
+
+  def test_kwargs(self):
+    i1 = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
+    i2 = VOP1(op=VOP1Op.V_MOV_B32_E32, vdst=v[5], src0=v[6])
+    self.assertEqual(i1._raw, i2._raw)
+
+  def test_kwargs_partial(self):
+    i1 = VOP1(VOP1Op.V_MOV_B32_E32, v[5], v[6])
+    i2 = VOP1(VOP1Op.V_MOV_B32_E32, src0=v[6], vdst=v[5])
+    self.assertEqual(i1._raw, i2._raw)
+
+class TestVDSTYField(unittest.TestCase):
+  def test_encode_even_vgpr(self):
+    f = VDSTYField(6, 0)  # 7-bit field
+    self.assertEqual(f.encode(v[0]), 0)
+    self.assertEqual(f.encode(v[2]), 1)
+    self.assertEqual(f.encode(v[4]), 2)
+    self.assertEqual(f.encode(v[254]), 127)
+
+  def test_encode_non_vgpr_raises(self):
+    f = VDSTYField(6, 0)
+    with self.assertRaises(ValueError) as ctx:
+      f.encode(s[0])
+    self.assertIn("VGPR", str(ctx.exception))
+
+  def test_encode_non_reg_raises(self):
+    f = VDSTYField(6, 0)
+    with self.assertRaises(TypeError) as ctx:
+      f.encode(42)
+    self.assertIn("Reg", str(ctx.exception))
+
+  def test_decode_returns_raw(self):
+    f = VDSTYField(6, 0)
+    # decode returns raw value, actual vdsty computed with vdstx context
+    self.assertEqual(f.decode(0), 0)
+    self.assertEqual(f.decode(127), 127)
+
+if __name__ == "__main__":
+  unittest.main()
@@ -0,0 +1,332 @@
+"""Tests for the pcode parser."""
+import unittest
+from collections import defaultdict
+from tinygrad.helpers import DEBUG
+from tinygrad.dtype import dtypes
+from tinygrad.uop.ops import UOp, Ops
+from extra.assembly.amd.emu import parse_pcode
+from extra.assembly.amd.pcode import parse_expr
+from extra.assembly.amd.autogen.rdna3.str_pcode import PCODE
+from extra.assembly.amd.autogen.rdna3.enum import VOP1Op, VOP2Op, VOP3Op, SOP1Op, SOP2Op, DSOp
+
+def _srcs():
+  """Create minimal source variables for pcode parsing."""
+  u32 = lambda v=0: UOp.const(dtypes.uint32, v)
+  return {'S0': u32(), 'S1': u32(), 'S2': u32(), 'SCC': u32(), 'VCC': UOp.const(dtypes.uint64, 0), 'laneId': u32()}
+
+class TestBasicParsing(unittest.TestCase):
+  """Test basic pcode parsing for common instruction patterns."""
+
+  def test_v_add_f32(self):
+    """Test parsing V_ADD_F32 pcode."""
+    _, assigns = parse_pcode(PCODE[VOP2Op.V_ADD_F32_E32], _srcs())
+    self.assertEqual(len(assigns), 1)
+    dest, _ = assigns[0]
+    self.assertTrue(dest.startswith('D0'))
+
+  def test_v_lshlrev_b32(self):
+    """Test parsing V_LSHLREV_B32 pcode."""
+    _, assigns = parse_pcode(PCODE[VOP2Op.V_LSHLREV_B32_E32], _srcs())
+    self.assertEqual(len(assigns), 1)
+
+  def test_s_cselect_b32(self):
+    """Test parsing S_CSELECT_B32 pcode with ternary."""
+    _, assigns = parse_pcode(PCODE[SOP2Op.S_CSELECT_B32], _srcs())
+    self.assertEqual(len(assigns), 1)
+
+  def test_v_add_co_ci_u32(self):
+    """Test parsing V_ADD_CO_CI_U32 with carry."""
+    _, assigns = parse_pcode(PCODE[VOP2Op.V_ADD_CO_CI_U32_E32], _srcs())
+    self.assertGreaterEqual(len(assigns), 1)
+
+class TestWithSources(unittest.TestCase):
+  """Test pcode parsing with actual source operand values."""
+
+  def test_v_add_f32_with_sources(self):
+    """Test V_ADD_F32 with actual float constants."""
+    s0 = UOp.const(dtypes.uint32, 0x3f800000)  # 1.0f
+    s1 = UOp.const(dtypes.uint32, 0x40000000)  # 2.0f
+    _, assigns = parse_pcode(PCODE[VOP2Op.V_ADD_F32_E32], {'S0': s0, 'S1': s1})
+    self.assertEqual(len(assigns), 1)
+    dest, val = assigns[0]
+    self.assertTrue(dest.startswith('D0'))
+    # Result should be an ADD operation
+    self.assertEqual(val.op, Ops.ADD)
+
+  def test_v_mul_f32_with_sources(self):
+    """Test V_MUL_F32 with actual float constants."""
+    s0 = UOp.const(dtypes.uint32, 0x40000000)  # 2.0f
+    s1 = UOp.const(dtypes.uint32, 0x40400000)  # 3.0f
+    _, assigns = parse_pcode(PCODE[VOP2Op.V_MUL_F32_E32], {'S0': s0, 'S1': s1})
+    self.assertEqual(len(assigns), 1)
+    dest, val = assigns[0]
+    self.assertEqual(val.op, Ops.MUL)
+
+class TestParseExpr(unittest.TestCase):
+  """Test the parse_expr function directly."""
+
+  def test_integer_literals(self):
+    """Test parsing integer literals."""
+    self.assertEqual(parse_expr('0', {}).arg, 0)
+    self.assertEqual(parse_expr('42', {}).arg, 42)
+    self.assertEqual(parse_expr('42U', {}).arg, 42)
+
+  def test_negative_integers(self):
+    """Test parsing negative integer literals."""
+    result = parse_expr('-1', {})
+    self.assertEqual(result.arg, -1)
+    self.assertEqual(result.dtype, dtypes.int)
+
+  def test_float_literals(self):
+    """Test parsing float literals."""
+    result = parse_expr('1.0F', {})
+    self.assertEqual(result.arg, 1.0)
+    self.assertEqual(result.dtype, dtypes.float32)
+
+  def test_hex_literals(self):
+    """Test parsing hex literals."""
+    result = parse_expr('0xFF', {})
+    self.assertEqual(result.arg, 255)
+
+  def test_variable_lookup(self):
+    """Test variable lookup in parse_expr."""
+    vars = {'x': UOp.const(dtypes.uint32, 42)}
+    result = parse_expr('x', vars)
+    self.assertEqual(result.arg, 42)
+
+  def test_binary_ops(self):
+    """Test parsing binary operations."""
+    vars = {'a': UOp.const(dtypes.uint32, 10), 'b': UOp.const(dtypes.uint32, 5)}
+
+    # Addition
+    result = parse_expr('a + b', vars)
+    self.assertEqual(result.op, Ops.ADD)
+
+    # Subtraction with constant folding
+    result = parse_expr('10 - 5', {})
+    self.assertEqual(result.op, Ops.CONST)
+    self.assertEqual(result.arg, 5)
+
+  def test_ternary(self):
+    """Test parsing ternary expressions."""
+    vars = {'cond': UOp.const(dtypes.bool, True), 'a': UOp.const(dtypes.uint32, 1), 'b': UOp.const(dtypes.uint32, 0)}
+    result = parse_expr('cond ? a : b', vars)
+    self.assertEqual(result.op, Ops.WHERE)
+
+class TestForLoopParsing(unittest.TestCase):
+  """Test for loop parsing (CLZ/CTZ patterns)."""
+
+  def test_clz_pcode_exists(self):
+    """Verify CLZ pcode is available."""
+    pcode = PCODE.get(VOP1Op.V_CLZ_I32_U32_E32)
+    self.assertIsNotNone(pcode)
+    self.assertIn('for', pcode.lower())
+
+  def test_clz_parsing(self):
+    """Test CLZ pcode parsing produces correct structure."""
+    pcode = PCODE[VOP1Op.V_CLZ_I32_U32_E32]
+    S0 = UOp.const(dtypes.uint32, 0xFFFFFFFF)  # All ones - CLZ should be 0
+    vars, assigns = parse_pcode(pcode, {'S0': S0})
+
+    self.assertEqual(len(assigns), 1)
+    dest, val = assigns[0]
+    self.assertTrue(dest.startswith('D0'))
+    # Result should be a nested WHERE structure
+    self.assertEqual(val.op, Ops.WHERE)
+
+  def test_clz_with_zero(self):
+    """Test CLZ with input 0 - should return -1."""
+    pcode = PCODE[VOP1Op.V_CLZ_I32_U32_E32]
+    S0 = UOp.const(dtypes.uint32, 0)
+    vars, assigns = parse_pcode(pcode, {'S0': S0})
+
+    # Check that the innermost value (default) is -1 (may be wrapped in CAST)
+    val = assigns[0][1]
+    # Traverse to innermost WHERE
+    while val.op == Ops.WHERE:
+      val = val.src[2]  # false branch
+    # Unwrap CAST if present
+    while val.op == Ops.CAST:
+      val = val.src[0]
+    self.assertEqual(val.arg, -1)
+
+  def test_ctz_parsing(self):
+    """Test CTZ pcode parsing."""
+    pcode = PCODE.get(VOP1Op.V_CTZ_I32_B32_E32)
+    if pcode is None:
+      self.skipTest("V_CTZ_I32_B32_E32 pcode not available")
+
+    S0 = UOp.const(dtypes.uint32, 1)  # LSB set - CTZ should be 0
+    vars, assigns = parse_pcode(pcode, {'S0': S0})
+    self.assertEqual(len(assigns), 1)
+
+class TestDSPcodePatterns(unittest.TestCase):
+  """Test DS instruction pcode patterns."""
+
+  def test_ds_load_b32_pcode(self):
+    """Test DS_LOAD_B32 pcode is parseable."""
+    pcode = PCODE.get(DSOp.DS_LOAD_B32)
+    self.assertIsNotNone(pcode)
+    self.assertIn('RETURN_DATA', pcode)
+    self.assertIn('MEM[', pcode)
+
+  def test_ds_store_b32_pcode(self):
+    """Test DS_STORE_B32 pcode is parseable."""
+    pcode = PCODE.get(DSOp.DS_STORE_B32)
+    self.assertIsNotNone(pcode)
+    self.assertIn('MEM[', pcode)
+    self.assertIn('DATA', pcode)
+
+  def test_mem_read_parsing(self):
+    """Test MEM[addr].type read expression parsing."""
+    # Create a mock LDS buffer
+    lds = UOp(Ops.PARAM, dtypes.uint32.ptr(16384), arg=3)
+    addr = UOp.const(dtypes.uint32, 0)
+    vars = {'_lds': lds, 'ADDR': addr, 'OFFSET': UOp.const(dtypes.uint32, 0)}
+
+    result = parse_expr('MEM[ADDR + OFFSET].b32', vars)
+    # Should be an INDEX operation into LDS
+    self.assertIsNotNone(result)
+
+  def test_ds_store_2addr_b32_parsing(self):
+    """Test DS_STORE_2ADDR_B32 pcode parsing produces MEM writes."""
+    pcode = PCODE.get(DSOp.DS_STORE_2ADDR_B32)
+    self.assertIsNotNone(pcode)
+    srcs = {
+      'ADDR': UOp.const(dtypes.uint32, 0),
+      'OFFSET0': UOp.const(dtypes.uint32, 0),
+      'OFFSET1': UOp.const(dtypes.uint32, 1),
+      'DATA': UOp.const(dtypes.uint32, 0xAAAAAAAA),
+      'DATA2': UOp.const(dtypes.uint32, 0xBBBBBBBB),
+    }
+    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
+    _, assigns = parse_pcode(pcode, srcs)
+    # Should have 2 MEM write assignments
+    self.assertEqual(len(assigns), 2)
+    for dest, val in assigns:
+      self.assertTrue(dest.startswith('MEM['))
+      # val should be (addr, write_val) tuple
+      self.assertIsInstance(val, tuple)
+      self.assertEqual(len(val), 2)
+
+  def test_ds_load_2addr_b32_parsing(self):
+    """Test DS_LOAD_2ADDR_B32 pcode parsing produces RETURN_DATA assignments."""
+    pcode = PCODE.get(DSOp.DS_LOAD_2ADDR_B32)
+    self.assertIsNotNone(pcode)
+    lds = UOp(Ops.PARAM, dtypes.uint32.ptr(16384), arg=3)
+    srcs = {
+      'ADDR': UOp.const(dtypes.uint32, 0),
+      'OFFSET0': UOp.const(dtypes.uint32, 0),
+      'OFFSET1': UOp.const(dtypes.uint32, 1),
+      '_lds': lds,
+    }
+    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
+    _, assigns = parse_pcode(pcode, srcs)
+    # Should have 2 RETURN_DATA assignments
+    self.assertEqual(len(assigns), 2)
+    self.assertEqual(assigns[0][0], 'RETURN_DATA[31:0]')
+    self.assertEqual(assigns[1][0], 'RETURN_DATA[63:32]')
+
+  def test_ds_store_address_calculation(self):
+    """Test DS_STORE_2ADDR_B32 calculates correct addresses (offset * 4)."""
+    pcode = PCODE.get(DSOp.DS_STORE_2ADDR_B32)
+    srcs = {
+      'ADDR': UOp.const(dtypes.uint32, 100),
+      'OFFSET0': UOp.const(dtypes.uint32, 2),
+      'OFFSET1': UOp.const(dtypes.uint32, 5),
+      'DATA': UOp.const(dtypes.uint32, 0xAAAAAAAA),
+      'DATA2': UOp.const(dtypes.uint32, 0xBBBBBBBB),
+    }
+    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
+    _, assigns = parse_pcode(pcode, srcs)
+    # Check addresses: 100 + 2*4 = 108, 100 + 5*4 = 120
+    addr0, _ = assigns[0][1]
+    addr1, _ = assigns[1][1]
+    self.assertEqual(addr0.simplify().arg, 108)
+    self.assertEqual(addr1.simplify().arg, 120)
+
+  def test_ds_store_data_values(self):
+    """Test DS_STORE_2ADDR_B32 uses correct data values."""
+    pcode = PCODE.get(DSOp.DS_STORE_2ADDR_B32)
+    srcs = {
+      'ADDR': UOp.const(dtypes.uint32, 0),
+      'OFFSET0': UOp.const(dtypes.uint32, 0),
+      'OFFSET1': UOp.const(dtypes.uint32, 1),
+      'DATA': UOp.const(dtypes.uint32, 0xAAAAAAAA),
+      'DATA2': UOp.const(dtypes.uint32, 0xBBBBBBBB),
+    }
+    srcs['laneId'] = UOp.const(dtypes.uint32, 0)
+    _, assigns = parse_pcode(pcode, srcs)
+    _, val0 = assigns[0][1]
+    _, val1 = assigns[1][1]
+    # DATA[31:0] should preserve the value
+    self.assertEqual(val0.simplify().arg, 0xAAAAAAAA)
+    self.assertEqual(val1.simplify().arg, 0xBBBBBBBB)
+
+class TestConditionalParsing(unittest.TestCase):
+  """Test conditional (if/elsif/else) pcode parsing."""
+
+  def test_ternary_in_assignment(self):
+    """Test parsing ternary expression (which becomes WHERE)."""
+    # S_CSELECT_B32: D0.u32 = SCC ? S0.u32 : S1.u32
+    pcode = PCODE[SOP2Op.S_CSELECT_B32]
+    s0 = UOp.const(dtypes.uint32, 10)
+    s1 = UOp.const(dtypes.uint32, 20)
+    scc = UOp.const(dtypes.uint32, 1)
+    vars, assigns = parse_pcode(pcode, {'S0': s0, 'S1': s1, 'SCC': scc})
+    self.assertEqual(len(assigns), 1)
+    dest, val = assigns[0]
+    self.assertTrue(dest.startswith('D0'))
+    # Result should be a WHERE (ternary becomes WHERE)
+    self.assertEqual(val.op, Ops.WHERE)
+
+class TestAllPcode(unittest.TestCase):
+  """Test that all pcode from all architectures can be parsed."""
+
+  def _make_srcs(self):
+    """Create dummy source variables for pcode parsing."""
+    u32, u64 = lambda v=0: UOp.const(dtypes.uint32, v), lambda v=0: UOp.const(dtypes.uint64, v)
+    lds = UOp(Ops.PARAM, dtypes.uint32.ptr(16384), arg=3)
+    return {'laneId': u32(), 'laneID': u32(), 'S0': u32(), 'S1': u32(), 'S2': u32(), 'S3': u32(), 'SRC0': u32(),
+            'D0': u32(), 'D1': u32(), 'DST': u32(), 'VDST': u32(), 'SDST': u32(),
+            'VCC': u64(), 'VCCZ': u32(), 'EXEC': u64(), 'EXEC_LO': u32(), 'EXECZ': u32(), 'SCC': u32(),
+            'SIMM16': u32(), 'SIMM32': u32(), 'OFFSET': u32(), 'OFFSET0': u32(), 'OFFSET1': u32(), 'offset1': u32(),
+            'ADDR': u32(), 'ADDR_BASE': u32(), 'TADDR': u32(), 'DATA': u32(), 'DATA0': u32(), 'DATA1': u32(), 'DATA2': u32(),
+            'VDATA': u32(), 'VDATA0': u32(), 'VDATA1': u32(), 'VDATA2': u32(), 'VDATA3': u32(),
+            'OPSEL': u32(), 'OPSEL_HI': u32(), 'NEG': u32(), 'NEG_HI': u32(), 'CLAMP': u32(),
+            'M0': u32(), 'PC': u64(), 'DENORM': u32(1), 'ROUND_MODE': u32(), 'ROUND_TOWARD_ZERO': u32(), 'ROUND_NEAREST_EVEN': u32(), 'WAVE_STATUS': u32(),
+            'MAX_FLOAT_F32': u32(0x7f7fffff), 'Unsigned': u32(1), 'clampedLOD': u32(),
+            '_lds': lds, '_vmem': lds, '_active': UOp.const(dtypes.bool, True)}
+
+  def _parse_all_pcode(self, pcode_dict, arch: str, min_pct: float):
+    """Parse all pcode. RuntimeError = parser limitation (ok), other exceptions = real bugs."""
+    srcs = self._make_srcs()
+    passed, skipped, errors = 0, 0, defaultdict(list)
+    for op, pcode in pcode_dict.items():
+      try:
+        parse_pcode(pcode, srcs)
+        passed += 1
+      except RuntimeError as e: skipped += 1; errors[str(e)].append(op.name)
+      except Exception as e: self.fail(f"[{arch}] {op.name}: {e}\nPcode: {pcode[:200]}")
+    total = len(pcode_dict)
+    pct = 100 * passed / total
+    print(f"{arch}: {passed}/{total} ({pct:.1f}%) parsed, {skipped} skipped")
+    if DEBUG >= 2:
+      for err, ops in sorted(errors.items(), key=lambda x: -len(x[1])):
+        print(f"  {err}: {', '.join(ops[:5])}{'...' if len(ops) > 5 else ''} ({len(ops)})")
+    self.assertGreaterEqual(pct, min_pct, f"[{arch}] {pct:.1f}% < {min_pct}% threshold")
+
+  def test_parse_all_cdna_pcode(self):
+    from extra.assembly.amd.autogen.cdna.str_pcode import PCODE as CDNA_PCODE
+    self._parse_all_pcode(CDNA_PCODE, "CDNA", min_pct=60)
+
+  def test_parse_all_rdna3_pcode(self):
+    from extra.assembly.amd.autogen.rdna3.str_pcode import PCODE as RDNA3_PCODE
+    self._parse_all_pcode(RDNA3_PCODE, "RDNA3", min_pct=90)
+
+  def test_parse_all_rdna4_pcode(self):
+    from extra.assembly.amd.autogen.rdna4.str_pcode import PCODE as RDNA4_PCODE
+    self._parse_all_pcode(RDNA4_PCODE, "RDNA4", min_pct=65)
+
+if __name__ == "__main__":
+  unittest.main()
@@ -1,176 +1,13 @@
 #!/usr/bin/env python3
-"""Test MUBUF, MTBUF, MIMG, EXP, DS formats against LLVM."""
+"""Test DS and other compute-relevant instruction formats.
+
+Note: Graphics-only formats (EXP, MUBUF, MTBUF, MIMG) are not supported - use GLOBAL/FLAT for memory access in compute.
+"""
 import unittest
 from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.dsl import encode_src, RawImm
-from extra.assembly.amd.asm import detect_format
-
-class TestMUBUF(unittest.TestCase):
-  """Test MUBUF (buffer) instructions."""
-
-  def test_buffer_load_b32_basic(self):
-    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]))
-
-  def test_buffer_load_b32_idxen(self):
-    # buffer_load_b32 v5, v0, s[8:11], s3 idxen offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, idxen=1)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x82,0x03]))
-
-  def test_buffer_load_b32_offen(self):
-    # buffer_load_b32 v5, v0, s[8:11], s3 offen offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x42,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, offen=1)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x42,0x03]))
-
-  def test_buffer_load_b32_glc(self):
-    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 glc
-    # GFX11: encoding: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, glc=1)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]))
-
-  def test_buffer_load_b32_slc(self):
-    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 slc
-    # GFX11: encoding: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, slc=1)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]))
-
-  def test_buffer_load_b32_dlc(self):
-    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 dlc
-    # GFX11: encoding: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, dlc=1)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]))
-
-  def test_buffer_load_b32_all_flags(self):
-    # buffer_load_b32 v5, off, s[8:11], s3 offset:4095 glc slc dlc
-    # GFX11: encoding: [0xff,0x7f,0x50,0xe0,0x00,0x05,0x02,0x03]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, glc=1, slc=1, dlc=1)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x7f,0x50,0xe0,0x00,0x05,0x02,0x03]))
-
-  def test_buffer_store_b32(self):
-    # buffer_store_b32 v1, off, s[12:15], s4 offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
-    inst = buffer_store_b32(vdata=v[1], vaddr=v[0], srsrc=s[12:16], soffset=s[4], offset=4095)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]))
-
-  def test_buffer_load_b64(self):
-    # buffer_load_b64 v[5:6], off, s[8:11], s3 offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
-    inst = buffer_load_b64(vdata=v[5:7], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]))
-
-  def test_buffer_load_soffset_m0(self):
-    # buffer_load_b32 v5, off, s[8:11], m0 offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7d]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=M0, offset=4095)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7d]))
-
-  def test_buffer_load_soffset_inline_const(self):
-    # buffer_load_b32 v5, off, s[8:11], 0 offset:4095
-    # GFX11: encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=0, offset=4095)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]))
-
-  def test_buffer_disasm_roundtrip(self):
-    inst = buffer_load_b32(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, glc=1)
-    decoded = MUBUF.from_bytes(inst.to_bytes())
-    self.assertEqual(decoded.to_bytes(), inst.to_bytes())
-
-
-class TestMTBUF(unittest.TestCase):
-  """Test MTBUF (typed buffer) instructions."""
-
-  def test_tbuffer_load_format_x(self):
-    # tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_FMT_32_FLOAT] offset:4095
-    # BUF_FMT_32_FLOAT = 22
-    # GFX11: encoding: [0xff,0x0f,0xb0,0xe8,0x00,0x05,0x02,0x03]
-    inst = tbuffer_load_format_x(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, format=22)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0xb0,0xe8,0x00,0x05,0x02,0x03]))
-
-  def test_tbuffer_store_format_x(self):
-    # tbuffer_store_format_x v5, off, s[8:11], s3 format:[BUF_FMT_32_FLOAT] offset:4095
-    # BUF_FMT_32_FLOAT = 22
-    # GFX11: encoding: [0xff,0x0f,0xb2,0xe8,0x00,0x05,0x02,0x03]
-    inst = tbuffer_store_format_x(vdata=v[5], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, format=22)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x0f,0xb2,0xe8,0x00,0x05,0x02,0x03]))
-
-  def test_tbuffer_load_format_xy(self):
-    # tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_FMT_32_32_FLOAT] offset:4095
-    # BUF_FMT_32_32_FLOAT = 50
-    # GFX11: encoding: [0xff,0x8f,0x90,0xe9,0x00,0x05,0x02,0x03]
-    inst = tbuffer_load_format_xy(vdata=v[5:7], vaddr=v[0], srsrc=s[8:12], soffset=s[3], offset=4095, format=50)
-    self.assertEqual(inst.to_bytes(), bytes([0xff,0x8f,0x90,0xe9,0x00,0x05,0x02,0x03]))
-
-
-class TestMIMG(unittest.TestCase):
-  """Test MIMG (image) instructions."""
-
-  def test_image_load_2d(self):
-    # image_load v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-    # GFX11: encoding: [0x04,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]
-    inst = image_load(vdata=v[0:4], vaddr=v[4:6], srsrc=s[0:8], dmask=0xf, dim=1)  # dim=1 is SQ_RSRC_IMG_2D
-    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]))
-
-  def test_image_store_2d(self):
-    # image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
-    # GFX11: encoding: [0x04,0x0f,0x18,0xf0,0x04,0x00,0x00,0x00]
-    inst = image_store(vdata=v[0:4], vaddr=v[4:6], srsrc=s[0:8], dmask=0xf, dim=1)
-    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x18,0xf0,0x04,0x00,0x00,0x00]))
-
-  def test_image_load_1d(self):
-    # image_load v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
-    # GFX11: encoding: [0x00,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]
-    inst = image_load(vdata=v[0:4], vaddr=v[4], srsrc=s[0:8], dmask=0xf, dim=0)  # dim=0 is SQ_RSRC_IMG_1D
-    self.assertEqual(inst.to_bytes(), bytes([0x00,0x0f,0x00,0xf0,0x04,0x00,0x00,0x00]))
-
-  def test_image_sample(self):
-    # image_sample v[0:3], v[4:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-    # GFX11: encoding: [0x04,0x0f,0x6c,0xf0,0x04,0x00,0x00,0x08]
-    inst = image_sample(vdata=v[0:4], vaddr=v[4:6], srsrc=s[0:8], ssamp=s[8:12], dmask=0xf, dim=1)
-    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x6c,0xf0,0x04,0x00,0x00,0x08]))
-
-  def test_image_load_d16(self):
-    # image_load v[0:1], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D d16
-    # GFX11: encoding: [0x04,0x0f,0x02,0xf0,0x04,0x00,0x00,0x00]
-    inst = image_load(vdata=v[0:2], vaddr=v[4:6], srsrc=s[0:8], dmask=0xf, dim=1, d16=1)
-    self.assertEqual(inst.to_bytes(), bytes([0x04,0x0f,0x02,0xf0,0x04,0x00,0x00,0x00]))
-
-
-class TestEXP(unittest.TestCase):
-  """Test EXP (export) instructions."""
-
-  def test_exp_mrt0(self):
-    # exp mrt0 v0, v1, v2, v3
-    # GFX11: encoding: [0x0f,0x00,0x00,0xf8,0x00,0x01,0x02,0x03]
-    inst = EXP(en=0xf, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[2], vsrc3=v[3])
-    self.assertEqual(inst.to_bytes(), bytes([0x0f,0x00,0x00,0xf8,0x00,0x01,0x02,0x03]))
-
-  def test_exp_mrtz(self):
-    # exp mrtz v4, v3, v2, v1
-    # GFX11: encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
-    inst = EXP(en=0xf, target=8, vsrc0=v[4], vsrc1=v[3], vsrc2=v[2], vsrc3=v[1])
-    self.assertEqual(inst.to_bytes(), bytes([0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]))
-
-  def test_exp_mrtz_done(self):
-    # exp mrtz v4, v3, v2, v1 done
-    # GFX11: encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
-    inst = EXP(en=0xf, target=8, vsrc0=v[4], vsrc1=v[3], vsrc2=v[2], vsrc3=v[3], done=1)
-    self.assertEqual(inst.to_bytes(), bytes([0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x03]))
-
-  def test_exp_partial_mask(self):
-    # exp mrt0 v0, v1, off, off (en=0x3, only first two components)
-    # GFX11: encoding: [0x03,0x00,0x00,0xf8,0x00,0x01,0x00,0x00]
-    inst = EXP(en=0x3, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[0], vsrc3=v[0])
-    self.assertEqual(inst.to_bytes(), bytes([0x03,0x00,0x00,0xf8,0x00,0x01,0x00,0x00]))
-
-  def test_exp_row_en(self):
-    # exp mrtz v4, v3, v2, v1 row_en
-    # GFX11: encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01]
-    inst = EXP(en=0xf, target=8, vsrc0=v[4], vsrc1=v[3], vsrc2=v[2], vsrc3=v[1], row=1)
-    self.assertEqual(inst.to_bytes(), bytes([0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01]))
+from extra.assembly.amd.dsl import VCC_HI, EXEC_LO, NULL
+OFF = NULL  # OFF is alias for NULL
+from extra.assembly.amd import detect_format


 class TestDS(unittest.TestCase):
@@ -197,7 +34,7 @@ class TestDS(unittest.TestCase):
  def test_ds_load_b64(self):
    # ds_load_b64 v[0:1], v2
    # GFX11: encoding: [0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x00]
-    inst = ds_load_b64(vdst=v[0:2], addr=v[2])
+    inst = ds_load_b64(vdst=v[0:1], addr=v[2])
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x00]))

  def test_ds_add_u32(self):
@@ -241,31 +78,31 @@ class TestFLAT(unittest.TestCase):
  def test_global_load_b32(self):
    # global_load_b32 v0, v[1:2], off (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x52,0xdc,0x01,0x00,0x7c,0x00]
-    inst = global_load_b32(vdst=v[0], addr=v[1:3], saddr=OFF)
+    inst = global_load_b32(vdst=v[0], addr=v[1:2], saddr=OFF)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x52,0xdc,0x01,0x00,0x7c,0x00]))

  def test_global_store_b32(self):
    # global_store_b32 v[0:1], v2, off (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x6a,0xdc,0x00,0x02,0x7c,0x00]
-    inst = global_store_b32(addr=v[0:2], data=v[2], saddr=OFF)
+    inst = global_store_b32(addr=v[0:1], data=v[2], saddr=OFF)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x6a,0xdc,0x00,0x02,0x7c,0x00]))

  def test_global_load_b32_saddr(self):
    # global_load_b32 v0, v1, s[0:1] (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x00]
-    inst = global_load_b32(vdst=v[0], addr=v[1], saddr=s[0:2])
+    inst = global_load_b32(vdst=v[0], addr=v[1], saddr=s[0:1])
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x00]))

  def test_global_load_b32_offset(self):
    # global_load_b32 v0, v[1:2], off offset:256 (seg=2 for global)
    # GFX11: encoding: [0x00,0x01,0x52,0xdc,0x01,0x00,0x7c,0x00]
-    inst = global_load_b32(vdst=v[0], addr=v[1:3], saddr=OFF, offset=256)
+    inst = global_load_b32(vdst=v[0], addr=v[1:2], saddr=OFF, offset=256)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x01,0x52,0xdc,0x01,0x00,0x7c,0x00]))

  def test_global_load_b64(self):
    # global_load_b64 v[0:1], v[2:3], off (seg=2 for global)
    # GFX11: encoding: [0x00,0x00,0x56,0xdc,0x02,0x00,0x7c,0x00]
-    inst = global_load_b64(vdst=v[0:2], addr=v[2:4], saddr=OFF)
+    inst = global_load_b64(vdst=v[0:1], addr=v[2:3], saddr=OFF)
    self.assertEqual(inst.to_bytes(), bytes([0x00,0x00,0x56,0xdc,0x02,0x00,0x7c,0x00]))


@@ -275,19 +112,19 @@ class TestSMEM(unittest.TestCase):
  def test_smem_dlc_bit_position(self):
    # s_load_b32 s5, s[2:3], s0 dlc - tests that DLC is at bit 13 (not bit 14)
    # GFX11: encoding: [0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00]
-    inst = s_load_b32(sdata=s[5], sbase=s[2], soffset=s[0], dlc=1)
+    inst = s_load_b32(sdata=s[5], sbase=s[2:3], soffset=s[0], dlc=1)
    self.assertEqual(inst.to_bytes(), bytes([0x41,0x21,0x00,0xf4,0x00,0x00,0x00,0x00]))

  def test_smem_glc_bit_position(self):
    # s_load_b32 s5, s[2:3], s0 glc - tests that GLC is at bit 14 (not bit 16)
    # GFX11: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
-    inst = s_load_b32(sdata=s[5], sbase=s[2], soffset=s[0], glc=1)
+    inst = s_load_b32(sdata=s[5], sbase=s[2:3], soffset=s[0], glc=1)
    self.assertEqual(inst.to_bytes(), bytes([0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]))

  def test_smem_glc_dlc_combined(self):
    # s_load_b32 s5, s[2:3], s0 glc dlc - tests both flags together
    # GFX11: encoding: [0x41,0x61,0x00,0xf4,0x00,0x00,0x00,0x00]
-    inst = s_load_b32(sdata=s[5], sbase=s[2], soffset=s[0], glc=1, dlc=1)
+    inst = s_load_b32(sdata=s[5], sbase=s[2:3], soffset=s[0], glc=1, dlc=1)
    self.assertEqual(inst.to_bytes(), bytes([0x41,0x61,0x00,0xf4,0x00,0x00,0x00,0x00]))

  def test_smem_disasm_roundtrip_dlc(self):
@@ -309,23 +146,20 @@ class TestVOP3Literal(unittest.TestCase):
  def test_vop3_with_literal(self):
    # v_add3_u32 v5, vcc_hi, 0xaf123456, v255
    # GFX11: encoding: [0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
-    from extra.assembly.amd.dsl import RawImm
-    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=RawImm(107), src1=0xaf123456, src2=v[255])
+    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=VCC_HI, src1=0xaf123456, src2=v[255])
    expected = bytes([0x05,0x00,0x55,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf])
    self.assertEqual(inst.to_bytes(), expected)

  def test_vop3_literal_null_operand(self):
    # v_add3_u32 v5, null, exec_lo, 0xaf123456
    # GFX11: encoding: [0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf]
-    from extra.assembly.amd.dsl import RawImm
-    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=NULL, src1=RawImm(126), src2=0xaf123456)
+    inst = VOP3(VOP3Op.V_ADD3_U32, vdst=v[5], src0=NULL, src1=EXEC_LO, src2=0xaf123456)
    expected = bytes([0x05,0x00,0x55,0xd6,0x7c,0xfc,0xfc,0x03,0x56,0x34,0x12,0xaf])
    self.assertEqual(inst.to_bytes(), expected)

  def test_vop3p_with_literal(self):
    # Test VOP3P literal encoding (also uses Inst64)
-    from extra.assembly.amd.dsl import RawImm
-    inst = VOP3P(VOP3POp.V_PK_ADD_F16, vdst=v[5], src0=RawImm(240), src1=0x12345678, src2=v[0])
+    inst = VOP3P(VOP3POp.V_PK_ADD_F16, vdst=v[5], src0=0.5, src1=0x12345678, src2=v[0])
    self.assertEqual(len(inst.to_bytes()), 12)  # 8 bytes + 4 byte literal


@@ -371,28 +205,16 @@ class TestDetectFormat(unittest.TestCase):
    self.assertEqual(detect_format(VOP3P(VOP3POp.V_PK_ADD_F16, v[0], v[1], v[2], v[3]).to_bytes()), VOP3P)

  def test_detect_smem(self):
-    self.assertEqual(detect_format(s_load_b32(s[0], s[2:3], 0).to_bytes()), SMEM)
-    self.assertEqual(detect_format(s_load_b64(s[0:1], s[2:3], s[5]).to_bytes()), SMEM)
+    self.assertEqual(detect_format(s_load_b32(sdata=s[0], sbase=s[2:3], offset=0).to_bytes()), SMEM)
+    self.assertEqual(detect_format(s_load_b64(sdata=s[0:1], sbase=s[2:3], soffset=s[5]).to_bytes()), SMEM)

  def test_detect_ds(self):
    self.assertEqual(detect_format(ds_load_b32(v[0], v[1]).to_bytes()), DS)
    self.assertEqual(detect_format(ds_store_b32(v[0], v[1]).to_bytes()), DS)

  def test_detect_flat(self):
-    self.assertEqual(detect_format(global_load_b32(v[0], v[1:3], RawImm(124)).to_bytes()), FLAT)
-    self.assertEqual(detect_format(global_store_b32(v[0:2], v[2], RawImm(124)).to_bytes()), FLAT)
-
-  def test_detect_mubuf(self):
-    self.assertEqual(detect_format(buffer_load_b32(v[0], v[1], s[0:4], s[5]).to_bytes()), MUBUF)
-
-  def test_detect_mtbuf(self):
-    self.assertEqual(detect_format(tbuffer_load_format_x(v[0], v[1], s[0:4], s[5], format=22).to_bytes()), MTBUF)
-
-  def test_detect_mimg(self):
-    self.assertEqual(detect_format(image_load(v[0:4], v[4:6], s[0:8], dmask=0xf, dim=1).to_bytes()), MIMG)
-
-  def test_detect_exp(self):
-    self.assertEqual(detect_format(EXP(en=0xf, target=0, vsrc0=v[0], vsrc1=v[1], vsrc2=v[2], vsrc3=v[3]).to_bytes()), EXP)
+    self.assertEqual(detect_format(global_load_b32(vdst=v[0], addr=v[1:2], saddr=NULL).to_bytes()), GLOBAL)
+    self.assertEqual(detect_format(global_store_b32(addr=v[0:1], data=v[2], saddr=NULL).to_bytes()), GLOBAL)

  def test_detect_vopd(self):
    inst = VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, vdstx=v[0], vdsty=v[1], srcx0=0, srcy0=0)
@@ -4,32 +4,32 @@
 import unittest, struct
 from extra.assembly.amd.autogen.rdna3.ins import *
 from extra.assembly.amd.dsl import Inst
-from extra.assembly.amd.asm import asm
 from extra.assembly.amd.test.test_roundtrip import compile_asm

-class TestIntegration(unittest.TestCase):
+class IntegrationTestBase(unittest.TestCase):
  inst: Inst
+  arch: str
  def tearDown(self):
    if not hasattr(self, 'inst'): return
    b = self.inst.to_bytes()
    st = self.inst.disasm()
-    reasm = asm(st)
-    desc = f"{st:25s} {self.inst} {b!r} {reasm}"
-    self.assertEqual(b, compile_asm(st), desc)
-    # TODO: this compare should work for valid things
-    #self.assertEqual(self.inst, reasm)
-    self.assertEqual(repr(self.inst), repr(reasm))
+    # Test that the instruction can be compiled by LLVM and produces the same bytes
+    desc = f"{st:25s} {self.inst} {b!r}"
+    self.assertEqual(b, compile_asm(st, arch=self.arch), desc)
    print(desc)

+class TestIntegration(IntegrationTestBase):
+  arch: str = "rdna3"
+
  def test_wmma(self):
-    self.inst = v_wmma_f32_16x16x16_f16(v[0:7], v[189:192], v[140:143], v[0:7])
+    self.inst = v_wmma_f32_16x16x16_f16(v[0:7], v[184:191], v[136:143], v[0:7])

  def test_load_b128(self):
    self.inst = s_load_b128(s[4:7], s[0:1], NULL, 0)

  def test_load_b128_wrong_size(self):
    # this should have to be 4 regs on the loaded to
-    with self.assertRaises(Exception):
+    with self.assertRaises(TypeError):
      self.inst = s_load_b128(s[4:6], s[0:1], NULL, 0)

  def test_mov_b32(self):
@@ -128,6 +128,17 @@ class TestIntegration(unittest.TestCase):
    int_inst = s_mov_b32(s[0], struct.unpack("I", struct.pack("f", 1337.0))[0])
    self.assertEqual(self.inst, int_inst)

+class TestIntegrationCDNA(IntegrationTestBase):
+  arch = "cdna"
+
+  def test_mfma(self):
+    from extra.assembly.amd.autogen.cdna.ins import v_mfma_f32_16x16x16_f16
+    self.inst = v_mfma_f32_16x16x16_f16(v[0:3], v[0:1], v[0:1], 0)
+
+  def test_mfma_fp8(self):
+    from extra.assembly.amd.autogen.cdna.ins import v_mfma_f32_16x16x128_f8f6f4
+    self.inst = v_mfma_f32_16x16x128_f8f6f4(v[0:3], v[0:5], v[0:5], 1, cbsz=2, blgp=2)
+
 class TestRegisterSliceSyntax(unittest.TestCase):
  """
  Issue: Register slice syntax should use AMD assembly convention (inclusive end).
@@ -143,7 +154,7 @@ class TestRegisterSliceSyntax(unittest.TestCase):
  def test_register_slice_count(self):
    # s[4:7] should give 4 registers: s4, s5, s6, s7 (AMD convention, inclusive)
    reg = s[4:7]
-    self.assertEqual(reg.count, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")
+    self.assertEqual(reg.sz, 4, "s[4:7] should give 4 registers (s4, s5, s6, s7)")

  def test_register_slice_roundtrip(self):
    # Round-trip: DSL -> disasm -> DSL should preserve register count
@@ -154,7 +165,7 @@ class TestRegisterSliceSyntax(unittest.TestCase):
    self.assertIn("s[4:7]", disasm)
    # And s[4:7] in DSL should give the same 4 registers
    reg_from_disasm = s[4:7]
-    self.assertEqual(reg_from_disasm.count, 4, "s[4:7] from disasm should give 4 registers")
+    self.assertEqual(reg_from_disasm.sz, 4, "s[4:7] from disasm should give 4 registers")

 class TestInstructionEquality(unittest.TestCase):
  """
@@ -1,9 +1,10 @@
 #!/usr/bin/env python3
 """Integration test: round-trip RDNA3 assembly through AMD toolchain."""
-import unittest, re, io, sys, subprocess
+import unittest, io, sys
 from extra.assembly.amd.autogen.rdna3.ins import *
-from extra.assembly.amd.asm import waitcnt, asm
-from extra.assembly.amd.test.helpers import get_llvm_mc
+
+def waitcnt(vmcnt: int = 0x3f, expcnt: int = 0x7, lgkmcnt: int = 0x3f) -> int:
+  return (expcnt & 0x7) | ((lgkmcnt & 0x3f) << 4) | ((vmcnt & 0x3f) << 10)

 def disassemble(lib: bytes, arch: str = "gfx1100") -> str:
  """Disassemble ELF binary using tinygrad's compiler, return raw output."""
@@ -40,7 +41,7 @@ def assemble_and_disassemble(instructions: list, arch: str = "gfx1100") -> list[
  return parse_disassembly(disassemble(lib, arch))

 class TestIntegration(unittest.TestCase):
-  """Test our assembler output matches LLVM disassembly."""
+  """Test our DSL output matches LLVM disassembly."""

  def test_simple_sop1(self):
    """Test SOP1 instructions round-trip."""
@@ -90,9 +91,9 @@ class TestIntegration(unittest.TestCase):
  def test_memory_ops(self):
    """Test memory instructions."""
    instructions = [
-      s_load_b32(s[0], s[0:2], NULL),
+      s_load_b32(s[0], s[0:1], NULL),
      s_waitcnt(simm16=waitcnt(lgkmcnt=0)),
-      global_store_b32(addr=v[0:2], data=v[2], saddr=OFF),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=OFF),
      s_endpgm(),
    ]
    disasm = assemble_and_disassemble(instructions)
@@ -108,12 +109,12 @@ class TestIntegration(unittest.TestCase):
      v_mov_b32_e32(v[0], s[0]),  # base addr low
      v_mov_b32_e32(v[1], s[1]),  # base addr high
      # Load value
-      global_load_b32(vdst=v[2], addr=v[0:2], saddr=OFF),
+      global_load_b32(vdst=v[2], addr=v[0:1], saddr=OFF),
      s_waitcnt(simm16=waitcnt(vmcnt=0)),
      # Add 1.0
      v_add_f32_e32(v[2], 1.0, v[2]),
      # Store result
-      global_store_b32(addr=v[0:2], data=v[2], saddr=OFF),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=OFF),
      s_endpgm(),
    ]
    disasm = assemble_and_disassemble(instructions)
@@ -148,79 +149,6 @@ class TestIntegration(unittest.TestCase):
        return
    self.fail("Could not find s_mov_b32 in disassembly")

-class TestAsm(unittest.TestCase):
-  """Test asm() string parsing."""
-
-  def test_asm_basic(self):
-    """Test basic instruction parsing."""
-    inst = asm('s_mov_b32 s0, s1')
-    self.assertEqual(inst.to_bytes(), s_mov_b32(s[0], s[1]).to_bytes())
-
-  def test_asm_with_immediates(self):
-    """Test parsing with immediate values."""
-    inst = asm('s_add_u32 s0, s1, 10')
-    self.assertEqual(inst.to_bytes(), s_add_u32(s[0], s[1], 10).to_bytes())
-
-  def test_asm_float_const(self):
-    """Test parsing float constants."""
-    inst = asm('v_mul_f32_e32 v0, 1.0, v1')
-    self.assertEqual(inst.to_bytes(), v_mul_f32_e32(v[0], 1.0, v[1]).to_bytes())
-
-  def test_asm_hex_immediate(self):
-    """Test parsing hex immediates."""
-    inst = asm('s_waitcnt 0xfc07')
-    self.assertEqual(inst.to_bytes(), s_waitcnt(simm16=0xfc07).to_bytes())
-
-  def test_asm_special_regs(self):
-    """Test parsing special registers."""
-    inst = asm('s_mov_b32 s0, vcc_lo')
-    self.assertEqual(inst.to_bytes(), s_mov_b32(s[0], VCC_LO).to_bytes())
-
-  def test_asm_register_range(self):
-    """Test parsing register ranges."""
-    inst = asm('s_load_b128 s[4:7], s[0:1], null')
-    self.assertEqual(inst.to_bytes(), s_load_b128(s[4:7], s[0:1], NULL).to_bytes())
-
-  def test_asm_matches_llvm(self):
-    """Test asm() output matches LLVM assembler."""
-    from tinygrad.runtime.support.compiler_amd import HIPCompiler
-    compiler = HIPCompiler('gfx1100')
-
-    def get_llvm_bytes(instr: str) -> bytes:
-      src = f'.text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n{instr}\n'
-      lib = compiler.compile(src)
-      raw = disassemble(lib)
-      for line in raw.splitlines():
-        if instr.split()[0] in line and '//' in line:
-          hex_str = line.split('//')[1].strip().split(':')[1].strip()
-          return bytes.fromhex(hex_str)[::-1]
-      return b''
-
-    tests = ['s_mov_b32 s0, s1', 's_endpgm', 'v_add_f32_e32 v0, v1, v2']
-    for t in tests:
-      self.assertEqual(asm(t).to_bytes(), get_llvm_bytes(t), f"mismatch for: {t}")
-
-  def test_asm_vop3_modifiers(self):
-    """Test asm() with VOP3 modifiers (neg, abs, clamp)."""
-    def get_llvm_encoding(instr: str) -> str:
-      result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', '-mcpu=gfx1100', '-show-encoding'],
-                              input=instr, capture_output=True, text=True)
-      if m := re.search(r'encoding:\s*\[(.*?)\]', result.stdout):
-        return m.group(1).replace('0x','').replace(',','').replace(' ','')
-      return ''
-
-    tests = [
-      'v_fma_f32 v0, -v1, v2, v3',       # neg on src0
-      'v_fma_f32 v0, v1, |v2|, v3',      # abs on src1
-      'v_fma_f32 v0, v1, v2, v3 clamp',  # clamp
-      'v_fma_f32 v0, -v1, |v2|, v3 clamp',  # all modifiers
-      'v_fma_f32 v0, -|v1|, v2, v3',     # neg+abs on same operand
-    ]
-    for t in tests:
-      our_hex = asm(t).to_bytes().hex()
-      llvm_hex = get_llvm_encoding(t)
-      self.assertEqual(our_hex, llvm_hex, f"mismatch for: {t}")
-
 class TestTinygradIntegration(unittest.TestCase):
  """Test that we can parse disassembled tinygrad kernels."""

@@ -1,36 +1,47 @@
 #!/usr/bin/env python3
-"""Test AMD assembler/disassembler against LLVM test vectors."""
+"""Test AMD assembler/disassembler against LLVM test vectors.
+
+Only compute-relevant instruction formats are tested. Graphics-only formats not supported:
+  - MUBUF/MTBUF: buffer instructions with resource descriptors (use GLOBAL/FLAT instead)
+  - MIMG: image/texture instructions
+  - EXP/VEXPORT: export instructions for pixel/vertex output
+  - VIMAGE/VSAMPLE: image sampling instructions (RDNA4)
+  - VBUFFER: buffer instructions (RDNA4)
+"""
 import unittest, re, subprocess, functools
 from tinygrad.helpers import fetch
-from extra.assembly.amd.asm import asm, disasm, detect_format
-from extra.assembly.amd.test.helpers import get_llvm_mc
+from extra.assembly.amd.disasm import disasm
+from extra.assembly.amd import decode_inst, detect_format
+from extra.assembly.amd.test.helpers import get_llvm_mc, get_target, get_mattr

 LLVM_BASE = "https://raw.githubusercontent.com/llvm/llvm-project/llvmorg-21.1.0/llvm/test/MC/AMDGPU"

+# RDNA3 (gfx11) test files for compute instructions
+# Excluded: gfx11_asm_mubuf.s, gfx11_asm_mtbuf.s, gfx11_asm_mimg.s, gfx11_asm_mubuf_alias.s, gfx11_asm_mtbuf_alias.s (graphics-only)
 RDNA_FILES = ['gfx11_asm_sop1.s', 'gfx11_asm_sop2.s', 'gfx11_asm_sopp.s', 'gfx11_asm_sopk.s', 'gfx11_asm_sopc.s',
  'gfx11_asm_vop1.s', 'gfx11_asm_vop2.s', 'gfx11_asm_vopc.s', 'gfx11_asm_vop3.s', 'gfx11_asm_vop3p.s', 'gfx11_asm_vinterp.s',
  'gfx11_asm_vopd.s', 'gfx11_asm_vopcx.s', 'gfx11_asm_vop3_from_vop1.s', 'gfx11_asm_vop3_from_vop2.s', 'gfx11_asm_vop3_from_vopc.s',
-  'gfx11_asm_vop3_from_vopcx.s', 'gfx11_asm_ds.s', 'gfx11_asm_smem.s', 'gfx11_asm_flat.s', 'gfx11_asm_mubuf.s', 'gfx11_asm_mtbuf.s',
-  'gfx11_asm_mimg.s', 'gfx11_asm_wmma.s', 'gfx11_asm_vop3_features.s', 'gfx11_asm_vop3p_features.s', 'gfx11_asm_vopd_features.s',
+  'gfx11_asm_vop3_from_vopcx.s', 'gfx11_asm_ds.s', 'gfx11_asm_smem.s', 'gfx11_asm_flat.s',
+  'gfx11_asm_wmma.s', 'gfx11_asm_vop3_features.s', 'gfx11_asm_vop3p_features.s', 'gfx11_asm_vopd_features.s',
  'gfx11_asm_vop3_alias.s', 'gfx11_asm_vop3p_alias.s', 'gfx11_asm_vopc_alias.s', 'gfx11_asm_vopcx_alias.s', 'gfx11_asm_vinterp_alias.s',
-  'gfx11_asm_smem_alias.s', 'gfx11_asm_mubuf_alias.s', 'gfx11_asm_mtbuf_alias.s']
-# CDNA test files - includes gfx9 files for shared instructions, plus gfx90a/gfx942 specific files
-# gfx90a_ldst_acc.s has MIMG mixed in, filtered via is_mimg check
+  'gfx11_asm_smem_alias.s']
+# CDNA (gfx9/gfx90a/gfx942/gfx950) test files for compute instructions
+# Excluded: gfx9_asm_mubuf.s, gfx9_asm_mtbuf.s, gfx90a_ldst_acc.s (has MIMG mixed in)
+# Exclude gfx90a: 'gfx90a_asm_features.s', 'mai-gfx90a.s',
+# Exclude gfx950: 'gfx950_asm_features.s' (disasm error)
 CDNA_FILES = ['gfx9_asm_sop1.s', 'gfx9_asm_sop2.s', 'gfx9_asm_sopp.s', 'gfx9_asm_sopk.s', 'gfx9_asm_sopc.s',
  'gfx9_asm_vop1.s', 'gfx9_asm_vop2.s', 'gfx9_asm_vopc.s', 'gfx9_asm_vop3.s', 'gfx9_asm_vop3p.s',
-  'gfx9_asm_ds.s', 'gfx9_asm_flat.s', 'gfx9_asm_smem.s', 'gfx9_asm_mubuf.s', 'gfx9_asm_mtbuf.s',
-  'gfx90a_ldst_acc.s', 'gfx90a_asm_features.s', 'flat-scratch-gfx942.s', 'gfx942_asm_features.s',
-  'mai-gfx90a.s', 'mai-gfx942.s']
-# RDNA4 (gfx12) test files - excludes alias/err/fake16/dpp files, and vimage/vsample (not supported)
-# NOTE: vflat/vdsdir excluded - not implemented; features.s has mixed formats
+  'gfx9_asm_ds.s', 'gfx9_asm_flat.s', 'gfx9_asm_smem.s',
+  'flat-scratch-gfx942.s', 'gfx942_asm_features.s', 'mai-gfx942.s',
+  'gfx950_asm_vop1.s', 'gfx950_asm_read_tr.s', 'mai-gfx950.s']
+# RDNA4 (gfx12) test files for compute instructions
+# Excluded: gfx12_asm_vbuffer_mubuf.s, gfx12_asm_vbuffer_mtbuf.s, gfx12_asm_exp.s (graphics-only)
 RDNA4_FILES = ['gfx12_asm_sop1.s', 'gfx12_asm_sop2.s', 'gfx12_asm_sopp.s', 'gfx12_asm_sopk.s', 'gfx12_asm_sopc.s',
  'gfx12_asm_vop1.s', 'gfx12_asm_vop2.s', 'gfx12_asm_vopc.s', 'gfx12_asm_vopcx.s', 'gfx12_asm_vop3.s', 'gfx12_asm_vop3c.s',
  'gfx12_asm_vop3cx.s', 'gfx12_asm_vop3p.s', 'gfx12_asm_vop3_from_vop1.s', 'gfx12_asm_vop3_from_vop2.s',
  'gfx12_asm_vop3p_features.s', 'gfx12_asm_vopd.s', 'gfx12_asm_vopd_features.s',
  'gfx12_asm_ds.s', 'gfx12_asm_smem.s',
-  'gfx12_asm_vbuffer_mubuf.s', 'gfx12_asm_vbuffer_mtbuf.s', 'gfx12_asm_wmma_w32.s', 'gfx12_asm_exp.s']
-
-def _is_mimg(data: bytes) -> bool: return (int.from_bytes(data[:4], 'little') >> 26) & 0x3f == 0b111100
+  'gfx12_asm_wmma_w32.s']

 def _parse_llvm_tests(text: str, pattern: str) -> list[tuple[str, bytes]]:
  tests = []
@@ -48,74 +59,125 @@ def _parse_llvm_tests(text: str, pattern: str) -> list[tuple[str, bytes]]:
      except ValueError: pass
  return tests

-@functools.cache
-def _get_tests(f: str, arch: str) -> list[tuple[str, bytes]]:
+def _get_tests_uncached(f: str, arch: str) -> list[tuple[str, bytes]]:
  text = fetch(f"{LLVM_BASE}/{f}").read_bytes().decode('utf-8', errors='ignore')
  if arch == "rdna3":
-    tests = _parse_llvm_tests(text, r'(?:GFX11|W32|W64)')
+    # Match GFX11 and W32 only (wavefront32 mode)
+    tests = _parse_llvm_tests(text, r'(?:GFX11|W32)')
  elif arch == "rdna4":
-    # Match GFX12 but not GFX1250 (which has different lit64 encoding)
-    tests = _parse_llvm_tests(text, r'(?:GFX12(?!50)|W32|W64)')
-  elif 'gfx90a' in f or 'gfx942' in f:
-    tests = _parse_llvm_tests(text, r'(?:GFX90A|GFX942)')
+    # Match GFX12 (but not GFX1250) and W32 only (wavefront32 mode)
+    tests = _parse_llvm_tests(text, r'(?:GFX12(?!50)|W32)')
+  elif 'gfx90a' in f or 'gfx942' in f or 'gfx950' in f:
+    tests = _parse_llvm_tests(text, r'(?:GFX90A|GFX942|GFX950)')
  else:
    tests = _parse_llvm_tests(text, r'(?:VI9|GFX9|CHECK)')
-  return [(a, d) for a, d in tests if not _is_mimg(d)] if arch == "cdna" else tests
+  # Exclude v_interp_* (graphics-only, not on CDNA)
+  if arch == "cdna": tests = [(asm, data) for asm, data in tests if not asm.startswith('v_interp_')]
+  # Filter out tests where original ASM isn't valid on target (e.g., gfx9 tests with gfx942/gfx950 constraints)
+  if arch == "cdna" and not ('gfx942' in f or 'gfx950' in f or 'gfx90a' in f): tests = _filter_valid_asm(tests, arch)
+  return tests

-def _compile_asm_batch(instrs: list[str], arch: str = "rdna3") -> list[bytes]:
+@functools.cache
+def _get_tests(f: str, arch: str) -> list[tuple[str, bytes]]: return _get_tests_uncached(f, arch)
+
+def _compile_asm_batch(instrs: list[str], arch: str = "rdna3", mcpu: str|None = None) -> list[bytes]:
  if not instrs: return []
-  mcpu = {'rdna3': 'gfx1100', 'rdna4': 'gfx1200'}.get(arch, 'gfx1100')
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', '-mattr=+real-true16,+wavefrontsize32', '-show-encoding'],
+  mcpu, mattr = mcpu or get_target(arch), get_mattr(arch)
+  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', f'-mattr={mattr}', '-show-encoding'],
    input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True, timeout=30)
  if result.returncode != 0: raise RuntimeError(f"llvm-mc failed: {result.stderr.strip()}")
  return [bytes.fromhex(line.split('encoding:')[1].strip()[1:-1].replace('0x', '').replace(',', '').replace(' ', ''))
          for line in result.stdout.split('\n') if 'encoding:' in line]

+def _filter_valid_asm(tests: list[tuple[str, bytes]], arch: str) -> list[tuple[str, bytes]]:
+  """Filter out tests where the original ASM isn't valid on the target (e.g., gfx9 tests with gfx942/gfx950 constraints)."""
+  if not tests: return []
+  mcpu = get_target(arch)
+  # Batch assemble all instructions, parse stderr to find which lines failed
+  instrs = [asm for asm, _ in tests]
+  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', '-show-encoding'],
+    input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True, timeout=30)
+  # Parse error lines from stderr (format: "<stdin>:N:..." where N is 1-indexed, line 1 is ".text")
+  failed_lines = set()
+  for line in result.stderr.split('\n'):
+    if m := re.match(r'<stdin>:(\d+):', line): failed_lines.add(int(m.group(1)) - 1)  # -1 for .text, so line 2 -> index 1 -> tests[0]
+  # Also filter out tests where LLVM roundtrip doesn't match original (reserved bits set in original)
+  valid = [(asm, data) for i, (asm, data) in enumerate(tests) if (i + 1) not in failed_lines]
+  if not valid: return []
+  llvm_result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', '-show-encoding'],
+    input=".text\n" + "\n".join(asm for asm, _ in valid) + "\n", capture_output=True, text=True, timeout=30)
+  llvm_bytes = [bytes.fromhex(line.split('encoding:')[1].strip()[1:-1].replace('0x', '').replace(',', '').replace(' ', ''))
+                for line in llvm_result.stdout.split('\n') if 'encoding:' in line]
+  return [(asm, data) for (asm, data), lb in zip(valid, llvm_bytes) if lb == data]
+
 def _make_test(f: str, arch: str, test_type: str):
  def test(self):
    tests = _get_tests(f, arch)
    name = f"{arch}_{test_type}_{f}"
+    mcpu = "gfx942" if arch == "cdna" and "gfx942" in f else get_target(arch)
    if test_type == "roundtrip":
-      for _, data in tests:
-        decoded = detect_format(data, arch).from_bytes(data)
-        self.assertEqual(decoded.to_bytes()[:len(data)], data)
-      print(f"{name}: {len(tests)} passed")
-    elif test_type == "asm":
      passed, skipped = 0, 0
-      for asm_text, expected in tests:
+      for _, data in tests:
        try:
-          self.assertEqual(asm(asm_text, arch).to_bytes(), expected)
+          decoded = detect_format(data, arch).from_bytes(data)
+          self.assertEqual(decoded.to_bytes()[:len(data)], data)
          passed += 1
-        except: skipped += 1
+        except ValueError: skipped += 1  # skip invalid opcodes not in enum
      print(f"{name}: {passed} passed, {skipped} skipped")
+      self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
+    elif test_type == "repr":
+      # Test that eval(repr(inst)) reproduces the instruction
+      if arch == "rdna3": import extra.assembly.amd.autogen.rdna3.ins as ins
+      elif arch == "rdna4": import extra.assembly.amd.autogen.rdna4.ins as ins
+      elif arch == "cdna": import extra.assembly.amd.autogen.cdna.ins as ins
+      ns = {k: getattr(ins, k) for k in dir(ins) if not k.startswith('_')}
+      passed, skipped = 0, 0
+      for _, data in tests:
+        try:
+          decoded = detect_format(data, arch).from_bytes(data)
+          if decoded.to_bytes()[:len(data)] != data: skipped += 1; continue  # skip if binary roundtrip fails
+          r = repr(decoded)
+          try:
+            decoded2 = eval(r, ns)  # noqa: S307
+            if decoded == decoded2: passed += 1
+            else: skipped += 1
+          except Exception: skipped += 1
+        except ValueError: skipped += 1
+      print(f"{name}: {passed} passed, {skipped} skipped")
+      self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
    elif test_type == "disasm":
      to_test = []
      for _, data in tests:
        try:
-          decoded = detect_format(data, arch).from_bytes(data)
+          decoded = decode_inst(data, arch)
+          enc = decoded.to_bytes()[:len(data)]
          # Skip if roundtrip fails, disasm fails, or op_name is missing (disasm starts with space)
-          if decoded.to_bytes()[:len(data)] == data and (d := disasm(decoded)) and not d.startswith(' '): to_test.append((data, d))
+          if enc == data and (d := disasm(decoded)) and not d.startswith(' '): to_test.append((enc, d))
        except: pass
      skipped = len(tests) - len(to_test)
      print(f"{name}: {len(to_test)} passed, {skipped} skipped")
-      if arch in ("rdna3", "rdna4"):
-        self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
-        for (data, _), llvm in zip(to_test, _compile_asm_batch([t[1] for t in to_test], arch)): self.assertEqual(llvm, data)
+      self.assertEqual(skipped, 0, f"{name}: {skipped} tests skipped, expected 0")
+      # Compare disasm->reassemble with original encoding (filter reserved bit cases where LLVM can't reproduce)
+      llvm_bytes = _compile_asm_batch([t[1] for t in to_test], arch, mcpu)
+      valid = [(enc, d, llvm) for (enc, d), llvm in zip(to_test, llvm_bytes) if llvm == enc]
+      print(f"{name}: {len(valid)}/{len(to_test)} matched LLVM encoding")
+      for enc, _, llvm in valid: self.assertEqual(llvm, enc)
  return test

 class TestLLVM(unittest.TestCase): pass

 for f in RDNA_FILES:
  setattr(TestLLVM, f"test_rdna3_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "roundtrip"))
-  setattr(TestLLVM, f"test_rdna3_asm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "asm"))
  setattr(TestLLVM, f"test_rdna3_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "disasm"))
+  setattr(TestLLVM, f"test_rdna3_repr_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna3", "repr"))
 for f in CDNA_FILES:
  setattr(TestLLVM, f"test_cdna_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "roundtrip"))
  setattr(TestLLVM, f"test_cdna_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "disasm"))
+  setattr(TestLLVM, f"test_cdna_repr_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "cdna", "repr"))
 for f in RDNA4_FILES:
  setattr(TestLLVM, f"test_rdna4_roundtrip_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "roundtrip"))
-  setattr(TestLLVM, f"test_rdna4_asm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "asm"))
  setattr(TestLLVM, f"test_rdna4_disasm_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "disasm"))
+  setattr(TestLLVM, f"test_rdna4_repr_{f.replace('.s', '').replace('-', '_')}", _make_test(f, "rdna4", "repr"))

 if __name__ == "__main__":
  unittest.main()
@@ -1,403 +0,0 @@
-#!/usr/bin/env python3
-"""Tests for the RDNA3 pseudocode DSL."""
-import unittest
-from extra.assembly.amd.pcode import (Reg, TypedView, TypedView, MASK32, MASK64,
-                                       _f32, _i32, _f16, _i16, f32_to_f16, isNAN, _bf16, _ibf16, bf16_to_f32, f32_to_bf16,
-                                       BYTE_PERMUTE, v_sad_u8, v_msad_u8, _compile_pseudocode, _expr, compile_pseudocode)
-from extra.assembly.amd.test.helpers import ExecContext
-from extra.assembly.amd.autogen.rdna3.str_pcode import VOP3SDOp_PCODE, VOPCOp_PCODE
-from extra.assembly.amd.autogen.rdna3.enum import VOP3SDOp, VOPCOp
-
-# Compile pseudocode functions on demand for regression tests
-_VOP3SDOp_V_DIV_SCALE_F32 = compile_pseudocode('VOP3SDOp', 'V_DIV_SCALE_F32', VOP3SDOp_PCODE[VOP3SDOp.V_DIV_SCALE_F32])
-_VOPCOp_V_CMP_CLASS_F32 = compile_pseudocode('VOPCOp', 'V_CMP_CLASS_F32', VOPCOp_PCODE[VOPCOp.V_CMP_CLASS_F32])
-
-class TestReg(unittest.TestCase):
-  def test_u32_read(self):
-    r = Reg(0xDEADBEEF)
-    self.assertEqual(int(r.u32), 0xDEADBEEF)
-
-  def test_u32_write(self):
-    r = Reg(0)
-    r.u32 = 0x12345678
-    self.assertEqual(r._val, 0x12345678)
-
-  def test_f32_read(self):
-    r = Reg(0x40400000)  # 3.0f
-    self.assertAlmostEqual(float(r.f32), 3.0)
-
-  def test_f32_write(self):
-    r = Reg(0)
-    r.f32 = 3.0
-    self.assertEqual(r._val, 0x40400000)
-
-  def test_i32_signed(self):
-    r = Reg(0xFFFFFFFF)  # -1 as signed
-    self.assertEqual(int(r.i32), -1)
-
-  def test_u64(self):
-    r = Reg(0xDEADBEEFCAFEBABE)
-    self.assertEqual(int(r.u64), 0xDEADBEEFCAFEBABE)
-
-  def test_f64(self):
-    r = Reg(0x4008000000000000)  # 3.0 as f64
-    self.assertAlmostEqual(float(r.f64), 3.0)
-
-class TestTypedView(unittest.TestCase):
-  def test_bit_slice(self):
-    r = Reg(0xDEADBEEF)
-    # Slices return TypedView which supports .u32, .u16 etc (matching pseudocode like S1.u32[1:0].u32)
-    self.assertEqual(r.u32[7:0].u32, 0xEF)
-    self.assertEqual(r.u32[15:8].u32, 0xBE)
-    self.assertEqual(r.u32[23:16].u32, 0xAD)
-    self.assertEqual(r.u32[31:24].u32, 0xDE)
-    # Also works with int() for arithmetic
-    self.assertEqual(int(r.u32[7:0]), 0xEF)
-
-  def test_single_bit_read(self):
-    r = Reg(0b11010101)
-    self.assertEqual(r.u32[0], 1)
-    self.assertEqual(r.u32[1], 0)
-    self.assertEqual(r.u32[2], 1)
-    self.assertEqual(r.u32[3], 0)
-
-  def test_single_bit_write(self):
-    r = Reg(0)
-    r.u32[5] = 1
-    r.u32[3] = 1
-    self.assertEqual(r._val, 0b00101000)
-
-  def test_nested_bit_access(self):
-    # S0.u32[S1.u32[4:0]] - access bit at position from another register
-    s0 = Reg(0b11010101)
-    s1 = Reg(3)
-    bit_pos = s1.u32[4:0]  # TypedView, int value = 3
-    bit_val = s0.u32[int(bit_pos)]  # bit 3 of s0 = 0
-    self.assertEqual(int(bit_pos), 3)
-    self.assertEqual(bit_val, 0)
-
-  def test_arithmetic(self):
-    r1 = Reg(0x40400000)  # 3.0f
-    r2 = Reg(0x40800000)  # 4.0f
-    result = r1.f32 + r2.f32
-    self.assertAlmostEqual(result, 7.0)
-
-  def test_comparison(self):
-    r1 = Reg(5)
-    r2 = Reg(3)
-    self.assertTrue(r1.u32 > r2.u32)
-    self.assertFalse(r1.u32 < r2.u32)
-    self.assertTrue(r1.u32 != r2.u32)
-
-class TestTypedView(unittest.TestCase):
-  def test_slice_read(self):
-    r = Reg(0x56781234)
-    self.assertEqual(r[15:0].u16, 0x1234)
-    self.assertEqual(r[31:16].u16, 0x5678)
-
-  def test_slice_write(self):
-    r = Reg(0)
-    r[15:0].u16 = 0x1234
-    r[31:16].u16 = 0x5678
-    self.assertEqual(r._val, 0x56781234)
-
-  def test_slice_f16(self):
-    r = Reg(0)
-    r[15:0].f16 = 3.0
-    self.assertAlmostEqual(_f16(r._val & 0xffff), 3.0, places=2)
-
-class TestCompiler(unittest.TestCase):
-  def test_ternary(self):
-    result = _expr("a > b ? 1 : 0")
-    self.assertIn("if", result)
-    self.assertIn("else", result)
-
-  def test_type_prefix_strip(self):
-    self.assertEqual(_expr("1'0U"), "0")
-    self.assertEqual(_expr("32'1"), "1")
-    self.assertEqual(_expr("16'0xFFFF"), "0xFFFF")
-
-  def test_suffix_strip(self):
-    self.assertEqual(_expr("0ULL"), "0")
-    self.assertEqual(_expr("1LL"), "1")
-    self.assertEqual(_expr("5U"), "5")
-    self.assertEqual(_expr("3.14F"), "3.14")
-
-  def test_boolean_ops(self):
-    self.assertIn("and", _expr("a && b"))
-    self.assertIn("or", _expr("a || b"))
-    self.assertIn("!=", _expr("a <> b"))
-
-  def test_pack16(self):
-    result = _expr("{ a, b }")
-    self.assertIn("_pack", result)
-
-  def test_type_cast_strip(self):
-    self.assertEqual(_expr("64'U(x)"), "(x)")
-    self.assertEqual(_expr("32'I(y)"), "(y)")
-
-class TestExecContext(unittest.TestCase):
-  def test_float_add(self):
-    ctx = ExecContext(s0=0x40400000, s1=0x40800000)  # 3.0f, 4.0f
-    ctx.D0.f32 = ctx.S0.f32 + ctx.S1.f32
-    self.assertAlmostEqual(_f32(ctx.D0._val), 7.0)
-
-  def test_float_mul(self):
-    ctx = ExecContext(s0=0x40400000, s1=0x40800000)  # 3.0f, 4.0f
-    ctx.run("D0.f32 = S0.f32 * S1.f32")
-    self.assertAlmostEqual(_f32(ctx.D0._val), 12.0)
-
-  def test_scc_comparison(self):
-    ctx = ExecContext(s0=42, s1=42)
-    ctx.run("SCC = S0.u32 == S1.u32")
-    self.assertEqual(ctx.SCC._val, 1)
-
-  def test_scc_comparison_false(self):
-    ctx = ExecContext(s0=42, s1=43)
-    ctx.run("SCC = S0.u32 == S1.u32")
-    self.assertEqual(ctx.SCC._val, 0)
-
-  def test_ternary(self):
-    code = _compile_pseudocode("D0.u32 = S0.u32 > S1.u32 ? 1'1U : 1'0U")
-    ctx = ExecContext(s0=5, s1=3)
-    ctx.run(code)
-    self.assertEqual(ctx.D0._val, 1)
-
-  def test_pack(self):
-    code = _compile_pseudocode("D0 = { S1[15:0].u16, S0[15:0].u16 }")
-    ctx = ExecContext(s0=0x1234, s1=0x5678)
-    ctx.run(code)
-    self.assertEqual(ctx.D0._val, 0x56781234)
-
-  def test_tmp_with_typed_access(self):
-    code = _compile_pseudocode("""tmp = S0.u32 + S1.u32
-D0.u32 = tmp.u32""")
-    ctx = ExecContext(s0=100, s1=200)
-    ctx.run(code)
-    self.assertEqual(ctx.D0._val, 300)
-
-  def test_s_add_u32_pattern(self):
-    # Real pseudocode pattern from S_ADD_U32
-    code = _compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
-SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U
-D0.u32 = tmp.u32""")
-    # Test overflow case
-    ctx = ExecContext(s0=0xFFFFFFFF, s1=0x00000001)
-    ctx.run(code)
-    self.assertEqual(ctx.D0._val, 0)  # Wraps to 0
-    self.assertEqual(ctx.SCC._val, 1)  # Carry set
-
-  def test_s_add_u32_no_overflow(self):
-    code = _compile_pseudocode("""tmp = 64'U(S0.u32) + 64'U(S1.u32)
-SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U
-D0.u32 = tmp.u32""")
-    ctx = ExecContext(s0=100, s1=200)
-    ctx.run(code)
-    self.assertEqual(ctx.D0._val, 300)
-    self.assertEqual(ctx.SCC._val, 0)  # No carry
-
-  def test_vcc_lane_read(self):
-    ctx = ExecContext(vcc=0b1010, lane=1)
-    # Lane 1 is set
-    self.assertEqual(ctx.VCC.u64[1], 1)
-    self.assertEqual(ctx.VCC.u64[2], 0)
-
-  def test_vcc_lane_write(self):
-    ctx = ExecContext(vcc=0, lane=0)
-    ctx.VCC.u64[3] = 1
-    ctx.VCC.u64[1] = 1
-    self.assertEqual(ctx.VCC._val, 0b1010)
-
-  def test_for_loop(self):
-    # CTZ pattern - find first set bit
-    code = _compile_pseudocode("""tmp = -1
-for i in 0 : 31 do
-  if S0.u32[i] == 1 then
-    tmp = i
-  endif
-endfor
-D0.i32 = tmp""")
-    ctx = ExecContext(s0=0b1000)  # Bit 3 is set
-    ctx.run(code)
-    self.assertEqual(ctx.D0._val & MASK32, 3)
-
-  def test_result_dict(self):
-    ctx = ExecContext(s0=5, s1=3)
-    ctx.D0.u32 = 42
-    ctx.SCC._val = 1
-    result = ctx.result()
-    self.assertEqual(result['d0'], 42)
-    self.assertEqual(result['scc'], 1)
-
-class TestPseudocodeRegressions(unittest.TestCase):
-  """Regression tests for pseudocode instruction emulation bugs."""
-
-  def test_v_div_scale_f32_vcc_always_returned(self):
-    """V_DIV_SCALE_F32 must always return VCC, even when VCC=0 (no scaling needed).
-    Bug: when VCC._val == vcc (both 0), VCC wasn't returned, so VCC bits weren't written.
-    This caused division to produce wrong results for multiple lanes."""
-    # Normal case: 1.0 / 3.0, no scaling needed, VCC should be 0
-    s0 = 0x3f800000  # 1.0
-    s1 = 0x40400000  # 3.0
-    s2 = 0x3f800000  # 1.0 (numerator)
-    result = _VOP3SDOp_V_DIV_SCALE_F32(s0, s1, s2, 0, 0, 0, 0, 0xffffffff, 0, None)
-    # Must always have VCC in result
-    self.assertIn('VCC', result, "V_DIV_SCALE_F32 must always return VCC")
-    self.assertEqual(result['VCC'] & 1, 0, "VCC lane 0 should be 0 when no scaling needed")
-
-  def test_v_cmp_class_f32_detects_quiet_nan(self):
-    """V_CMP_CLASS_F32 must correctly identify quiet NaN vs signaling NaN.
-    Bug: isQuietNAN and isSignalNAN both used math.isnan which can't distinguish them."""
-    quiet_nan = 0x7fc00000   # quiet NaN: exponent=255, bit22=1
-    signal_nan = 0x7f800001  # signaling NaN: exponent=255, bit22=0
-    # Test quiet NaN detection (bit 1 in mask)
-    s1_quiet = 0b0000000010  # bit 1 = quiet NaN
-    result = _VOPCOp_V_CMP_CLASS_F32(quiet_nan, s1_quiet, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 1, "Should detect quiet NaN with quiet NaN mask")
-    # Test signaling NaN detection (bit 0 in mask)
-    s1_signal = 0b0000000001  # bit 0 = signaling NaN
-    result = _VOPCOp_V_CMP_CLASS_F32(signal_nan, s1_signal, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 1, "Should detect signaling NaN with signaling NaN mask")
-    # Test that quiet NaN doesn't match signaling NaN mask
-    result = _VOPCOp_V_CMP_CLASS_F32(quiet_nan, s1_signal, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 0, "Quiet NaN should not match signaling NaN mask")
-    # Test that signaling NaN doesn't match quiet NaN mask
-    result = _VOPCOp_V_CMP_CLASS_F32(signal_nan, s1_quiet, 0, 0, 0, 0, 0, 0xffffffff, 0, None)
-    self.assertEqual(result['D0'] & 1, 0, "Signaling NaN should not match quiet NaN mask")
-
-  def testisNAN_with_typed_view(self):
-    """isNAN must work with TypedView objects, not just Python floats.
-    Bug: isNAN checked isinstance(x, float) which returned False for TypedView."""
-    nan_reg = Reg(0x7fc00000)  # quiet NaN
-    normal_reg = Reg(0x3f800000)  # 1.0
-    inf_reg = Reg(0x7f800000)  # +inf
-    self.assertTrue(isNAN(nan_reg.f32), "isNAN should return True for NaN TypedView")
-    self.assertFalse(isNAN(normal_reg.f32), "isNAN should return False for normal TypedView")
-    self.assertFalse(isNAN(inf_reg.f32), "isNAN should return False for inf TypedView")
-
-class TestBF16(unittest.TestCase):
-  """Tests for BF16 (bfloat16) support."""
-
-  def test_bf16_conversion(self):
-    """Test bf16 <-> f32 conversion."""
-    # bf16 is just the top 16 bits of f32
-    # 1.0f = 0x3f800000, bf16 = 0x3f80
-    self.assertAlmostEqual(_bf16(0x3f80), 1.0, places=2)
-    self.assertEqual(_ibf16(1.0), 0x3f80)
-    # 2.0f = 0x40000000, bf16 = 0x4000
-    self.assertAlmostEqual(_bf16(0x4000), 2.0, places=2)
-    self.assertEqual(_ibf16(2.0), 0x4000)
-    # -1.0f = 0xbf800000, bf16 = 0xbf80
-    self.assertAlmostEqual(_bf16(0xbf80), -1.0, places=2)
-    self.assertEqual(_ibf16(-1.0), 0xbf80)
-
-  def test_bf16_special_values(self):
-    """Test bf16 special values (inf, nan)."""
-    import math
-    # +inf: f32 = 0x7f800000, bf16 = 0x7f80
-    self.assertTrue(math.isinf(_bf16(0x7f80)))
-    self.assertEqual(_ibf16(float('inf')), 0x7f80)
-    # -inf: f32 = 0xff800000, bf16 = 0xff80
-    self.assertTrue(math.isinf(_bf16(0xff80)))
-    self.assertEqual(_ibf16(float('-inf')), 0xff80)
-    # NaN: quiet NaN bf16 = 0x7fc0
-    self.assertTrue(math.isnan(_bf16(0x7fc0)))
-    self.assertEqual(_ibf16(float('nan')), 0x7fc0)
-
-  def test_bf16_register_property(self):
-    """Test Reg.bf16 property."""
-    r = Reg(0)
-    r.bf16 = 3.0  # 3.0f = 0x40400000, bf16 = 0x4040
-    self.assertEqual(r._val & 0xffff, 0x4040)
-    self.assertAlmostEqual(float(r.bf16), 3.0, places=1)
-
-  def test_bf16_slice_property(self):
-    """Test TypedView.bf16 property."""
-    r = Reg(0x40404040)  # Two bf16 3.0 values
-    self.assertAlmostEqual(r[15:0].bf16, 3.0, places=1)
-    self.assertAlmostEqual(r[31:16].bf16, 3.0, places=1)
-
-class TestBytePermute(unittest.TestCase):
-  """Tests for BYTE_PERMUTE helper function (V_PERM_B32)."""
-
-  def test_byte_select_0_to_7(self):
-    """Test selecting bytes 0-7 from 64-bit data."""
-    # data = {s0, s1} where s0 is bytes 0-3, s1 is bytes 4-7
-    # Combined: 0x0706050403020100 (byte 0 = 0x00, byte 7 = 0x07)
-    data = 0x0706050403020100
-    for i in range(8):
-      self.assertEqual(BYTE_PERMUTE(data, i), i, f"byte {i} should be {i}")
-
-  def test_sign_extend_bytes(self):
-    """Test sign extension selectors 8-11."""
-    # sel 8: sign of byte 1 (bits 15:8)
-    # sel 9: sign of byte 3 (bits 31:24)
-    # sel 10: sign of byte 5 (bits 47:40)
-    # sel 11: sign of byte 7 (bits 63:56)
-    data = 0x8000800080008000  # All relevant bytes have sign bit set
-    self.assertEqual(BYTE_PERMUTE(data, 8), 0xff)
-    self.assertEqual(BYTE_PERMUTE(data, 9), 0xff)
-    self.assertEqual(BYTE_PERMUTE(data, 10), 0xff)
-    self.assertEqual(BYTE_PERMUTE(data, 11), 0xff)
-    data = 0x7f007f007f007f00  # No sign bits set
-    self.assertEqual(BYTE_PERMUTE(data, 8), 0x00)
-    self.assertEqual(BYTE_PERMUTE(data, 9), 0x00)
-    self.assertEqual(BYTE_PERMUTE(data, 10), 0x00)
-    self.assertEqual(BYTE_PERMUTE(data, 11), 0x00)
-
-  def test_constant_zero(self):
-    """Test selector 12 returns 0x00."""
-    self.assertEqual(BYTE_PERMUTE(0xffffffffffffffff, 12), 0x00)
-
-  def test_constant_ff(self):
-    """Test selectors >= 13 return 0xFF."""
-    for sel in [13, 14, 15, 255]:
-      self.assertEqual(BYTE_PERMUTE(0, sel), 0xff, f"sel {sel} should be 0xff")
-
-class TestSADHelpers(unittest.TestCase):
-  """Tests for V_SAD_U8 and V_MSAD_U8 helper functions."""
-
-  def test_v_sad_u8_basic(self):
-    """Test v_sad_u8 with simple values."""
-    # s0 = 0x04030201, s1 = 0x04030201 -> diff = 0 for all bytes
-    result = v_sad_u8(0x04030201, 0x04030201, 0)
-    self.assertEqual(result, 0)
-    # s0 = 0x05040302, s1 = 0x04030201 -> diff = 1+1+1+1 = 4
-    result = v_sad_u8(0x05040302, 0x04030201, 0)
-    self.assertEqual(result, 4)
-
-  def test_v_sad_u8_with_accumulator(self):
-    """Test v_sad_u8 with non-zero accumulator."""
-    # s0 = 0x05040302, s1 = 0x04030201, s2 = 100 -> 4 + 100 = 104
-    result = v_sad_u8(0x05040302, 0x04030201, 100)
-    self.assertEqual(result, 104)
-
-  def test_v_sad_u8_large_diff(self):
-    """Test v_sad_u8 with maximum byte differences."""
-    # s0 = 0xffffffff, s1 = 0x00000000 -> diff = 255*4 = 1020
-    result = v_sad_u8(0xffffffff, 0x00000000, 0)
-    self.assertEqual(result, 1020)
-
-  def test_v_msad_u8_basic(self):
-    """Test v_msad_u8 masks when reference byte is 0."""
-    # s0 = 0x10101010, s1 = 0x00000000 -> all masked, result = 0
-    result = v_msad_u8(0x10101010, 0x00000000, 0)
-    self.assertEqual(result, 0)
-    # s0 = 0x10101010, s1 = 0x01010101 -> diff = |0x10-0x01|*4 = 15*4 = 60
-    result = v_msad_u8(0x10101010, 0x01010101, 0)
-    self.assertEqual(result, 60)
-
-  def test_v_msad_u8_partial_mask(self):
-    """Test v_msad_u8 with partial masking."""
-    # s0 = 0x10101010, s1 = 0x00010001 -> bytes 1 and 3 masked
-    # diff = |0x10-0x01| + |0x10-0x01| = 15 + 15 = 30
-    result = v_msad_u8(0x10101010, 0x00010001, 0)
-    self.assertEqual(result, 30)
-
-  def test_v_msad_u8_with_accumulator(self):
-    """Test v_msad_u8 with non-zero accumulator."""
-    result = v_msad_u8(0x10101010, 0x01010101, 50)
-    self.assertEqual(result, 110)  # 60 + 50
-
-if __name__ == '__main__':
-  unittest.main()
@@ -1,51 +1,29 @@
 #!/usr/bin/env python3
-"""Test pdf.py PDF parser and enum generation."""
-import unittest, tempfile, importlib.util
-from extra.assembly.amd.pdf import extract, extract_tables, extract_enums, extract_pcode, write_enums, PDF_URLS
+"""Test PDF pseudocode extraction from generate.py."""
+import unittest
+from extra.assembly.amd.generate import extract_pdf_text, extract_pcode, parse_xml, ARCHS, FIXES

-EXPECTED = {
-  "rdna3": {"pages": 655, "tables": 115, "sop2_ops": 67, "sop2_first": "S_ADD_U32"},
-  "rdna4": {"pages": 711, "tables": 125, "sop2_ops": 74, "sop2_first": "S_ADD_CO_U32"},
-  "cdna":  {"pages": 610, "tables": 104, "sop2_ops": 52, "sop2_first": "S_ADD_U32"},
-}
+EXPECTED_PAGES = {"rdna3": 655, "rdna4": 711, "cdna": 610}

-class TestPDF2(unittest.TestCase):
+class TestPcodePDF(unittest.TestCase):
  @classmethod
  def setUpClass(cls):
-    cls.data = {name: extract(url) for name, url in PDF_URLS.items()}
-    cls.tables = {name: extract_tables(pages) for name, pages in cls.data.items()}
-    cls.enums = {name: extract_enums(cls.tables[name]) for name in PDF_URLS}
-    cls.pcode = {name: extract_pcode(cls.data[name], cls.enums[name]) for name in PDF_URLS}
+    cls.pages = {arch: extract_pdf_text(cfg["pdf"]) for arch, cfg in ARCHS.items()}
+    cls.enums = {}
+    for arch, cfg in ARCHS.items():
+      _, enums, _, _, _, _ = parse_xml(cfg["xml"])
+      for fmt, ops in FIXES.get(arch, {}).items(): enums.setdefault(fmt, {}).update(ops)
+      cls.enums[arch] = enums
+    cls.pcode = {arch: extract_pcode(cls.pages[arch], {n: op for ops in cls.enums[arch].values() for op, n in ops.items()}) for arch in ARCHS}

  def test_page_counts(self):
-    for name, exp in EXPECTED.items():
-      self.assertEqual(len(self.data[name]), exp["pages"], f"{name} page count")
+    for name, exp in EXPECTED_PAGES.items():
+      self.assertEqual(len(self.pages[name]), exp, f"{name} page count")

-  def test_table_counts(self):
-    for name, exp in EXPECTED.items():
-      self.assertEqual(len(self.tables[name]), exp["tables"], f"{name} table count")
-
-  def test_tables_sequential(self):
-    for name in PDF_URLS:
-      nums = sorted(self.tables[name].keys())
-      missing = set(range(1, max(nums) + 1)) - set(nums)
-      self.assertEqual(missing, set(), f"{name} missing tables: {missing}")
-
-  def test_generate_enums(self):
-    for name, exp in EXPECTED.items():
-      with tempfile.NamedTemporaryFile(mode='w', suffix='.py', delete=False) as f:
-        write_enums(self.enums[name], name, f.name)
-        spec = importlib.util.spec_from_file_location("enum", f.name)
-        mod = importlib.util.module_from_spec(spec)
-        spec.loader.exec_module(mod)
-        # Check SOP2Op
-        self.assertTrue(hasattr(mod, 'SOP2Op'), f"{name} missing SOP2Op")
-        self.assertEqual(len(mod.SOP2Op), exp["sop2_ops"], f"{name} SOP2Op count")
-        self.assertEqual(mod.SOP2Op(0).name, exp["sop2_first"], f"{name} SOP2Op first")
-        # Check all enums have at least 2 ops
-        for attr in dir(mod):
-          if attr.endswith('Op'):
-            self.assertGreaterEqual(len(getattr(mod, attr)), 2, f"{name} {attr} has too few ops")
+  def test_pcode_extracted(self):
+    """Check we extracted a reasonable number of pcode entries."""
+    for name in ARCHS:
+      self.assertGreater(len(self.pcode[name]), 500, f"{name} pcode count too low")

  def test_pcode_rdna3_tricky(self):
    """Test specific pseudocode patterns that are tricky to extract correctly."""
@@ -62,9 +40,8 @@ class TestPDF2(unittest.TestCase):

  def test_pcode_no_examples(self):
    """Pseudocode should not contain example lines with '=>'."""
-    for name in PDF_URLS:
+    for name in ARCHS:
      for (op_name, opcode), code in self.pcode[name].items():
-        # No example lines (test vectors like "S_CTZ_I32_B32(0xaaaaaaaa) => 1")
        self.assertNotIn('=>', code, f"{name} {op_name} contains example line with '=>'")

 if __name__ == "__main__":
@@ -37,10 +37,10 @@ class TestRDNA3Asm(unittest.TestCase):
      v_add_co_u32(v[2], VCC_LO, s[6], v[2]),
      v_add_co_ci_u32_e32(v[3], s[7], v[3]),
      v_add_co_u32(v[0], VCC_LO, s[4], v[0]),
-      global_load_b32(vdst=v[2], addr=v[2], saddr=OFF),
+      global_load_b32(vdst=v[2], addr=v[2:3], saddr=OFF),
      v_add_co_ci_u32_e32(v[1], s[5], v[1]),
      s_waitcnt(0x03f7),  # vmcnt(0)
-      global_store_b32(addr=v[0], data=v[2], saddr=OFF),
+      global_store_b32(addr=v[0:1], data=v[2], saddr=OFF),
      s_endpgm(),
    ]

@@ -0,0 +1,98 @@
+import unittest, ctypes
+from extra.assembly.amd.autogen.rdna4 import ins as ir4
+from extra.assembly.amd.dsl import v, s
+from extra.assembly.amd.emu import WaveState, decode_program
+from tinygrad.device import Buffer, BufferSpec
+from tinygrad.dtype import dtypes
+
+class TestRDNA4Emu(unittest.TestCase):
+  def _run(self, insts: list, sgprs: dict[int, int] = None, vgprs: dict[tuple[int, int], int] = None) -> WaveState:
+    """Run instructions and return final WaveState."""
+    # Add S_ENDPGM if not present
+    if not any(isinstance(i, ir4.SOPP) and i.op == ir4.SOPPOp.S_ENDPGM for i in insts):
+      insts = list(insts) + [ir4.SOPP(ir4.SOPPOp.S_ENDPGM, simm=0)]
+
+    # Assemble and decode
+    code = b''.join(i.to_bytes() for i in insts)
+    code_buf = (ctypes.c_uint8 * len(code)).from_buffer_copy(code)
+    code_addr = ctypes.addressof(code_buf)
+    program_raw = decode_program(code, "rdna4")
+    program = {code_addr + offset: val for offset, val in program_raw.items()}
+
+    # Setup wave state
+    st = WaveState(n_lanes=1)
+    st.pc = code_addr
+    if sgprs:
+      for idx, val in sgprs.items(): st._write_sgpr(idx, val)
+    if vgprs:
+      for (reg, lane), val in vgprs.items(): st._write_vgpr(reg, lane, val)
+
+    # Setup vmem buffer with external_ptr=0 (maps to address 0, allows any pointer access)
+    vmem_buf = Buffer('CPU', 1 << 40, dtypes.uint32, options=BufferSpec(external_ptr=0)).ensure_allocated()
+
+    # Execute
+    c_bufs = [ctypes.c_uint64(st.sgpr_buf._buf.va_addr), ctypes.c_uint64(st.vgpr_buf._buf.va_addr),
+              ctypes.c_uint64(vmem_buf._buf.va_addr), ctypes.c_uint64(0), ctypes.c_uint64(0)]
+    for _ in range(100):
+      if (pc := st.pc) == 0xFFFFFFFFFFFFFFFF or pc not in program: break
+      _, fxn, globals_list, _ = program[pc]
+      fxn(*[c_bufs[g] for g in globals_list])
+    return st
+
+  def test_vopd_dual_mov(self):
+    """Test VOPD with two V_DUAL_MOV_B32 operations: v[1]=s[1], v[2]=s[2]."""
+    insts = [ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
+                      vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0])]
+    st = self._run(insts, sgprs={1: 0x40e00000, 2: 0x41100000})  # 7.0f, 9.0f
+    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
+    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
+
+  def test_vopd_dual_mov_after_other_vopd(self):
+    """Test VOPD reuse: first VOPD(v[3]=0, v[0]=?), then VOPD(v[1]=s[1], v[2]=s[2])."""
+    # This matches the BEAM kernel sequence that fails
+    insts = [
+      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
+               vdstx=v[3], vdsty=v[0], srcx0=0, srcy0=s[0], vsrcx1=v[0], vsrcy1=v[0]),  # v[3]=0, v[0]=s[0]
+      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
+               vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0]),  # v[1]=s[1], v[2]=s[2]
+    ]
+    st = self._run(insts, sgprs={0: 0x40a00000, 1: 0x40e00000, 2: 0x41100000})  # 5.0f, 7.0f, 9.0f
+    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
+    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
+
+  def test_vopd_with_s_add_f32_sequence(self):
+    """Test full BEAM kernel sequence: s_add_f32 then VOPD."""
+    # This is the exact sequence from the failing BEAM kernel
+    insts = [
+      ir4.SOP2(ir4.SOP2Op.S_ADD_F32, sdst=s[0], ssrc0=s[0], ssrc1=s[8]),   # s[0] = s[0] + s[8]
+      ir4.SOP2(ir4.SOP2Op.S_ADD_F32, sdst=s[1], ssrc0=s[1], ssrc1=s[9]),   # s[1] = s[1] + s[9]
+      ir4.SOP2(ir4.SOP2Op.S_ADD_F32, sdst=s[2], ssrc0=s[2], ssrc1=s[10]),  # s[2] = s[2] + s[10]
+      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
+               vdstx=v[3], vdsty=v[0], srcx0=0, srcy0=s[0], vsrcx1=v[0], vsrcy1=v[0]),
+      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
+               vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0]),
+    ]
+    # Input: s[0:2] = [1,2,3], s[8:10] = [4,5,6]
+    # After s_add_f32: s[0:2] = [5,7,9]
+    st = self._run(insts, sgprs={0: 0x3f800000, 1: 0x40000000, 2: 0x40400000,  # 1.0, 2.0, 3.0
+                                  8: 0x40800000, 9: 0x40a00000, 10: 0x40c00000})  # 4.0, 5.0, 6.0
+    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
+    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
+
+  def test_s_mov_b32_then_vopd(self):
+    """Test s_mov_b32 followed by VOPD - simulates BEAM kernel sequence."""
+    # Use s_mov_b32 with SGPR source (copy from pre-initialized SGPRs)
+    # s[10:12] will have values set by test harness, copy to s[0:2], then VOPD to VGPRs
+    insts = [
+      ir4.SOP1(ir4.SOP1Op.S_MOV_B32, sdst=s[0], ssrc0=s[10]),  # s[0] = s[10]
+      ir4.SOP1(ir4.SOP1Op.S_MOV_B32, sdst=s[1], ssrc0=s[11]),  # s[1] = s[11]
+      ir4.SOP1(ir4.SOP1Op.S_MOV_B32, sdst=s[2], ssrc0=s[12]),  # s[2] = s[12]
+      ir4.VOPD(ir4.VOPDOp.V_DUAL_MOV_B32, ir4.VOPDOp.V_DUAL_MOV_B32,
+               vdstx=v[1], vdsty=v[2], srcx0=s[1], srcy0=s[2], vsrcx1=v[0], vsrcy1=v[0]),
+    ]
+    st = self._run(insts, sgprs={10: 0x40a00000, 11: 0x40e00000, 12: 0x41100000})  # 5.0, 7.0, 9.0
+    self.assertEqual(st._read_vgpr(1, 0), 0x40e00000)  # v[1] = 7.0
+    self.assertEqual(st._read_vgpr(2, 0), 0x41100000)  # v[2] = 9.0
+
+if __name__ == '__main__':
+  unittest.main()
@@ -2,15 +2,8 @@
 """Roundtrip tests: generate tinygrad kernels, decode instructions, re-encode, verify match."""
 import unittest, io, sys, re, subprocess, os
 from extra.assembly.amd.dsl import Inst
-from extra.assembly.amd.asm import asm, detect_format
-from extra.assembly.amd.test.helpers import get_llvm_mc, get_llvm_objdump
-
-# arch: (mcpu, mattr)
-ARCH_CONFIG = {
-  'rdna3': ('gfx1100', '+real-true16,+wavefrontsize32'),
-  'rdna4': ('gfx1200', '+real-true16,+wavefrontsize32'),
-  'cdna': ('gfx942', '+wavefrontsize64'),
-}
+from extra.assembly.amd import decode_inst, detect_format
+from extra.assembly.amd.test.helpers import get_llvm_mc, get_llvm_objdump, get_target, get_mattr

 def disassemble_lib(lib: bytes, compiler) -> list[tuple[str, bytes]]:
  """Disassemble ELF binary and return list of (instruction_text, machine_code_bytes)."""
@@ -42,8 +35,7 @@ def compile_asm(instr: str, arch: str = 'rdna3') -> bytes:
 def compile_asm_batch(instrs: list[str], arch: str = 'rdna3') -> list[bytes]:
  """Compile multiple instructions with a single llvm-mc call."""
  if not instrs: return []
-  mcpu, mattr = ARCH_CONFIG[arch]
-  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={mcpu}', f'-mattr={mattr}', '-show-encoding'],
+  result = subprocess.run([get_llvm_mc(), '-triple=amdgcn', f'-mcpu={get_target(arch)}', f'-mattr={get_mattr(arch)}', '-show-encoding'],
                          input=".text\n" + "\n".join(instrs) + "\n", capture_output=True, text=True)
  if result.returncode != 0: raise RuntimeError(f"llvm-mc batch failed: {result.stderr.strip()}")
  encodings = []
@@ -59,7 +51,7 @@ def compile_and_disasm_batch(instrs: list[str], arch: str = 'rdna3') -> list[str
  """Compile instructions with LLVM and get LLVM's disassembly."""
  import tempfile
  if not instrs: return []
-  mcpu, mattr = ARCH_CONFIG[arch]
+  mcpu, mattr = get_target(arch), get_mattr(arch)
  src = ".text\n.globl test\n.p2align 8\n.type test,@function\ntest:\n" + "\n".join(f"  {instr}" for instr in instrs) + "\n"
  with tempfile.NamedTemporaryFile(suffix='.o', delete=False) as f:
    obj_path = f.name
@@ -85,24 +77,27 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
  def _test_kernel_roundtrip(self, op_fn):
    """Generate kernel from op_fn, test:
    1. decode -> reencode matches original bytes
-    2. asm(disasm()) matches LLVM output
-    3. our disasm() matches LLVM's disassembly string exactly
+    2. disasm() -> LLVM asm -> bytes matches original (validates disasm correctness)
+    3. our disasm() matches LLVM's disassembly string (informational)
    """
    arch = self.arch
-    mcpu, mattr = ARCH_CONFIG[arch]

    from extra.assembly.amd.test.test_compare_emulators import get_kernels_from_tinygrad
-    from tinygrad.runtime.support.compiler_amd import HIPCompiler
+    from tinygrad.runtime.support.elf import elf_loader
+    from tinygrad.runtime.support.compiler_amd import HIPCompiler, AMDLLVMCompiler
+    from tinygrad.helpers import AMD_LLVM

    kernels, _, _ = get_kernels_from_tinygrad(op_fn)
-    compiler = HIPCompiler(mcpu)
+    # rendered source can be C or llvmir
+    compiler = (AMDLLVMCompiler if AMD_LLVM else HIPCompiler)(get_target(arch))

    # First pass: decode all instructions and collect info
    decoded_instrs: list[tuple] = []  # list of (ki, offset, orig_bytes, decoded, our_disasm, decode_ok, decode_err)
    for ki, kernel in enumerate(kernels):
      offset = 0
-      while offset < len(kernel.code):
-        remaining = kernel.code[offset:]
+      code = next((s.content for s in elf_loader(compiler.compile(kernel.src))[1] if s.name == ".text"))
+      while offset < len(code):
+        remaining = code[offset:]
        fmt = detect_format(remaining, arch)
        if fmt is None:
          decoded_instrs.append((ki, offset, None, None, None, False, "no format"))
@@ -129,19 +124,19 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
        offset += size

    # Collect disasm strings for batched LLVM calls - skip unknown opcodes (op_X) that LLVM can't compile
-    asm_test_instrs: list[tuple[int, str]] = []  # (idx, our_disasm) for asm test
+    asm_test_instrs: list[tuple[int, str, bytes]] = []  # (idx, our_disasm, orig_bytes) for asm test
    disasm_test_instrs: list[tuple[int, str]] = []  # (idx, our_disasm) for disasm comparison test

    for idx, (ki, offset, orig_bytes, decoded, our_disasm, decode_ok, decode_err) in enumerate(decoded_instrs):
      if our_disasm is None: continue
-      # Skip unknown opcodes and malformed instructions for both tests
+      # Skip unknown opcodes and malformed instructions
      if our_disasm.startswith('op_') or re.search(r', \d+, \d+, \d+,', our_disasm): continue
-      asm_test_instrs.append((idx, our_disasm))
+      asm_test_instrs.append((idx, our_disasm, orig_bytes))
      disasm_test_instrs.append((idx, our_disasm))

-    # Batch compile for asm test
-    asm_llvm_results = compile_asm_batch([d for _, d in asm_test_instrs], arch)
-    asm_llvm_map = {idx: result for (idx, _), result in zip(asm_test_instrs, asm_llvm_results)}
+    # Batch compile for asm test (our disasm -> LLVM asm -> bytes)
+    asm_llvm_results = compile_asm_batch([d for _, d, _ in asm_test_instrs], arch)
+    asm_llvm_map = {idx: (result, orig) for (idx, _, orig), result in zip(asm_test_instrs, asm_llvm_results)}

    # Batch compile+disasm for disasm comparison test
    disasm_llvm_results = compile_and_disasm_batch([d for _, d in disasm_test_instrs], arch)
@@ -165,20 +160,16 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
        decode_failed += 1
        decode_failures.append(f"K{ki}@{offset}: {our_disasm}: {decode_err}")

-      # Asm test
+      # Asm test: our disasm -> LLVM asm -> compare bytes with original
      if our_disasm is None:
        asm_skipped += 1
      elif idx in asm_llvm_map:
-        llvm_bytes = asm_llvm_map[idx]
-        try:
-          our_bytes = asm(our_disasm).to_bytes()
-          if our_bytes[:len(llvm_bytes)] == llvm_bytes:
-            asm_passed += 1
-          else:
-            asm_failed += 1
-            asm_failures.append(f"K{ki}@{offset}: '{our_disasm}': ours={our_bytes[:len(llvm_bytes)].hex()} llvm={llvm_bytes.hex()}")
-        except Exception:
-          asm_skipped += 1
+        llvm_bytes, orig = asm_llvm_map[idx]
+        if llvm_bytes == orig[:len(llvm_bytes)]:
+          asm_passed += 1
+        else:
+          asm_failed += 1
+          asm_failures.append(f"K{ki}@{offset}: '{our_disasm}': llvm={llvm_bytes.hex()} orig={orig[:len(llvm_bytes)].hex()}")
      else:
        asm_skipped += 1

@@ -196,7 +187,7 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
        disasm_skipped += 1

    print(f"[{arch}] decode roundtrip: {decode_passed} passed, {decode_failed} failed, {decode_skipped} skipped")
-    print(f"[{arch}] asm vs llvm: {asm_passed} passed, {asm_failed} failed, {asm_skipped} skipped")
+    print(f"[{arch}] asm via llvm: {asm_passed} passed, {asm_failed} failed, {asm_skipped} skipped")
    print(f"[{arch}] disasm vs llvm: {disasm_passed} passed, {disasm_failed} failed, {disasm_skipped} skipped")
    self.assertEqual(decode_failed, 0, f"Decode failures:\n" + "\n".join(decode_failures[:20]))
    self.assertEqual(asm_failed, 0, f"Asm failures:\n" + "\n".join(asm_failures[:20]))
@@ -247,10 +238,9 @@ class TestTinygradKernelRoundtrip(unittest.TestCase):
  # Fused ops
  def test_fma(self): self._test_kernel_roundtrip(lambda T: (T([1.0, 2.0]) * T([3.0, 4.0]) + T([5.0, 6.0])))

-@unittest.skip("no asm support for RDNA4")
 class TestTinygradKernelRoundtripRDNA4(TestTinygradKernelRoundtrip): arch = 'rdna4'

-@unittest.skip("no asm support for CDNA")
+@unittest.skip("CDNA decode roundtrip not yet supported")
 class TestTinygradKernelRoundtripCDNA(TestTinygradKernelRoundtrip): arch = 'cdna'

 if __name__ == "__main__":
@@ -1,15 +1,16 @@
 #!/usr/bin/env python3
 """Tests for SQTT packet decoding using real captured examples."""
-import pickle, unittest, ctypes
+import pickle, unittest, ctypes, threading
 from pathlib import Path
-from tinygrad.helpers import DEBUG, colored
+from tinygrad.helpers import DEBUG
 from tinygrad.runtime.autogen import rocprof
 from tinygrad.runtime.support.elf import elf_loader
-from extra.assembly.amd.asm import detect_format
+from extra.assembly.amd import decode_inst
 from extra.assembly.amd.autogen.rdna3.ins import SOPP
 from extra.assembly.amd.autogen.rdna3.enum import SOPPOp
-from extra.assembly.amd.sqtt import (decode, LAYOUT_HEADER, WAVESTART, WAVEEND, INST, VALUINST, IMMEDIATE, IMMEDIATE_MASK,
-                                     ALUEXEC, VMEMEXEC, PACKET_TYPES, InstOp, AluSrc, MemSrc)
+from extra.assembly.amd.sqtt import (decode, LAYOUT_HEADER, WAVESTART, WAVESTART_L4, WAVEEND, INST, INST_L4, VALUINST, IMMEDIATE, IMMEDIATE_MASK,
+                                     ALUEXEC, VMEMEXEC, PACKET_TYPES_L3, PACKET_TYPES_L4, InstOp, InstOpL4, print_packets)
+from extra.assembly.amd.test.helpers import TARGET_TO_ARCH

 EXAMPLES_DIR = Path(__file__).parent.parent.parent.parent / "sqtt/examples"
 # INST ops for non-traced SIMDs (excluded from instruction count)
@@ -18,40 +19,13 @@ OTHER_SIMD_OPS = {InstOp.OTHER_LDS_LOAD, InstOp.OTHER_LDS_STORE, InstOp.OTHER_LD
                  InstOp.OTHER_FLAT_STORE_128, InstOp.OTHER_GLOBAL_LOAD, InstOp.OTHER_GLOBAL_LOAD_VADDR,
                  InstOp.OTHER_GLOBAL_STORE_64, InstOp.OTHER_GLOBAL_STORE_96, InstOp.OTHER_GLOBAL_STORE_128,
                  InstOp.OTHER_GLOBAL_STORE_VADDR_128}
-
-PACKET_COLORS = {
-  "INST": "WHITE", "VALUINST": "BLACK", "VMEMEXEC": "yellow", "ALUEXEC": "yellow",
-  "IMMEDIATE": "YELLOW", "IMMEDIATE_MASK": "YELLOW", "WAVERDY": "cyan", "WAVEALLOC": "cyan",
-  "WAVEEND": "blue", "WAVESTART": "blue", "PERF": "magenta", "EVENT": "red", "EVENT_BIG": "red",
-  "REG": "green", "LAYOUT_HEADER": "white", "SNAPSHOT": "white", "UTILCTR": "green",
-}
-
-def format_packet(p, time_offset: int = 0) -> str:
-  name, cycle = type(p).__name__, p._time - time_offset
-  if isinstance(p, INST):
-    op_name = p.op.name if isinstance(p.op, InstOp) else f"0x{p.op:02x}"
-    fields = f"wave={p.wave} op={op_name}" + (" flag1" if p.flag1 else "") + (" flag2" if p.flag2 else "")
-  elif isinstance(p, VALUINST): fields = f"wave={p.wave}" + (" flag" if p.flag else "")
-  elif isinstance(p, ALUEXEC): fields = f"src={p.src.name if isinstance(p.src, AluSrc) else p.src}"
-  elif isinstance(p, VMEMEXEC): fields = f"src={p.src.name if isinstance(p.src, MemSrc) else p.src}"
-  elif isinstance(p, (WAVESTART, WAVEEND)): fields = f"wave={p.wave} simd={p.simd} cu={p.cu}"
-  elif hasattr(p, '_values'):
-    fields = " ".join(f"{k}=0x{v:x}" if k in {'snap', 'val32'} else f"{k}={v}"
-                      for k, v in p._values.items() if not k.startswith('_') and k != 'delta')
-  else: fields = ""
-  return f"{cycle:8}: {colored(f'{name:18}', PACKET_COLORS.get(name, 'white'))} {fields}"
-
-def print_packets(packets: list) -> None:
-  skip = {"NOP", "TS_DELTA_SHORT", "TS_WAVE_STATE", "TS_DELTA_OR_MARK", "TS_DELTA_S5_W2", "TS_DELTA_S5_W3", "TS_DELTA_S8_W3", "REG", "EVENT"}
-  time_offset = packets[0]._time if packets else 0
-  for p in packets:
-    if type(p).__name__ not in skip: print(format_packet(p, time_offset))
+OTHER_SIMD_OPS_L4 = {InstOpL4.OTHER_VMEM, InstOpL4.UNK_60}

 # ═══════════════════════════════════════════════════════════════════════════════
 # ROCPROF DECODER
 # ═══════════════════════════════════════════════════════════════════════════════

-def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int):
+def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int, target: str):
  """Run rocprof decoder on SQTT blobs, returning raw occupancy and instruction records."""
  image, sections, _ = elf_loader(lib)
  text = next((sh for sh in sections if sh.name == ".text"), None)
@@ -86,6 +60,7 @@ def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int):
          wave_insts.append([(inst.time, inst.stall) for inst in insts])
    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS

+  arch = TARGET_TO_ARCH[target]
  @rocprof.rocprof_trace_decoder_isa_callback_t
  def isa_cb(instr_ptr, mem_size_ptr, size_ptr, pc, _):
    offset = pc.address - base
@@ -93,8 +68,9 @@ def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int):
      mem_size_ptr[0] = 0
      return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
    try:
-      inst = detect_format(data := image[offset:]).from_bytes(data)
+      inst = decode_inst(image[offset:], arch=arch)
      mem_size_ptr[0] = inst._size()
+    # this could be an error in our decode_inst
    except (ValueError, AssertionError):
      mem_size_ptr[0] = 0
      return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS
@@ -105,14 +81,25 @@ def run_rocprof_decoder(blobs: list[bytes], lib: bytes, base: int):
    size_ptr[0] = min(5, max_sz - 1)
    return rocprof.ROCPROFILER_THREAD_TRACE_DECODER_STATUS_SUCCESS

-  rocprof.rocprof_trace_decoder_parse_data(copy_cb, trace_cb, isa_cb, None)
+  exc = None
+  def worker():
+    nonlocal exc
+    try: rocprof.rocprof_trace_decoder_parse_data(copy_cb, trace_cb, isa_cb, None)
+    except Exception as e: exc = e
+  (t:=threading.Thread(target=worker, daemon=True)).start()
+  t.join(timeout=1)
+  if exc is not None: raise exc
+  if t.is_alive(): raise RuntimeError("rocprof decoder timeout")
  return occupancy_records, wave_insts

-class TestSQTTExamples(unittest.TestCase):
+class SQTTExamplesTestBase(unittest.TestCase):
+  target: str
+
  @classmethod
  def setUpClass(cls):
+    if cls is SQTTExamplesTestBase: raise unittest.SkipTest("base class")
    cls.examples = {}
-    for pkl_path in sorted(EXAMPLES_DIR.glob("*.pkl")):
+    for pkl_path in sorted((EXAMPLES_DIR/cls.target).glob("*.pkl")):
      with open(pkl_path, "rb") as f:
        data = pickle.load(f)
      sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
@@ -127,24 +114,26 @@ class TestSQTTExamples(unittest.TestCase):
    for name, (events, *_) in self.examples.items():
      for i, event in enumerate(events):
        with self.subTest(example=name, event=i):
-          packets = decode(event.blob)
+          packets = list(decode(event.blob))
          if DEBUG >= 2: print(f"\n=== {name} event {i} ==="); print_packets(packets)
          self.assertGreater(len(packets), 0, f"no packets decoded from {name} event {i}")
          self.assertIsInstance(packets[0], LAYOUT_HEADER, f"first packet should be LAYOUT_HEADER in {name}")

  def test_packet_types_valid(self):
+    all_classes = set(PACKET_TYPES_L3.values()) | set(PACKET_TYPES_L4.values())
    for name, (events, *_) in self.examples.items():
      for i, event in enumerate(events):
        with self.subTest(example=name, event=i):
          for pkt in decode(event.blob):
-            self.assertIn(type(pkt), PACKET_TYPES, f"unknown packet type {type(pkt)} in {name}")
+            # Use isinstance to handle layout-specific subclasses (e.g., WAVESTART_L4)
+            self.assertTrue(any(isinstance(pkt, cls) for cls in all_classes), f"unknown packet type {type(pkt)} in {name}")

  def test_wave_lifecycle(self):
    for name, (events, *_) in self.examples.items():
      if "empty" in name: continue
      with self.subTest(example=name):
        all_packets = [p for e in events for p in decode(e.blob)]
-        self.assertGreater(len([p for p in all_packets if isinstance(p, WAVESTART)]), 0, f"no WAVESTART in {name}")
+        self.assertGreater(len([p for p in all_packets if isinstance(p, (WAVESTART, WAVESTART_L4))]), 0, f"no WAVESTART in {name}")
        self.assertGreater(len([p for p in all_packets if isinstance(p, WAVEEND)]), 0, f"no WAVEEND in {name}")

  def test_time_monotonic(self):
@@ -159,13 +148,22 @@ class TestSQTTExamples(unittest.TestCase):
      if "gemm" not in name: continue
      with self.subTest(example=name):
        all_packets = [p for e in events for p in decode(e.blob)]
-        self.assertGreater(len([p for p in all_packets if isinstance(p, INST)]), 0, f"no INST packets in {name}")
+        self.assertGreater(len([p for p in all_packets if isinstance(p, (INST, INST_L4))]), 0, f"no INST packets in {name}")
+
+  expected: dict[str, list[int]] = {}  # override in subclasses
+  def test_packet_counts(self):
+    if not self.expected: self.skipTest("no expected packet counts for this target")
+    for name, (events, *_) in self.examples.items():
+      with self.subTest(example=name):
+        if not self.expected.get(name): continue
+        counts = [len(list(decode(e.blob))) for e in events]
+        self.assertEqual(counts, self.expected[name], f"packet count mismatch in {name}")

  def test_rocprof_wave_times_match(self):
    """Wave start/end times must match rocprof exactly."""
    for name, (events, lib, base) in self.examples.items():
      with self.subTest(example=name):
-        occupancy, _ = run_rocprof_decoder([e.blob for e in events], lib, base)
+        occupancy, _ = run_rocprof_decoder([e.blob for e in events], lib, base, self.target)
        # extract from rocprof occupancy records
        roc_starts: dict[tuple[int, int, int], int] = {}
        roc_waves: list[tuple[int, int]] = []
@@ -176,10 +174,9 @@ class TestSQTTExamples(unittest.TestCase):
        # extract from our decoder
        our_waves: list[tuple[int, int]] = []
        for event in events:
-          packets = decode(event.blob)
          wave_starts: dict[tuple[int, int, int], int] = {}
-          for p in packets:
-            if isinstance(p, WAVESTART): wave_starts[(p.wave, p.simd, p.cu)] = p._time
+          for p in decode(event.blob):
+            if isinstance(p, (WAVESTART, WAVESTART_L4)): wave_starts[(p.wave, p.simd, p.cu)] = p._time
            elif isinstance(p, WAVEEND) and (key := (p.wave, p.simd, p.cu)) in wave_starts:
              our_waves.append((wave_starts[key], p._time))
        self.assertEqual(sorted(our_waves), sorted(roc_waves), f"wave times mismatch in {name}")
@@ -188,7 +185,7 @@ class TestSQTTExamples(unittest.TestCase):
    """Instruction times must match rocprof exactly (excluding s_endpgm)."""
    for name, (events, lib, base) in self.examples.items():
      with self.subTest(example=name):
-        _, wave_insts = run_rocprof_decoder([e.blob for e in events], lib, base)
+        _, wave_insts = run_rocprof_decoder([e.blob for e in events], lib, base, self.target)
        # skip last inst per wave (s_endpgm) - it needs special handling (time + duration instead of time + stall)
        roc_insts = [time + stall for insts in wave_insts for time, stall in insts[:-1]]
        # extract from our decoder
@@ -196,11 +193,32 @@ class TestSQTTExamples(unittest.TestCase):
        for event in events:
          for p in decode(event.blob):
            if isinstance(p, INST) and p.op not in OTHER_SIMD_OPS: our_insts.append(p._time)
+            elif isinstance(p, INST_L4) and p.op not in OTHER_SIMD_OPS_L4: our_insts.append(p._time)
            elif isinstance(p, VALUINST): our_insts.append(p._time)
            elif isinstance(p, IMMEDIATE): our_insts.append(p._time)
            elif isinstance(p, IMMEDIATE_MASK):
              for _ in range(bin(p.mask).count('1')): our_insts.append(p._time)
        self.assertEqual(sorted(our_insts), sorted(roc_insts), f"instruction times mismatch in {name}")

+class TestSQTTExamplesRDNA3(SQTTExamplesTestBase):
+  target = "gfx1100"
+  expected = {
+    "profile_empty_run_0": [1844, 1885, 1905, 1956, 1983, 1889],
+    "profile_empty_run_1": [1780, 1885, 1905, 1956, 1983, 1889],
+    "profile_gemm_run_0": [2656, 2025, 2045, 2096, 2123, 2029, 3183, 2019, 2039, 2090, 2117, 2023, 19119, 2013, 2033, 2084, 2111, 2017],
+    "profile_gemm_run_1": [2662, 2025, 2045, 2096, 2123, 2029, 3179, 2019, 2039, 2090, 2117, 2023, 19113, 2071, 2091, 2142, 2169, 2075],
+    "profile_plus_run_0": [1886, 2013, 2033, 2084, 2111, 2017],
+    "profile_plus_run_1": [1988, 2071, 2091, 2142, 2169, 2075],
+  }
+
+class TestSQTTExamplesRDNA4(SQTTExamplesTestBase): target = "gfx1200"
+# CDNA/MI300 (gfx950) uses a completely different 16-bit header packet format, not the nibble-based format.
+# See decode_tt_header_stream in ghidra/librocprof-trace-decoder.c - it reads 16-bit headers and uses
+# pkt_fmt = header & 0xf to look up packet_class (0x10=2bytes, 0x20=4bytes, 0x30=6bytes, 0x40=8bytes).
+# This is NOT implemented yet - the nibble decoder produces garbage for CDNA data.
+@unittest.skip("CDNA/MI300 uses 16-bit header format, not nibble-based - decoder not implemented")
+class TestSQTTExamplesCDNA(SQTTExamplesTestBase):
+  target = "gfx950"
+
 if __name__ == "__main__":
  unittest.main()
@@ -0,0 +1,170 @@
+"""Tests comparing sqtt.py PACKET_TYPES_L3/L4 against AMD's rocprof-trace-decoder binary."""
+import unittest, struct, ctypes, pickle
+from pathlib import Path
+
+ROCPROF_LIB = Path("/usr/lib/librocprof-trace-decoder.so")
+EXAMPLES_DIR = Path(__file__).parent.parent.parent.parent / "sqtt/examples"
+
+def _find_segment(perms: str):
+  """Find a segment of the loaded library with given permissions (e.g. 'rw-p', 'r--p')."""
+  with open('/proc/self/maps', 'r') as f:
+    for line in f:
+      if 'librocprof-trace-decoder.so' in line and f' {perms} ' in line:
+        parts = line.split()
+        return int(parts[0].split('-')[0], 16), int(parts[2], 16)
+  return None, None
+
+def _read_array(file_offset: int, count: int):
+  """Read an array of uint8 at file_offset from the loaded library."""
+  base, seg_offset = _find_segment('rw-p')
+  if base is None: return None
+  return list((ctypes.c_uint8 * count).from_address(base + (file_offset - seg_offset)))
+
+def _load_lib():
+  if not ROCPROF_LIB.exists(): return False
+  ctypes.CDLL(str(ROCPROF_LIB))
+  return True
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# RDNA EXTRACTION (nibble-based format)
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def extract_bit_tables():
+  """Extract bit budget tables. Returns (layout2, layout3, layout4) or None."""
+  if not _load_lib(): return None
+  return _read_array(0x2d220, 32), _read_array(0x2d280, 32), _read_array(0x2d2c0, 32)
+
+def extract_delta_fields():
+  """Extract delta bitfield tables. Returns (layout2, layout3, layout4) dicts mapping type_id -> (lo, hi)."""
+  if not _load_lib(): return None
+  ro_base, ro_offset = _find_segment('r--p')
+  if ro_base is None: return None
+
+  def read_table(file_offset, num_entries):
+    addr = ro_base + (file_offset - ro_offset)
+    data = bytes((ctypes.c_uint8 * (num_entries * 12)).from_address(addr))
+    return {type_id: (lo, hi) for j in range(0, len(data), 12)
+            for type_id, lo, hi in [struct.unpack('<III', data[j:j+12])] if type_id < 32}
+
+  return read_table(0x26800, 24), read_table(0x26dc0, 25), read_table(0x27300, 27)
+
+def extract_packet_encodings():
+  """Extract packet encodings. Returns (L2, L3, L4) dicts mapping type_id -> (mask, value)."""
+  if not _load_lib(): return None
+  rw_base, rw_offset = _find_segment('rw-p')
+  if rw_base is None: return None
+
+  # Read base encodings from registration vector at 0x2d340
+  vec_start = ctypes.c_void_p.from_address(rw_base + (0x2d340 - rw_offset)).value
+  vec_end = ctypes.c_void_p.from_address(rw_base + (0x2d348 - rw_offset)).value
+  base = {}
+  if vec_start and vec_end:
+    for i in range((vec_end - vec_start) // 32):
+      addr = vec_start + i * 32
+      type_id = ctypes.c_uint8.from_address(addr).value
+      pat_start = ctypes.c_void_p.from_address(addr + 8).value
+      pat_end = ctypes.c_void_p.from_address(addr + 16).value
+      if pat_start and pat_end and 0 < (n := pat_end - pat_start) <= 8:
+        pat = list((ctypes.c_uint8 * n).from_address(pat_start))
+        base[type_id] = (sum(1 << j for j in range(n)), sum(b << j for j, b in enumerate(pat)))
+
+  return {**base, 17: (0x7f, 0x51), 25: (0x7f, 0x31)}, base, {**base}  # L2 has overrides
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# CDNA EXTRACTION (16-bit header format)
+# ═══════════════════════════════════════════════════════════════════════════════
+
+def extract_cdna_packet_sizes():
+  """Extract CDNA pkt_fmt -> size mapping by running rocprof decoder to populate its hash table."""
+  from extra.assembly.amd.test.test_sqtt_examples import run_rocprof_decoder
+
+  if not (pkl_path := next((EXAMPLES_DIR / "gfx950").glob("*.pkl"), None)): return None
+  with open(pkl_path, "rb") as f: data = pickle.load(f)
+  sqtt_events = [e for e in data if type(e).__name__ == "ProfileSQTTEvent"]
+  prg = next((e for e in data if type(e).__name__ == "ProfileProgramEvent"), None)
+  if not sqtt_events or not prg: return None
+
+  # Run decoder to trigger hash table initialization
+  run_rocprof_decoder([e.blob for e in sqtt_events], prg.lib, prg.base, "gfx950")
+
+  # Extract hash table: head at 0x2d4f0, nodes are 16 bytes (next[8], key[4], value[4])
+  rw_base, rw_offset = _find_segment('rw-p')
+  if not (head := ctypes.c_void_p.from_address(rw_base + (0x2d4f0 - rw_offset)).value if rw_base else None): return None
+
+  pkt_sizes, node, seen = {}, head, set()
+  while node and node not in seen and len(pkt_sizes) < 20:
+    seen.add(node)
+    key, val = ctypes.c_uint32.from_address(node + 8).value, ctypes.c_uint32.from_address(node + 12).value
+    if key < 16 and val in (0x10, 0x20, 0x30, 0x40): pkt_sizes[key] = {0x10: 2, 0x20: 4, 0x30: 6, 0x40: 8}[val]
+    node = ctypes.c_void_p.from_address(node).value
+  return pkt_sizes if len(pkt_sizes) == 16 else None
+
+# ═══════════════════════════════════════════════════════════════════════════════
+# TESTS
+# ═══════════════════════════════════════════════════════════════════════════════
+
+class TestSQTTMatchesBinary(unittest.TestCase):
+  def test_bit_counts_match_layout3(self): self._test_bit_counts(3)
+  def test_bit_counts_match_layout4(self): self._test_bit_counts(4)
+  def test_encodings_match_layout3(self): self._test_encodings(3)
+  def test_encodings_match_layout4(self): self._test_encodings(4)
+  def test_delta_fields_match_layout3(self): self._test_delta_fields(3)
+  def test_delta_fields_match_layout4(self): self._test_delta_fields(4)
+
+  def test_cdna_packet_sizes(self):
+    """Extract and verify CDNA pkt_fmt -> size mapping from rocprof's hash table."""
+    if not (EXAMPLES_DIR / "gfx950").exists(): self.skipTest("no CDNA examples")
+    pkt_sizes = extract_cdna_packet_sizes()
+    self.assertIsNotNone(pkt_sizes, "failed to extract CDNA packet sizes")
+    from extra.assembly.amd.sqtt_cdna import CDNA_PKT_SIZES
+    for pkt_fmt, size in CDNA_PKT_SIZES.items():
+      with self.subTest(pkt_fmt=pkt_fmt): self.assertEqual(pkt_sizes.get(pkt_fmt), size)
+
+  def _test_bit_counts(self, layout: int):
+    if not (tables := extract_bit_tables()): self.skipTest("rocprof-trace-decoder not installed")
+    from extra.assembly.amd.sqtt import PACKET_TYPES_L3, PACKET_TYPES_L4
+    for type_id, pkt_cls in {3: PACKET_TYPES_L3, 4: PACKET_TYPES_L4}[layout].items():
+      with self.subTest(packet=pkt_cls.__name__):
+        self.assertEqual(pkt_cls._size_nibbles * 4, tables[layout - 2][type_id])
+
+  def _test_encodings(self, layout: int):
+    if not (encodings := extract_packet_encodings()): self.skipTest("rocprof-trace-decoder not installed")
+    from extra.assembly.amd.sqtt import PACKET_TYPES_L3, PACKET_TYPES_L4
+    for type_id, pkt_cls in {3: PACKET_TYPES_L3, 4: PACKET_TYPES_L4}[layout].items():
+      with self.subTest(packet=pkt_cls.__name__):
+        self.assertEqual((pkt_cls.encoding.mask, pkt_cls.encoding.default), encodings[layout - 2][type_id])
+
+  def _test_delta_fields(self, layout: int):
+    if not (deltas := extract_delta_fields()): self.skipTest("rocprof-trace-decoder not installed")
+    from extra.assembly.amd.sqtt import PACKET_TYPES_L3, PACKET_TYPES_L4
+    for type_id, pkt_cls in {3: PACKET_TYPES_L3, 4: PACKET_TYPES_L4}[layout].items():
+      if type_id not in deltas[layout - 2]: continue
+      delta = getattr(pkt_cls, 'delta', None)
+      actual = (0, 0) if delta is None else (delta.lo, delta.hi + 1)
+      with self.subTest(packet=pkt_cls.__name__): self.assertEqual(actual, deltas[layout - 2][type_id])
+
+if __name__ == "__main__":
+  tables = extract_bit_tables()
+  encodings = extract_packet_encodings()
+  deltas = extract_delta_fields()
+
+  TYPE_NAMES = {1: 'VALUINST', 2: 'VMEMEXEC', 3: 'ALUEXEC', 4: 'IMMEDIATE', 5: 'IMMEDIATE_MASK', 6: 'WAVERDY',
+    7: 'TS_DELTA_S8_W3', 8: 'WAVEEND', 9: 'WAVESTART', 10: 'TS_DELTA_S5_W2', 11: 'WAVEALLOC', 12: 'TS_DELTA_S5_W3',
+    13: 'PERF', 14: 'UTILCTR', 15: 'TS_DELTA_SHORT', 16: 'NOP', 17: 'TS_WAVE_STATE', 18: 'EVENT', 19: 'EVENT_BIG',
+    20: 'REG', 21: 'SNAPSHOT', 22: 'TS_DELTA_OR_MARK', 23: 'LAYOUT_HEADER', 24: 'INST', 25: 'UNK_25'}
+
+  print("L2:", tables[0], "\nL3:", tables[1], "\nL4:", tables[2])
+  if encodings and tables:
+    print(f"\n{'TypeID':>6} {'Name':>18} {'L2 enc':>12} {'L3 enc':>12} {'L4 enc':>12} {'L2':>4} {'L3':>4} {'L4':>4} {'L2 delta':>12} {'L3 delta':>12} {'L4 delta':>12}")
+    print("-" * 140)
+    for type_id in sorted(set(encodings[0]) | set(encodings[1]) | set(encodings[2])):
+      name = TYPE_NAMES.get(type_id, f'UNK_{type_id}')
+      bits = [tables[i][type_id] if type_id < len(tables[i]) else 0 for i in range(3)]
+      enc_strs = [f"0x{encodings[i][type_id][0]:02x}/0x{encodings[i][type_id][1]:02x}" if type_id in encodings[i] else "-" for i in range(3)]
+      delta_strs = [f"[{d[1]-1}:{d[0]}]" if (d := deltas[i].get(type_id, (0, 0)))[1] > d[0] else "-" for i in range(3)]
+      print(f"{type_id:6d} {name:>18} {enc_strs[0]:>12} {enc_strs[1]:>12} {enc_strs[2]:>12} {bits[0]:4d} {bits[1]:4d} {bits[2]:4d} {delta_strs[0]:>12} {delta_strs[1]:>12} {delta_strs[2]:>12}")
+
+  cdna = extract_cdna_packet_sizes()
+  if cdna: print(f"\nCDNA packet sizes: {cdna}")
+
+  unittest.main()
@@ -67,12 +67,11 @@ def export_model_clang(functions:Dict[str,str], statements:Dict[str,Tuple[str,in
  forward_args = ",".join(f"{dtype}{'*' if name not in symbolic_vars.values() else ''} {name}" for name,dtype,_ in (outputs+inputs if wasm else inputs+outputs))

  if not wasm:
-    thread_id = 0 # NOTE: export does not support threading, thread_id is always 0
    for name,cl in bufs_to_save.items():
      weight = ''.join(["\\x%02X"%x for x in bytes(to_mv(cl._buf.va_addr, cl._buf.size))])
      cprog.append(f"unsigned char {name}_data[] = \"{weight}\";")
    cprog += [f"{dtype_map[dtype]} {name}[{len}];" if name not in bufs_to_save else f"{dtype_map[dtype]} *{name} = ({dtype_map[dtype]} *){name}_data;" for name,(len,dtype,_key) in bufs.items() if name not in input_names+output_names]
-    cprog += [f"void net({forward_args}) {{"] + [f"{name}({', '.join(args)}, {thread_id});" for (name, args, _global_size, _local_size) in statements] + ["}"]
+    cprog += [f"void net({forward_args}) {{"] + [f"{name}({', '.join(args)});" for (name, args, _global_size, _local_size) in statements] + ["}"]
    return '\n'.join(headers + cprog)
  else:
    if bufs_to_save:
@@ -6,14 +6,15 @@
 # Workgroup: 128 threads (arranged as 32x4 for coalesced memory access)
 # Inner loop: 8 iterations per K-block, processing 8 columns of A and 8 rows of B
 #
-# Accumulators: 128 vgprs (v[2-117], v[120-124], v[126-129], v[131-133])
+# Accumulators: 128 vgprs (v[2-129])

 import numpy as np
 from pathlib import Path
 from tinygrad import Tensor, Device, Context, GlobalCounters
+from tinygrad.uop.ops import UOp, Ops, KernelInfo
 from tinygrad.helpers import getenv, colored
-from tinygrad.engine.realize import Runner, Estimates, ExecItem
-from extra.assembly.amd.dsl import s, v, VCC_LO, RawImm, EXEC_LO
+from tinygrad.engine.realize import Estimates
+from extra.assembly.amd.dsl import s, v, VCC_LO, NULL
 from extra.assembly.amd.autogen.rdna3.ins import *

 # =============================================================================
@@ -26,30 +27,25 @@ LDS_B_STRIDE = 0x200  # LDS stride for B tile (512 bytes)
 LDS_BASE_OFFSET = 0x1080  # Base LDS offset for tiles
 ADDR_MASK = 0x3fffff80    # Address alignment mask

-# s_waitcnt encodings: wait for memory operations to complete
-WAIT_LGKM = 64519    # wait for LDS/GDS/KMEM (lgkm_cnt=0)
-WAIT_ALL = 0         # wait for everything
-WAIT_VMEM = 1015     # wait for VMEM only (vm_cnt=0, lgkm_cnt=63)
-
 # =============================================================================
-# Named register assignments (VGPRs) - COMPACT LAYOUT
+# Named register assignments (VGPRs)
 # =============================================================================
-V_LANE_ID_MOD8 = 214      # lane_id & 7 (column within 8-wide tile chunk)
-V_OUTPUT_ROW = 131        # output row coordinate
-V_LANE_MOD8_X4 = 134      # V_LANE_ID_MOD8 << 2 (byte offset)
-V_LANE_DIV8_X4 = 135      # (lane_id >> 3) << 2
-V_ADDR_HI_ZERO = 136      # always 0 (for 64-bit address high bits)
-V_LDS_A_BASE = 133        # LDS A-tile base address for inner loop (in ACC_RESERVED gap)
-V_LDS_B_BASE = 130        # LDS B-tile base address for inner loop (in ACC_RESERVED gap)
-V_GLOBAL_A_ADDR = 131     # global memory A prefetch address (reuses V_OUTPUT_ROW slot during main loop)
-V_GLOBAL_B_ADDR = 154     # global memory B prefetch address
+V_LANE_ID = 0             # lane_id set on startup
+# Use tile gaps (v146-159) for named regs to minimize max VGPR
+V_LANE_ID_MOD8 = 146      # lane_id & 7
+V_LANE_MOD8_X4 = 147      # (lane_id & 7) << 2
+V_LANE_DIV8_X4 = 150      # ((lane_id >> 3) & 3) << 2
+V_LDS_B_BASE = 151        # LDS B-tile base address for inner loop
+V_LDS_A_BASE = 154        # LDS A-tile base address for inner loop
+V_GLOBAL_A_ADDR = 155     # global memory A prefetch address
+V_GLOBAL_B_ADDR = 158     # global memory B prefetch address
+V_LDS_A_ADDR = 159        # single base register for A stores
+V_LDS_B_ADDR = 162        # single base register for B stores

 # LDS tile register destinations - SEPARATE from DATA to avoid overlap
-# DATA regs (v155-170) receive global prefetch
 # A on banks 2-3, B on banks 0-1 to avoid bank conflicts in VOPD
-# This layout matches kernel8's optimization for VGPR cache utilization
-V_A_TILE_REGS = [186, 190, 194, 198]  # A tile: banks 2,2,2,2 (186%4=2, 190%4=2, etc.)
-V_B_TILE_REGS = [184, 188, 192, 196, 200, 204, 208, 212]  # B tile: banks 0,0,0,0,0,0,0,0
+V_A_TILE_REGS = [130, 134, 138, 142]  # A tile: banks 2,2,2,2 (130%4=2, etc.)
+V_B_TILE_REGS = [132, 136, 140, 144, 148, 152, 156, 160]  # B tile: banks 0,0,0,0,0,0,0,0

 # =============================================================================
 # Named register assignments (SGPRs)
@@ -59,14 +55,11 @@ S_TILE_X = 2              # workgroup_x << 7
 S_TILE_Y = 3              # workgroup_y << 7
 S_DIM_N = 4               # matrix dimension N
 S_LOOP_BOUND = 7          # K-8 (loop termination bound)
-S_A_PTR = (8, 9)          # A matrix base pointer
-S_B_PTR = (10, 11)        # B matrix base pointer
 S_LOOP_CTR = 12           # loop counter (increments by 8)
 S_PREFETCH_FLAG = 13      # prefetch condition flag / row stride in epilogue
 S_WORKGROUP_X = 14        # workgroup_id_x
 S_WORKGROUP_Y = 15        # workgroup_id_y
-# Kernarg load destinations (before copy to working regs)
-S_KERNARG_OUT = (16, 17)  # output pointer from kernarg
+# Kernarg load destinations
 S_KERNARG_A = (20, 21)    # A pointer from kernarg
 S_KERNARG_B = (22, 23)    # B pointer from kernarg
 # Prefetch base pointers (8 pairs each, 16KB/256KB apart)
@@ -101,8 +94,6 @@ FMAC_PAIR_ORDER = [

 def derive_fmac_pattern(acc_grid, a_tile_regs=None, b_tile_regs=None):
  """Generate 64 dual FMAC ops from accumulator grid with optimized iteration order."""
-  if a_tile_regs is None: a_tile_regs = V_A_TILE_REGS
-  if b_tile_regs is None: b_tile_regs = V_B_TILE_REGS
  pattern = []
  for idx, (a_pair, b_pair) in enumerate(FMAC_PAIR_ORDER):
    a_even, a_odd = a_pair * 2, a_pair * 2 + 1
@@ -121,14 +112,14 @@ def derive_fmac_pattern(acc_grid, a_tile_regs=None, b_tile_regs=None):
  return pattern

 # Derived: 64 dual FMAC operations
-FMAC_PATTERN = derive_fmac_pattern(ACC_GRID)
+FMAC_PATTERN = derive_fmac_pattern(ACC_GRID, V_A_TILE_REGS, V_B_TILE_REGS)

 def derive_permute_swaps(acc_grid, out_regs):
  """Derive swap sequence to permute accumulators from FMAC layout to output order.

  After FMAC loop: acc_grid[a][b] holds C[a,b]
  Output order: for row_half in 0,1; col_group in 0-3; row_in_group in 0-3; b_off in 0-3
-    -> need C[row_half*4 + row_in_group, col_group*4 + b_off] in descending reg order
+    -> need C[row_half*4 + row_in_group, col_group*4 + b_off] in specified reg order
  """
  def target_ab(i):
    row_half, col_group = i // 64, (i // 16) % 4
@@ -151,90 +142,69 @@ def derive_permute_swaps(acc_grid, out_regs):
  return swaps

 # Derived: swap sequence to arrange accumulators for output
-OUT_REGS = list(range(129, 1, -1))
+# Each group of 4 registers is ascending for direct global_store_b128
+OUT_REGS = [r for i in range(32) for r in range(126 - i*4, 130 - i*4)]
 PERMUTE_SWAPS = derive_permute_swaps(ACC_GRID, OUT_REGS)

 # =============================================================================
-# LDS tile staging registers - COMPACT LAYOUT
+# LDS tile staging registers
 # =============================================================================
 # DATA regs receive contiguous global prefetch, then write to LDS
 # TILE regs receive scattered LDS loads (ds_load_b64 pairs), then feed FMACs
-# These are SEPARATE - DATA lives during prefetch/store, TILE lives during inner loop
-V_LDS_A_ADDR = 153                            # single base register for A stores (use +512 offsets)
-V_LDS_A_DATA = list(range(155, 163))          # 8 data registers for A prefetch (v155-162)
-V_LDS_B_ADDR = 145                            # single base register for B stores (use 16-bit offsets)
-V_LDS_B_DATA = list(range(163, 171))          # 8 data registers for B prefetch (v163-170)
+# Contiguous layout with mod4=[3,0,1,2,3,0,1,2] for bank conflict avoidance
+V_LDS_A_DATA = [163, 164, 165, 166, 167, 168, 169, 170]
+V_LDS_B_DATA = [171, 172, 173, 174, 175, 176, 177, 178]
+
+# Initial tile prefetch: (vdst, saddr_lo) - load into A data regs using B prefetch pointers (s[24:31])
+INIT_PREFETCH = [(V_LDS_A_DATA[i], S_PREFETCH_B+2*i) for i in range(4)]

 # Global memory prefetch schedule: (vdst1, vdst2, addr_vreg, saddr_lo1, saddr_lo2)
 # First 2 pairs from B prefetch pointers (s[32:39]), next 4 pairs from A prefetch pointers (s[40:55])
 PREFETCH_LOADS = [(V_LDS_A_DATA[4+2*i], V_LDS_A_DATA[4+2*i+1], V_GLOBAL_B_ADDR, S_PREFETCH_B+8+4*i, S_PREFETCH_B+10+4*i) for i in range(2)] + \
                 [(V_LDS_B_DATA[2*(i-2)], V_LDS_B_DATA[2*(i-2)+1], V_GLOBAL_A_ADDR, S_PREFETCH_A+4*(i-2), S_PREFETCH_A+2+4*(i-2)) for i in range(2, 6)]

-# Initial tile prefetch: (vdst, saddr_lo) - load into A data regs using B prefetch pointers (s[24:31])
-INIT_PREFETCH = [(V_LDS_A_DATA[i], S_PREFETCH_B+2*i) for i in range(4)]
-
-# Initial tile loads: (vdst, addr_lo) pairs - use temp regs in accumulator gaps
-INIT_TILE_LOADS = [(23,5),(24,9),(25,7),(26,2),(27,11),(28,13),(29,6),(30,8),(31,10),(12,12),(13,14),(3,2),(4,4),(5,8),(6,6),(7,10)]
-
-# A matrix row offset registers (scattered to avoid accumulator conflicts)
-ROW_REGS = list(range(137, 145))  # v137-v144 (8 regs)
-
 # =============================================================================
 # Kernel class
 # =============================================================================

 class Kernel:
-  def __init__(self, arch='gfx1100'):
-    self.instructions, self.labels, self.branch_targets, self.arch = [], {}, {}, arch
+  def __init__(self, arch='gfx1100'): self.instructions, self.labels, self.pos, self.arch = [], {}, 0, arch
+  def label(self, name): self.labels[name] = self.pos

-  def emit(self, inst): self.instructions.append(inst); return inst
-  def label(self, name): self.labels[name] = len(self.instructions)
-  def branch_to(self, label): self.branch_targets[len(self.instructions) - 1] = label
-
-  def add64(self, dst_lo, dst_hi, src_lo, src_hi, off):
-    """s[dst_lo:dst_hi] = s[src_lo:src_hi] + off"""
-    if off: self.emit(s_add_u32(s[dst_lo], s[src_lo], off)); self.emit(s_addc_u32(s[dst_hi], s[src_hi], 0))
-    elif dst_lo != src_lo: self.emit(s_mov_b64(s[dst_lo:dst_hi], s[src_lo:src_hi]))
-
-  def global_load(self, vdst, addr, saddr=None):
-    """Global load b32"""
-    self.emit(global_load_b32(vdst=v[vdst], addr=v[addr:addr+1],
-              saddr=s[saddr:saddr+2] if saddr else RawImm(124)))
+  def emit(self, inst, target=None):
+    self.instructions.append(inst)
+    inst._target, inst._pos = target, self.pos
+    self.pos += inst.size()
+    return inst

  def waitcnt(self, lgkm=None, vm=None):
    """Wait for memory operations. lgkm=N waits until N lgkm ops remain, vm=N waits until N vmem ops remain."""
-    from extra.assembly.amd.asm import waitcnt as encode_waitcnt
-    if lgkm == 0 and vm is None: self.emit(s_waitcnt(simm16=WAIT_LGKM))
-    elif vm == 0 and lgkm is None: self.emit(s_waitcnt(simm16=WAIT_VMEM))
-    elif lgkm == 0 and vm == 0: self.emit(s_waitcnt(simm16=WAIT_ALL))
-    elif vm is not None and lgkm is None:
-      self.emit(s_waitcnt(simm16=encode_waitcnt(vmcnt=vm, expcnt=7, lgkmcnt=63)))
-    elif lgkm is not None and vm is None:
-      self.emit(s_waitcnt(simm16=encode_waitcnt(vmcnt=63, expcnt=7, lgkmcnt=lgkm)))
-    else: raise ValueError(f"unsupported waitcnt: lgkm={lgkm}, vm={vm}")
-
-  def barrier(self): self.emit(s_barrier())
+    vmcnt, lgkmcnt, expcnt = vm if vm is not None else 63, lgkm if lgkm is not None else 63, 7
+    waitcnt = (expcnt & 0x7) | ((lgkmcnt & 0x3f) << 4) | ((vmcnt & 0x3f) << 10)
+    self.emit(s_waitcnt(simm16=waitcnt))

  def to_asm(self):
-    import re
-    # Instruction stream with labels
-    label_at = {pos: name for name, pos in self.labels.items()}
-    body = []
-    for i, inst in enumerate(self.instructions):
-      if i in label_at: body.append(f'.{label_at[i]}:')
-      asm = inst.disasm()
-      if i in self.branch_targets:
-        asm = re.sub(r'(s_cbranch_\w+|s_branch)\s+\S+', rf'\1 .{self.branch_targets[i]}', asm)
-      body.append('\t' + asm)
+    # Patch branch offsets: simm16 = (target_pos - branch_end_pos) / 4
+    for inst in self.instructions:
+      if inst._target is None: continue
+      offset_dwords = (self.labels[inst._target] - inst._pos - inst.size()) // 4
+      if not -32768 <= offset_dwords <= 32767: raise ValueError(f"branch to '{inst._target}' offset {offset_dwords} exceeds simm16 range")
+      inst.simm16 = offset_dwords
+
+    # TODO: replace this with direct ELF
+    body = ['\t' + inst.disasm() for inst in self.instructions]
+
+    # limit wave occupancy by using more LDS
+    lds_size = max(LDS_SIZE, 65536//getenv("LIMIT_OCC", 65536))

    # HSA kernel descriptor attributes (zeros included for compatibility)
    hsa = [
-      ('group_segment_fixed_size', LDS_SIZE), ('private_segment_fixed_size', 0), ('kernarg_size', 36),
+      ('group_segment_fixed_size', lds_size), ('private_segment_fixed_size', 0), ('kernarg_size', 36),
      ('user_sgpr_count', 14), ('user_sgpr_dispatch_ptr', 0), ('user_sgpr_queue_ptr', 0),
      ('user_sgpr_kernarg_segment_ptr', 1), ('user_sgpr_dispatch_id', 0), ('user_sgpr_private_segment_size', 0),
      ('wavefront_size32', 1), ('uses_dynamic_stack', 0), ('enable_private_segment', 0),
      ('system_sgpr_workgroup_id_x', 1), ('system_sgpr_workgroup_id_y', 1), ('system_sgpr_workgroup_id_z', 0),
-      ('system_sgpr_workgroup_info', 0), ('system_vgpr_workitem_id', 0), ('next_free_vgpr', 214),
+      ('system_sgpr_workgroup_info', 0), ('system_vgpr_workitem_id', 0), ('next_free_vgpr', 179),
      ('next_free_sgpr', 16), ('float_round_mode_32', 0), ('float_round_mode_16_64', 0),
      ('float_denorm_mode_32', 3), ('float_denorm_mode_16_64', 3), ('dx10_clamp', 1), ('ieee_mode', 1),
      ('fp16_overflow', 0), ('workgroup_processor_mode', 0), ('memory_ordered', 1), ('forward_progress', 0),
@@ -249,10 +219,10 @@ class Kernel:
      '\t.end_amdhsa_kernel', '\t.text', '.Lfunc_end0:', '\t.size\tkernel, .Lfunc_end0-kernel',
      '\t.amdgpu_metadata', '---', 'amdhsa.kernels:', '  - .args:',
      *[f'      - .address_space: global\n        .offset: {i*8}\n        .size: 8\n        .value_kind: global_buffer' for i in range(3)],
-      f'    .group_segment_fixed_size: {LDS_SIZE}', '    .kernarg_segment_align: 8',
+      f'    .group_segment_fixed_size: {lds_size}', '    .kernarg_segment_align: 8',
      '    .kernarg_segment_size: 24', '    .max_flat_workgroup_size: 128', '    .name: kernel',
      '    .private_segment_fixed_size: 0', '    .sgpr_count: 60', '    .symbol: kernel.kd',
-      '    .vgpr_count: 214', '    .wavefront_size: 32', f'amdhsa.target: amdgcn-amd-amdhsa--{self.arch}',
+      '    .vgpr_count: 179', '    .wavefront_size: 32', f'amdhsa.target: amdgcn-amd-amdhsa--{self.arch}',
      'amdhsa.version:', '  - 1', '  - 2', '...', '\t.end_amdgpu_metadata'])


@@ -266,173 +236,87 @@ def build_kernel(arch='gfx1100'):
  # ===========================================================================
  # PROLOGUE: Load kernel arguments, compute tile coordinates and addresses
  # ===========================================================================
-  k.emit(s_load_b128(sdata=s[S_KERNARG_A[0]:S_KERNARG_B[1]], sbase=s[0:1], offset=0x0, soffset=RawImm(124)))
-  k.emit(s_load_b64(sdata=s[S_KERNARG_OUT[0]:S_KERNARG_OUT[1]], sbase=s[0:1], offset=0x10, soffset=RawImm(124)))
+  k.emit(s_load_b128(sdata=s[S_KERNARG_A[0]:S_KERNARG_B[1]], sbase=s[0:1], offset=0x0, soffset=NULL))
+  k.emit(s_load_b64(sdata=s[S_OUT_PTR[0]:S_OUT_PTR[1]], sbase=s[0:1], offset=0x10, soffset=NULL))
  k.emit(s_mov_b32(s[S_DIM_N], MATRIX_DIM))
  k.emit(s_mov_b32(s[S_LOOP_CTR], 0))  # used by LDS swizzle, always 0 for valid workgroups
  k.emit(s_lshl_b32(s[S_TILE_X], s[S_WORKGROUP_X], 7))
  k.emit(s_lshl_b32(s[S_TILE_Y], s[S_WORKGROUP_Y], 7))

  # Lane-derived values
-  k.emit(v_and_b32_e32(v[V_LANE_ID_MOD8], 7, v[0]))
-  k.emit(v_lshrrev_b32_e32(v[4], 3, v[0]))
-  k.emit(v_or_b32_e32(v[1], s[S_TILE_X], v[0]))
+  k.emit(v_and_b32_e32(v[V_LANE_ID_MOD8], 7, v[V_LANE_ID]))
+  k.emit(v_lshrrev_b32_e32(v[4], 3, v[V_LANE_ID]))
+  k.emit(v_or_b32_e32(v[1], s[S_TILE_X], v[V_LANE_ID]))
  k.emit(v_or_b32_e32(v[22], s[S_TILE_Y], v[4]))
  k.emit(v_lshlrev_b32_e32(v[V_LANE_MOD8_X4], 2, v[V_LANE_ID_MOD8]))
-  k.emit(v_mov_b32_e32(v[2], 0))  # v[1] always positive, sign extension is 0
-  k.emit(v_lshlrev_b64(v[5:6], 2, v[1:2]))
  k.waitcnt(lgkm=0)

-  # Copy pointers to working registers
-  k.emit(s_mov_b64(s[S_OUT_PTR[0]:S_OUT_PTR[1]], s[S_KERNARG_OUT[0]:S_KERNARG_OUT[1]]))
-  k.emit(s_mov_b64(s[S_A_PTR[0]:S_A_PTR[1]], s[S_KERNARG_A[0]:S_KERNARG_A[1]]))
-  k.emit(s_mov_b64(s[S_B_PTR[0]:S_B_PTR[1]], s[S_KERNARG_B[0]:S_KERNARG_B[1]]))
-
  # Compute 8 A and B matrix tile base pointers for prefetch
-  for i in range(8): k.add64(S_PREFETCH_B + i*2, S_PREFETCH_B + i*2 + 1, S_KERNARG_B[0], S_KERNARG_B[1], i * 0x4000)   # B: 16KB apart
-  for i in range(8): k.add64(S_PREFETCH_A + i*2, S_PREFETCH_A + i*2 + 1, S_KERNARG_A[0], S_KERNARG_A[1], i * 0x40000)  # A: 256KB apart
+  k.emit(s_mov_b64(s[S_PREFETCH_B:S_PREFETCH_B+1], s[S_KERNARG_B[0]:S_KERNARG_B[1]]))  # B[0]: no offset
+  for i in range(1, 8):  # B: 16KB apart
+    k.emit(s_add_u32(s[S_PREFETCH_B+i*2], s[S_KERNARG_B[0]], i * 0x4000))
+    k.emit(s_addc_u32(s[S_PREFETCH_B+i*2+1], s[S_KERNARG_B[1]], 0))
+  k.emit(s_mov_b64(s[S_PREFETCH_A:S_PREFETCH_A+1], s[S_KERNARG_A[0]:S_KERNARG_A[1]]))  # A[0]: no offset
+  for i in range(1, 8):  # A: 256KB apart
+    k.emit(s_add_u32(s[S_PREFETCH_A+i*2], s[S_KERNARG_A[0]], i * 0x40000))
+    k.emit(s_addc_u32(s[S_PREFETCH_A+i*2+1], s[S_KERNARG_A[1]], 0))

  # Global prefetch addresses: B = (tile_x + lane_id) * 4, A = ((tile_y << 12) + (lane_id/8)*4K + lane_id%8) * 4
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_B_ADDR], s[S_TILE_X], v[0]))
+  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_B_ADDR], s[S_TILE_X], v[V_LANE_ID]))
  k.emit(v_lshlrev_b32_e32(v[V_GLOBAL_B_ADDR], 2, v[V_GLOBAL_B_ADDR]))
  k.emit(s_lshl_b32(s[19], s[S_TILE_Y], 12))
  k.emit(v_lshl_add_u32(v[V_GLOBAL_A_ADDR], v[4], 12, v[V_LANE_ID_MOD8]))  # (lane_id/8)*4K + lane_id%8
  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_A_ADDR], s[19], v[V_GLOBAL_A_ADDR]))
  k.emit(v_lshlrev_b32_e32(v[V_GLOBAL_A_ADDR], 2, v[V_GLOBAL_A_ADDR]))

-  # ===========================================================================
-  # Tile address computation for initial A/B matrix loads
-  # ===========================================================================
-  k.emit(s_lshl_b32(s[S_LOOP_BOUND], s[S_DIM_N], 4))  # row stride = 16*N
-  k.emit(v_mul_lo_u32(v[ROW_REGS[0]], v[22], s[S_DIM_N]))  # A matrix row offsets
-  for i in range(1, 8): k.emit(v_add_nc_u32_e32(v[ROW_REGS[i]], s[S_LOOP_BOUND], v[ROW_REGS[i-1]]))
-
-  def addr64(dst, base_s):  # 64-bit address: v[dst:dst+1] = s[base_s:base_s+1] + v[dst]*4
-    k.emit(v_mov_b32_e32(v[dst+1], 0))  # offset always positive, sign ext = 0
-    k.emit(v_lshlrev_b64(v[dst:dst+1], 2, v[dst:dst+1]))
-    k.emit(v_add_co_u32(v[dst], VCC_LO, s[base_s], v[dst]))
-    k.emit(v_add_co_ci_u32_e32(v[dst+1], s[base_s+1], v[dst+1]))
-
-  def b_addr(dst, mult, tmp=None):  # B address for col + mult*N
-    tmp = tmp if tmp is not None else dst
-    k.emit(v_mad_u32_u24(v[tmp], s[S_DIM_N], mult, v[1]))
-    if tmp != dst:
-      k.emit(v_mov_b32_e32(v[tmp+1], 0))  # offset always positive
-      k.emit(v_lshlrev_b64(v[dst:dst+1], 2, v[tmp:tmp+1]))
-      k.emit(v_add_co_u32(v[dst], VCC_LO, s[S_B_PTR[0]], v[dst]))
-      k.emit(v_add_co_ci_u32_e32(v[dst+1], s[S_B_PTR[1]], v[dst+1]))
-    else: addr64(dst, S_B_PTR[0])
-
-  def a_addr(dst, row_reg, tmp):  # A address for row_reg + lane_id_mod8
-    k.emit(v_add_nc_u32_e32(v[tmp], v[row_reg], v[V_LANE_ID_MOD8]))
-    k.emit(v_mov_b32_e32(v[tmp+1], 0))  # offset always positive
-    k.emit(v_lshlrev_b64(v[dst:dst+1], 2, v[tmp:tmp+1]))
-    k.emit(v_add_co_u32(v[dst], VCC_LO, s[S_A_PTR[0]], v[dst]))
-    k.emit(v_add_co_ci_u32_e32(v[dst+1], s[S_A_PTR[1]], v[dst+1]))
-
-  # Batch 1: B addresses (cols 0-5) and loads
-  k.emit(v_add_co_u32(v[5], VCC_LO, s[S_B_PTR[0]], v[5]))
-  k.emit(v_add_co_ci_u32_e32(v[6], s[S_B_PTR[1]], v[6]))
-  for dst, mult in [(9,1), (7,2), (2,3), (11,4), (13,5)]: b_addr(dst, mult)
-  k.emit(s_clause(simm16=5))  # 6 consecutive global loads
-  for vdst, addr in INIT_TILE_LOADS[:6]: k.global_load(vdst, addr)
-
-  # Batch 2: A addresses (rows 0-4) and loads
-  for dst, ri in [(6,0), (8,1), (10,2), (12,3), (14,4)]:
-    k.emit(v_add_nc_u32_e32(v[dst], v[ROW_REGS[ri]], v[V_LANE_ID_MOD8]))
-    addr64(dst, S_A_PTR[0])
-  k.emit(s_clause(simm16=4))  # 5 consecutive global loads
-  for vdst, addr in INIT_TILE_LOADS[6:11]: k.global_load(vdst, addr)
-
-  # Batch 3: B cols 6-7, A rows 5-7, and loads
-  for dst, mult, tmp in [(2,6,15), (4,7,4)]: b_addr(dst, mult, tmp)
-  for dst, ri, tmp in [(8,5,16), (6,6,18), (10,7,20)]: a_addr(dst, ROW_REGS[ri], tmp)
-  k.emit(s_clause(simm16=4))  # 5 consecutive global loads
-  for vdst, addr in INIT_TILE_LOADS[11:]: k.global_load(vdst, addr)
+  # Do initial loads
+  for vdst, saddr_lo in INIT_PREFETCH:
+    k.emit(global_load_b32(vdst=v[vdst], addr=v[V_GLOBAL_B_ADDR], saddr=s[saddr_lo:saddr_lo+1]))
+  for iter in range(6):
+    vdst1, vdst2, addr, slo1, slo2 = PREFETCH_LOADS[iter]
+    k.emit(global_load_b32(vdst=v[vdst1], addr=v[addr], saddr=s[slo1:slo1+1]))
+    k.emit(global_load_b32(vdst=v[vdst2], addr=v[addr], saddr=s[slo2:slo2+1]))

  # ===========================================================================
  # LDS store address computation (bank-conflict-avoiding swizzle)
  # ===========================================================================
  # This section computes LDS store addresses with a swizzle pattern to avoid bank conflicts.
-  # Key outputs:
-  #   v[8]: A-tile initial store base (used only for initial stores with stride64)
-  #   V_LDS_B_ADDR (v145): B-tile store base (used for both initial and main loop)
-  #   V_LANE_DIV8_X4 (v135): (lane_id >> 3) << 2 for epilogue
-  #
  # The swizzle ensures that threads in the same wavefront write to different LDS banks.
  # Formula: swizzled_addr = base + (lane_id & 7) * LDS_A_STRIDE + swizzle_offset
  # where swizzle_offset depends on (lane_id >> 3) to distribute across banks.
-
-  # v[22] = tile_y | (lane_id >> 3) from prologue, used as base for row offsets
-  # Compute 7 row offsets for B-tile rows 1-7 (row 0 computed separately in v[9])
-  k.emit(v_add_nc_u32_e32(v[9], s[S_LOOP_CTR], v[22]))  # row 0 base (S_LOOP_CTR=0)
-  for i in range(7): k.emit(v_or_b32_e32(v[10 + i if i < 2 else 12 + i], 16 * (i + 1), v[22]))  # rows 1-7
-
-  # Extract sign bit of workgroup_x (always 0 for valid workgroups, used for masking)
-  k.emit(s_bfe_i32(s[S_LOOP_BOUND], s[S_WORKGROUP_X], 0x10018))
+  k.emit(v_add_nc_u32_e32(v[9], s[S_LOOP_CTR], v[22]))  # row 0 base
  k.emit(v_and_b32_e32(v[9], ADDR_MASK, v[9]))
-  k.emit(s_lshr_b32(s[S_LOOP_BOUND], s[S_LOOP_BOUND], 25))
-
-  # Compute masked row offsets for bank conflict avoidance pattern
-  # Pattern: v[row] = row_val - (row_val & ADDR_MASK) extracts lower bits
-  k.emit(v_add_nc_u32_e32(v[19], s[S_LOOP_CTR], v[10]))
-  k.emit(v_add_nc_u32_e32(v[8], s[S_LOOP_BOUND], v[1]))  # A-tile base computation
-  for d, r in zip([20, 21, 32, 33, 34, 35], [11, 14, 15, 16, 17, 18]):
-    k.emit(v_add_nc_u32_e32(v[d], s[S_LOOP_CTR], v[r]))
-  k.emit(v_and_b32_e32(v[8], ADDR_MASK, v[8]))
  k.emit(v_sub_nc_u32_e32(v[9], v[22], v[9]))  # row 0 swizzle offset
-  for d, s_ in zip([19, 20, 21, 22, 32, 33, 34], [20, 21, 22, 32, 33, 34, 35]):
-    k.emit(v_and_b32_e32(v[d], ADDR_MASK, v[s_]))
-  k.emit(v_sub_nc_u32_e32(v[8], v[1], v[8]))  # A-tile swizzle
-
-  # Apply swizzle offsets and scale to byte offsets
-  k.emit(v_lshlrev_b32_e32(v[9], 2, v[9]))  # row 0 offset * 4
-  for r, t in zip([10, 11, 14, 15, 16, 17, 18], [19, 20, 21, 22, 32, 33, 34]):
-    k.emit(v_sub_nc_u32_e32(v[r], v[r], v[t]))  # rows 1-7 swizzle
-  k.emit(v_bfe_u32(v[2], v[0], 3, 2))  # v[2] = (lane_id >> 3) & 3
-  k.emit(v_lshlrev_b32_e32(v[8], 2, v[8]))  # A-tile base * 4
-
-  # Compute B-tile base address: LDS_A_STRIDE * (lane_id % 8) + row0_offset
+  k.emit(v_lshlrev_b32_e32(v[9], 2, v[9]))  # * 4
  k.emit(v_mad_u32_u24(v[V_LDS_B_ADDR], LDS_A_STRIDE, v[V_LANE_ID_MOD8], v[9]))
-  # Scale row offsets 1-7 to byte offsets (row 0 already in v[9])
-  for d, r in zip([9, 10, 11, 14, 15, 16, 17], [10, 11, 14, 15, 16, 17, 18]):
-    k.emit(v_lshlrev_b32_e32(v[d], 2, v[r]))
+
+  # For V_LDS_A_BASE and epilogue
+  k.emit(v_bfe_u32(v[2], v[V_LANE_ID], 3, 2))  # v[2] = (lane_id >> 3) & 3
  k.emit(v_lshlrev_b32_e32(v[V_LANE_DIV8_X4], 2, v[2]))
-  k.emit(v_add_nc_u32_e32(v[8], 0x80, v[8]))  # A-tile initial store base + 128

-  # Store initial tile data to LDS
-  k.waitcnt(vm=0)
-  for i, (d0, d1) in enumerate([(0,1), (2,3), (4,5), (11,12)]):
-    k.emit(ds_store_2addr_stride64_b32(addr=v[8], data0=v[INIT_TILE_LOADS[d0][0]], data1=v[INIT_TILE_LOADS[d1][0]], offset0=16+i*4, offset1=18+i*4))
-  # B stores: single base with offsets 0,64,128,192,256,320,384,448
-  for i, idx in enumerate([6,7,8,9,10,13,14,15]):
-    offset = i * 64
-    k.emit(ds_store_b32(addr=v[V_LDS_B_ADDR], data0=v[INIT_TILE_LOADS[idx][0]], offset0=offset & 0xFF, offset1=offset >> 8))
-  k.waitcnt(lgkm=0)
-  k.barrier()
-
-  # ===========================================================================
-  # INIT: Compute LDS base addresses, then zero accumulators
-  # ===========================================================================
-  # v[3] = v[1] & 0x7F (lower 7 bits) since S_LOOP_BOUND=0 for valid workgroups
+  # Compute LDS load/store base addresses for inner loop
  k.emit(v_lshlrev_b32_e32(v[2], 4, v[2]))
-  k.emit(v_add_nc_u32_e32(v[3], s[S_LOOP_BOUND], v[1]))
-  k.emit(v_and_b32_e32(v[3], ADDR_MASK, v[3]))
-  k.emit(v_sub_nc_u32_e32(v[3], v[1], v[3]))
+  k.emit(v_and_b32_e32(v[3], 0x7F, v[1]))  # simplified from 3 lines
  k.emit(v_lshl_or_b32(v[V_LDS_B_BASE], v[V_LANE_ID_MOD8], 4, LDS_BASE_OFFSET))
  k.emit(v_lshl_add_u32(v[V_LDS_A_ADDR], v[3], 2, LDS_BASE_OFFSET))
-  k.emit(v_lshlrev_b32_e32(v[3], 2, v[0]))
+  k.emit(v_lshlrev_b32_e32(v[3], 2, v[V_LANE_ID]))
  k.emit(v_and_or_b32(v[V_LDS_A_BASE], 0x180, v[3], v[2]))

+  # Do initial stores
+  k.waitcnt(vm=0)
+  for i in range(4):  # A tile: 8 values via 4 stride64 stores
+    k.emit(ds_store_2addr_stride64_b32(addr=v[V_LDS_A_ADDR], data0=v[V_LDS_A_DATA[i*2]], data1=v[V_LDS_A_DATA[i*2+1]], offset0=i*4, offset1=i*4+2))
+  for i in range(8):  # B tile: 8 values via 8 scalar stores with 64-byte spacing
+    offset = i * 64
+    k.emit(ds_store_b32(addr=v[V_LDS_B_ADDR], data0=v[V_LDS_B_DATA[i]], offset0=offset & 0xFF, offset1=offset >> 8))
+
  # Zero all 128 accumulators using VOPD dual moves (64 instructions instead of 128)
  for i in range(0, len(OUT_REGS), 2):
    k.emit(VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32, vdstx=v[OUT_REGS[i]], vdsty=v[OUT_REGS[i+1]], srcx0=0, srcy0=0))
-
  k.emit(s_add_i32(s[S_LOOP_BOUND], s[S_DIM_N], -8))
-  k.emit(s_add_u32(s[S_A_PTR[0]], s[S_A_PTR[0]], 32))
-  k.emit(s_addc_u32(s[S_A_PTR[1]], s[S_A_PTR[1]], 0))
+
  # S_LOOP_CTR is already 0 from prologue initialization
-  k.emit(s_branch(simm16=0)); k.branch_to('LOOP_ENTRY')
+  k.emit(s_branch(), target='LOOP_ENTRY')

  # ===========================================================================
  # MAIN GEMM LOOP
@@ -443,28 +327,43 @@ def build_kernel(arch='gfx1100'):
  k.label('LOOP_INC')
  k.emit(s_add_i32(s[S_LOOP_CTR], s[S_LOOP_CTR], 8))
  k.emit(s_cmp_ge_i32(s[S_LOOP_CTR], s[S_DIM_N]))
-  k.emit(s_cbranch_scc1(simm16=0)); k.branch_to('EPILOGUE')
+  k.emit(s_cbranch_scc1(), target='EPILOGUE')

  k.label('LOOP_ENTRY')
  k.emit(s_cmp_lt_i32(s[S_LOOP_CTR], s[S_LOOP_BOUND]))
  k.emit(s_cselect_b32(s[S_PREFETCH_FLAG], -1, 0))  # s_cselect doesn't modify SCC
-  k.emit(s_cbranch_scc0(simm16=0)); k.branch_to('SKIP_PREFETCH')  # branch if loop_ctr >= loop_bound
-
-  # Advance prefetch pointers
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_B_ADDR], 0x20000, v[V_GLOBAL_B_ADDR]))
-  k.emit(v_add_nc_u32_e32(v[V_GLOBAL_A_ADDR], 0x20, v[V_GLOBAL_A_ADDR]))
+  k.emit(s_cbranch_scc0(), target='SKIP_PREFETCH')  # branch if loop_ctr >= loop_bound

  if not NO_GLOBAL:
+    # Advance prefetch pointers (VGPR)
+    #k.emit(v_add_nc_u32_e32(v[V_GLOBAL_B_ADDR], 0x20000, v[V_GLOBAL_B_ADDR]))
+    #k.emit(v_add_nc_u32_e32(v[V_GLOBAL_A_ADDR], 0x20, v[V_GLOBAL_A_ADDR]))
+
+    # Advance prefetch pointers (64-bit adds)
+    k.emit(s_clause(simm16=31))
+    for i in range(8):
+      k.emit(s_add_u32(s[S_PREFETCH_B+i*2], s[S_PREFETCH_B+i*2], 0x20000))
+      k.emit(s_addc_u32(s[S_PREFETCH_B+i*2+1], s[S_PREFETCH_B+i*2+1], 0))
+    for i in range(8):
+      k.emit(s_add_u32(s[S_PREFETCH_A+i*2], s[S_PREFETCH_A+i*2], 0x20))
+      k.emit(s_addc_u32(s[S_PREFETCH_A+i*2+1], s[S_PREFETCH_A+i*2+1], 0))
+
+    # do the fetch
    for vdst, saddr_lo in INIT_PREFETCH:
-      k.global_load(vdst, V_GLOBAL_B_ADDR, saddr_lo)
+      k.emit(global_load_b32(vdst=v[vdst], addr=v[V_GLOBAL_B_ADDR], saddr=s[saddr_lo:saddr_lo+1]))

  k.label('SKIP_PREFETCH')

+  # wait for local stores to finish (either initial or loop)
+  # then sync the warp so it's safe to load local
+  k.waitcnt(lgkm=0)
+  k.emit(s_barrier())
+
  # 8 inner loop iterations
  for iter in range(8):
    # Load A tile (4 pairs) and B tile (8 pairs) from LDS
    if not NO_DS:
-      k.emit(s_clause(simm16=11))  # 12 loads total: 4 A + 8 B
+      k.emit(s_clause(simm16=len(V_A_TILE_REGS) + len(V_B_TILE_REGS) - 1))  # 12 loads total: 4 A + 8 B
      # A tile: 4 ds_load_b64
      for i, vdst in enumerate(V_A_TILE_REGS):
        a_off = (i & 1) * 8 + (i >> 1) * 64 + iter * LDS_A_STRIDE
@@ -473,39 +372,38 @@ def build_kernel(arch='gfx1100'):
      for i, vdst in enumerate(V_B_TILE_REGS):
        b_off = (i & 1) * 8 + (i & 2) * 64 + (i >> 2) * 256 + iter * LDS_B_STRIDE
        k.emit(ds_load_b64(vdst=v[vdst:vdst+1], addr=v[V_LDS_B_BASE], offset0=b_off & 0xFF, offset1=b_off >> 8))
-      k.waitcnt(lgkm=0)
+
+    # Issue global prefetch (first 6 iterations only)
+    if iter < 6 and not NO_GLOBAL:
+      vdst1, vdst2, addr, slo1, slo2 = PREFETCH_LOADS[iter]
+      k.emit(global_load_b32(vdst=v[vdst1], addr=v[addr], saddr=s[slo1:slo1+1]))
+      k.emit(global_load_b32(vdst=v[vdst2], addr=v[addr], saddr=s[slo2:slo2+1]))

    # 64 dual FMACs
-    k.emit(s_clause(simm16=63))
+    k.waitcnt(lgkm=0)
+    k.emit(s_clause(simm16=len(FMAC_PATTERN)-1))
    for i, (vdst_x, vdst_y, ax, bx, ay, by) in enumerate(FMAC_PATTERN):
      k.emit(VOPD(VOPDOp.V_DUAL_FMAC_F32, VOPDOp.V_DUAL_FMAC_F32,
                  vdstx=v[vdst_x], vdsty=v[vdst_y], srcx0=v[ax], vsrcx1=v[bx], srcy0=v[ay], vsrcy1=v[by]))

-    # Issue global prefetch AFTER FMACs (first 6 iterations only)
-    if iter < 6 and not NO_GLOBAL:
-      vdst1, vdst2, addr, slo1, slo2 = PREFETCH_LOADS[iter]
-      k.global_load(vdst1, addr, slo1)
-      k.global_load(vdst2, addr, slo2)
-
-  k.emit(s_and_not1_b32(VCC_LO, EXEC_LO, s[S_PREFETCH_FLAG]))
+  # wait for all global loads to finish
+  # then sync the warp so it's safe to store local
  k.waitcnt(vm=0)
-  k.barrier()
-  k.emit(s_cbranch_vccnz(simm16=0)); k.branch_to('LOOP_INC')
+  k.emit(s_barrier())

  # Store prefetched data to LDS
  # NOTE: Register naming reflects LDS tile organization, not source matrix:
  #   V_LDS_A_DATA (v155-162) holds data that goes to LDS A-tile region
  #   V_LDS_B_DATA (v163-170) holds data that goes to LDS B-tile region
  # The data sources are swapped: A-tile receives B matrix rows, B-tile receives A matrix columns
-  for i in range(4):  # A tile: 8 values via 4 stride64 stores
-    k.emit(ds_store_2addr_stride64_b32(addr=v[V_LDS_A_ADDR], data0=v[V_LDS_A_DATA[i*2]], data1=v[V_LDS_A_DATA[i*2+1]], offset0=i*4, offset1=i*4+2))
-  for i in range(8):  # B tile: 8 values via 8 scalar stores with 64-byte spacing
-    offset = i * 64
-    k.emit(ds_store_b32(addr=v[V_LDS_B_ADDR], data0=v[V_LDS_B_DATA[i]], offset0=offset & 0xFF, offset1=offset >> 8))
+  if not NO_DS:
+    for i in range(4):  # A tile: 8 values via 4 stride64 stores
+      k.emit(ds_store_2addr_stride64_b32(addr=v[V_LDS_A_ADDR], data0=v[V_LDS_A_DATA[i*2]], data1=v[V_LDS_A_DATA[i*2+1]], offset0=i*4, offset1=i*4+2))
+    for i in range(8):  # B tile: 8 values via 8 scalar stores with 64-byte spacing
+      offset = i * 64
+      k.emit(ds_store_b32(addr=v[V_LDS_B_ADDR], data0=v[V_LDS_B_DATA[i]], offset0=offset & 0xFF, offset1=offset >> 8))

-  k.waitcnt(lgkm=0)
-  k.barrier()
-  k.emit(s_branch(simm16=0)); k.branch_to('LOOP_INC')
+  k.emit(s_branch(), target='LOOP_INC')

  # ===========================================================================
  # EPILOGUE: Permute and store results
@@ -516,56 +414,49 @@ def build_kernel(arch='gfx1100'):
  for a, b in PERMUTE_SWAPS:
    k.emit(v_swap_b32_e32(v[a], v[b]))

-  # Compute output coordinates: v[V_LANE_ID_MOD8] = col, v[V_OUTPUT_ROW] = row
-  k.emit(VOPD(VOPDOp.V_DUAL_MOV_B32, VOPDOp.V_DUAL_MOV_B32,
-              vdstx=v[149], vdsty=v[150], srcx0=v[V_LANE_MOD8_X4], vsrcx1=v[0], srcy0=v[V_LANE_DIV8_X4], vsrcy1=v[0]))
-  k.emit(v_and_b32_e32(v[0], 0x60, v[0]))
-  k.emit(v_or_b32_e32(v[V_LANE_ID_MOD8], s[S_TILE_X], v[149]))
-  k.emit(v_add_nc_u32_e32(v[0], s[S_TILE_Y], v[0]))
-  k.emit(v_or_b32_e32(v[V_OUTPUT_ROW], v[0], v[150]))
+  # Compute output base coordinates
+  # v[130] = col_base = tile_x + (lane_id & 7) * 4
+  # v[131] = row_base = tile_y + (lane_id & 0x60) + ((lane_id >> 3) & 3) * 4
+  # v[132] = 0 (for 64-bit address high part)
+  k.emit(v_add_nc_u32_e32(v[130], s[S_TILE_X], v[V_LANE_MOD8_X4]))
+  k.emit(v_and_b32_e32(v[131], 0x60, v[V_LANE_ID]))
+  k.emit(v_add_nc_u32_e32(v[131], s[S_TILE_Y], v[131]))
+  k.emit(v_add_nc_u32_e32(v[131], v[V_LANE_DIV8_X4], v[131]))
+  k.emit(v_mov_b32_e32(v[132], 0))

-  # Precompute row offsets: v[144-147] for rows 0-3, v[148-151] for rows 16-19
-  for base, row_off in [(144, 0), (148, 16)]:
-    if row_off: k.emit(v_or_b32_e32(v[1], row_off, v[V_OUTPUT_ROW]))
-    k.emit(v_mul_lo_u32(v[base], v[1] if row_off else v[V_OUTPUT_ROW], s[S_DIM_N]))
-    for i in range(3): k.emit(v_add_nc_u32_e32(v[base + 1 + i], s[S_DIM_N], v[base + i]))
+  # Precompute row offsets: v[133-136] for rows 0-3, v[137-140] for rows 16-19
+  for base, row_off in [(133, 0), (137, 16)]:
+    if row_off: k.emit(v_add_nc_u32_e32(v[141], row_off, v[131]))
+    k.emit(v_mul_lo_u32(v[base], v[141] if row_off else v[131], s[S_DIM_N]))
+    for j in range(3): k.emit(v_add_nc_u32_e32(v[base + 1 + j], s[S_DIM_N], v[base + j]))

-  k.emit(v_mov_b32_e32(v[V_ADDR_HI_ZERO], 0))
-  k.emit(s_lshl_b32(s[S_PREFETCH_FLAG], s[S_DIM_N], 2))  # row stride in bytes
+  # s[S_PREFETCH_FLAG] = row stride in bytes (N * 4)
+  k.emit(s_lshl_b32(s[S_PREFETCH_FLAG], s[S_DIM_N], 2))

  # Store 128 output values as 32 groups of 4 (128-bit stores)
  # Layout: 2 row halves (0-3, 16-19) x 4 col groups x 4 rows = 32 stores of 4 floats
-  epilogue_reserved = {V_LANE_ID_MOD8, V_OUTPUT_ROW, V_LANE_MOD8_X4, V_LANE_DIV8_X4, V_ADDR_HI_ZERO}
-
  for i, (row_half, col_off, row_in_group) in enumerate([(rh, co, ri)
      for rh in range(2) for co in [0, 32, 64, 96] for ri in range(4)]):
    row = row_half * 16 + row_in_group
-    srcs = OUT_REGS[i*4:(i+1)*4]
+    src = OUT_REGS[i*4]  # first reg of ascending group of 4

-    # Find temp register for scaled values (must not conflict with reserved regs)
-    tmp = max(srcs) + 5
-    while any(r in epilogue_reserved for r in range(tmp, tmp + 4)): tmp += 1
+    if row_in_group == 0:
+      # First row of group: compute full address
+      if col_off == 0: k.emit(v_mov_b32_e32(v[141], v[130]))
+      else: k.emit(v_add_nc_u32_e32(v[141], col_off, v[130]))
+      row_base = 133 + row if row < 4 else 137 + row - 16
+      k.emit(v_add_nc_u32_e32(v[141], v[row_base], v[141]))
+      k.emit(v_lshlrev_b32_e32(v[141], 2, v[141]))
+      k.emit(v_add_co_u32(v[141], VCC_LO, s[S_OUT_PTR[0]], v[141]))
+      k.emit(v_add_co_ci_u32_e32(v[142], s[S_OUT_PTR[1]], v[132]))
+    else:
+      # Subsequent rows: add stride
+      k.emit(v_add_co_u32(v[141], VCC_LO, s[S_PREFETCH_FLAG], v[141]))
+      k.emit(v_add_co_ci_u32_e32(v[142], v[142], v[132]))

-    # Copy values to temp regs for output (alpha=1.0 hardcoded, so just move)
-    for j, src in enumerate(srcs):
-      k.emit(v_mov_b32_e32(v[tmp + j], v[src]))
+    k.emit(global_store_b128(addr=v[141:142], data=v[src:src+3], saddr=NULL))

-    # Compute output address
-    if row_in_group == 0:  # first row: compute base address for this column group
-      if col_off == 0: k.emit(v_mov_b32_e32(v[0], v[V_LANE_ID_MOD8]))
-      else: k.emit(v_add_nc_u32_e32(v[0], col_off, v[V_LANE_ID_MOD8]))
-      row_base = 144 + row if row < 4 else 148 + row - 16
-      k.emit(v_add_nc_u32_e32(v[0], v[row_base], v[0]))
-      k.emit(v_lshlrev_b32_e32(v[0], 2, v[0]))
-      k.emit(v_add_co_u32(v[0], VCC_LO, s[S_OUT_PTR[0]], v[0]))
-      k.emit(v_add_co_ci_u32_e32(v[1], s[S_OUT_PTR[1]], v[V_ADDR_HI_ZERO]))
-    else:  # subsequent rows: just add stride
-      k.emit(v_add_co_u32(v[0], VCC_LO, s[S_PREFETCH_FLAG], v[0]))
-      k.emit(v_add_co_ci_u32_e32(v[1], v[1], v[V_ADDR_HI_ZERO]))
-
-    k.emit(global_store_b128(addr=v[0:1], data=v[tmp:tmp+3], saddr=RawImm(124)))
-
-  k.emit(s_sendmsg(simm16=3))
+  k.emit(s_sendmsg(simm16=3))  # DEALLOC_VGPRS
  k.emit(s_endpgm())

  return k.to_asm()
@@ -580,7 +471,7 @@ THREADS = 128

 def test_matmul():
  dev = Device[Device.DEFAULT]
-  print(f"Device arch: {dev.arch}")
+  print(f"Device arch: {dev.renderer.arch}")

  if getenv("STOCK", 0):
    # Load the stock kernel from amd_seb/kernel8_batched_gmem.s
@@ -588,8 +479,7 @@ def test_matmul():
    asm = stock_path.read_text()
    print(f"Loaded stock kernel from {stock_path}")
  else:
-    asm = build_kernel(dev.arch)
-  if getenv("PRINT_ASM", 0): print(asm)
+    asm = build_kernel(dev.renderer.arch)

  binary = dev.compiler.compile(asm)
  print(f"Compiled! Binary size: {len(binary)} bytes")
@@ -603,15 +493,16 @@ def test_matmul():
  grid, local = (N // BLOCK_N, N // BLOCK_M, 1), (THREADS, 1, 1)
  print(f"Grid: {grid}, Local: {local}")

-  _prg = dev.runtime("kernel", binary)
-  class AsmRunner(Runner):
-    def __init__(self):
-      super().__init__(colored("kernel", "cyan"), Device.DEFAULT, Estimates(ops=N*N*N*2, mem=N*N*4*3))
-    def __call__(self, rawbufs, var_vals, wait=False):
-      c_buf, a_buf, b_buf = [x.ensure_allocated()._buf for x in rawbufs]
-      return _prg(a_buf, b_buf, c_buf, global_size=grid, local_size=local, wait=wait)
-
-  ei = ExecItem(None, [c.uop.buffer, a.uop.buffer, b.uop.buffer], prg=AsmRunner())
+  dname:str = Device.DEFAULT
+  def asm_kernel(A:UOp, B:UOp, C:UOp) -> UOp:
+    gidxs = [UOp.special(n, f"gidx{i}") for i,n in enumerate(grid)]
+    lidxs = [UOp.special(n, f"lidx{i}") for i,n in enumerate(local)]
+    sink = UOp.sink(A.base, B.base, C.base, *gidxs, *lidxs, arg=KernelInfo(name=colored("kernel", "cyan"),
+                                                                           estimates=Estimates(ops=N*N*N*2, mem=N*N*4*3)))
+    return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=dname), UOp(Ops.LINEAR, src=(*sink.src, sink)), UOp(Ops.SOURCE, arg=asm),
+                                 UOp(Ops.BINARY, arg=binary)))
+  c = Tensor.custom_kernel(a, b, c, fxn=asm_kernel)[2]
+  ei = c.schedule()[0].lower()

  ets = []
  with Context(DEBUG=2):
@@ -623,7 +514,7 @@ def test_matmul():
    with Context(DEBUG=2): tc = (a @ b).realize()
    with Context(DEBUG=0): err = (c - tc).square().mean().item()
    print(f"mean squared error {err}")
-    if err > 1e-06: raise RuntimeError("matmul is wrong!")
+    if err != err or err > 1e-06: raise RuntimeError("matmul is wrong!")

 def run_sqtt():
  """Run with SQTT profiling and write trace files."""
@@ -0,0 +1,96 @@
+import atexit, functools
+from tinygrad.runtime.support.compiler_amd import HIPCompiler
+from tinygrad import Tensor, Device, dtypes
+from tinygrad.uop.ops import UOp, Ops, KernelInfo, AxisType
+from tinygrad.renderer import Estimates
+from tinygrad.helpers import getenv, all_same, dedup
+from extra.gemm.asm.cdna.asm import build_kernel, GEMM_ARGS
+
+# ** CDNA4 assembly gemm
+
+WORKGROUP_SIZE = 256
+
+def custom_asm_gemm(C:UOp, A:UOp, B:UOp, dname:str, arch:str, wg:int) -> UOp:
+  batch, M, K = A.shape
+  K2, N = B.shape[(1 if B.ndim == 3 else 0):]
+  assert K == K2
+  lidx = UOp.special(WORKGROUP_SIZE, "lidx0")
+  gidx = UOp.special(wg, "gidx0")
+  k = build_kernel(batch, M, N, K, A.dtype.base)
+  sink = UOp.sink(C.base, A.base, B.base, lidx, gidx,
+                  arg=KernelInfo(name=k.name, estimates=Estimates(ops=2*batch*M*N*K, mem=(batch*M*K + K*N + batch*M*N)*2)))
+  binary = HIPCompiler(arch).compile(k.to_asm())
+  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=dname), UOp(Ops.LINEAR, src=(*sink.src, sink)),
+                               UOp(Ops.SOURCE, arg=k.to_text()), UOp(Ops.BINARY, arg=binary)))
+
+counters = {"used":0, "todos":[]}
+def todo(msg:str) -> bool: counters["todos"].append(msg); return False
+atexit.register(lambda: print(f'asm_gemm: {counters["used"]} used, {len(counters["todos"])} not used'))
+
+def can_use_asm_gemm(a:Tensor, b:Tensor) -> bool:
+  if a.dtype != b.dtype: return todo(f"dtypes must match {a.dtype} != {b.dtype}")
+  if a.dtype not in {dtypes.bfloat16, dtypes.float16}: return todo(f"only bfloat16/float16, got {a.dtype}")
+  # only sharding on the batch is tested, others might work too
+  if isinstance(a.device, tuple) and not (a.ndim == 3 and a.uop.axis == 0 and b.uop.axis is None):
+    return todo(f"sharding mismatch a.ndim={a.ndim} a.uop.axis={a.uop.axis} b.uop.axis={b.uop.axis}")
+  batch, M, K = (1, *a.shape) if a.ndim == 2 else a.shape
+  N = b.shape[1]
+  if isinstance(a.device, tuple):
+    batch //= len(a.device)
+    dname = a.device[0]
+  else: dname = a.device
+  arch = getattr(Device[dname].renderer, "arch", "")
+  if batch not in {1, 2}: return todo(f"GEMM batch size {batch}")
+  if (key:=(M, N, K)) not in GEMM_ARGS and arch == "gfx950": return todo(f"GEMM shape not supported {key} on {arch}")
+  return True
+
+# ** UOp gemm to test Tensor.custom_kernel multi and backward correctness on non cdna4
+# note: this can be removed after we have GEMM on mixins
+
+def custom_uop_gemm(C:UOp, A:UOp, B:UOp) -> UOp:
+  M, K = A.shape[0]*A.shape[1], A.shape[2]
+  K2, N = B.shape[(1 if B.ndim == 3 else 0):]
+  assert K == K2
+  m = UOp.range(M, 1, AxisType.LOOP)
+  n = UOp.range(N, 2, AxisType.LOOP)
+  k = UOp.range(K, 0, AxisType.REDUCE)
+  mul = (A.index((m*UOp.const(dtypes.index, K)+k))*B.index((k*UOp.const(dtypes.index, N)+n))).cast(dtypes.float32)
+  red = mul.reduce(k, arg=Ops.ADD, dtype=dtypes.float32).cast(C.dtype.base)
+  store = C.index((m*UOp.const(dtypes.index, N)+n), ptr=True).store(red).end(m, n)
+  return store.sink(arg=KernelInfo(name=f'uop_gemm_{M}_{N}_{K}'))
+
+# ** backward gemm, might use the asm gemm
+
+def custom_gemm_bw(gradient:UOp, kernel:UOp):
+  out, a, b = kernel.src
+  assert all_same([gradient.device, a.device, b.device, out.device])
+  a_t, b_t, g_t = Tensor(a, device=a.device), Tensor(b, device=a.device), Tensor(gradient, device=a.device)
+  grad_a = (g_t @ b_t.T).uop
+  grad_b = (a_t.permute(2, 0, 1).reshape(a_t.shape[2], -1) @ g_t.reshape(-1, g_t.shape[-1])).uop
+  return (None, grad_a, grad_b)
+
+# ** main gemm function
+
+def asm_gemm(a:Tensor, b:Tensor) -> Tensor:
+  assert can_use_asm_gemm(a, b), f"{counters['todos'][-1]}"
+  counters["used"] += 1
+  squeeze = a.ndim == 2
+  if squeeze: a = a.unsqueeze(0)
+
+  batch, M, K = a.shape
+  N = b.shape[1]
+  is_multi = isinstance(a.device, tuple)
+
+  if is_multi:
+    out = Tensor(Tensor.empty(batch//len(a.device), M, N, dtype=a.dtype, device=a.device).uop.multi(0), device=a.device)
+  else:
+    out = Tensor.empty(batch, M, N, dtype=a.dtype, device=a.device)
+
+  dname = a.device[0] if is_multi else a.device
+  arch = getattr(Device[dname].renderer, "arch", "")
+  if arch.startswith("gfx950") and getenv("USE_ASM", 1):
+    numWG = GEMM_ARGS[(M, N, K)][0]
+    out = Tensor.custom_kernel(out, a, b, fxn=functools.partial(custom_asm_gemm, dname=dname, wg=numWG, arch=arch), grad_fxn=custom_gemm_bw)[0]
+  else:
+    out = Tensor.custom_kernel(out, a, b, fxn=custom_uop_gemm, grad_fxn=custom_gemm_bw)[0]
+  return out.squeeze(0) if squeeze else out
@@ -1,78 +0,0 @@
-.text
-.section	.text.
-.global	gemm
-.p2align	8
-.type	gemm,@function
-
-gemm:
-INSTRUCTIONS
-
-.section .rodata,"a",@progbits
-.p2align 6, 0x0
-.amdhsa_kernel gemm
-  # basic memory requirements
-  .amdhsa_group_segment_fixed_size 133120
-  .amdhsa_private_segment_fixed_size 0
-  .amdhsa_kernarg_size 28
-  # register usage (RSRC1)
-  .amdhsa_next_free_vgpr 504
-  .amdhsa_next_free_sgpr 96
-  # workgroup / workitem IDs (RSRC2)
-  .amdhsa_system_sgpr_workgroup_id_x 1
-  .amdhsa_system_sgpr_workgroup_id_y 1
-  .amdhsa_system_sgpr_workgroup_id_z 1
-  # user SGPRs, we only specify the kernel args ptr in s[0:1]
-  .amdhsa_user_sgpr_kernarg_segment_ptr 1
-  .amdhsa_user_sgpr_count 2
-  .amdhsa_user_sgpr_kernarg_preload_length 0
-  .amdhsa_user_sgpr_kernarg_preload_offset 0
-  # gfx90a / gfx940 specifics (RSRC3)
-  .amdhsa_accum_offset 248
-  .amdhsa_uses_dynamic_stack 0
-  .amdhsa_tg_split 0
-.end_amdhsa_kernel
-
-.amdgpu_metadata
---
-amdhsa.kernels:
-  - .name: gemm
-    .symbol: gemm.kd
-    .args:
-      - .name: C
-        .address_space: global
-        .offset: 0
-        .size: 8
-        .value_kind: global_buffer
-        .value_type: bf16
-      - .name: B
-        .address_space: global
-        .offset: 8
-        .size: 8
-        .value_kind: global_buffer
-        .value_type: bf16
-      - .name: A
-        .address_space: global
-        .offset: 16
-        .size: 8
-        .value_kind: global_buffer
-        .value_type: bf16
-      - .name: sz
-        .offset: 24
-        .size: 4
-        .value_kind: by_value
-        .value_type: u32
-    .group_segment_fixed_size: 133120
-    .private_segment_fixed_size: 0
-    .kernarg_segment_align: 8
-    .kernarg_segment_size: 28
-    .max_flat_workgroup_size: 256
-    .sgpr_count: 88
-    .sgpr_spill_count: 0
-    .vgpr_count: 248
-    .vgpr_spill_count: 0
-    .wavefront_size: 64
-amdhsa.version:
-  - 1
-  - 0
-...
-.end_amdgpu_metadata
@@ -1,72 +0,0 @@
-# Run assembly on the AMD runtime and check correctness
-# VIZ=2 to profile
-import pathlib
-from tinygrad import Tensor, Device, dtypes, Context
-from tinygrad.uop.ops import UOp, Ops, KernelInfo
-from tinygrad.helpers import getenv
-
-fp = pathlib.Path(__file__).parent/"gemm.s"
-
-N = getenv("N", 8192)
-THREADS_PER_WG = 256
-NUM_WG = N//THREADS_PER_WG * N//THREADS_PER_WG
-
-assert N % THREADS_PER_WG == 0, "N must be divisible by THREADS_PER_WG"
-
-# ** generate inputs on CPU
-
-scale = 10.0
-
-import torch
-torch.manual_seed(0)
-A = (torch.randn(N, N, dtype=torch.float32, device="cpu") / scale).to(torch.bfloat16).contiguous()
-B = (torch.randn(N, N, dtype=torch.float32, device="cpu") / scale).to(torch.bfloat16).contiguous()
-Bt = B.t().contiguous() # transpose B for the asm gemm
-C_torch = A@B
-
-# ** copy buffers to AMD
-
-# input creation and validation run on the copy engine for simpler tracing
-
-def from_torch(t:torch.Tensor) -> Tensor:
-  return Tensor.from_blob(t.data_ptr(), t.shape, dtype=dtypes.bfloat16, device="cpu").to(Device.DEFAULT).realize()
-
-C_tiny = from_torch(A) @ from_torch(B)
-C_asm = Tensor.empty_like(C_tiny)
-
-# ** assembly custom kernel
-
-def custom_asm_gemm(C:UOp, A:UOp, B:UOp) -> UOp:
-  lidx = UOp.special(THREADS_PER_WG, "lidx0")
-  gidx = UOp.special(NUM_WG, "gidx0")
-
-  src = (pathlib.Path(__file__).parent/"template.s").read_text().replace("INSTRUCTIONS", fp.read_text())
-
-  sz = UOp.variable("SZ", 256, 8192)
-
-  sink = UOp.sink(C.base, A.base, B.base, sz, lidx, gidx, arg=KernelInfo(name="gemm"))
-  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=Device.DEFAULT), UOp(Ops.LINEAR, src=(*sink.src, sink)), UOp(Ops.SOURCE, arg=src)), arg=())
-
-C_asm = Tensor.custom_kernel(C_asm, from_torch(A), from_torch(Bt), fxn=custom_asm_gemm)[0]
-
-# ** run gemms
-
-sched = Tensor.schedule(C_tiny, C_asm)
-eis = [si.lower() for si in sched]
-
-with Context(DEBUG=2):
-  for ei in eis:
-    et = ei.run({"SZ":N}, wait=True)
-    print(f"{(N*N*N*2 / et)*1e-12:.2f} REAL TFLOPS")
-
-# ** correctness
-
-import ctypes
-
-def torch_bf16(t:Tensor) -> torch.tensor:
-  asm_out = t.to("cpu").realize().uop.buffer._buf
-  buf = (ctypes.c_uint16*C_asm.uop.size).from_address(asm_out.va_addr)
-  return torch.frombuffer(buf, dtype=torch.bfloat16, count=C_asm.uop.size).reshape(C_asm.shape)
-
-assert torch.allclose(torch_bf16(C_asm), C_torch, rtol=1e-2, atol=1e-3)
-assert torch.allclose(torch_bf16(C_tiny), C_torch, rtol=1e-2, atol=1e-3)
@@ -24,7 +24,7 @@ def asm_kernel() -> UOp:
  src = template.replace("INSTRUCTIONS", (pathlib.Path(__file__).parent/"gemm.s").read_text())

  sink = UOp.sink(a, b, c, lidx, gidx, arg=KernelInfo(name="gemm"))
-  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=dname), UOp(Ops.LINEAR, src=(*sink.src, sink)), UOp(Ops.SOURCE, arg=src)), arg=())
+  return UOp(Ops.PROGRAM, src=(sink, UOp(Ops.DEVICE, arg=dname), UOp(Ops.LINEAR, src=(*sink.src, sink)), UOp(Ops.SOURCE, arg=src)))

 if __name__ == "__main__":
  test_matmul(asm_kernel(), dtype=dtypes.half, N=N)
@@ -37,7 +37,7 @@ b.copyin(row.data)
 c.copyin(mat.data)
 ret = prog(a._buf, b._buf, c._buf, global_size=[1,1,1], local_size=[8,1,1], wait=True)
 print(ret)
-out = np.frombuffer(a.as_buffer(), np.float32)
+out = np.frombuffer(a.as_memoryview(), np.float32)
 real = row.astype(np.float32)@mat.T.astype(np.float32)
 print("out:", out)
 print("real", real)
@@ -98,10 +98,10 @@ if __name__ == "__main__":
  # check correctness
  if getenv("VERIFY"):
    from tinygrad.engine.realize import run_schedule
-    triton_buf = np.frombuffer(si.bufs[0].as_buffer(), np.float16).reshape(M,N)
+    triton_buf = np.frombuffer(si.bufs[0].as_memoryview(), np.float16).reshape(M,N)
    print(triton_buf)
    run_schedule(sched)
-    tinygrad_buf = np.frombuffer(si.bufs[0].as_buffer(), np.float16).reshape(M,N)
+    tinygrad_buf = np.frombuffer(si.bufs[0].as_memoryview(), np.float16).reshape(M,N)
    print(tinygrad_buf)
    np.testing.assert_allclose(triton_buf, tinygrad_buf)
    print("correct!")
--- a/Show More
+++ b/Show More