feat: tag 0.10.3 (#10310 )

small changes from O(1) multi [pr] (#10309 )
hotfix: filter_too_much (#10308 )
2026-08-22 00:06:07 +00:00 · 2025-05-14 15:45:13 -07:00 · 2025-05-14 15:34:07 -07:00 · 2025-05-14 15:31:51 -07:00 · 2025-05-14 15:16:40 -07:00 · 2025-05-14 14:50:37 -07:00
345 changed files with 346034 additions and 734864 deletions
@@ -44,6 +44,9 @@ runs:
      uses: actions/setup-python@v5
      with:
        python-version: ${{ inputs.python-version }}
+    - name: Upgrade pip
+      shell: bash
+      run: python -m pip install --upgrade pip

    # **** Caching packages ****
    # TODO: key should include input.deps, but it can't since it can't contain commas
@@ -121,9 +124,8 @@ runs:
        echo -e 'Package: *\nPin: release o=repo.radeon.com\nPin-Priority: 600' | sudo tee /etc/apt/preferences.d/rocm-pin-600
        sudo apt update || true
        sudo apt install --no-install-recommends --allow-unauthenticated -y hsa-rocr comgr hsa-rocr-dev liburing-dev libc6-dev
-        curl -s https://api.github.com/repos/Qazalin/remu/releases/latest | \
-        jq -r '.assets[] | select(.name == "libremu.so").browser_download_url' | \
-        sudo xargs curl -L -o /usr/local/lib/libremu.so
+        cargo build --release --manifest-path ./extra/remu/Cargo.toml
+        sudo ln -sf ${{ github.workspace }}/extra/remu/target/release/libremu.so /usr/local/lib/libremu.so
        sudo tee --append /etc/ld.so.conf.d/rocm.conf <<'EOF'
          /opt/rocm/lib
          /opt/rocm/lib64
@@ -137,9 +139,7 @@ runs:
        curl -s -H "Authorization: token $GH_TOKEN" curl -s https://api.github.com/repos/nimlgen/amdcomgr_dylib/releases/latest | \
          jq -r '.assets[] | select(.name == "libamd_comgr.dylib").browser_download_url' | \
          sudo xargs curl -L -o /usr/local/lib/libamd_comgr.dylib
-        curl -s -H "Authorization: token $GH_TOKEN" curl -s https://api.github.com/repos/Qazalin/remu/releases/latest | \
-          jq -r '.assets[] | select(.name == "libremu.dylib").browser_download_url' | \
-          sudo xargs curl -L -o /usr/local/lib/libremu.dylib
+        cargo build --release --manifest-path ./extra/remu/Cargo.toml

    # **** CUDA ****

@@ -175,7 +175,7 @@ runs:
        git checkout b16039dc940dc6bc4ea0a98380495769ff35ed99
        mkdir build
        cd build
-        cmake .. -Wno-dev -G Ninja -DOCELOT_BUILD_TOOLS=OFF -DCMAKE_BUILD_ALWAYS=0 -DBUILD_TESTS_CUDA=OFF
+        cmake .. -Wno-dev -G Ninja -DOCELOT_BUILD_TOOLS=OFF -DCMAKE_BUILD_ALWAYS=0 -DBUILD_TESTS_CUDA=OFF -DCMAKE_POLICY_VERSION_MINIMUM=3.5
        ninja
    - name: Install gpuocelot
      if: inputs.cuda == 'true'
@@ -221,4 +221,4 @@ runs:
      if: inputs.llvm == 'true' && runner.os == 'macOS'
      shell: bash
      run: |
-        brew install llvm
+        brew install llvm@19
@@ -24,6 +24,9 @@ on:
 jobs:
  testmacbenchmark:
    name: Mac Benchmark
+    env:
+      # since sudo is required for usbgpu on macos, move the cache to a new location, as some of the files are owned by root
+      PYTHONPYCACHEPREFIX: /tmp/tiny_python_pycache
    runs-on: [self-hosted, macOS]
    timeout-minutes: 20
    defaults:
@@ -54,24 +57,25 @@ jobs:
      run: JIT=1 python3.11 examples/stable_diffusion.py --seed 0 --noshow --timing | tee sd_no_fp16.txt
    - name: Run Stable Diffusion v2
      run: JIT=1 python3.11 examples/sdv2.py --fp16 --seed 0 --noshow --timing | tee sdv2.txt
+    # process replay can't capture this, the graph is too large
    - name: Run SDXL
-      run: JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
+      run: CAPTURE_PROCESS_REPLAY=0 JIT=1 python3.11 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run model inference benchmark
      run: METAL=1 python3.11 test/external/external_model_benchmark.py
    - name: Test speed vs torch
      run: BIG=2 MPS=1 python3.11 test/test_speed_v_torch.py | tee torch_speed.txt
    - name: Test tensor cores
-      run: METAL=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+      run: METAL=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
    - name: Test AMX tensor cores
      run: |
-        DEBUG=2 CPU=1 AMX=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
-        DEBUG=2 LLVM=1 AMX=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+        DEBUG=2 CPU=1 AMX=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
+        DEBUG=2 LLVM=1 AMX=1 python3.11 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
    - name: Run Tensor Core GEMM (float)
-      run: DEBUG=2 python3.11 extra/gemm/simple_matmul.py | tee matmul.txt
+      run: DEBUG=2 SHOULD_USE_TC=1 python3.11 extra/gemm/simple_matmul.py | tee matmul.txt
    - name: Run Tensor Core GEMM (half)
-      run: DEBUG=2 HALF=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_half.txt
+      run: DEBUG=2 SHOULD_USE_TC=1 HALF=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_half.txt
    - name: Run Tensor Core GEMM (bfloat16)
-      run: DEBUG=2 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
+      run: DEBUG=2 SHOULD_USE_TC=1 BFLOAT16=1 python3.11 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
    - name: Fuzz Padded Tensor Core GEMM
      run: METAL=1 M_START=6 M_STOP=10 M_STEP=1 N_START=6 N_STOP=10 N_STEP=1 K_START=6 K_STOP=24 K_STEP=1 TC_OPT=2 DEBUG=2 python3.11 ./extra/gemm/fuzz_matmul.py
    - name: Run LLaMA
@@ -84,6 +88,10 @@ jobs:
      run: |
        python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize int8 | tee llama_int8.txt
        python3.11 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing --quantize nf4 | tee llama_nf4.txt
+    - name: Run quantized LLaMA3
+      run: |
+        python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize int8 | tee llama3_int8.txt
+        python3.11 examples/llama3.py --size 8B --temperature 0 --benchmark --quantize nf4 | tee llama3_nf4.txt
    #- name: Run LLaMA 7B on 4 (virtual) GPUs
    #  run: python3.11 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 10 --temperature 0  --timing | tee llama_four_gpu.txt
    - name: Run GPT2
@@ -94,6 +102,8 @@ jobs:
      run: HALF=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half.txt
    - name: Run GPT2 w HALF/BEAM
      run: HALF=1 JITBEAM=2 IGNORE_BEAM_CACHE=1 python3.11 examples/gpt2.py --count 10 --temperature 0 --timing | tee gpt2_half_beam.txt
+    - name: Run OLMoE
+      run: python3.11 examples/olmoe.py
    - name: Train MNIST
      run: time PYTHONPATH=. TARGET_EVAL_ACC_PCT=96.0 python3.11 examples/beautiful_mnist.py | tee beautiful_mnist.txt
    - name: Run 10 CIFAR training steps
@@ -104,6 +114,14 @@ jobs:
    #  run: STEPS=10 DEFAULT_FLOAT=BFLOAT16 python3.11 examples/hlb_cifar10.py | tee train_cifar_bf16.txt
    - name: Run 10 CIFAR training steps w winograd
      run: JIT=1 WINO=1 STEPS=10 python3.11 examples/hlb_cifar10.py | tee train_cifar_wino.txt
+    - name: UsbGPU boot time
+      run: sudo -E PYTHONPATH=. DEBUG=2 AM_RESET=1 AMD=1 AMD_IFACE=USB time python3.11 test/test_tiny.py TestTiny.test_plus
+    - name: UsbGPU tiny tests
+      run: sudo -E PYTHONPATH=. AMD=1 AMD_IFACE=USB python3.11 test/test_tiny.py
+    - name: UsbGPU copy speeds
+      run: sudo -E PYTHONPATH=. AMD=1 AMD_IFACE=USB python3.11 test/external/external_test_usb_asm24.py TestDevCopySpeeds
+    - name: UsbGPU openpilot test
+      run: sudo -E PYTHONPATH=. AMD=1 AMD_IFACE=USB AMD_LLVM=1 NOLOCALS=0 IMAGE=0 GRAPH_ONE_KERNEL=1 python3.11 examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/9118973ed03c1ae1d40cf69a29507ec2cc78efd7/selfdrive/modeld/models/supercombo.onnx
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (Mac)
@@ -115,6 +133,8 @@ jobs:
          llama_beam.txt
          llama_int8.txt
          llama_nf4.txt
+          llama3_int8.txt
+          llama3_nf4.txt
          llama_four_gpu.txt
          gpt2_unjitted.txt
          gpt2_jitted.txt
@@ -174,17 +194,17 @@ jobs:
      run: NV=1 python test/external/external_benchmark_multitensor_allreduce.py
    - name: Test tensor cores
      run: |
-        NV=1 ALLOW_TF32=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
-        PTX=1 ALLOW_TF32=1 NV=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+        NV=1 ALLOW_TF32=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
+        PTX=1 ALLOW_TF32=1 NV=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
    - name: Run Tensor Core GEMM (CUDA)
      run: |
-        CUDA=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul.txt
-        CUDA=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
-        CUDA=1 ALLOW_TF32=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_tf32.txt
+        CUDA=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul.txt
+        CUDA=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_bfloat16.txt
+        CUDA=1 SHOULD_USE_TC=1 ALLOW_TF32=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_tf32.txt
    - name: Run Tensor Core GEMM (PTX)
-      run: NV=1 PTX=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_ptx.txt
+      run: NV=1 PTX=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_ptx.txt
    - name: Run Tensor Core GEMM (NV)
-      run: NV=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_nv.txt
+      run: NV=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_nv.txt
    - name: Test NV=1
      run: DEBUG=2 NV=1 python -m pytest -rA test/test_tiny.py
    - name: Test CUDA=1
@@ -192,7 +212,7 @@ jobs:
    - name: Run Stable Diffusion
      run: NV=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    - name: Run SDXL
-      run: NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
+      run: CAPTURE_PROCESS_REPLAY=0 NV=1 CAPTURE_PROCESS_REPLAY=0 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run LLaMA
      run: |
        NV=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
@@ -303,7 +323,7 @@ jobs:
      run: NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt
    - name: Run 10 MLPerf Bert training steps (6 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
+      run: NV=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=6 BERT_LAYERS=2 FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (NVIDIA Training)
@@ -369,9 +389,12 @@ jobs:
    - name: Test speed vs theoretical
      run: AMD=1 IGNORE_BEAM_CACHE=1 BEAM_DEBUG=1 DEBUG=1 python -m pytest -rA test/external/speed_v_theoretical.py --durations=20
    - name: Test tensor cores
-      run: AMD=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+      run: |
+        AMD=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded_amd TestLinearizer.test_tensor_cores_padded_uops
+        AMD=1 AMD_LLVM=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_emulation TestLinearizer.test_tensor_cores_padded_amd TestLinearizer.test_tensor_cores_padded_uops
+        AMD=1 SHOULD_USE_TC=1 BFLOAT16=1 DEBUG=2 python3 extra/gemm/simple_matmul.py
    - name: Run Tensor Core GEMM (AMD)
-      run: AMD=1 HALF=1 DEBUG=2 python3 extra/gemm/simple_matmul.py | tee matmul_amd.txt
+      run: AMD=1 SHOULD_USE_TC=1 HALF=1 DEBUG=2 ATOL=2e-2 python3 extra/gemm/simple_matmul.py | tee matmul_amd.txt
    - name: Test AMD=1
      run: DEBUG=2 AMD=1 python -m pytest -rA test/test_tiny.py
    - name: Test HIP=1
@@ -380,7 +403,7 @@ jobs:
    #- name: Fuzz Padded Tensor Core GEMM
    #  run: HSA=1 M_START=12 M_STOP=20 M_STEP=1 N_START=12 N_STOP=20 N_STEP=1 K_START=28 K_STOP=36 K_STEP=1 HALF=1 TC_OPT=2 DEBUG=2 python3 ./extra/gemm/fuzz_matmul.py
    - name: Remove amdgpu
-      run: sleep 5 && sudo rmmod amdgpu # sleep a bit to let the driver unload the prev pid.
+      run: sleep 10 && sudo rmmod amdgpu # sleep a bit to let the driver unload the prev pid.
    - name: Test AM cold start time
      run: time AMD=1 AM_RESET=1 python3 test/test_tiny.py TestTiny.test_plus
    - name: Test AM warm start time
@@ -388,7 +411,7 @@ jobs:
    - name: Run Stable Diffusion
      run: AMD=1 python3 examples/stable_diffusion.py --fp16 --seed 0 --noshow --timing | tee sd.txt
    - name: Run SDXL
-      run: AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
+      run: CAPTURE_PROCESS_REPLAY=0 AMD=1 python3 examples/sdxl.py --seed 0 --noshow --timing | tee sdxl.txt
    - name: Run LLaMA 7B
      run: |
        AMD=1 JIT=0 python3 examples/llama.py --gen 1 --prompt "Hello." --count 10 --temperature 0 --timing | tee llama_unjitted.txt
@@ -496,7 +519,7 @@ jobs:
      run: AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=1536 GPUS=6 MODEL=resnet python3 examples/mlperf/model_train.py | tee train_resnet.txt
    - name: Run 10 MLPerf Bert training steps (6 gpu)
      # TODO: remove BERT_LAYERS once scheduler is fast
-      run: AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=6 BERT_LAYERS=2 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
+      run: AMD=1 CAPTURE_PROCESS_REPLAY=0 DEFAULT_FLOAT=HALF BENCHMARK=10 BS=66 GPUS=6 BERT_LAYERS=2 FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 MODEL=bert python3 examples/mlperf/model_train.py | tee train_bert.txt
    - uses: actions/upload-artifact@v4
      with:
        name: Speed (AMD Training)
@@ -29,9 +29,9 @@ jobs:
    - name: External Benchmark Schedule
      run: PYTHONPATH="." python3 test/external/external_benchmark_schedule.py
    - name: Speed Test
-      run: LLVM=1 LLVMOPT=1 python3 test/test_speed_v_torch.py
+      run: LLVM=1 python3 test/test_speed_v_torch.py
    - name: Speed Test (BEAM=2)
-      run: BEAM=2 LLVM=1 LLVMOPT=1 python3 test/test_speed_v_torch.py
+      run: BEAM=2 LLVM=1 python3 test/test_speed_v_torch.py

  docs:
    name: Docs
@@ -88,7 +88,7 @@ jobs:
  autogen:
    name: Autogen
    runs-on: ubuntu-22.04
-    timeout-minutes: 10
+    timeout-minutes: 15
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -116,14 +116,17 @@ jobs:
    - name: Verify AMD autogen
      run: |
        cp tinygrad/runtime/autogen/hsa.py /tmp/hsa.py.bak
+        cp tinygrad/runtime/autogen/kfd.py /tmp/kfd.py.bak
        cp tinygrad/runtime/autogen/comgr.py /tmp/comgr.py.bak
        cp tinygrad/runtime/autogen/amd_gpu.py /tmp/amd_gpu.py.bak
        cp tinygrad/runtime/autogen/sqtt.py /tmp/sqtt.py.bak
        ./autogen_stubs.sh hsa
+        ./autogen_stubs.sh kfd
        ./autogen_stubs.sh comgr
        ./autogen_stubs.sh amd
        ./autogen_stubs.sh sqtt
        diff /tmp/hsa.py.bak tinygrad/runtime/autogen/hsa.py
+        diff /tmp/kfd.py.bak tinygrad/runtime/autogen/kfd.py
        diff /tmp/comgr.py.bak tinygrad/runtime/autogen/comgr.py
        diff /tmp/amd_gpu.py.bak tinygrad/runtime/autogen/amd_gpu.py
        diff /tmp/sqtt.py.bak tinygrad/runtime/autogen/sqtt.py
@@ -149,7 +152,9 @@ jobs:
  torchbackend:
    name: Torch Backend Tests
    runs-on: ubuntu-latest
-    timeout-minutes: 10
+    timeout-minutes: 15
+    env:
+      IGNORE_OOB: 0
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -176,8 +181,8 @@ jobs:
      run: PYTHONPATH=. python3 extra/torch_backend/test.py
    - name: Test one op in torch tests
      run: PYTHONPATH=. DEBUG=2 python3 extra/torch_backend/torch_tests.py TestTinyBackendPRIVATEUSE1.test_unary_log_tiny_float32
-    - name: Test Ops with TINY_BACKEND (expect failure)
-      run: PYTHONPATH=. LLVM=1 LLVMOPT=0 TINY_BACKEND=1 python3 -m pytest -n auto test/test_ops.py --durations=20 || true
+    - name: Test Ops with TINY_BACKEND
+      run: PYTHONPATH=. LLVM=1 LLVMOPT=0 TINY_BACKEND=1 python3 -m pytest -n auto test/test_ops.py --durations=20
    - name: Test in-place operations on views
      run: PYTHONPATH=. TORCH_DEBUG=1 python3 extra/torch_backend/test_inplace.py
    - name: Test multi-gpu
@@ -186,7 +191,9 @@ jobs:
  torchbackendmore:
    name: Torch Backend Tests More
    runs-on: ubuntu-latest
-    timeout-minutes: 10
+    timeout-minutes: 15
+    env:
+      IGNORE_OOB: 0
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -201,7 +208,7 @@ jobs:
        sudo apt update || true
        sudo apt install -y --no-install-recommends ninja-build
    - name: Test beautiful_mnist in torch with TINY_BACKEND
-      run: PYTHONPATH=. LLVM=1 TARGET_EVAL_ACC_PCT=96.0 TINY_BACKEND=1 python3 examples/other_mnist/beautiful_mnist_torch.py
+      run: SPLIT_REDUCEOP=0 FUSE_ARANGE=1 PYTHONPATH=. LLVM=1 TARGET_EVAL_ACC_PCT=96.0 TINY_BACKEND=1 python3 examples/other_mnist/beautiful_mnist_torch.py
    - name: Test some torch tests (expect failure)
      run: PYTHONPATH=. python3 -m pytest extra/torch_backend/torch_tests.py -v --tb=no || true

@@ -209,6 +216,8 @@ jobs:
    name: Tensor Core tests
    runs-on: ubuntu-latest
    timeout-minutes: 10
+    env:
+      IGNORE_OOB: 0
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -224,7 +233,8 @@ jobs:
    - name: Test emulated METAL tensor cores
      run: |
        DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_big_gemm
-        PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+        PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores
+        PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
    - name: Test emulated AMX tensor cores
      run: PYTHONPATH=. DEBUG=2 AMX=1 EMULATE_AMX=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm
    - name: Test emulated AMD tensor cores
@@ -233,17 +243,28 @@ jobs:
        PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py
        PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py
        PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py
-        PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded_amd TestLinearizer.test_tensor_cores_padded_uops
    - name: Test emulated AMD MFMA tensor cores
      run: |
        PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py
-        PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_MFMA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
+    - name: Test emulated AMD RDNA4 tensor cores
+      run: |
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=16 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 N=64 HALF=1 ACC_HALF=1 python3 ./extra/gemm/simple_matmul.py
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores
+        PYTHONPATH=. DEBUG=2 EMULATE_AMD_RDNA4=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
    - name: Test emulated CUDA tensor cores
      run: |
        DEBUG=2 EMULATE_CUDA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm_fp16
        DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm
        DEBUG=2 EMULATE_CUDA_SM75=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm_fp16
-        PYTHONPATH="." DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores TestLinearizer.test_tensor_cores_padded
+        PYTHONPATH="." DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores
+        PYTHONPATH="." DEBUG=2 EMULATE_CUDA=1 ALLOW_TF32=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_linearizer.py TestLinearizer.test_tensor_cores_padded TestLinearizer.test_tensor_cores_padded_uops
    - name: Test emulated INTEL OpenCL tensor cores
      run: DEBUG=2 EMULATE_INTEL=1 FORWARD_ONLY=1 PYTHON=1 HALF=1 N=64 python3 ./extra/gemm/simple_matmul.py
    - name: Full test tensor cores
@@ -255,12 +276,12 @@ jobs:
        PYTHONPATH=. DEBUG=2 AMX=1 EMULATE_AMX=1 FORWARD_ONLY=1 PYTHON=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores
    - name: Test tensor cores (TC=3)
      run: |
-        TC=3 DEBUG=3 EMULATE_METAL=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm
-        TC=3 PYTHONPATH=. DEBUG=3 EMULATE_AMD=1 PYTHON=1 N=16 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py
-        TC=3 PYTHONPATH=. DEBUG=3 EMULATE_AMD_MFMA=1 PYTHON=1 N=16 HALF=1 ACC_HALF=0 python3 ./extra/gemm/simple_matmul.py
-        TC=3 DEBUG=3 EMULATE_CUDA=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm_fp16
-        TC=3 PYTHONPATH=. DEBUG=3 EMULATE_INTEL=1 PYTHON=1 N=16 HALF=1 python3 ./extra/gemm/simple_matmul.py
-        TC=3 PYTHONPATH=. DEBUG=3 AMX=1 EMULATE_AMX=1 FORWARD_ONLY=1 PYTHON=1 python3 test/test_ops.py TestOps.test_gemm
+        PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_METAL=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation
+        PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_AMD=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation
+        PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_AMD_MFMA=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation
+        PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_CUDA=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation
+        PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_INTEL=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation
+        PYTHONPATH=. DEBUG=2 PYTHON=1 EMULATE_AMX=1 AMX=1 python3 ./test/test_linearizer.py TestLinearizer.test_tensor_cores_emulation
    - name: Test device flop counts
      run: |
        PYTHONPATH=. DEBUG=2 EMULATE_METAL=1 PYTHON=1 python3 ./test/test_uops_stats.py TestUOpsStatsMatmulHalf
@@ -273,6 +294,8 @@ jobs:
    name: Python Backend
    runs-on: ubuntu-latest
    timeout-minutes: 10
+    env:
+      IGNORE_OOB: 0
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -291,6 +314,8 @@ jobs:
      run: PYTHONPATH=. PYTHON=1 python3 test/test_symbolic_ops.py
    - name: test_linearizer_failures with Python emulator
      run: PYTHONPATH=. PYTHON=1 python3 -m pytest -rA test/test_linearizer_failures.py::TestLinearizerFailures::test_failure_1
+    - name: test_renderer_failures with Python emulator
+      run: PYTHONPATH=. PYTHON=1 python3 -m pytest -rA test/test_renderer_failures.py::TestRendererFailures

  linter:
    name: Linters
@@ -313,6 +338,7 @@ jobs:
      run: |
        pip3 install --upgrade --force-reinstall ruff==0.11.0
        python3 -m ruff check .
+        python3 -m ruff check examples/mlperf/model_train.py --ignore E501
    - name: Lint tinygrad with pylint
      run: python -m pylint tinygrad/
    - name: Run mypy
@@ -335,8 +361,15 @@ jobs:
      run: awk '/```python/{flag=1;next}/```/{flag=0}flag' README.md > README.py &&  PYTHONPATH=. python README.py
    - name: Run unit tests
      run: PYTHONPATH="." python -m pytest -n=auto test/unit/
-    - name: Repo line count < 12000 lines
-      run: MAX_LINE_COUNT=12000 python sz.py
+    - name: Run targetted tests on NULL backend
+      run: PYTHONPATH="." NULL=1 python3 test/test_multitensor.py TestMultiTensor.test_data_parallel_resnet_train_step
+    # TODO: support fake weights
+    #- name: Run LLaMA 7B on 4 fake devices
+    #  run: NULL=1 python3 examples/llama.py --gen 1 --size 7B --shard 4 --prompt "Hello." --count 3 --temperature 0 --timing
+    - name: Run GC tests
+      run: PYTHONPATH="." python test/external/external_uop_gc.py
+    - name: Repo line count < 13000 lines
+      run: MAX_LINE_COUNT=13000 python sz.py

  fuzzing:
    name: Fuzzing
@@ -352,6 +385,8 @@ jobs:
        deps: testing_minimal
    - name: Fuzz Test symbolic
      run: python test/external/fuzz_symbolic.py
+    - name: Fuzz Test fast idiv
+      run: python test/external/fuzz_fast_idiv.py
    - name: Fuzz Test shapetracker
      run: |
        PYTHONPATH="." python test/external/fuzz_shapetracker.py
@@ -361,6 +396,8 @@ jobs:
    name: 'GPU IMAGE Tests'
    runs-on: ubuntu-22.04
    timeout-minutes: 10
+    env:
+      IGNORE_OOB: 0
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -385,6 +422,8 @@ jobs:
    name: 'openpilot Compile Tests'
    runs-on: ubuntu-22.04
    timeout-minutes: 10
+    env:
+      IGNORE_OOB: 0
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -394,6 +433,7 @@ jobs:
          key: openpilot-compile
          deps: testing
          opencl: 'true'
+          llvm: 'true'
      - name: Test openpilot model kernel count and gate usage
        run: |
          PYTHONPATH="." ALLOWED_KERNEL_COUNT=209 ALLOWED_READ_IMAGE=2138 ALLOWED_GATED_READ_IMAGE=29 FLOAT16=0 GPU=1 IMAGE=2 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx
@@ -401,6 +441,8 @@ jobs:
        run: PYTHONPATH="." FLOAT16=0 DEBUGCL=1 GPU=1 IMAGE=2 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/3799fe46b3a629e491d4b8498b8ae83e4c88c304/selfdrive/modeld/models/supercombo.onnx
      - name: Test openpilot fastvits model correctness (float32)
        run: PYTHONPATH="." FLOAT16=0 DEBUGCL=1 GPU=1 IMAGE=2 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/9118973ed03c1ae1d40cf69a29507ec2cc78efd7/selfdrive/modeld/models/supercombo.onnx
+      - name: Test openpilot LLVM compile
+        run: PYTHONPATH="." LLVM=1 LLVMOPT=1 JIT=2 BEAM=0 IMAGE=0 python examples/openpilot/compile3.py https://github.com/commaai/openpilot/raw/9118973ed03c1ae1d40cf69a29507ec2cc78efd7/selfdrive/modeld/models/supercombo.onnx
      - name: Run process replay tests
        uses: ./.github/actions/process-replay

@@ -408,6 +450,8 @@ jobs:
    name: 'ONNX+Optimization Tests'
    runs-on: ubuntu-22.04
    timeout-minutes: 20
+    env:
+      IGNORE_OOB: 0

    steps:
      - name: Checkout Code
@@ -430,11 +474,11 @@ jobs:
        run: CPU=1 PYTHONPATH=. python3 test/external/external_test_onnx_ops.py
      - name: Test Quantize ONNX
        run: CPU=1 PYTHONPATH=. python3 test/test_quantize_onnx.py
-      - name: Run CLOUD=1 Test
+      - name: Run REMOTE=1 Test
        run: |
-          CLOUDDEV=CPU CLOUD=1 python3 test/test_tiny.py
-          CLOUDDEV=GPU CLOUD=1 python3 test/test_tiny.py
-          CLOUDDEV=GPU IMAGE=2 CLOUD=1 python3 test/test_tiny.py
+          REMOTEDEV=CPU REMOTE=1 python3 -m pytest test/test_tiny.py test/test_jit.py test/test_multitensor.py
+          REMOTEDEV=GPU REMOTE=1 python3 -m pytest test/test_tiny.py test/test_image_dtype.py test/test_jit.py
+          REMOTEDEV=GPU IMAGE=2 REMOTE=1 python3 -m pytest test/test_tiny.py test/test_image_dtype.py
      - name: Test Optimization Helpers
        run: PYTHONPATH="." DEBUG=1 python3 extra/optimization/test_helpers.py
      - name: Test Action Space
@@ -452,6 +496,8 @@ jobs:
    name: Models (llvm+cpu+gpu)
    runs-on: ubuntu-22.04
    timeout-minutes: 10
+    env:
+      IGNORE_OOB: 0
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -475,6 +521,8 @@ jobs:
    name: Linux (DSP)
    runs-on: ubuntu-24.04
    timeout-minutes: 15
+    env:
+      IGNORE_OOB: 0
    steps:
    - name: Checkout Code
      uses: actions/checkout@v4
@@ -535,11 +583,50 @@ jobs:
    - name: Run process replay tests
      uses: ./.github/actions/process-replay

-  tests:
+  testamd:
    strategy:
      fail-fast: false
      matrix:
-        backend: [llvm, cpu, gpu, ptx, amd, nv] #, triton]
+        backend: [amd, amdllvm]
+
+    name: Linux (${{ matrix.backend }})
+    runs-on: ubuntu-22.04
+    timeout-minutes: 20
+    env:
+      IGNORE_OOB: 0
+      AMD: 1
+      MOCKGPU: 1
+      FORWARD_ONLY: 1
+      AMD_LLVM: ${{ matrix.backend == 'amdllvm' && '1' || matrix.backend != 'amdllvm' && '0' }}
+    steps:
+      - name: Checkout Code
+        uses: actions/checkout@v4
+      - name: Setup Environment
+        uses: ./.github/actions/setup-tinygrad
+        with:
+          key: ${{ matrix.backend }}-minimal
+          deps: testing_minimal
+          amd: 'true'
+          llvm: ${{ matrix.backend == 'amdllvm' && 'true' }}
+      - name: Check Device.DEFAULT and print some source
+        run: |
+          PYTHONPATH=${{ github.workspace }} python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['AMD'], Device.DEFAULT"
+          DEBUG=5 PYTHONPATH=${{ github.workspace }} FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
+      - name: Run LLVM test
+        if: matrix.backend=='amdllvm'
+        run: PYTHONPATH="." python test/test_amd_llvm.py
+      - name: Run pytest (amd)
+        run: python -m pytest -n=auto test/test_ops.py test/test_dtype.py test/test_dtype_alu.py test/test_linearizer.py test/test_randomness.py test/imported/test_indexing.py test/test_hcq.py test/external/external_test_am.py --durations=20
+      - name: Run TRANSCENDENTAL math
+        run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20
+      - name: Run process replay tests
+        uses: ./.github/actions/process-replay
+
+  testnvidia:
+    strategy:
+      fail-fast: false
+      matrix:
+        backend: [ptx, nv]

    name: Linux (${{ matrix.backend }})
    runs-on: ubuntu-22.04
@@ -552,29 +639,49 @@ jobs:
        uses: ./.github/actions/setup-tinygrad
        with:
          key: ${{ matrix.backend }}-minimal
-          deps: testing_minimal${{matrix.backend=='ptx'&&',cuda'||matrix.backend=='triton'&&',triton'||''}}
-          opencl: ${{ matrix.backend == 'gpu' && 'true' }}
-          amd: ${{ matrix.backend == 'amd' && 'true' }}
-          llvm: ${{ (matrix.backend == 'amd' || matrix.backend == 'llvm') && 'true' }}
-          cuda: ${{ (matrix.backend == 'ptx' || matrix.backend == 'triton' || matrix.backend == 'nv') && 'true' }}
+          deps: testing_minimal
+          cuda: 'true'
      - name: Set env
-        run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1' || matrix.backend == 'gpu' && 'GPU=1' || matrix.backend == 'PTX' && 'FORWARD_ONLY=1\nJIT=1\nOPT=2\nCUDA=1\nPTX=1\nMOCKGPU=1' || matrix.backend == 'triton' && 'FORWARD_ONLY=1\nJIT=1\nOPT=2\nNV=1\nMOCKGPU=1\nTRITON=1\nTRITON_PTXAS_PATH=/usr/bin/ptxas' || matrix.backend == 'amd' && 'AMD=1\nMOCKGPU=1\nFORWARD_ONLY=1' || matrix.backend == 'nv' && 'NV=1\nMOCKGPU=1\nFORWARD_ONLY=1' }}" >> $GITHUB_ENV
+        run: printf "${{ matrix.backend == 'PTX' && 'FORWARD_ONLY=1\nJIT=1\nOPT=2\nCUDA=1\nPTX=1\nMOCKGPU=1' || matrix.backend == 'nv' && 'NV=1\nMOCKGPU=1\nFORWARD_ONLY=1' }}" >> $GITHUB_ENV
      - name: Check Device.DEFAULT and print some source
        run: |
-          PYTHONPATH=${{ github.workspace }} python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['LLVM','CPU','CUDA','GPU','AMD','NV'], Device.DEFAULT"
+          PYTHONPATH=${{ github.workspace }} python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['CUDA','NV'], Device.DEFAULT"
          DEBUG=5 PYTHONPATH=${{ github.workspace }} FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
-      - name: Run pytest (not cuda or amd)
-        if: matrix.backend!='ptx' && matrix.backend!='triton' && matrix.backend != 'amd' && matrix.backend != 'nv'
-        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
      - name: Run pytest (cuda)
-        if: matrix.backend=='ptx'||matrix.backend=='triton'||matrix.backend=='nv'
        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --ignore test/test_gc.py --durations=20
-      - name: Run pytest (amd)
-        if: matrix.backend=='amd'
-        run: python -m pytest -n=auto test/test_ops.py test/test_dtype.py test/test_dtype_alu.py test/test_linearizer.py test/test_randomness.py test/imported/test_indexing.py test/test_hcq.py test/external/external_test_am.py --durations=20
-      - name: Run pytest (amd with llvm backend)
-        if: matrix.backend=='amd'
-        run: AMD_LLVM=1 python -m pytest -n=auto test/test_ops.py test/test_dtype.py test/test_dtype_alu.py test/test_linearizer.py test/test_randomness.py test/imported/test_indexing.py test/test_hcq.py test/external/external_test_am.py test/test_amd_llvm.py --durations=20
+      - name: Run process replay tests
+        uses: ./.github/actions/process-replay
+
+  tests:
+    strategy:
+      fail-fast: false
+      matrix:
+        backend: [llvm, cpu, gpu]
+
+    name: Linux (${{ matrix.backend }})
+    runs-on: ubuntu-22.04
+    timeout-minutes: 20
+    env:
+      IGNORE_OOB: 0
+
+    steps:
+      - name: Checkout Code
+        uses: actions/checkout@v4
+      - name: Setup Environment
+        uses: ./.github/actions/setup-tinygrad
+        with:
+          key: ${{ matrix.backend }}-minimal
+          deps: testing_minimal
+          opencl: ${{ matrix.backend == 'gpu' && 'true' }}
+          llvm: ${{ matrix.backend == 'llvm' && 'true' }}
+      - name: Set env
+        run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1' || matrix.backend == 'gpu' && 'GPU=1' }}" >> $GITHUB_ENV
+      - name: Check Device.DEFAULT and print some source
+        run: |
+          PYTHONPATH=${{ github.workspace }} python3 -c "from tinygrad import Device; assert Device.DEFAULT in ['LLVM','CPU','GPU'], Device.DEFAULT"
+          DEBUG=5 PYTHONPATH=${{ github.workspace }} FORWARD_ONLY=1 python3 test/test_ops.py TestOps.test_add
+      - name: Run pytest (not cuda)
+        run: python -m pytest -n=auto test/ --ignore=test/models --ignore=test/unit --durations=20
      - name: Run TRANSCENDENTAL math
        run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20
      - name: Run process replay tests
@@ -586,6 +693,8 @@ jobs:
    name: MacOS (unit)
    runs-on: macos-14
    timeout-minutes: 20
+    env:
+      IGNORE_OOB: 0

    steps:
    - name: Checkout Code
@@ -600,11 +709,11 @@ jobs:
        cuda: 'true'
        llvm: 'true'
    - name: Run real world test
-      run: JIT=2 METAL=1 python -m pytest -n=auto test/models/test_real_world.py --durations=20
+      run: METAL=1 python -m pytest -n=auto test/models/test_real_world.py --durations=20
    - name: Test models (Metal)
-      run: JIT=2 METAL=1 python -m pytest -n=auto test/models --durations=20
+      run: METAL=1 python -m pytest test/models -v --durations=20
    - name: Run ONNX
-      run: JIT=2 METAL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
+      run: METAL=1 python -m pytest -n=auto test/external/external_test_onnx_backend.py --durations=20
    - name: Test tensor core ops (fake)
      run: TC=2 METAL=1 DEBUG=3 python test/test_ops.py TestOps.test_gemm
    - name: Test tensor core ops (real)
@@ -615,8 +724,6 @@ jobs:
      run: PYTHONPATH="." METAL=1 IGNORE_BEAM_CACHE=1 python3 -m pytest extra/optimization/test_beam_search.py
    - name: Fuzz Test linearizer
      run: PYTHONPATH="." METAL=1 DEPTH=4 FUZZ_N=50 FUZZ_MAX_SIZE=1000000 python test/external/fuzz_linearizer.py
-    # - name: Fuzz Test models schedule
-    # run: FUZZ_SCHEDULE=1 FUZZ_SCHEDULE_MAX_PATHS=5 python -m pytest test/models/test_train.py test/models/test_end2end.py
    - name: Run TRANSCENDENTAL math
      run: TRANSCENDENTAL=2 python -m pytest -n=auto test/test_ops.py::TestOps::test_sin test/test_ops.py::TestOps::test_cos test/test_ops.py::TestOps::test_tan test/test_ops.py::TestOps::test_exp test/test_ops.py::TestOps::test_log --durations=20
    - name: Run pytest (amd)
@@ -656,7 +763,10 @@ jobs:
      uses: ./.github/actions/setup-tinygrad
      with:
        key: osx-webgpu
+        deps: testing_minimal
        webgpu: 'true'
+    - name: Test infinity math in WGSL
+      run: WEBGPU=1 python -m pytest -n=auto test/test_renderer_failures.py::TestWGSLFailures::test_multiply_infinity --durations=20
    - name: Build WEBGPU Efficientnet
      run: WEBGPU=1 WEBGPU_BACKEND="WGPUBackendType_Metal" python3 -m examples.compile_efficientnet
    - name: Clean npm cache
@@ -666,6 +776,30 @@ jobs:
    - name: Run WEBGPU Efficientnet
      run: node test/web/test_webgpu.js

+  osxremote:
+    name: MacOS (remote)
+    runs-on: macos-15
+    timeout-minutes: 10
+    env:
+      REMOTE: 1
+      REMOTEDEV: METAL
+    steps:
+      - name: Checkout Code
+        uses: actions/checkout@v4
+      - name: Setup Environment
+        uses: ./.github/actions/setup-tinygrad
+        with:
+          key: macos-remote
+          deps: testing_minimal
+      - name: Check Device.DEFAULT and print some source
+        run: |
+          python -c "from tinygrad import Device; assert Device.DEFAULT == 'REMOTE', Device.DEFAULT"
+          python -c "from tinygrad import Device; assert Device.default.properties.real_device == 'METAL', Device.default.properties.real_device"
+          DEBUG=4 python3 test/test_tiny.py TestTiny.test_plus
+      - name: Run REMOTE=1 Test
+        run: |
+          python3 -m pytest test/test_tiny.py test/test_jit.py test/test_multitensor.py
+
  osxtests:
    strategy:
      fail-fast: false
@@ -674,6 +808,8 @@ jobs:
    name: MacOS (${{ matrix.backend }})
    runs-on: macos-15
    timeout-minutes: 20
+    env:
+      IGNORE_OOB: 0
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -684,7 +820,7 @@ jobs:
          deps: testing_minimal
          llvm: ${{ matrix.backend == 'llvm' && 'true' }}
      - name: Set env
-        run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1' || matrix.backend == 'metal' && 'METAL=1\nJIT=2'}}" >> $GITHUB_ENV
+        run: printf "${{ matrix.backend == 'llvm' && 'LLVM=1' || matrix.backend == 'cpu' && 'CPU=1' || matrix.backend == 'metal' && 'METAL=1'}}" >> $GITHUB_ENV
      - name: Check Device.DEFAULT and print some source
        run: |
          python -c "from tinygrad import Device; assert Device.DEFAULT == '${{ matrix.backend }}'.upper(), Device.DEFAULT"
@@ -707,7 +843,9 @@ jobs:

    name: Windows (${{ matrix.backend }})
    runs-on: windows-latest
-    timeout-minutes: 10
+    timeout-minutes: 15
+    env:
+      IGNORE_OOB: 0
    steps:
      - name: Checkout Code
        uses: actions/checkout@v4
@@ -60,3 +60,5 @@ comgr_*
 site/
 profile_stats
 *.log
+target
+.mypy_cache
@@ -35,7 +35,7 @@ def _try_dlopen_$name():
  for candidate in PATHS_TO_TRY:
    try: return ctypes.CDLL(candidate)
    except OSError: pass
-  raise RuntimeError("library $name not found")
+  return None
 EOF
 }

@@ -78,11 +78,11 @@ generate_kfd() {
  clang2py /usr/include/linux/kfd_ioctl.h -o $BASE/kfd.py -k cdefstum

  fixup $BASE/kfd.py
-  sed -i "s\import ctypes\import ctypes, os\g" $BASE/kfd.py
-  sed -i "s\import fcntl, functools\import functools" $BASE/kfd.py
-  sed -i "s\import ctypes,os\a from tinygrad.runtime.support import HWInterface\g" $BASE/kfd.py
-  sed -i "s\def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, **kwargs):\def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:HWInterface, **kwargs):\g" $BASE/kfd.py
-  sed -i "s\fcntl.ioctl(__fd, (__idir<<30)\__fd.ioctl((__idir<<30)\g" $BASE/kfd.py
+  sed -i "s/import ctypes/import ctypes, os/g" $BASE/kfd.py
+  sed -i "s/import fcntl, functools/import functools/g" $BASE/kfd.py
+  sed -i "/import functools/a from tinygrad.runtime.support.hcq import FileIOInterface" $BASE/kfd.py
+  sed -i "s/def _do_ioctl(__idir, __base, __nr, __user_struct, __fd, \*\*kwargs):/def _do_ioctl(__idir, __base, __nr, __user_struct, __fd:FileIOInterface, \*\*kwargs):/g" $BASE/kfd.py
+  sed -i "s/fcntl.ioctl(__fd, (__idir<<30)/__fd.ioctl((__idir<<30)/g" $BASE/kfd.py
  python3 -c "import tinygrad.runtime.autogen.kfd"
 }

@@ -287,11 +287,19 @@ generate_vfio() {
  fixup $BASE/vfio.py
  sed -i "s\import ctypes\import ctypes, os\g" $BASE/vfio.py
  sed -i "s\import fcntl, functools\import functools" $BASE/vfio.py
-  sed -i "s\import ctypes,os\a from tinygrad.runtime.support import HWInterface\g" $BASE/vfio.py
+  sed -i "s\import ctypes,os\a from tinygrad.runtime.support import FileIOInterface\g" $BASE/vfio.py
  sed -i "s\fcntl.ioctl(__fd, (__idir<<30)\return __fd.ioctl((__idir<<30)\g" $BASE/vfio.py
 }

 generate_am() {
+  AMKERN_COMMIT_HASH=ceb12c04e2b5b53ec0779362831f5ee40c4921e4
+  AMKERN_SRC=/tmp/ROCK-Kernel-Driver-$AMKERN_COMMIT_HASH
+  if [ ! -d "$AMKERN_SRC" ]; then
+    git clone https://github.com/ROCm/ROCK-Kernel-Driver $AMKERN_SRC --depth 1
+  fi
+  AMKERN_AMD=$AMKERN_SRC/drivers/gpu/drm/amd/
+  AMKERN_INC=$AMKERN_AMD/include/
+
  clang2py -k cdefstum \
    extra/amdpci/headers/v11_structs.h \
    extra/amdpci/headers/v12_structs.h \
@@ -302,7 +310,7 @@ generate_am() {
    extra/amdpci/headers/amdgpu_psp.h \
    extra/amdpci/headers/amdgpu_irq.h \
    extra/amdpci/headers/amdgpu_doorbell.h \
-    extra/amdpci/headers/soc15_ih_clientid.h \
+    $AMKERN_INC/soc15_ih_clientid.h \
    --clang-args="-include stdint.h" \
    -o $BASE/am/am.py
  fixup $BASE/am/am.py
@@ -310,188 +318,193 @@ generate_am() {
  sed -i "s\AMDGPU_PTE_MTYPE_VG10(2)\AMDGPU_PTE_MTYPE_VG10(0, 2)\g" $BASE/am/am.py # incorrect parsing (TODO: remove when clang2py is gone).

  clang2py -k cdefstum \
-    extra/hip_gpu_driver/kfd_pm4_headers_ai.h \
-    extra/hip_gpu_driver/soc15d.h \
+    $AMKERN_AMD/amdkfd/kfd_pm4_headers_ai.h \
+    $AMKERN_AMD/amdgpu/soc15d.h \
    -o $BASE/am/pm4_soc15.py
  fixup $BASE/am/pm4_soc15.py

  clang2py -k cdefstum \
-    extra/hip_gpu_driver/kfd_pm4_headers_ai.h \
-    extra/hip_gpu_driver/nvd.h \
+    $AMKERN_AMD/amdkfd/kfd_pm4_headers_ai.h \
+    $AMKERN_AMD/amdgpu/nvd.h \
    -o $BASE/am/pm4_nv.py
  fixup $BASE/am/pm4_nv.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/vega10_enum.h \
+    $AMKERN_INC/vega10_enum.h \
    -o $BASE/am/vega10.py
  fixup $BASE/am/vega10.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/navi10_enum.h \
+    $AMKERN_INC/navi10_enum.h \
    -o $BASE/am/navi10.py
  fixup $BASE/am/navi10.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/soc21_enum.h \
+    $AMKERN_INC/soc21_enum.h \
    -o $BASE/am/soc21.py
  fixup $BASE/am/soc21.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/soc24_enum.h \
+    $AMKERN_INC/soc24_enum.h \
    -o $BASE/am/soc24.py
  fixup $BASE/am/soc24.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/mp_13_0_0_offset.h \
-    extra/amdpci/headers/mp_13_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/mp/mp_13_0_0_offset.h \
+    $AMKERN_INC/asic_reg/mp/mp_13_0_0_sh_mask.h \
    -o $BASE/am/mp_13_0_0.py
  fixup $BASE/am/mp_13_0_0.py

  # 14_0_3 reuses 14_0_2
  clang2py -k cdefstum \
-    extra/amdpci/headers/mp_14_0_2_offset.h \
-    extra/amdpci/headers/mp_14_0_2_sh_mask.h \
+    $AMKERN_INC/asic_reg/mp/mp_14_0_2_offset.h \
+    $AMKERN_INC/asic_reg/mp/mp_14_0_2_sh_mask.h \
    -o $BASE/am/mp_14_0_3.py
  fixup $BASE/am/mp_14_0_3.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/mp_11_0_offset.h \
-    extra/amdpci/headers/mp_11_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/mp/mp_11_0_offset.h \
+    $AMKERN_INC/asic_reg/mp/mp_11_0_sh_mask.h \
    -o $BASE/am/mp_11_0.py
  fixup $BASE/am/mp_11_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/gc_9_4_3_offset.h \
-    extra/amdpci/headers/gc_9_4_3_sh_mask.h \
+    $AMKERN_INC/asic_reg/gc/gc_9_4_3_offset.h \
+    $AMKERN_INC/asic_reg/gc/gc_9_4_3_sh_mask.h \
    extra/amdpci/overlay/gc_9_4_3.h \
    -o $BASE/am/gc_9_4_3.py
  fixup $BASE/am/gc_9_4_3.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/gc_10_3_0_offset.h \
-    extra/amdpci/headers/gc_10_3_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/gc/gc_10_3_0_offset.h \
+    $AMKERN_INC/asic_reg/gc/gc_10_3_0_sh_mask.h \
    -o $BASE/am/gc_10_3_0.py
  fixup $BASE/am/gc_10_3_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/gc_11_0_0_offset.h \
-    extra/amdpci/headers/gc_11_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/gc/gc_11_0_0_offset.h \
+    $AMKERN_INC/asic_reg/gc/gc_11_0_0_sh_mask.h \
    -o $BASE/am/gc_11_0_0.py
  fixup $BASE/am/gc_11_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/gc_12_0_0_offset.h \
-    extra/amdpci/headers/gc_12_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/gc/gc_12_0_0_offset.h \
+    $AMKERN_INC/asic_reg/gc/gc_12_0_0_sh_mask.h \
    -o $BASE/am/gc_12_0_0.py
  fixup $BASE/am/gc_12_0_0.py

  clang2py -k cdefstum \
    extra/hip_gpu_driver/sdma_registers.h \
-    extra/hip_gpu_driver/vega10_sdma_pkt_open.h \
+    $AMKERN_AMD/amdgpu/vega10_sdma_pkt_open.h \
    --clang-args="-I/opt/rocm/include -x c++" \
    -o $BASE/am/sdma_4_0_0.py
  fixup $BASE/am/sdma_4_0_0.py

  clang2py -k cdefstum \
    extra/hip_gpu_driver/sdma_registers.h \
-    extra/hip_gpu_driver/navi10_sdma_pkt_open.h \
+    $AMKERN_AMD/amdgpu/navi10_sdma_pkt_open.h \
    --clang-args="-I/opt/rocm/include -x c++" \
    -o $BASE/am/sdma_5_0_0.py
  fixup $BASE/am/sdma_5_0_0.py

  clang2py -k cdefstum \
    extra/hip_gpu_driver/sdma_registers.h \
-    extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h \
+    $AMKERN_AMD/amdgpu/sdma_v6_0_0_pkt_open.h \
    --clang-args="-I/opt/rocm/include -x c++" \
    -o $BASE/am/sdma_6_0_0.py
  fixup $BASE/am/sdma_6_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/mmhub_3_0_0_offset.h \
-    extra/amdpci/headers/mmhub_3_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/mmhub/mmhub_3_0_0_offset.h \
+    $AMKERN_INC/asic_reg/mmhub/mmhub_3_0_0_sh_mask.h \
    -o $BASE/am/mmhub_3_0_0.py
  fixup $BASE/am/mmhub_3_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/mmhub_3_0_2_offset.h \
-    extra/amdpci/headers/mmhub_3_0_2_sh_mask.h \
+    $AMKERN_INC/asic_reg/mmhub/mmhub_3_0_2_offset.h \
+    $AMKERN_INC/asic_reg/mmhub/mmhub_3_0_2_sh_mask.h \
    -o $BASE/am/mmhub_3_0_2.py
  fixup $BASE/am/mmhub_3_0_2.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/nbio_2_3_offset.h \
-    extra/amdpci/headers/nbio_2_3_sh_mask.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_2_3_offset.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_2_3_sh_mask.h \
    -o $BASE/am/nbio_2_3_0.py
  fixup $BASE/am/nbio_2_3_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/mmhub_4_1_0_offset.h \
-    extra/amdpci/headers/mmhub_4_1_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_7_2_0_offset.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_7_2_0_sh_mask.h \
+    -o $BASE/am/nbio_7_2_0.py
+  fixup $BASE/am/nbio_7_2_0.py
+
+  clang2py -k cdefstum \
+    $AMKERN_INC/asic_reg/mmhub/mmhub_4_1_0_offset.h \
+    $AMKERN_INC/asic_reg/mmhub/mmhub_4_1_0_sh_mask.h \
    -o $BASE/am/mmhub_4_1_0.py
  fixup $BASE/am/mmhub_4_1_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/nbio_4_3_0_offset.h \
-    extra/amdpci/headers/nbio_4_3_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_4_3_0_offset.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_4_3_0_sh_mask.h \
    -o $BASE/am/nbio_4_3_0.py
  fixup $BASE/am/nbio_4_3_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/nbif_6_3_1_offset.h \
-    extra/amdpci/headers/nbif_6_3_1_sh_mask.h \
+    $AMKERN_INC/asic_reg/nbif/nbif_6_3_1_offset.h \
+    $AMKERN_INC/asic_reg/nbif/nbif_6_3_1_sh_mask.h \
    -o $BASE/am/nbif_6_3_1.py
  fixup $BASE/am/nbif_6_3_1.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/nbio_7_9_0_offset.h \
-    extra/amdpci/headers/nbio_7_9_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_7_9_0_offset.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_7_9_0_sh_mask.h \
    -o $BASE/am/nbio_7_9_0.py
  fixup $BASE/am/nbio_7_9_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/nbio_7_11_0_offset.h \
-    extra/amdpci/headers/nbio_7_11_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_7_11_0_offset.h \
+    $AMKERN_INC/asic_reg/nbio/nbio_7_11_0_sh_mask.h \
    -o $BASE/am/nbio_7_11_0.py
  fixup $BASE/am/nbio_7_11_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/osssys_6_0_0_offset.h \
-    extra/amdpci/headers/osssys_6_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/oss/osssys_6_0_0_offset.h \
+    $AMKERN_INC/asic_reg/oss/osssys_6_0_0_sh_mask.h \
    -o $BASE/am/osssys_6_0_0.py
  fixup $BASE/am/osssys_6_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/osssys_7_0_0_offset.h \
-    extra/amdpci/headers/osssys_7_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/oss/osssys_7_0_0_offset.h \
+    $AMKERN_INC/asic_reg/oss/osssys_7_0_0_sh_mask.h \
    -o $BASE/am/osssys_7_0_0.py
  fixup $BASE/am/osssys_7_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/smu_v13_0_0_ppsmc.h \
-    extra/amdpci/headers/smu13_driver_if_v13_0_0.h \
+    $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h \
+    $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h \
    extra/amdpci/headers/amdgpu_smu.h \
    -o $BASE/am/smu_v13_0_0.py
  fixup $BASE/am/smu_v13_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/smu_v14_0_0_pmfw.h \
-    extra/amdpci/headers/smu_v14_0_2_ppsmc.h \
-    extra/amdpci/headers/smu14_driver_if_v14_0_0.h \
-    extra/amdpci/headers/smu14_driver_if_v14_0.h \
+    $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h \
+    $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h \
+    $AMKERN_AMD/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h \
    extra/amdpci/headers/amdgpu_smu.h \
    --clang-args="-include stdint.h" \
    -o $BASE/am/smu_v14_0_3.py
  fixup $BASE/am/smu_v14_0_3.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/hdp_6_0_0_offset.h \
-    extra/amdpci/headers/hdp_6_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/hdp/hdp_6_0_0_offset.h \
+    $AMKERN_INC/asic_reg/hdp/hdp_6_0_0_sh_mask.h \
    -o $BASE/am/hdp_6_0_0.py
  fixup $BASE/am/hdp_6_0_0.py

  clang2py -k cdefstum \
-    extra/amdpci/headers/hdp_7_0_0_offset.h \
-    extra/amdpci/headers/hdp_7_0_0_sh_mask.h \
+    $AMKERN_INC/asic_reg/hdp/hdp_7_0_0_offset.h \
+    $AMKERN_INC/asic_reg/hdp/hdp_7_0_0_sh_mask.h \
    -o $BASE/am/hdp_7_0_0.py
  fixup $BASE/am/hdp_7_0_0.py
 }
@@ -515,6 +528,19 @@ generate_webgpu() {
  python3 -c "import tinygrad.runtime.autogen.webgpu"
 }

+generate_libusb() {
+  clang2py -k cdefstum \
+    /usr/include/libusb-1.0/libusb.h \
+    -o $BASE/libusb.py
+
+  fixup $BASE/libusb.py
+  sed -i "s\import ctypes\import ctypes, os\g" $BASE/libusb.py
+  sed -i "s/FIXME_STUB/libusb/g" "$BASE/libusb.py"
+  sed -i "s/libusb_le16_to_cpu = libusb_cpu_to_le16//g" "$BASE/libusb.py"
+  sed -i "s/FunctionFactoryStub()/None if (lib_path:=os.getenv('LIBUSB_PATH', ctypes.util.find_library('usb-1.0'))) is None else ctypes.CDLL(lib_path)/g" "$BASE/libusb.py"
+  python3 -c "import tinygrad.runtime.autogen.libusb"
+}
+
 if [ "$1" == "opencl" ]; then generate_opencl
 elif [ "$1" == "hip" ]; then generate_hip
 elif [ "$1" == "comgr" ]; then generate_comgr
@@ -535,6 +561,7 @@ elif [ "$1" == "adreno" ]; then generate_adreno
 elif [ "$1" == "pci" ]; then generate_pci
 elif [ "$1" == "vfio" ]; then generate_vfio
 elif [ "$1" == "webgpu" ]; then generate_webgpu
+elif [ "$1" == "libusb" ]; then generate_libusb
 elif [ "$1" == "all" ]; then generate_opencl; generate_hip; generate_comgr; generate_cuda; generate_nvrtc; generate_hsa; generate_kfd; generate_nv; generate_amd; generate_io_uring; generate_libc; generate_am; generate_webgpu
 else echo "usage: $0 <type>"
 fi
@@ -1,7 +1,7 @@
 # tinygrad is a tensor library, and as a tensor library it has multiple parts
 # 1. a "runtime". this allows buffer management, compilation, and running programs
 # 2. a "Device" that uses the runtime but specifies compute in an abstract way for all
-# 3. a "LazyBuffer" that fuses the compute into kernels, using memory only when needed
+# 3. a "UOp" that fuses the compute into kernels, using memory only when needed
 # 4. a "Tensor" that provides an easy to use frontend with autograd ".backward()"


@@ -74,30 +74,47 @@ fxn.exec([out, a, b])
 assert out.as_buffer().cast('I')[0] == 5


-print("******** third, the LazyBuffer ***********")
+print("******** third, the UOp ***********")

 from tinygrad.engine.realize import run_schedule
 from tinygrad.engine.schedule import create_schedule_with_vars
+from tinygrad.engine.grouper import get_becomes_map

 # allocate some values + load in values
-a = UOp.metaop(Ops.EMPTY, (1,), dtypes.int32, DEVICE)
-b = UOp.metaop(Ops.EMPTY, (1,), dtypes.int32, DEVICE)
+a = UOp.new_buffer(DEVICE, 1, dtypes.int32)
+b = UOp.new_buffer(DEVICE, 1, dtypes.int32)
 a.buffer.allocate().copyin(memoryview(bytearray(struct.pack("I", 2))))
 b.buffer.allocate().copyin(memoryview(bytearray(struct.pack("I", 3))))

 # describe the computation
-out = a.alu(Ops.ADD, b)
+out = a + b
+s = UOp(Ops.SINK, dtypes.void, (out,))

-# schedule the computation as a list of kernels
-sched, _, becomes_map = create_schedule_with_vars(out.sink())
-for si in sched: print(si.ast.op)  # NOTE: the first two convert it to CPU
-# NOTE: UOps are no longer mutable, the scheduler gives you a map to lookup which BUFFER the result was written to
-out = becomes_map[out]
+# group the computation into kernels
+becomes_map = get_becomes_map(s)
+
+# the compute maps to an assign
+assign = becomes_map[a+b]
+
+# the first source is the output buffer (data)
+assert assign.src[0].op is Ops.BUFFER
+# the second source is the kernel (compute)
+assert assign.src[1].op is Ops.KERNEL
+
+# schedule the kernel graph in a linear list
+s = UOp(Ops.SINK, dtypes.void, (assign,))
+sched, _, becomes_map = create_schedule_with_vars(s)
+assert len(sched) == 1

 # DEBUGGING: print the compute ast
 print(sched[-1].ast)
 # NOTE: sched[-1].ast is the same as st_0 above

+# the output will be stored in a new buffer
+out = becomes_map[assign]
+assert out.op is Ops.BUFFER and not out.buffer.is_allocated()
+print(out)
+
 # run that schedule
 run_schedule(sched)

@@ -1,6 +1,6 @@
 # AM Driver

-AM driver is a userspace driver targeting AMD's 7900XTX. You only need tinygrad to send compute tasks to your GPU!
+AM driver is a userspace driver targeting AMD's RDNA3/RDNA4. You only need tinygrad to send compute tasks to your GPU!

 ## How to run?
 Make sure that amdgpu module is unloaded and just run tinygrad with `AMD=1`!
@@ -0,0 +1,109 @@
+# Kernel Creation
+
+Tinygrad lazily builds up a graph of Tensor operations. The Tensor graph includes a mix of:
+
+- Buffer and Assignment Ops: `BUFFER`, `BUFFER_VIEW`, `COPY`, `ASSIGN`
+- Movement Ops: `RESHAPE`, `EXPAND`, `PERMUTE`, `PAD`, `SHRINK`, `FLIP`
+- Compute Ops: `ADD`, `MUL`, `REDUCE_AXIS`, ...
+
+`Tensor.kernelize` creates the kernels and buffers needed to realize the output Tensor(s).
+
+## Kernelize flow
+
+Let's see how a multiply add Tensor graph becomes a fused elementwise kernel.
+
+```py
+# initialize 3 input buffers on the device
+a = Tensor([1]).realize()
+b = Tensor([2]).realize()
+c = Tensor([3]).realize()
+
+# create the Tensor graph
+mul = a*b
+out = mul+c
+
+print(mul) # <Tensor <UOp METAL (1,) int (<Ops.MUL: 48>, None)> on METAL with grad None>
+print(out) # <Tensor <UOp METAL (1,) int (<Ops.ADD: 52>, None)> on METAL with grad None>
+
+out.kernelize()
+
+print(mul) # <Tensor <UOp METAL (1,) int (<Ops.MUL: 48>, None)> on METAL with grad None>
+print(out) # <Tensor <UOp METAL (1,) int (<Ops.ASSIGN: 66>, None)> on METAL with grad None>
+```
+
+The multiply Tensor stays the same because it is fused. The output Tensor's UOp becomes a new ASSIGN UOp:
+
+```py
+print(out.lazydata)
+```
+
+The first source is the output BUFFER:
+
+```
+UOp(Ops.BUFFER, dtypes.int, arg=1, src=(
+  UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()),
+  UOp(Ops.UNIQUE, dtypes.void, arg=6, src=()),))
+```
+
+And the second source is the KERNEL and its 4 buffer edges (output_buffer, a, b, c):
+
+```
+UOp(Ops.KERNEL, dtypes.void, arg=<Kernel 12 SINK(<Ops.STORE: 45>,) (__add__, __mul__)>, src=(
+  UOp(Ops.BUFFER, dtypes.int, arg=1, src=(
+    x1:=UOp(Ops.DEVICE, dtypes.void, arg='METAL', src=()),
+    UOp(Ops.UNIQUE, dtypes.void, arg=6, src=()),)),
+  UOp(Ops.BUFFER, dtypes.int, arg=1, src=(
+     x1,
+    UOp(Ops.UNIQUE, dtypes.void, arg=1, src=()),)),
+  UOp(Ops.BUFFER, dtypes.int, arg=1, src=(
+     x1,
+    UOp(Ops.UNIQUE, dtypes.void, arg=3, src=()),)),
+  UOp(Ops.BUFFER, dtypes.int, arg=1, src=(
+     x1,
+    UOp(Ops.UNIQUE, dtypes.void, arg=5, src=()),)),))
+```
+
+KERNEL describes the compute AST, metadata and memory dependencies.
+
+BUFFER holds a reference to the device memory where the output will be stored.
+
+Once a Tensor is kernelized, all children will LOAD its BUFFER, instead of fusing it:
+
+```py
+child = out+2
+child.kernelize()
+print(child.lazydata.src[1].arg.ast)
+```
+
+```
+UOp(Ops.SINK, dtypes.void, arg=None, src=(
+  UOp(Ops.STORE, dtypes.void, arg=None, src=(
+    UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=0, src=()),
+    x2:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=()),
+    UOp(Ops.ADD, dtypes.int, arg=None, src=(
+      UOp(Ops.LOAD, dtypes.int, arg=None, src=(
+        UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=1, src=()),
+         x2,)),
+      UOp(Ops.CONST, dtypes.int, arg=2, src=(
+         x2,)),)),)),))
+```
+
+`Tensor.realize` will execute the kernels and write outputs to memory:
+
+```py
+Tensor.realize(out)
+print(out)        # <Tensor <UOp METAL (1,) int (<Ops.BUFFER: 23>, <buf real:True device:METAL size:1 dtype:dtypes.int offset:0>)> on METAL with grad None>
+print(out.item()) # 5
+```
+
+<hr />
+
+**Summary**
+
+- The large Tensor graph is built from a mix of data, compute and movement Ops.
+
+- `Tensor.kernelize` splits the Tensor graph into data (BUFFER), compute (KERNEL) and links dependencies with ASSIGN.
+
+- `Tensor.realize` executes KERNELs on device and replaces the Tensor graph with just a BUFFER.
+
+- Kernelize can be called multiple times on a Tensor. This allows for incrementally building the kernel fusion layout of a large Tensor graph, without having to call `realize` or `schedule`.
@@ -30,7 +30,7 @@ These control the behavior of core tinygrad even when used as a library.

 Variable | Possible Value(s) | Description
 ---|---|---
-DEBUG               | [1-6]      | enable debugging output, with 4 you get operations, timings, speed, generated code and more
+DEBUG               | [1-7]      | enable debugging output (operations, timings, speed, generated code and more)
 GPU                 | [1]        | enable the GPU (OpenCL) backend
 CUDA                | [1]        | enable CUDA backend
 AMD                 | [1]        | enable AMD backend
@@ -49,4 +49,17 @@ VISIBLE_DEVICES     | [list[int]]| restricts the NV/AMD devices that are availab
 JIT                 | [0-2]      | 0=disabled, 1=[jit enabled](quickstart.md#jit) (default), 2=jit enabled, but graphs are disabled
 VIZ                 | [1]        | 0=disabled, 1=[viz enabled](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/viz)
 ALLOW_TF32          | [1]        | enable TensorFloat-32 tensor cores on Ampere or newer GPUs.
-WEBGPU_BACKEND      | [WGPUBackendType_Metal, ...]          | Force select a backend for WebGPU (Metal, DirectX, OpenGL, Vulkan...)
+WEBGPU_BACKEND      | [WGPUBackendType_Metal, ...]          | Force select a backend for WebGPU (Metal, DirectX, OpenGL, Vulkan...)
+CUDA_PATH           | str        | Use `CUDA_PATH/include` for CUDA headers for CUDA and NV backends. If not set, TinyGrad will use `/usr/local/cuda/include`, `/usr/include` and `/opt/cuda/include`.
+
+## Debug breakdown
+
+Variable | Value | Description
+---|---|---
+DEBUG               | >= 1       | Enables debugging and lists devices being used
+DEBUG               | >= 2       | Provides performance metrics for operations, including timing, memory usage, bandwidth for each kernel execution
+DEBUG               | >= 3       | Outputs buffers used for each kernel (shape, dtype and strides) and the applied optimizations at a kernel level
+DEBUG               | >= 4       | Outputs the generated kernel code
+DEBUG               | >= 5       | Displays the intermediate representation of the computation UOps (AST)
+DEBUG               | >= 6       | Displays the intermediate representation of the computation UOps in a linearized manner, detailing the operation sequence
+DEBUG               | >= 7       | Outputs the assembly code generated for the target hardware
@@ -5,7 +5,7 @@ tinygrad supports various runtimes, enabling your code to scale across a wide ra
 | Runtime | Description | Requirements |
 |---------|-------------|--------------|
 | [NV](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_nv.py) | Provides acceleration for NVIDIA GPUs | Ampere/Ada series GPUs |
-| [AMD](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_amd.py) | Provides acceleration for AMD GPUs | RDNA2/RDNA3 series GPUs |
+| [AMD](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_amd.py) | Provides acceleration for AMD GPUs | RDNA2/RDNA3/RDNA4 series GPUs. You can select one of the interfaces for communication by setting `AMD_IFACE=(KFD|PCI)`. See [AMD interfaces](#amd-interfaces) for more details. |
 | [QCOM](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_qcom.py) | Provides acceleration for QCOM GPUs | 6xx series GPUs |
 | [METAL](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_metal.py) | Utilizes Metal for acceleration on Apple devices | M1+ Macs; Metal 3.0+ for `bfloat` support |
 | [CUDA](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_cuda.py) | Utilizes CUDA for acceleration on NVIDIA GPUs | NVIDIA GPU with CUDA support |
@@ -64,3 +64,11 @@ rawbuf_ptr = to_mv(cl_buf_desc_ptr, 0x100).cast('Q')[20] # offset 0xA0 is a raw
 # create tiny tensor
 tiny = Tensor.from_blob(rawbuf_ptr, (h*w*4,), dtype=dtypes.imagef((h,w)), device='QCOM')
 ```
+
+## AMD Interfaces
+AMD backend supports several interfaces for communicating with devices:
+
+* `KFD`: uses the amdgpu driver
+* `PCI`: uses the [AM driver](developer/am.md)
+
+You can force an interface by setting `AMD_IFACE` to one of these values. In the case of `AMD_IFACE=PCI`, this may unbind your GPU from the amdgpu driver.
@@ -22,6 +22,7 @@
 ::: tinygrad.Tensor.rand
 ::: tinygrad.Tensor.rand_like
 ::: tinygrad.Tensor.randn
+::: tinygrad.Tensor.randn_like
 ::: tinygrad.Tensor.randint
 ::: tinygrad.Tensor.normal
 ::: tinygrad.Tensor.uniform
@@ -1,4 +1,4 @@
-# model based off https://towardsdatascience.com/going-beyond-99-mnist-handwritten-digits-recognition-cfff96337392
+# model based off https://medium.com/data-science/going-beyond-99-mnist-handwritten-digits-recognition-cfff96337392
 from typing import List, Callable
 from tinygrad import Tensor, TinyJit, nn, GlobalCounters
 from tinygrad.helpers import getenv, colored, trange
@@ -1,12 +1,12 @@
-import sys, onnx, time
-from tinygrad import TinyJit, Device, GlobalCounters, fetch, getenv
+import sys, onnx, time, pickle
+from tinygrad import TinyJit, GlobalCounters, fetch, getenv
 from tinygrad.frontend.onnx import OnnxRunner
 from extra.onnx_helpers import get_example_inputs, validate

 def load_onnx_model(onnx_file):
  onnx_model = onnx.load(onnx_file)
  run_onnx = OnnxRunner(onnx_model)
-  run_onnx_jit = TinyJit(lambda **kwargs: next(iter(run_onnx({k:v.to(Device.DEFAULT) for k,v in kwargs.items()}).values())), prune=True)
+  run_onnx_jit = TinyJit(lambda **kwargs: next(iter(run_onnx({k:v.to(None) for k,v in kwargs.items()}).values())), prune=True, optimize=True)
  return run_onnx_jit, run_onnx.graph_inputs

 if __name__ == "__main__":
@@ -33,4 +33,4 @@ if __name__ == "__main__":

  if getenv("ORT"):
    validate(onnx_file, new_inputs, rtol=1e-3, atol=1e-3)
-    print("model validated")
+    print("model validated")
@@ -34,8 +34,8 @@ if __name__ == "__main__":
    part2 = nn.state.torch_load(fetch("https://huggingface.co/teknium/OpenHermes-2.5-Mistral-7B/resolve/main/pytorch_model-00002-of-00002.bin?download=true"))

  with Timing("weights -> model: "):
-    nn.state.load_state_dict(model, fix_bf16(convert_from_huggingface(part1, model, 32, 8)), strict=False)
-    nn.state.load_state_dict(model, fix_bf16(convert_from_huggingface(part2, model, 32, 8)), strict=False)
+    nn.state.load_state_dict(model, fix_bf16(convert_from_huggingface(part1, 32, 32, 8)), strict=False)
+    nn.state.load_state_dict(model, fix_bf16(convert_from_huggingface(part2, 32, 32, 8)), strict=False)

  if not os.path.isfile("/tmp/tokenizer.model"): create_fixed_tokenizer("/tmp/tokenizer.model")
  spp = SentencePieceProcessor(model_file="/tmp/tokenizer.model")
@@ -189,7 +189,7 @@ class GPT2:
          tokens = Variable("tokens", 0, VOCAB_SIZE).bind(toks[0][start_pos])
        else:
          tokens = Tensor([x[start_pos:] for x in toks])
-        tok = self.model(tokens, Variable("start_pos", 1 if start_pos else 0, MAX_CONTEXT).bind(start_pos), temperature).tolist()
+        tok = self.model(tokens, Variable("start_pos", 1 if start_pos else 0, MAX_CONTEXT-1).bind(start_pos), temperature).tolist()
      start_pos = len(toks[0])
      for i,t in enumerate(tok): toks[i].append(t)
    return [self.tokenizer.decode(x) for x in toks]
@@ -3,6 +3,7 @@ from extra.mcts_search import mcts_search
 from examples.mlperf.helpers import get_mlperf_bert_model
 from tinygrad import Tensor, Device, dtypes, nn
 from tinygrad.codegen.kernel import Kernel
+from tinygrad.codegen.heuristic import hand_coded_optimizations
 from tinygrad.ops import Ops, sym_infer
 from tinygrad.device import Compiled
 from tinygrad.engine.search import beam_search, bufs_from_lin
@@ -83,7 +84,7 @@ if __name__ == "__main__":

    # always try hand coded opt
    lin = Kernel(si.ast, opts=device.renderer)
-    lin.hand_coded_optimizations()
+    lin.apply_opts(hand_coded_optimizations(lin))
    lins.append((lin, "HC"))

    # maybe try tensor cores
@@ -211,11 +211,13 @@ class LLaMa:
    else:
      weights = load(str(model_path))
    if "model.embed_tokens.weight" in weights:
-      weights = convert_from_huggingface(weights, model, params["args"]["n_heads"], params["args"].get("n_kv_heads", params["args"]["n_heads"]))
+      weights = convert_from_huggingface(weights, params["args"]["n_layers"], params["args"]["n_heads"], params["args"].get("n_kv_heads", params["args"]["n_heads"]))

    weights = fix_bf16(weights)

-    with Context(BEAM=0):
+    # prevent tracking model weights
+    # this is a part of a larger problem with BUFFER UOps and gc in TRACK_MATCH_STATS=2
+    with Context(BEAM=0, TRACK_MATCH_STATS=0):
      # quantize
      if quantize is not None:
        weights = linear.quantize(weights, device)
@@ -126,7 +126,8 @@ def NF4Linear(block_size):
      return x.linear(unscaled.reshape(self.out_features, self.in_features).T)

    @staticmethod
-    def quantize(state_dict: dict[str, Tensor], device, scale_dtype=dtypes.float16) -> dict[str, Tensor]:
+    def quantize(state_dict: dict[str, Tensor], device, scale_dtype=dtypes.float16, quantize_embeds=False) -> dict[str, Tensor]:
+      assert not quantize_embeds  # TODO: support this?
      new_state_dict = {}
      for k, v in state_dict.items():
        if "feed_forward" in k or "attention.w" in k:
@@ -173,9 +174,9 @@ def build_transformer(model_path: Path, model_size="8B", quantize=None, scale_dt
  else:
    weights = load(str(model_path))
  if "model.embed_tokens.weight" in weights:
-    weights = convert_from_huggingface(weights, model, MODEL_PARAMS[model_size]["args"]["n_heads"], MODEL_PARAMS[model_size]["args"]["n_kv_heads"])
+    weights = convert_from_huggingface(weights, MODEL_PARAMS[model_size]["args"]["n_layers"], MODEL_PARAMS[model_size]["args"]["n_heads"], MODEL_PARAMS[model_size]["args"]["n_kv_heads"])
  elif "token_embd.weight" in weights:
-    weights = convert_from_gguf(weights, model)
+    weights = convert_from_gguf(weights, MODEL_PARAMS[model_size]["args"]["n_layers"])
  weights = fix_bf16(weights)

  with Context(BEAM=0):
@@ -25,7 +25,7 @@ if __name__ == "__main__":
  Tensor.training = True
  optimizer = nn.optim.Adam(nn.state.get_parameters(model), lr=1e-4)
  warmup_count = getenv("WARMUP", 3)
-  for i in range(warmup_count):  # TODO: why does it take three and not two to stablize
+  for i in range(warmup_count):  # TODO: why does it take three and not two to stabilize
    GlobalCounters.reset()
    X = Tensor.empty(4, 64, dtype=dtypes.int).reshape(B, T)
    Y = Tensor.empty(4, 64, dtype=dtypes.int).reshape(B, T)
@@ -0,0 +1,157 @@
+# much taken from https://github.com/cloneofsimo/minRF
+from tinygrad import Tensor, nn, GlobalCounters, TinyJit
+from tinygrad.helpers import getenv, trange
+from extra.models.llama import Attention, FeedForward, precompute_freqs_cis
+
+def modulate(x:Tensor, shift:Tensor, scale:Tensor) -> Tensor: return x * (1 + scale.unsqueeze(1)) + shift.unsqueeze(1)
+
+# TODO: why doesn't the TimestepEmbedder from minRF work?
+class TimestepEmbedder:
+  def __init__(self, hidden_size): self.mlp = [nn.Linear(1, hidden_size), Tensor.silu, nn.Linear(hidden_size, hidden_size)]
+  def __call__(self, t:Tensor): return t.reshape(-1, 1).sequential(self.mlp)
+
+class TransformerBlock:
+  def __init__(self, dim, n_heads, norm_eps=1e-5):
+    self.attention = Attention(dim, n_heads)
+    self.feed_forward = FeedForward(dim, 4*dim)
+    self.attention_norm = nn.LayerNorm(dim, eps=norm_eps)
+    self.ffn_norm = nn.LayerNorm(dim, eps=norm_eps)
+    self.adaLN_modulation = nn.Linear(dim, 6 * dim, bias=True)
+
+  def __call__(self, x:Tensor, freqs_cis:Tensor, adaln_input:Tensor):
+    shift_msa, scale_msa, gate_msa, shift_mlp, scale_mlp, gate_mlp = self.adaLN_modulation(adaln_input.silu()).chunk(6, dim=1)
+    x = x + gate_msa.unsqueeze(1) * self.attention(modulate(self.attention_norm(x), shift_msa, scale_msa), 0, freqs_cis)
+    x = x + gate_mlp.unsqueeze(1) * self.feed_forward(modulate(self.ffn_norm(x), shift_mlp, scale_mlp))
+    return x.contiguous().contiguous_backward()
+
+class FinalLayer:
+  def __init__(self, dim, patch_size, out_channels):
+    self.norm_final = nn.LayerNorm(dim, elementwise_affine=False, eps=1e-6)
+    self.linear = nn.Linear(dim, patch_size*patch_size*out_channels, bias=True)
+    self.adaLN_modulation = nn.Linear(dim, 2 * dim, bias=True)
+
+    # init weights/bias to 0
+    self.linear.weight.replace(self.linear.weight.zeros_like().contiguous())
+    self.linear.bias.replace(self.linear.bias.zeros_like().contiguous())
+
+  def __call__(self, x:Tensor, c:Tensor):
+    shift, scale = self.adaLN_modulation(c.silu()).chunk(2, dim=1)
+    x = modulate(self.norm_final(x), shift, scale)
+    return self.linear(x)
+
+# channels=1, input_size=32, dim=64, n_layers=6, n_heads=4, num_classes=10
+class DiT_Llama:
+  def __init__(self, in_channels=1, dim=64, n_layers=6, n_heads=4, num_classes=10, patch_size=2):
+    self.patch_size = patch_size
+    self.out_channels = in_channels
+    self.num_classes = num_classes
+
+    self.init_conv_seq = [
+      nn.Conv2d(in_channels, dim // 2, kernel_size=5, padding=2, stride=1), Tensor.silu, nn.GroupNorm(32, dim//2),
+      nn.Conv2d(dim //2, dim // 2, kernel_size=5, padding=2, stride=1), Tensor.silu, nn.GroupNorm(32, dim//2),
+    ]
+
+    self.x_embedder = nn.Linear(self.patch_size * self.patch_size * dim // 2, dim, bias=True)
+    self.t_embedder = TimestepEmbedder(dim)
+    self.y_embedder = nn.Embedding(num_classes+1, dim)
+    self.final_layer = FinalLayer(dim, self.patch_size, self.out_channels)
+
+    self.freqs_cis = precompute_freqs_cis(dim // n_heads, 4096)
+    self.layers = [TransformerBlock(dim, n_heads) for _ in range(n_layers)]
+
+  def unpatchify(self, x:Tensor):
+    c, p = self.out_channels, self.patch_size
+    h = w = int(x.shape[1] ** 0.5)
+    x = x.reshape(shape=(x.shape[0], h, w, p, p, c))
+    x = x.rearrange("n h w p q c -> n c h p w q")
+    return x.reshape(shape=(x.shape[0], c, h * p, h * p))
+
+  def patchify(self, x:Tensor):
+    B, C, H, W = x.shape
+    x = x.reshape(B, C, H // self.patch_size, self.patch_size, W // self.patch_size, self.patch_size)
+    x = x.permute(0, 2, 4, 1, 3, 5).flatten(-3).flatten(1, 2)
+    return x  # B <H*W ish> <C*patch_size*patch_size>
+
+  def __call__(self, x:Tensor, t:Tensor, y:Tensor) -> Tensor:
+    x = x.sequential(self.init_conv_seq)
+    x = self.patchify(x)
+    x = self.x_embedder(x)
+    adaln_input = self.t_embedder(t) + self.y_embedder(y)
+    adaln_input = adaln_input.contiguous()
+    for layer in self.layers:
+      x = layer(x, self.freqs_cis[:, :x.size(1)], adaln_input=adaln_input)
+    x = self.final_layer(x, adaln_input)
+    return self.unpatchify(x)
+
+  def rf(self, x:Tensor, cond:Tensor):
+    b = x.shape[0]
+    # self.ln is True
+    t = Tensor.randn((b,)).sigmoid()
+    texp = t.view([b, *([1] * len(x.shape[1:]))])
+
+    # conditional dropout
+    dropout_prob = 0.1
+    cond = (Tensor.rand(cond.shape[0]) < dropout_prob).where(cond.full_like(self.num_classes), cond)
+
+    # this is rectified flow
+    z1 = x.randn_like()
+    zt = (1 - texp) * x + texp * z1
+    vtheta = self(zt, t, cond)
+
+    # MSE loss
+    return ((z1 - x) - vtheta).square().mean()
+
+  def sample(self, z, cond, null_cond, sample_steps=50, cfg=2.0):
+    b = z.size(0)
+    dt = Tensor.full((b,)+(1,)*len(z.shape[1:]), fill_value=1.0/sample_steps).contiguous()
+    images = [z]
+    for i in range(sample_steps, 0, -1):
+      t = Tensor.full((b,), fill_value=i/sample_steps).contiguous()
+      vc = self(z, t, cond)
+      vu = self(z, t, null_cond)
+      vc = vu + cfg * (vc - vu)
+      z = z - dt * vc
+      z = z.contiguous()
+      images.append(z)
+    return images
+
+def mviz(t:Tensor):
+  assert len(t.shape) == 4 and t.shape[1] == 1
+  ft = t.permute(1,2,0,3).reshape(32, -1)
+  assert ft.shape[-1]%32 == 0
+  print("")
+  for y in ((ft+1)/2).clamp(0,1).tolist():
+    ln = [f"\033[38;5;{232+int(x*23)}m██" for x in y]
+    print(''.join(ln) + "\033[0m")
+
+if __name__ == "__main__":
+  X_train, Y_train, X_test, Y_test = nn.datasets.mnist()
+  X_train = X_train.pad((2,2,2,2))
+  X_train = ((X_train.float()/255)-0.5)/0.5
+  Y_train = Y_train.int()
+
+  model = DiT_Llama(patch_size=getenv("PATCH_SIZE", 2))
+  for r in nn.state.get_parameters(model): r.realize()
+  optimizer = nn.optim.Adam(nn.state.get_parameters(model), lr=5e-4)
+
+  @TinyJit
+  @Tensor.train()
+  def train_step():
+    if getenv("OVERFIT"): samples = Tensor.zeros(getenv("BS", 256), dtype='int')
+    else: samples = Tensor.randint(getenv("BS", 256), high=X_train.shape[0])
+    optimizer.zero_grad()
+    loss = model.rf(X_train[samples], Y_train[samples])
+    loss.backward()
+    optimizer.step()
+    return loss
+
+  @TinyJit
+  @Tensor.test()
+  def sample(z:Tensor, cond:Tensor) -> Tensor:
+    return model.sample(z, cond, Tensor.full_like(cond, 10), sample_steps=getenv("SAMPLE_STEPS", 20))[-1]
+
+  for steps in (t:=trange(getenv("STEPS", 5000))):
+    if steps%10 == 0: mviz(sample(Tensor.randn(3, 1, 32, 32), Tensor([5,0,4], dtype='int')))
+    GlobalCounters.reset()
+    loss = train_step()
+    t.set_description(f"loss: {loss.item():9.2f}")
@@ -532,7 +532,7 @@ if __name__ == "__main__":
  def load_retinanet(val):
    from extra.datasets.openimages import BASEDIR, download_dataset
    from pycocotools.coco import COCO
-    dataset = COCO(download_dataset(base_dir:=getenv("BASE_DIR", BASEDIR), "validation" if val else "train"))
+    dataset = COCO(download_dataset(base_dir:=getenv("BASEDIR", BASEDIR), "validation" if val else "train"))
    with tqdm(total=len(dataset.imgs.keys())) as pbar:
      for x in batch_load_retinanet(dataset, val, base_dir):
        pbar.update(x[0].shape[0])
@@ -295,3 +295,62 @@ def generate_anchors(input_size:tuple[int, int], scales:Optional[tuple[Tensor, .
    anchors.append((shifts[:, None] + base_anchors[None, :]).reshape(-1, 4))

  return anchors
+
+
+class BoxCoder(object):
+  def __init__(self, weights, bbox_xform_clip=math.log(1000. / 16), apply_to_remove=True):
+    self.weights = weights
+    self.bbox_xform_clip = bbox_xform_clip
+    self.apply_to_remove = apply_to_remove
+
+  def encode(self, reference_boxes, proposals):
+    TO_REMOVE = self.apply_to_remove  # TODO remove
+    ex_widths = proposals[..., 2] - proposals[..., 0] + TO_REMOVE
+    ex_heights = proposals[..., 3] - proposals[..., 1] + TO_REMOVE
+    ex_ctr_x = proposals[..., 0] + 0.5 * ex_widths
+    ex_ctr_y = proposals[..., 1] + 0.5 * ex_heights
+
+    gt_widths = reference_boxes[..., 2] - reference_boxes[..., 0] + TO_REMOVE
+    gt_heights = reference_boxes[..., 3] - reference_boxes[..., 1] + TO_REMOVE
+    gt_ctr_x = reference_boxes[..., 0] + 0.5 * gt_widths
+    gt_ctr_y = reference_boxes[..., 1] + 0.5 * gt_heights
+
+    wx, wy, ww, wh = self.weights
+    targets_dx = wx * (gt_ctr_x - ex_ctr_x) / ex_widths
+    targets_dy = wy * (gt_ctr_y - ex_ctr_y) / ex_heights
+    targets_dw = ww * Tensor.log(gt_widths / ex_widths)
+    targets_dh = wh * Tensor.log(gt_heights / ex_heights)
+
+    targets = Tensor.stack(targets_dx, targets_dy, targets_dw, targets_dh, dim=-1)
+    return targets
+
+  def decode(self, rel_codes, boxes):
+    boxes = boxes.cast(rel_codes.dtype)
+    rel_codes = rel_codes
+
+    TO_REMOVE = self.apply_to_remove  # TODO remove
+    widths = boxes[:, 2] - boxes[:, 0] + TO_REMOVE
+    heights = boxes[:, 3] - boxes[:, 1] + TO_REMOVE
+    ctr_x = boxes[:, 0] + 0.5 * widths
+    ctr_y = boxes[:, 1] + 0.5 * heights
+
+    wx, wy, ww, wh = self.weights
+    dx = rel_codes[:, 0::4] / wx
+    dy = rel_codes[:, 1::4] / wy
+    dw = rel_codes[:, 2::4] / ww
+    dh = rel_codes[:, 3::4] / wh
+
+    # Prevent sending too large values into Tensor.exp()
+    dw = dw.clip(min_=dw.min(), max_=self.bbox_xform_clip)
+    dh = dh.clip(min_=dh.min(), max_=self.bbox_xform_clip)
+
+    pred_ctr_x = dx * widths[:, None] + ctr_x[:, None]
+    pred_ctr_y = dy * heights[:, None] + ctr_y[:, None]
+    pred_w = dw.exp() * widths[:, None]
+    pred_h = dh.exp() * heights[:, None]
+    x = pred_ctr_x - 0.5 * pred_w
+    y = pred_ctr_y - 0.5 * pred_h
+    w = pred_ctr_x + 0.5 * pred_w - 1
+    h = pred_ctr_y + 0.5 * pred_h - 1
+    pred_boxes = Tensor.stack(x, y, w, h).permute(1,2,0).reshape(rel_codes.shape[0], rel_codes.shape[1])
+    return pred_boxes
@@ -53,7 +53,9 @@ class EmbeddingBert(nn.Embedding):
    arange_shp, weight_shp, big_shp = (1, 1, self.vocab_sz, 1), (1, 1, self.vocab_sz, self.embed_sz), idx.shape+(self.vocab_sz, self.embed_sz,)
    if not hasattr(self, 'arange'): self.arange = Tensor.arange(self.vocab_sz, requires_grad=False, device=self.weight.device).reshape(arange_shp)
    arange, idx, vals = self.arange.expand(big_shp), idx.reshape(idx.shape+(1, 1,)).expand(big_shp), self.weight.cast(dtypes.default_float).reshape(weight_shp).expand(big_shp)
-    return (arange == idx).mul(vals).sum(2, dtype=vals.dtype)
+    # TODO: contiguous() here because the embedding dropout creates different asts on each device, and search becomes very slow.
+    # Should fix with fixing random ast on multi device, and fuse arange to make embedding fast.
+    return (arange == idx).mul(vals).sum(2, dtype=vals.dtype).contiguous()

 class LayerNormBert:
  def __init__(self, normalized_shape:Union[int, tuple[int, ...]], eps:float=1e-12, elementwise_affine:bool=True):
@@ -66,3 +68,62 @@ class LayerNormBert:
    xn = x.cast(dtypes.float32).layernorm(eps=self.eps, axis=self.axis).cast(x.dtype)
    if not self.elementwise_affine: return xn
    return (xn * self.weight.cast(dtypes.default_float) + self.bias.cast(dtypes.default_float))
+
+class FrozenBatchNorm2dRetinaNet(nn.BatchNorm2d):
+  def __init__(self, sz:int, eps=1e-5, affine=True, track_running_stats=True, momentum=0.1):
+    self.eps, self.track_running_stats, self.momentum = eps, track_running_stats, momentum
+
+    self.weight = Tensor.ones(sz, dtype=dtypes.float32, requires_grad=False) if affine else None
+    self.bias = Tensor.zeros(sz, dtype=dtypes.float32, requires_grad=False) if affine else None
+
+    if track_running_stats: self.running_mean, self.running_var = Tensor.zeros(sz, dtype=dtypes.float32, requires_grad=False), Tensor.ones(sz, dtype=dtypes.float32, requires_grad=False)
+    self.num_batches_tracked = Tensor.zeros(1, dtype=dtypes.long, requires_grad=False)
+
+  def __call__(self, x:Tensor) -> Tensor:
+    batch_mean, batch_var = super().calc_stats(x.cast(dtypes.float32))
+    if self.track_running_stats and Tensor.training:
+      self.running_mean.assign((1-self.momentum) * self.running_mean + self.momentum * batch_mean.detach().cast(self.running_mean.dtype))
+      self.running_var.assign((1-self.momentum) * self.running_var + self.momentum * x.numel()/(x.numel()-x.shape[1]) * batch_var.detach().cast(self.running_var.dtype))
+      self.num_batches_tracked += 1
+    return x.cast(dtypes.float32).batchnorm(self.weight, self.bias, batch_mean, batch_var.add(self.eps).rsqrt()).cast(x.dtype)
+
+class Conv2dNormalRetinaNet(nn.Conv2d):
+  def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...],
+               stride:int=1, padding:int|tuple[int, ...]|str=0, dilation:int=1, groups:int=1,
+               bias:bool=True, prior_prob:float|None=None):
+    super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias)
+    self.weight = Tensor.normal(*self.weight.shape, std=0.01, dtype=dtypes.float32)
+    if bias:
+      if prior_prob:
+        prior_prob = Tensor(prior_prob, device=self.bias.device, dtype=dtypes.float32).expand(*self.bias.shape)
+        self.bias = -(((1 - prior_prob) / prior_prob).log())
+      else: self.bias = Tensor.zeros_like(self.bias, dtype=dtypes.float32)
+
+  def __call__(self, x:Tensor) -> Tensor:
+    return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None,
+                    groups=self.groups, stride=self.stride, padding=self.padding)
+
+class Conv2dKaimingUniformRetinaNet(nn.Conv2d):
+  def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...],
+               stride:int=1, padding:int|tuple[int, ...]|str=0, dilation:int=1, groups:int=1,
+               bias:bool=True):
+    super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias)
+    self.weight = Tensor.kaiming_uniform(*self.weight.shape, a=1, dtype=dtypes.float32)
+    if bias: self.bias = Tensor.zeros_like(self.bias, dtype=dtypes.float32)
+
+  def __call__(self, x:Tensor) -> Tensor:
+    return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None,
+                    groups=self.groups, stride=self.stride, padding=self.padding)
+
+class Conv2dRetinaNet(nn.Conv2d):
+  def __init__(self, in_channels:int, out_channels:int, kernel_size:int|tuple[int, ...],
+               stride:int=1, padding:int|tuple[int, ...]|str=0, dilation:int=1, groups:int=1,
+               bias:bool=True):
+    super().__init__(in_channels, out_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=groups, bias=bias)
+    scale = 1 / math.sqrt(in_channels * prod(self.kernel_size))
+    self.weight = Tensor.uniform(out_channels, in_channels//groups, *self.kernel_size, low=-scale, high=scale, dtype=dtypes.float32)
+    self.bias: Tensor|None = Tensor.uniform(out_channels, low=-scale, high=scale, dtype=dtypes.float32) if bias else None
+
+  def __call__(self, x:Tensor) -> Tensor:
+    return x.conv2d(self.weight.cast(dtypes.default_float), self.bias.cast(dtypes.default_float) if self.bias is not None else None,
+                    groups=self.groups, stride=self.stride, dilation=self.dilation, padding=self.padding)
@@ -81,47 +81,43 @@ def eval_unet3d():

 def eval_retinanet():
  # RetinaNet with ResNeXt50_32X4D
+  from examples.mlperf.dataloader import batch_load_retinanet
+  from extra.datasets.openimages import normalize, download_dataset, BASEDIR
  from extra.models.resnet import ResNeXt50_32X4D
  from extra.models.retinanet import RetinaNet
-  mdl = RetinaNet(ResNeXt50_32X4D())
-  mdl.load_from_pretrained()
-
-  input_mean = Tensor([0.485, 0.456, 0.406]).reshape(1, -1, 1, 1)
-  input_std = Tensor([0.229, 0.224, 0.225]).reshape(1, -1, 1, 1)
-  def input_fixup(x):
-    x = x.permute([0,3,1,2]) / 255.0
-    x -= input_mean
-    x /= input_std
-    return x
-
-  from extra.datasets.openimages import download_dataset, iterate, BASEDIR
  from pycocotools.coco import COCO
  from pycocotools.cocoeval import COCOeval
  from contextlib import redirect_stdout
-  coco = COCO(download_dataset(base_dir:=getenv("BASE_DIR", BASEDIR), 'validation'))
+  tlog("imports")
+
+  mdl = RetinaNet(ResNeXt50_32X4D())
+  mdl.load_from_pretrained()
+  tlog("loaded models")
+
+  coco = COCO(download_dataset(base_dir:=getenv("BASEDIR", BASEDIR), 'validation'))
  coco_eval = COCOeval(coco, iouType="bbox")
  coco_evalimgs, evaluated_imgs, ncats, narea = [], [], len(coco_eval.params.catIds), len(coco_eval.params.areaRng)
+  tlog("loaded dataset")

-  from tinygrad.engine.jit import TinyJit
-  mdlrun = TinyJit(lambda x: mdl(input_fixup(x)).realize())
-
-  n, bs = 0, 8
+  iterator = batch_load_retinanet(coco, True, Path(base_dir), getenv("BS", 8), shuffle=False)
+  def data_get():
+    x, img_ids, img_sizes, cookie = next(iterator)
+    return x.to(Device.DEFAULT).realize(), img_ids, img_sizes, cookie
+  n = 0
+  proc = data_get()
+  tlog("loaded initial data")
  st = time.perf_counter()
-  for x, targets in iterate(coco, base_dir, bs):
-    dat = Tensor(x.astype(np.float32))
-    mt = time.perf_counter()
-    if dat.shape[0] == bs:
-      outs = mdlrun(dat).numpy()
-    else:
-      mdlrun._jit_cache = []
-      outs =  mdl(input_fixup(dat)).numpy()
-    et = time.perf_counter()
-    predictions = mdl.postprocess_detections(outs, input_size=dat.shape[1:3], orig_image_sizes=[t["image_size"] for t in targets])
-    ext = time.perf_counter()
-    n += len(targets)
-    print(f"[{n}/{len(coco.imgs)}] == {(mt-st)*1000:.2f} ms loading data, {(et-mt)*1000:.2f} ms to run model, {(ext-et)*1000:.2f} ms for postprocessing")
-    img_ids = [t["image_id"] for t in targets]
-    coco_results  = [{"image_id": targets[i]["image_id"], "category_id": label, "bbox": box.tolist(), "score": score}
+  while proc is not None:
+    GlobalCounters.reset()
+    proc = (mdl(normalize(proc[0])), proc[1], proc[2], proc[3])
+    run = time.perf_counter()
+    # load the next data here
+    try: next_proc = data_get()
+    except StopIteration: next_proc = None
+    nd = time.perf_counter()
+    predictions, img_ids = mdl.postprocess_detections(proc[0].numpy(), orig_image_sizes=proc[2]), proc[1]
+    pd = time.perf_counter()
+    coco_results  = [{"image_id": img_ids[i], "category_id": label, "bbox": box.tolist(), "score": score}
      for i, prediction in enumerate(predictions) for box, score, label in zip(*prediction.values())]
    with redirect_stdout(None):
      coco_eval.cocoDt = coco.loadRes(coco_results)
@@ -129,13 +125,18 @@ def eval_retinanet():
      coco_eval.evaluate()
    evaluated_imgs.extend(img_ids)
    coco_evalimgs.append(np.array(coco_eval.evalImgs).reshape(ncats, narea, len(img_ids)))
-    st = time.perf_counter()
+    n += len(proc[0])
+    et = time.perf_counter()
+    tlog(f"****** {(run-st)*1000:7.2f} ms to enqueue, {(et-run)*1000:7.2f} ms to realize ({(nd-run)*1000:7.2f} ms fetching, {(pd-run)*1000:4.2f} ms postprocess_detections). {(len(proc))/(et-st):8.2f} examples/sec. {GlobalCounters.global_ops*1e-12/(et-st):5.2f} TFLOPS")
+    st = et
+    proc, next_proc = next_proc, None

  coco_eval.params.imgIds = evaluated_imgs
  coco_eval._paramsEval.imgIds = evaluated_imgs
  coco_eval.evalImgs = list(np.concatenate(coco_evalimgs, -1).flatten())
  coco_eval.accumulate()
  coco_eval.summarize()
+  tlog("done")

 def eval_rnnt():
  # RNN-T
@@ -1,11 +1,11 @@
-import os, time, math, functools
+import os, time, math, functools, random
 from pathlib import Path
 import multiprocessing

 from tinygrad import Device, GlobalCounters, Tensor, TinyJit, dtypes
-from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, FUSE_CONV_BW
+from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, FUSE_CONV_BW, Profiling
 from tinygrad.nn.state import get_parameters, get_state_dict, safe_load, safe_save
-from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup
+from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, Adam

 from extra.lr_scheduler import LRSchedulerGroup
 from examples.mlperf.helpers import get_training_state, load_training_state
@@ -343,8 +343,347 @@ def train_resnet():
        safe_save(get_training_state(model, optimizer_group, scheduler_group), fn)

 def train_retinanet():
-  # TODO: Retinanet
-  pass
+  from contextlib import redirect_stdout
+  from examples.mlperf.dataloader import batch_load_retinanet
+  from examples.mlperf.initializers import FrozenBatchNorm2dRetinaNet, Conv2dNormalRetinaNet, Conv2dKaimingUniformRetinaNet, Linear, Conv2dRetinaNet
+  from extra.datasets.openimages import MLPERF_CLASSES, BASEDIR, download_dataset, normalize, get_dataset_count
+  from extra.models import resnet, retinanet
+  from pycocotools.coco import COCO
+  from pycocotools.cocoeval import COCOeval
+  from tinygrad.helpers import colored
+  from typing import Iterator
+
+  import numpy as np
+
+  config, target_metric = {}, 0.34
+
+  config["SEED"] = SEED = getenv("SEED", random.SystemRandom().randint(0, 2**32 - 1))
+  Tensor.manual_seed(SEED)
+
+  NUM_CLASSES = len(MLPERF_CLASSES)
+  BASEDIR = getenv("BASEDIR", BASEDIR)
+  BENCHMARK = getenv("BENCHMARK")
+  INITMLPERF = getenv("INITMLPERF")
+  RUNMLPERF = getenv("RUNMLPERF")
+
+  if getenv("LOGMLPERF"):
+    from mlperf_logging import mllog
+    import mlperf_logging.mllog.constants as mllog_constants
+
+    mllog.config(filename=f"result_retinanet_{SEED}.log")
+    mllog.config(root_dir=Path(__file__).parents[3].as_posix())
+    MLLOGGER = mllog.get_mllogger()
+    MLLOGGER.logger.propagate = False
+
+    if INITMLPERF:
+      assert BENCHMARK, "BENCHMARK must be set for INITMLPERF"
+      MLLOGGER.event(key=mllog_constants.SUBMISSION_ORG, value="tinycorp")
+      MLLOGGER.event(key=mllog_constants.SUBMISSION_PLATFORM, value=getenv("SUBMISSION_PLATFORM", "tinybox"))
+      MLLOGGER.event(key=mllog_constants.SUBMISSION_DIVISION, value=mllog_constants.CLOSED)
+      MLLOGGER.event(key=mllog_constants.SUBMISSION_STATUS, value=mllog_constants.ONPREM)
+
+      MLLOGGER.event(key=mllog_constants.SUBMISSION_BENCHMARK, value=mllog_constants.RETINANET)
+
+      diskcache_clear()
+      MLLOGGER.event(key=mllog_constants.CACHE_CLEAR, value=True)
+      MLLOGGER.start(key=mllog_constants.INIT_START)
+
+    if RUNMLPERF:
+      MLLOGGER.start(key=mllog_constants.RUN_START)
+      MLLOGGER.event(key=mllog_constants.SEED, value=SEED)
+  else:
+    MLLOGGER = None
+
+  config["gpus"] = GPUS = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 6))]
+
+  for x in GPUS: Device[x]
+  print(f"training on {GPUS}")
+
+  def _freeze_backbone_layers(backbone:resnet.ResNet, trainable_layers:int):
+    layers_to_train = ["layer4", "layer3", "layer2", "layer1", "conv1"][:trainable_layers]
+    for k, v in get_state_dict(backbone).items():
+      if all([not k.startswith(layer) for layer in layers_to_train]):
+        v.requires_grad = False
+
+  def _data_get(it:Iterator[tuple[Tensor, ...]], val:bool=False):
+    if val:
+      x, img_ids, img_sizes, cookie = next(it)
+      return x.shard(GPUS, axis=0), img_ids, img_sizes, cookie
+
+    x, y_boxes, y_labels, matches, anchors, cookie = next(it)
+    return x.shard(GPUS, axis=0), y_boxes.shard(GPUS, axis=0), y_labels.shard(GPUS, axis=0), matches.shard(GPUS, axis=0), anchors.shard(GPUS, axis=0), cookie
+
+  def _fake_data_get(bs:int, val:bool=False):
+    x = Tensor.empty(bs, 800, 800, 3, dtype=dtypes.uint8)
+    if val:
+      img_ids, img_sizes = [0] * bs, [(800, 800)] * bs
+      return x.shard(GPUS, axis=0), img_ids, img_sizes, None
+
+    y_boxes = Tensor.empty(bs, 120087, 4, dtype=dtypes.float32)
+    y_labels = Tensor.empty(bs, 120087, dtype=dtypes.int64)
+    matches = Tensor.empty(bs, 120087, dtype=dtypes.int64)
+    anchors = Tensor.empty(bs, 120087, 4, dtype=dtypes.float64)
+    return x.shard(GPUS, axis=0), y_boxes.shard(GPUS, axis=0), y_labels.shard(GPUS, axis=0), matches.shard(GPUS, axis=0), anchors.shard(GPUS, axis=0), None
+
+  @TinyJit
+  def _train_step(model, optim, loss_scaler, x, **kwargs):
+    optim.zero_grad()
+
+    losses = model(normalize(x, GPUS), **kwargs)
+    loss = sum(losses.values())
+
+    (loss * loss_scaler).backward()
+    for t in optim.params: t.grad = t.grad / loss_scaler
+
+    optim.step()
+
+    return loss.realize(), losses
+
+  @TinyJit
+  def _eval_step(model, x, **kwargs):
+    out = model(normalize(x, GPUS), **kwargs)
+    # reassemble on GPUS[0] before sending back to CPU for speed
+    return out.to(GPUS[0]).realize()
+
+  # ** hyperparameters **
+  config["BS"] = BS = getenv("BS", 16 * len(GPUS) if dtypes.default_float == dtypes.float16 else 12 * len(GPUS))
+  config["EVAL_BS"] = EVAL_BS = getenv("EVAL_BS", BS)
+  config["EPOCHS"] = EPOCHS = getenv("EPOCHS", 4)
+  config["TRAIN_BEAM"] = TRAIN_BEAM = getenv("TRAIN_BEAM", BEAM.value)
+  config["EVAL_BEAM"] = EVAL_BEAM = getenv("EVAL_BEAM", BEAM.value)
+  config["LR"] = lr = getenv("LR", 9.5e-5 * (BS / 96))
+  config["LOSS_SCALER"] = loss_scaler = getenv("LOSS_SCALER", 2**11 if dtypes.default_float == dtypes.float16 else 1.0)
+  config["DEFAULT_FLOAT"] = dtypes.default_float.name
+  config["EVAL_FREQ"] = eval_freq = getenv("EVAL_FREQ", 1)
+
+  # ** initialize wandb **
+  if (WANDB:=getenv("WANDB")):
+    import wandb
+    wandb.init(config=config, project="MLPerf-RetinaNet")
+
+  # ** model initializers **
+  resnet.BatchNorm = FrozenBatchNorm2dRetinaNet
+  resnet.Linear = Linear
+  resnet.Conv2d = Conv2dRetinaNet
+
+  retinanet.ConvHead = Conv2dNormalRetinaNet
+  retinanet.ConvClassificationHeadLogits = functools.partial(Conv2dNormalRetinaNet, prior_prob=0.01)
+  retinanet.ConvFPN = Conv2dKaimingUniformRetinaNet
+
+  # ** model setup **
+  backbone = resnet.ResNeXt50_32X4D(num_classes=None)
+  if RUNMLPERF:
+    backbone.load_from_pretrained()
+  _freeze_backbone_layers(backbone, 3)
+
+  model = retinanet.RetinaNet(backbone, num_classes=NUM_CLASSES)
+  params = get_parameters(model)
+
+  if not RUNMLPERF:
+    # for init, zero out all weights
+    for p in params:
+      p = p.assign(Tensor.zeros_like(p).contiguous()).realize()
+
+  if len(GPUS) > 1:
+    for p in params: p.to_(GPUS)
+
+  step_times, start_epoch = [], 0
+
+  # ** optimizer **
+  optim = Adam(params, lr=lr)
+
+  # ** dataset **
+  config["STEPS_IN_TRAIN_EPOCH"] = steps_in_train_epoch = round_up(get_dataset_count((base_dir_path:=Path(BASEDIR)), False), BS) // BS
+  config["STEPS_IN_VAL_EPOCH"] = steps_in_val_epoch = (round_up(get_dataset_count(base_dir_path, True), EVAL_BS) // EVAL_BS)
+
+  # log mlperf hparams
+  if MLLOGGER:
+    if RUNMLPERF:
+      MLLOGGER.event(key=mllog_constants.GLOBAL_BATCH_SIZE, value=config["BS"])
+      MLLOGGER.event(key=mllog_constants.TRAIN_SAMPLES, value=config["STEPS_IN_TRAIN_EPOCH"])
+      MLLOGGER.event(key=mllog_constants.EVAL_SAMPLES, value=config["STEPS_IN_VAL_EPOCH"])
+      MLLOGGER.event(key=mllog_constants.EPOCH_COUNT, value=config["EPOCHS"])
+      MLLOGGER.event(key=mllog_constants.FIRST_EPOCH_NUM, value=start_epoch)
+
+      MLLOGGER.event(key=mllog_constants.OPT_NAME, value=mllog_constants.ADAM)
+      MLLOGGER.event(key=mllog_constants.OPT_BASE_LR, value=config["LR"])
+      MLLOGGER.event(key=mllog_constants.OPT_WEIGHT_DECAY, value=0)
+      MLLOGGER.event(key=mllog_constants.OPT_LR_WARMUP_EPOCHS, value=0)
+      MLLOGGER.event(key=mllog_constants.OPT_LR_WARMUP_FACTOR, value=0)
+      MLLOGGER.event(key=mllog_constants.GRADIENT_ACCUMULATION_STEPS, value=1)
+
+  if RUNMLPERF:
+    train_dataset = COCO(download_dataset(BASEDIR, "train"))
+    val_dataset = COCO(download_dataset(BASEDIR, "validation"))
+    coco_val = COCOeval(cocoGt=val_dataset, iouType="bbox")
+
+  print(f"training with batch size {BS} for {EPOCHS} epochs")
+
+  for e in range(start_epoch, EPOCHS):
+    # ** training loop **
+    if MLLOGGER and RUNMLPERF:
+      MLLOGGER.start(key=mllog_constants.EPOCH_START, value=e + 1, metadata={"epoch_num": e + 1})
+
+    BEAM.value = TRAIN_BEAM
+
+    if not RUNMLPERF:
+      i, proc = 0, _fake_data_get(BS)
+    else:
+      train_dataloader = batch_load_retinanet(train_dataset, False, base_dir_path, batch_size=BS, seed=SEED)
+      it = iter(tqdm(train_dataloader, total=steps_in_train_epoch, desc=f"epoch {e + 1}", disable=BENCHMARK))
+      i, proc = 0, _data_get(it)
+
+    prev_cookies = []
+    st = time.perf_counter()
+
+    while proc is not None:
+      GlobalCounters.reset()
+
+      x, y_bboxes, y_labels, matches, anchors, proc = proc
+      loss, losses = _train_step(model, optim, loss_scaler, x, labels=y_labels, matches=matches, anchors=anchors, bboxes=y_bboxes)
+
+      pt = time.perf_counter()
+
+      if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = []  # free previous cookies after gpu work has been enqueued
+      try:
+        if not RUNMLPERF:
+          next_proc = _fake_data_get(BS)
+        else:
+          next_proc = _data_get(it)
+      except StopIteration:
+        next_proc = None
+
+      dt = time.perf_counter()
+
+      device_str = loss.device if isinstance(loss.device, str) else f"{loss.device[0]} * {len(loss.device)}"
+      loss = loss.item()
+
+      cl = time.perf_counter()
+      if BENCHMARK: step_times.append(cl - st)
+
+      if not math.isfinite(loss):
+        print("loss is nan")
+        return
+
+      tqdm.write(
+        f"{i:5} {((cl - st)) * 1000.0:7.2f} ms run, {(pt - st) * 1000.0:7.2f} ms python, {(dt - pt) * 1000.0:6.2f} ms fetch data, "
+        f"{(cl - dt) * 1000.0:7.2f} ms {device_str}, {loss:5.2f} loss, {losses['classification_loss'].item():5.4f} classification loss, {losses['regression_loss'].item():5.4f} regression loss, "
+        f"{optim.lr.numpy()[0]:.6f} LR, {GlobalCounters.mem_used / 1e9:.2f} GB used, {GlobalCounters.global_ops * 1e-9 / (cl - st):9.2f} GFLOPS"
+      )
+
+      if WANDB:
+        wandb.log({"lr": optim.lr.numpy(), "train/loss": loss, "train/classification_loss": losses["classification_loss"].item(), "train/regression_loss": losses["regression_loss"].item(),
+                  "train/step_time": cl - st, "train/python_time": pt - st, "train/data_time": dt - pt, "train/cl_time": cl - dt,
+                  "train/GFLOPS": GlobalCounters.global_ops * 1e-9 / (cl - st), "epoch": e + (i + 1) / steps_in_train_epoch})
+
+      st = cl
+      prev_cookies.append(proc)
+      proc, next_proc = next_proc, None  # return old cookie
+      i += 1
+
+      if i == BENCHMARK:
+        assert not math.isnan(loss)
+        median_step_time = sorted(step_times)[(BENCHMARK + 1) // 2]  # in seconds
+        estimated_total_minutes = int(median_step_time * steps_in_train_epoch * EPOCHS / 60)
+        print(f"Estimated training time: {estimated_total_minutes // 60}h{estimated_total_minutes % 60}m")
+        print(f"epoch global_ops: {steps_in_train_epoch * GlobalCounters.global_ops:_}, "
+              f"epoch global_mem: {steps_in_train_epoch * GlobalCounters.global_mem:_}")
+        # if we are doing beam search, run the first eval too
+        if (TRAIN_BEAM or EVAL_BEAM) and e == start_epoch: break
+        return
+
+    if MLLOGGER and RUNMLPERF:
+      MLLOGGER.event(key=mllog_constants.EPOCH_STOP, value=e + 1, metadata={"epoch_num": e + 1})
+
+    # ** eval loop **
+    if (e + 1) % eval_freq == 0:
+      if MLLOGGER and RUNMLPERF:
+        MLLOGGER.start(key=mllog_constants.EVAL_START, value=e + 1, metadata={"epoch_num": e + 1})
+
+      BEAM.value = EVAL_BEAM
+
+      if getenv("RESET_STEP", 1): _train_step.reset()
+
+      with Tensor.train(mode=False), Tensor.test():
+        if not RUNMLPERF:
+          i, proc = 0, _fake_data_get(EVAL_BS, val=(val:=True))
+        else:
+          val_dataloader = batch_load_retinanet(val_dataset, (val:=True), Path(BASEDIR), batch_size=EVAL_BS, shuffle=False, seed=SEED)
+          it = iter(tqdm(val_dataloader, total=steps_in_val_epoch))
+          i, proc = 0, _data_get(it, val=val)
+          val_img_ids, val_imgs, ncats, narea = [], [], len(coco_val.params.catIds), len(coco_val.params.areaRng)
+
+        eval_times, prev_cookies = [], []
+
+        while proc is not None:
+          GlobalCounters.reset()
+          st = time.time()
+
+          out, img_ids, img_sizes, proc = _eval_step(model, (x:=proc[0])).numpy(), proc[1], proc[2], proc[3]
+
+          if RUNMLPERF:
+            out = model.postprocess_detections(out, input_size=x.shape[1:3], orig_image_sizes=img_sizes)
+            coco_results  = [{"image_id": img_ids[i], "category_id": label, "bbox": box.tolist(), "score": score}
+              for i, prediction in enumerate(out) for box, score, label in zip(*prediction.values())]
+
+            with redirect_stdout(None):
+              coco_val.cocoDt = val_dataset.loadRes(coco_results)
+              coco_val.params.imgIds = img_ids
+              coco_val.evaluate()
+
+            val_img_ids.extend(img_ids)
+            val_imgs.append(np.array(coco_val.evalImgs).reshape(ncats, narea, len(img_ids)))
+
+          if len(prev_cookies) == getenv("STORE_COOKIES", 1): prev_cookies = []  # free previous cookies after gpu work has been enqueued
+          try:
+            if not RUNMLPERF:
+              next_proc = _fake_data_get(EVAL_BS, val=val)
+            else:
+              next_proc = _data_get(it, val=val)
+          except StopIteration:
+            next_proc = None
+
+          prev_cookies.append(proc)
+          proc, next_proc = next_proc, None
+          i += 1
+
+          et = time.time()
+          eval_times.append(et - st)
+
+          if i == BENCHMARK:
+            # assume INITMLPERF has BENCHMARK set
+            if MLLOGGER and INITMLPERF:
+              MLLOGGER.event(key=mllog_constants.INIT_STOP)
+            return
+
+        if getenv("RESET_STEP", 1): _eval_step.reset()
+        total_fw_time = sum(eval_times) / len(eval_times)
+
+        if RUNMLPERF:
+          coco_val.params.imgIds = val_img_ids
+          coco_val._paramsEval.imgIds = val_img_ids
+          coco_val.evalImgs = list(np.concatenate(val_imgs, -1).flatten())
+          coco_val.accumulate()
+          coco_val.summarize()
+
+          val_metric = coco_val.stats[0]
+
+          tqdm.write(f"eval time: {total_fw_time:.2f}, eval metric: {val_metric:.4f}")
+
+          if WANDB:
+            wandb.log({"eval/forward_time": total_fw_time, "eval/metric": val_metric, "epoch": e + 1})
+
+          if MLLOGGER:
+            MLLOGGER.event(key=mllog_constants.EVAL_ACCURACY, value=val_metric, metadata={"epoch_num": e + 1}, clear_line=True)
+            MLLOGGER.end(key=mllog_constants.EVAL_STOP, value=e + 1, metadata={"epoch_num": e + 1})
+
+          if val_metric >= target_metric:
+            print(colored(f"target metric reached: {val_metric:.2f}/{target_metric:.2f}", color="green"))
+
+            if MLLOGGER:
+              MLLOGGER.end(key=mllog_constants.RUN_STOP, metadata={"status": mllog_constants.SUCCESS})
+
+            break

 def train_unet3d():
  """
@@ -551,7 +890,7 @@ def train_unet3d():

        if mean_dice >= TARGET_METRIC:
          is_successful = True
-          save_checkpoint(get_state_dict(model), f"./ckpts/unet3d.safe")
+          save_checkpoint(get_state_dict(model), "./ckpts/unet3d.safe")
        elif mean_dice < 1e-6:
          print("Model diverging. Aborting.")
          diverged = True
@@ -583,12 +922,13 @@ def train_step_bert(model, optimizer, scheduler, loss_scaler:float, input_ids:Te
  loss = model.loss(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels)
  (loss * loss_scaler).backward()

-  global_norm = Tensor([0.0], dtype=dtypes.float32, device=optimizer[0].device).realize()
+  global_norm = Tensor([0.0], dtype=dtypes.float32, device=optimizer[0].device)
  for p in optimizer.params:
    p.grad = p.grad / loss_scaler
    global_norm += p.grad.float().square().sum()
-  global_norm = global_norm.sqrt()
-  for p in optimizer.params: p.grad = (p.grad / Tensor.where(global_norm > 1.0, global_norm, 1.0)).cast(p.grad.dtype)
+  global_norm = global_norm.sqrt().contiguous()
+  for p in optimizer.params:
+    p.grad = (global_norm > 1.0).where((p.grad/global_norm).cast(p.grad.dtype), p.grad)

  optimizer.step()
  scheduler.step()
@@ -637,7 +977,7 @@ def train_bert():
    MLLOGGER.logger.propagate = False

    if INITMLPERF:
-      assert BENCHMARK, f"BENCHMARK must be set for INITMLPERF"
+      assert BENCHMARK, "BENCHMARK must be set for INITMLPERF"
      MLLOGGER.event(key=mllog_constants.SUBMISSION_ORG, value="tinycorp")
      MLLOGGER.event(key=mllog_constants.SUBMISSION_PLATFORM, value=getenv("SUBMISSION_PLATFORM", "tinybox"))
      MLLOGGER.event(key=mllog_constants.SUBMISSION_DIVISION, value=mllog_constants.CLOSED)
@@ -659,8 +999,10 @@ def train_bert():
  BS                 = config["GLOBAL_BATCH_SIZE"]      = getenv("BS", 11 * len(GPUS) if dtypes.default_float in (dtypes.float16, dtypes.bfloat16) else 8 * len(GPUS))
  EVAL_BS            = config["EVAL_BS"]                = getenv("EVAL_BS", 1 * len(GPUS))
  max_lr             = config["OPT_BASE_LEARNING_RATE"] = getenv("OPT_BASE_LEARNING_RATE", 0.000175 * math.sqrt(BS/96))
+  opt_lamb_beta_1    = config["OPT_LAMB_BETA_1"]        = getenv("OPT_LAMB_BETA_1", 0.9)
+  opt_lamb_beta_2    = config["OPT_LAMB_BETA_2"]        = getenv("OPT_LAMB_BETA_2", 0.999)

-  train_steps        = config["TRAIN_STEPS"]            = getenv("TRAIN_STEPS", 3300000 // BS)
+  train_steps        = config["TRAIN_STEPS"]            = getenv("TRAIN_STEPS", 3600000 // BS)
  warmup_steps       = config["NUM_WARMUP_STEPS"]       = getenv("NUM_WARMUP_STEPS", 1)
  max_eval_steps     = config["MAX_EVAL_STEPS"]         = getenv("MAX_EVAL_STEPS", (10000 + EVAL_BS - 1) // EVAL_BS) # EVAL_BS * MAX_EVAL_STEPS >= 10000
  eval_step_freq     = config["EVAL_STEP_FREQ"]         = getenv("EVAL_STEP_FREQ", int((math.floor(0.05 * (230.23 * BS + 3000000) / 25000) * 25000) / BS)) # Round down
@@ -713,8 +1055,8 @@ def train_bert():
  # ** Optimizer **
  parameters_no_wd = [v for k, v in get_state_dict(model).items() if "bias" in k or "LayerNorm" in k]
  parameters = [x for x in parameters if x not in set(parameters_no_wd)]
-  optimizer_wd = LAMB(parameters, lr=max_lr, eps=epsilon, weight_decay=decay, adam=False)
-  optimizer_no_wd = LAMB(parameters_no_wd, lr=max_lr, eps=epsilon, weight_decay=0.0, adam=False)
+  optimizer_wd = LAMB(parameters, lr=max_lr, b1=opt_lamb_beta_1, b2=opt_lamb_beta_2, eps=epsilon, weight_decay=decay, adam=False)
+  optimizer_no_wd = LAMB(parameters_no_wd, lr=max_lr, b1=opt_lamb_beta_1, b2=opt_lamb_beta_2, eps=epsilon, weight_decay=0.0, adam=False)
  optimizer_group = OptimizerGroup(optimizer_wd, optimizer_no_wd)

  # ** LR scheduler **
@@ -733,8 +1075,8 @@ def train_bert():
      MLLOGGER.event(key=mllog_constants.OPT_NAME, value="LAMB")
      MLLOGGER.event(key=mllog_constants.OPT_BASE_LR, value=config["OPT_BASE_LEARNING_RATE"])
      MLLOGGER.event(key=mllog_constants.OPT_LAMB_WEIGHT_DECAY, value=config["DECAY"])
-      MLLOGGER.event(key=mllog_constants.OPT_LAMB_BETA_1, value=optimizer_wd.b1)
-      MLLOGGER.event(key=mllog_constants.OPT_LAMB_BETA_2, value=optimizer_wd.b2)
+      MLLOGGER.event(key=mllog_constants.OPT_LAMB_BETA_1, value=config["OPT_LAMB_BETA_1"])
+      MLLOGGER.event(key=mllog_constants.OPT_LAMB_BETA_2, value=config["OPT_LAMB_BETA_2"])
      MLLOGGER.event(key=mllog_constants.OPT_LAMB_LR_DECAY_POLY_POWER, value=config["POLY_POWER"])
      MLLOGGER.event(key=mllog_constants.OPT_LAMB_EPSILON, value=config["EPSILON"])

@@ -797,6 +1139,7 @@ def train_bert():

      device_str = parameters[0].device if isinstance(parameters[0].device, str) else f"{parameters[0].device[0]} * {len(parameters[0].device)}"
      loss = loss.item()
+      assert not math.isnan(loss)
      lr = lr.item()

      cl = time.perf_counter()
@@ -825,8 +1168,8 @@ def train_bert():
    if i % eval_step_freq == 0 or (BENCHMARK and i == BENCHMARK) or i == train_steps:
      if MLLOGGER and RUNMLPERF:
        MLLOGGER.start(key=mllog_constants.EVAL_START, value=None, metadata={"epoch_num": i*BS, "step_num": i})
-      if getenv("RESET_STEP", 0): train_step_bert.reset()
-      elif train_step_bert.captured is not None: train_step_bert.captured.free_intermediates()
+      if getenv("RESET_STEP"): train_step_bert.reset()
+      elif getenv("FREE_INTERMEDIATE", 1) and train_step_bert.captured is not None: train_step_bert.captured.free_intermediates()
      eval_lm_losses = []
      eval_clsf_losses = []
      eval_lm_accs = []
@@ -853,14 +1196,15 @@ def train_bert():
        et = time.time()
        eval_times.append(et - st)

-        if BENCHMARK and j == BENCHMARK:
+        if BENCHMARK and (j+1) == min(BENCHMARK, max_eval_steps):
          # assume INITMLPERF has BENCHMARK set
          if MLLOGGER and INITMLPERF:
            MLLOGGER.event(key=mllog_constants.INIT_STOP, value=None)
          return

-      if getenv("RESET_STEP", 0): eval_step_bert.reset()
-      elif eval_step_bert.captured is not None: eval_step_bert.captured.free_intermediates()
+      if getenv("RESET_STEP"): eval_step_bert.reset()
+      elif getenv("FREE_INTERMEDIATE", 1) and eval_step_bert.captured is not None: eval_step_bert.captured.free_intermediates()
+
      del eval_data
      avg_lm_loss = sum(eval_lm_losses) / len(eval_lm_losses)
      avg_clsf_loss = sum(eval_clsf_losses) / len(eval_clsf_losses)
@@ -873,7 +1217,7 @@ def train_bert():

      if WANDB:
        wandb.log({"eval/lm_loss": avg_lm_loss, "eval/clsf_loss": avg_clsf_loss, "eval/lm_accuracy": avg_lm_acc, \
-                    "eval/clsf_accuracy": avg_clsf_acc, "eval/forward_time": avg_fw_time})
+                    "eval/clsf_accuracy": avg_clsf_acc, "eval/forward_time": avg_fw_time, "epoch": (i+1)*BS})

      if MLLOGGER and RUNMLPERF:
        MLLOGGER.end(key=mllog_constants.EVAL_STOP, value=i*BS, metadata={"epoch_count": i*BS, "step_num": i, "samples_count": config["EVAL_BS"] * config["MAX_EVAL_STEPS"]})
@@ -900,11 +1244,14 @@ def train_bert():
        # stop once hitting the target
        break

+    # should not happen, BENCHMARK not properly terminated
+    if BENCHMARK: assert i < BENCHMARK, i
+
    if getenv("CKPT") and i % save_ckpt_freq == 0:
      if MLLOGGER and RUNMLPERF:
        if previous_step:
          MLLOGGER.end(key=mllog_constants.BLOCK_STOP, value=None, metadata={"first_epoch_num": 1, "epoch_num": 1, "first_step_num": i, "step_num": i, "step_count": i - previous_step})
-        MLLOGGER.start(key="checkpoint_start", value=None, metadata={"step_num" : i})
+        MLLOGGER.start(key="checkpoint_start", value=None, metadata={"step_num": i})
      if not os.path.exists(ckpt_dir := save_ckpt_dir): os.mkdir(ckpt_dir)
      if WANDB and wandb.run is not None:
        fn = f"{ckpt_dir}/{time.strftime('%Y%m%d_%H%M%S')}_{wandb.run.id}.safe"
@@ -934,4 +1281,4 @@ if __name__ == "__main__":
      nm = f"train_{m}"
      if nm in globals():
        print(f"training {m}")
-        globals()[nm]()
+        with Profiling(enabled=getenv("PYPROFILE")): globals()[nm]()
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1
+export MODEL="bert"
+export DEFAULT_FLOAT="HALF" GPUS=1 BS=128 EVAL_BS=128
+
+export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export IGNORE_JIT_FIRST_BEAM=1
+# export BEAM_LOG_SURPASS_MAX=1
+# export BASEDIR="/raid/datasets/wiki"
+
+export RESET_STEP=1
+export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2
+
+python3 examples/mlperf/model_train.py
@@ -0,0 +1,69 @@
+# 1. Problem
+
+This problem uses BERT for NLP.
+
+## Requirements
+
+Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0.
+```
+git clone https://github.com/tinygrad/tinygrad.git
+python3 -m pip install -e ".[mlperf]"
+```
+Also install gdown (for dataset), numpy, tqdm and tensorflow.
+```
+pip install gdown numpy tqdm tensorflow
+```
+
+### tinybox_green
+Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md)
+This is the default on production tinybox green.
+
+# 2. Directions
+
+## Steps to download and verify data
+
+### 1. Download raw data
+
+```
+BASEDIR="/raid/datasets/wiki" WIKI_TRAIN=1 VERIFY_CHECKSUM=1 python3 extra/datasets/wikipedia_download.py
+```
+
+### 2. Preprocess train and validation data
+
+Note: The number of threads used for preprocessing is limited by available memory. With 128GB of RAM, a maximum of 16 threads is recommended. 
+
+#### Training:
+```
+BASEDIR="/raid/datasets/wiki" NUM_WORKERS=16 python3 extra/datasets/wikipedia.py pre-train all
+```
+
+Generating a specific topic (Between 0 and 499)
+```
+BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-train 42
+```
+
+#### Validation:
+```
+BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval
+```
+## Running
+
+### tinybox_green
+
+#### Steps to run benchmark
+```
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh
+```
+
+### tinybox_red
+
+#### Steps to run benchmark
+```
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh
+```
+### tinybox_8xMI300X
+
+#### Steps to run benchmark
+```
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh
+```
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1
+export MODEL="bert"
+export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
+export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
+
+export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
+export BASEDIR="/raid/datasets/wiki"
+
+export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2
+
+python3 examples/mlperf/model_train.py
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1
+export MODEL="bert"
+export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
+
+# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54
+export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
+export TRAIN_STEPS=3900
+
+export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
+export BASEDIR="/raid/datasets/wiki"
+
+export WANDB=1 PARALLEL=0
+
+RUNMLPERF=1 python3 examples/mlperf/model_train.py
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1
+export MODEL="bert"
+export SUBMISSION_PLATFORM="tinybox_8xMI300X"
+export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024
+
+# similar to https://github.com/mlcommons/training_results_v3.1/blob/d06288b2bd675a9d88e0e6181f5bb5626b71ec19/Quanta_Cloud_Technology/results/D54U-3U/bert/result_1.txt#L54
+export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1
+export TRAIN_STEPS=3900
+
+export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0
+export BASEDIR="/raid/datasets/wiki"
+
+# pip install -e ".[mlperf]"
+export LOGMLPERF=1
+
+export SEED=$RANDOM
+DATETIME=$(date "+%m%d%H%M")
+LOGFILE="bert_8xMI300x_${DATETIME}_${SEED}.log"
+
+# init  # TODO: without DEBUG=2 it hangs
+BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 DEBUG=2 python3 examples/mlperf/model_train.py | tee $LOGFILE
+
+# run
+PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE
@@ -4,24 +4,20 @@ This problem uses BERT for NLP.

 ## Requirements

-Install tinygrad and mlperf-logging from master.
+Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0.
 ```
 git clone https://github.com/tinygrad/tinygrad.git
 python3 -m pip install -e ".[mlperf]"
 ```
-Also install tqdm and tensorflow.
+Also install gdown (for dataset), numpy, tqdm and tensorflow.
 ```
-pip install tqdm tensorflow
+pip install gdown numpy tqdm tensorflow
 ```

 ### tinybox_green
 Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md)
 This is the default on production tinybox green.

-### tinybox_red
-Disable cwsr + increase mes timeout.
-Install the custom amdgpu driver per [README](https://github.com/nimlgen/amdgpu_ubuntu_22_04/blob/v6.1.3/readme.md)
-
 # 2. Directions

 ## Steps to download and verify data
@@ -56,18 +52,18 @@ BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval

 #### Steps to run benchmark
 ```
-examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh
 ```

 ### tinybox_red

-#### One time setup
-
+#### Steps to run benchmark
 ```
-examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh
 ```
+### tinybox_8xMI300X

 #### Steps to run benchmark
 ```
-examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh
 ```
@@ -1,14 +1,16 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." NV=1
 export MODEL="bert"
-export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=24
+export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export BEAM=4 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0
+
+export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
 export BEAM_LOG_SURPASS_MAX=1
 export BASEDIR="/raid/datasets/wiki"

-export BENCHMARK=10 DEBUG=2
+export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2

 python3 examples/mlperf/model_train.py
@@ -1,10 +1,12 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." NV=1
 export MODEL="bert"
-export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=24
+export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export BEAM=4 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0
+
+export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
 export BASEDIR="/raid/datasets/wiki"

@@ -1,11 +1,13 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." NV=1
 export MODEL="bert"
 export SUBMISSION_PLATFORM="tinybox_green"
-export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=24
+export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export BEAM=4 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0
+
+export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
 export BASEDIR="/raid/datasets/wiki"

@@ -17,7 +19,7 @@ DATETIME=$(date "+%m%d%H%M")
 LOGFILE="bert_green_${DATETIME}_${SEED}.log"

 # init
-BENCHMARK=10 INITMLPERF=1 BEAM_LOG_SURPASS_MAX=1 python3 examples/mlperf/model_train.py | tee $LOGFILE
+BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 python3 examples/mlperf/model_train.py | tee $LOGFILE

 # run
 PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE
@@ -4,24 +4,20 @@ This problem uses BERT for NLP.

 ## Requirements

-Install tinygrad and mlperf-logging from master.
+Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0.
 ```
 git clone https://github.com/tinygrad/tinygrad.git
 python3 -m pip install -e ".[mlperf]"
 ```
-Also install tqdm and tensorflow.
+Also install gdown (for dataset), numpy, tqdm and tensorflow.
 ```
-pip install tqdm tensorflow
+pip install gdown numpy tqdm tensorflow
 ```

 ### tinybox_green
 Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md)
 This is the default on production tinybox green.

-### tinybox_red
-Disable cwsr + increase mes timeout.
-Install the custom amdgpu driver per [README](https://github.com/nimlgen/amdgpu_ubuntu_22_04/blob/v6.1.3/readme.md)
-
 # 2. Directions

 ## Steps to download and verify data
@@ -56,18 +52,18 @@ BASEDIR="/raid/datasets/wiki" python3 extra/datasets/wikipedia.py pre-eval

 #### Steps to run benchmark
 ```
-examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh
 ```

 ### tinybox_red

-#### One time setup
-
+#### Steps to run benchmark
 ```
-examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/setup.sh
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh
 ```
+### tinybox_8xMI300X

 #### Steps to run benchmark
 ```
-examples/mlperf/training_submission_v4.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh
 ```
@@ -1,15 +1,17 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0
+
+export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
 export BEAM_LOG_SURPASS_MAX=1
 export BASEDIR="/raid/datasets/wiki"

 export RESET_STEP=1
-export BENCHMARK=10 DEBUG=2
+export BENCHMARK=10 BERT_LAYERS=2 DEBUG=2

 python3 examples/mlperf/model_train.py
@@ -1,10 +1,12 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0
+
+export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
 export BASEDIR="/raid/datasets/wiki"

@@ -1,11 +1,13 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." AMD=1
 export MODEL="bert"
 export SUBMISSION_PLATFORM="tinybox_red"
 export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96

-export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
+export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0
+
+export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5
 export IGNORE_JIT_FIRST_BEAM=1
 export BASEDIR="/raid/datasets/wiki"

@@ -16,12 +18,13 @@ export SEED=$RANDOM
 DATETIME=$(date "+%m%d%H%M")
 LOGFILE="bert_red_${DATETIME}_${SEED}.log"

+export HCQDEV_WAIT_TIMEOUT_MS=100000  # prevents hang?
+
 # init
-sudo rmmod amdgpu || true
-BENCHMARK=10 INITMLPERF=1 BEAM_LOG_SURPASS_MAX=1 python3 examples/mlperf/model_train.py | tee $LOGFILE
+sleep 5 && sudo rmmod amdgpu || true
+BENCHMARK=10 INITMLPERF=1 BERT_LAYERS=2 python3 examples/mlperf/model_train.py | tee $LOGFILE

 # run
-# TODO: AMD driver hangs during init, but is 5% faster per step in real run.
+# TODO: AM driver resulted in nan
 sudo modprobe amdgpu
 PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE
-sudo rmmod amdgpu || true
@@ -1,8 +0,0 @@
-#!/bin/bash
-
-rocm-smi --setprofile compute
-rocm-smi --setmclk 3
-rocm-smi --setperflevel high
-
-# power cap to 350W
-# echo "350000000" | sudo tee /sys/class/drm/card{1..6}/device/hwmon/hwmon*/power1_cap
@@ -1,6 +1,6 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." NV=1
 export MODEL="resnet"
 export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192

@@ -1,6 +1,6 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." NV=1
 export MODEL="resnet"
 export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192

@@ -1,6 +1,6 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." NV=1
 export MODEL="resnet"
 export SUBMISSION_PLATFORM="tinybox_green"
 export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192
@@ -1,6 +1,6 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." AMD=1
 export MODEL="resnet"
 export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192

@@ -1,6 +1,6 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." AMD=1
 export MODEL="resnet"
 export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192

@@ -1,6 +1,6 @@
 #!/bin/bash

-export PYTHONPATH="."
+export PYTHONPATH="." AMD=1
 export MODEL="resnet"
 export SUBMISSION_PLATFORM="tinybox_red"
 export DEFAULT_FLOAT="HALF" GPUS=6 BS=1536 EVAL_BS=192
@@ -0,0 +1,38 @@
+# 1. Problem
+
+This problem uses RetinaNet for SSD.
+
+## Requirements
+
+Install tinygrad and mlperf-logging (uncomment mlperf from setup.py) from branch mlperf_training_v5.0.
+```
+git clone https://github.com/tinygrad/tinygrad.git
+python3 -m pip install -e ".[mlperf]"
+```
+
+Also install the following dependencies:
+```
+pip install tqdm numpy pycocotools boto3 pandas torch torchvision
+```
+
+### tinybox_green
+Install the p2p driver per [README](https://github.com/tinygrad/open-gpu-kernel-modules/blob/550.54.15-p2p/README.md)
+This is the default on production tinybox green.
+
+# 2. Directions
+
+## Steps to download data
+
+Run the following:
+```
+BASEDIR=/raid/datasets/openimages python3 extra/datasets/openimages.py
+```
+
+## Running
+
+### tinybox_green
+
+#### Steps to run benchmark
+```
+examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh
+```
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+export PYTHONPATH="." NV=1
+export MODEL="retinanet"
+export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96
+export BASEDIR="/raid/datasets/openimages"
+
+# export RESET_STEP=0
+
+export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0
+
+export BENCHMARK=5 DEBUG=2
+
+python examples/mlperf/model_train.py
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+export PYTHONPATH="." NV=1
+export MODEL="retinanet"
+export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96
+export BASEDIR="/raid/datasets/openimages"
+
+# export RESET_STEP=0
+
+export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0
+
+export WANDB=1 PARALLEL=0
+export RUNMLPERF=1
+
+python examples/mlperf/model_train.py
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+export PYTHONPATH="." NV=1
+export MODEL="retinanet"
+export SUBMISSION_PLATFORM="tinybox_green"
+export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96
+
+export TRAIN_BEAM=2 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0
+export IGNORE_JIT_FIRST_BEAM=1
+export BASEDIR="/raid/datasets/openimages"
+
+# pip install -e ".[mlperf]"
+export LOGMLPERF=1
+
+export SEED=$RANDOM
+DATETIME=$(date "+%m%d%H%M")
+LOGFILE="retinanet_green_${DATETIME}_${SEED}.log"
+
+# init
+BENCHMARK=10 INITMLPERF=1 python3 examples/mlperf/model_train.py | tee $LOGFILE
+
+# run
+PARALLEL=0 RUNMLPERF=1 python3 examples/mlperf/model_train.py | tee -a $LOGFILE
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1
+export MODEL="retinanet"
+export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96
+export BASEDIR="/raid/datasets/openimages"
+
+# export RESET_STEP=0
+
+export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0
+
+export BENCHMARK=5 DEBUG=2
+
+python examples/mlperf/model_train.py
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+export PYTHONPATH="." AMD=1
+export MODEL="retinanet"
+export DEFAULT_FLOAT="HALF" GPUS=6 BS=96 EVAL_BS=96
+export BASEDIR="/raid/datasets/openimages"
+
+# export RESET_STEP=0
+
+export TRAIN_BEAM=2 IGNORE_JIT_FIRST_BEAM=1 BEAM_UOPS_MAX=1500 BEAM_UPCAST_MAX=64 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 BEAM_PADTO=0
+
+export WANDB=1 PARALLEL=0
+export RUNMLPERF=1
+
+python examples/mlperf/model_train.py
@@ -0,0 +1,39 @@
+{
+    "submitter": "tinycorp",
+    "division": "closed",
+    "status": "Available on-premise",
+    "system_name": "tinybox 8xMI300X",
+    "number_of_nodes": "1",
+    "host_processors_per_node": "2",
+    "host_processor_model_name": "AMD EPYC 9354 32-Core Processor",
+    "host_processor_core_count": "32",
+    "host_processor_vcpu_count": "64",
+    "host_processor_frequency": "",
+    "host_processor_caches": "",
+    "host_processor_interconnect": "",
+    "host_memory_capacity": "2304GB",
+    "host_storage_type": "NVMe SSD",
+    "host_storage_capacity": "3x 4TB raid array",
+    "host_networking": "",
+    "host_networking_topology": "",
+    "host_memory_configuration": "24x 96GB DDR5",
+    "accelerators_per_node": "8",
+    "accelerator_model_name": "AMD Instinct MI300X",
+    "accelerator_host_interconnect": "PCIe 5.0 x16",
+    "accelerator_frequency": "",
+    "accelerator_on-chip_memories": "",
+    "accelerator_memory_configuration": "HBM3",
+    "accelerator_memory_capacity": "192GB",
+    "accelerator_interconnect": "",
+    "accelerator_interconnect_topology": "",
+    "cooling": "air",
+    "hw_notes": "",
+    "framework": "tinygrad, branch mlperf_training_v5.0",
+    "other_software_stack": {
+      "python": "3.10.16",
+      "ROCm": "3.0.0+94441cb"
+    },
+    "operating_system": "Ubuntu 24.04.1 LTS",
+    "sw_notes": ""
+  }
+  
@@ -28,7 +28,7 @@
  "accelerator_interconnect_topology": "",
  "cooling": "air",
  "hw_notes": "",
-  "framework": "tinygrad, commit b5546912e24e0a864b35924da4efa5d71cfe368b",
+  "framework": "tinygrad, branch mlperf_training_v5.0",
  "other_software_stack": {
    "python": "3.10.12",
    "CUDA": "12.4"
@@ -28,10 +28,9 @@
  "accelerator_interconnect_topology": "",
  "cooling": "air",
  "hw_notes": "",
-  "framework": "tinygrad, commit b5546912e24e0a864b35924da4efa5d71cfe368b",
+  "framework": "tinygrad, branch mlperf_training_v5.0",
  "other_software_stack": {
-    "python": "3.10.12",
-    "ROCm": "6.1.3"
+    "python": "3.10.12"
  },
  "operating_system": "Ubuntu 22.04.4",
  "sw_notes": ""
@@ -55,7 +55,7 @@ if __name__ == "__main__":
    del model_state_dict['freqs_cis']

  with Timing("load weights to GPU: "):
-    nhf_state = convert_from_huggingface(fetch_weights(), model, 16, 16)
+    nhf_state = convert_from_huggingface(fetch_weights(), 16, 16, 16)
    # NOTE: i'm not sure this actually needs float32, it may just change the type of things downstream from it. but doesn't match torch w/o this
    for needs_float32 in ['tok_embeddings.weight']: nhf_state[needs_float32] = nhf_state[needs_float32].float()
  print(f"ram used: {GlobalCounters.mem_used/1e9:.2f} GB")
@@ -54,7 +54,7 @@ if __name__ == "__main__":
    return loss

  test_acc = float('nan')
-  for i in (t:=trange(70)):
+  for i in (t:=trange(getenv("STEPS", 70))):
    samples = torch.randint(0, X_train.shape[0], (512,))  # putting this in JIT didn't work well
    loss = step(samples)
    if i%10 == 9: test_acc = ((model(X_test).argmax(axis=-1) == Y_test).sum() * 100 / X_test.shape[0]).item()
@@ -44,7 +44,7 @@ def load_model(model_path:Path, model_params:Dict[str, Union[int, float]]) -> Tr
  model.layers = updated_layers

  # load weights
-  weights = fix_bf16(convert_from_huggingface(load(str(model_path / "model.safetensors.index.json")), model, model_params["n_heads"], model_params["n_kv_heads"], permute_layers=False))
+  weights = fix_bf16(convert_from_huggingface(load(str(model_path / "model.safetensors.index.json")), model_params["n_layers"], model_params["n_heads"], model_params["n_kv_heads"], permute_layers=False))

  # replace weights in model
  load_state_dict(model, weights, strict=False, consume=True)
@@ -5,7 +5,7 @@

 from tinygrad import Tensor, TinyJit, dtypes, GlobalCounters
 from tinygrad.nn import Conv2d, GroupNorm
-from tinygrad.nn.state import safe_load, load_state_dict
+from tinygrad.nn.state import safe_load, load_state_dict, get_state_dict
 from tinygrad.helpers import fetch, trange, colored, Timing
 from extra.models.clip import Embedder, FrozenClosedClipEmbedder, FrozenOpenClipEmbedder
 from extra.models.unet import UNetModel, Upsample, Downsample, timestep_embedding
@@ -356,8 +356,7 @@ class DPMPP2MSampler:
          c=c,
          uc=uc,
        )
-        x.realize()
-        old_denoised.realize()
+        x.realize(old_denoised)

    return x

@@ -385,7 +384,12 @@ if __name__ == "__main__":

  default_weight_url = 'https://huggingface.co/stabilityai/stable-diffusion-xl-base-1.0/resolve/main/sd_xl_base_1.0.safetensors'
  weights = args.weights if args.weights else fetch(default_weight_url, 'sd_xl_base_1.0.safetensors')
-  load_state_dict(model, safe_load(weights), strict=False)
+  loaded_weights = load_state_dict(model, safe_load(weights), strict=False, verbose=False, realize=False)
+
+  start_mem_used = GlobalCounters.mem_used
+  with Timing("loaded weights in ", lambda et_ns: f", {(B:=(GlobalCounters.mem_used-start_mem_used))/1e9:.2f} GB loaded at {B/et_ns:.2f} GB/s"):
+    Tensor.realize(*loaded_weights)
+    del loaded_weights

  N = 1
  C = 4
@@ -396,8 +400,7 @@ if __name__ == "__main__":

  c, uc = model.create_conditioning([args.prompt], args.width, args.height)
  del model.conditioner
-  for v in c .values(): v.realize()
-  for v in uc.values(): v.realize()
+  Tensor.realize(*c.values(), *uc.values())
  print("created batch")

  # https://github.com/Stability-AI/generative-models/blob/fbdc58cab9f4ee2be7a5e1f2e2787ecd9311942f/sgm/inference/helpers.py#L101
@@ -5,10 +5,13 @@
 #  - symbolic removal

 from examples.beautiful_mnist import Model
-from tinygrad import Tensor, nn, getenv, GlobalCounters
+from tinygrad import Tensor, nn, getenv, GlobalCounters, Variable
 from tinygrad.nn.datasets import mnist
 from tinygrad.helpers import trange, DEBUG

+# STEPS=70 python3 examples/stunning_mnist.py
+# NOTE: it's broken with STACK=1, why?
+
 if __name__ == "__main__":
  X_train, Y_train, X_test, Y_test = mnist()
  print("*** got data")
@@ -24,19 +27,21 @@ if __name__ == "__main__":
  print("*** got samples")

  with Tensor.train():
-    # TODO: this shouldn't be a for loop. something like: (contract is still up in the air)
    """
    i = UOp.range(samples.shape[0])  # TODO: fix range function on UOp
    losses = model(X_samp[i]).sparse_categorical_crossentropy(Y_samp[i]).backward().contract(i)
    opt.schedule_steps(i)
    """
+    # TODO: this shouldn't be a for loop. something like: (contract is still up in the air)
+    vi = Variable('i', 0, samples.shape[0]-1)
    losses = []
    for i in range(samples.shape[0]):
+      vib = vi.bind(i)
      opt.zero_grad()
-      losses.append(model(X_samp[i]).sparse_categorical_crossentropy(Y_samp[i]).backward())
+      losses.append(model(X_samp[vib]).sparse_categorical_crossentropy(Y_samp[vib]).backward())
      opt.schedule_step()
    # TODO: this stack currently breaks the "generator" aspect of losses. it probably shouldn't
-    #losses = Tensor.stack(*losses)
+    if getenv("STACK", 0): losses = Tensor.stack(*losses)
  print("*** scheduled training")

  # evaluate the model
@@ -49,5 +54,8 @@ if __name__ == "__main__":

  # only actually do anything at the end
  if getenv("LOSS", 1):
-    for i in (t:=trange(len(losses))): t.set_description(f"loss: {losses[i].item():6.2f}")
-  print(f"test_accuracy: {test_acc.item():5.2f}%")
+    for i in (t:=trange(len(losses))):
+      GlobalCounters.reset()
+      t.set_description(f"loss: {losses[i].item():6.2f}")
+  if getenv("TEST", 1):
+    print(f"test_accuracy: {test_acc.item():5.2f}%")
@@ -70,7 +70,7 @@ if __name__ == "__main__":
    GlobalCounters.reset()
    p = run_onnx_jit(**{t_name:img})
    assert p.shape == (1,1000)
-    t = p.argmax().item()
+    t = p.to('cpu').argmax().item()
    hit += y==t
    print(f"target: {y:3d}  pred: {t:3d}  acc: {hit/(i+1)*100:.2f}%")

@@ -0,0 +1,19 @@
+import sys, pickle
+from tinygrad import GlobalCounters
+from tinygrad.helpers import fetch, getenv
+from examples.test_onnx_imagenet import imagenet_dataloader
+
+if __name__ == "__main__":
+  with open(fetch(sys.argv[1]), "rb") as f:
+    run_onnx_jit = pickle.load(f)
+  input_name = run_onnx_jit.captured.expected_names[0]
+  device = run_onnx_jit.captured.expected_st_vars_dtype_device[0][-1]
+  print(f"input goes into {input_name=} on {device=}")
+  hit = 0
+  for i,(img,y) in enumerate(imagenet_dataloader(cnt=getenv("CNT", 100))):
+    GlobalCounters.reset()
+    p = run_onnx_jit(**{input_name:img.to(device)})
+    assert p.shape == (1,1000)
+    t = p.to('cpu').argmax().item()
+    hit += y==t
+    print(f"target: {y:3d}  pred: {t:3d}  acc: {hit/(i+1)*100:.2f}%")
@@ -17,7 +17,7 @@ def make_dataset():
  random.shuffle(ds)
  ds = np.array(ds).astype(np.float32)
  ds_X = ds[:, 0:6]
-  ds_Y = np.copy(ds[:, 1:])
+  ds_Y = np.copy(ds[:, 1:]).astype(np.int32)
  ds_X_train, ds_X_test = ds_X[0:8000], ds_X[8000:]
  ds_Y_train, ds_Y_test = ds_Y[0:8000], ds_Y[8000:]
  return ds_X_train, ds_Y_train, ds_X_test, ds_Y_test
@@ -12,7 +12,7 @@ if __name__ == "__main__":
    yolo_infer = YOLOv8(w=0.25, r=2.0, d=0.33, num_classes=80)
    state_dict = safe_load(get_weights_location(yolo_variant))
    load_state_dict(yolo_infer, state_dict)
-    prg, inp_sizes, out_sizes, state = export_model(yolo_infer, Device.DEFAULT.lower(), Tensor.randn(1,3,416,416), model_name="yolov8")
+    prg, inp_sizes, out_sizes, state = export_model(yolo_infer, Device.DEFAULT.lower(), Tensor.randn(1,3,640,640), model_name="yolov8")
    dirname = Path(__file__).parent
    safe_save(state, (dirname / "net.safetensors").as_posix())
    with open(dirname / f"net.js", "w") as text_file:
@@ -111,7 +111,7 @@
    </div>
    <script>
        let net = null;
-        const modelInputSize = 416;
+        const modelInputSize = 640;
        let lastCalledTime;
        let fps = 0, accumFps = 0, frameCounter = 0;

@@ -127,14 +127,22 @@
        const offscreenContext = offscreenCanvas.getContext('2d');


-        if (navigator.mediaDevices && navigator.mediaDevices.getUserMedia) {
-            navigator.mediaDevices.getUserMedia({ audio: false,  video: { facingMode: { ideal: "environment" }}}).then(function (stream) {
+        if (navigator.mediaDevices?.getUserMedia) {
+            const tryCamera = facing => navigator.mediaDevices.getUserMedia({ audio: false, video: { facingMode: { ideal: facing } } });
+            const handle = stream => {
                video.srcObject = stream;
                video.onloadedmetadata = function() {
                    canvas.width = video.clientWidth;
                    canvas.height = video.clientHeight;
-                }
-            });
+                };
+            };
+            tryCamera("environment").then(handle).catch(() => 
+                tryCamera("user").then(handle).catch(e => {
+                    wgpuError.textContent = "Error: Could not access camera."
+                    wgpuError.style.display = "block";
+                    loadingContainer.style.display = "none";
+                })
+            );
        }

        async function processFrame() {
@@ -176,10 +184,12 @@
            offscreenContext.clearRect(0, 0, modelInputSize, modelInputSize);
            offscreenContext.drawImage(video, offsetX, offsetY, targetWidth, targetHeight);
            const boxes = await detectObjectsOnFrame(offscreenContext);
-            drawBoxes(offscreenCanvas, boxes, targetWidth, targetHeight, offsetX, offsetY);
+            const validBoxes = [];
+            for (let i = 0; i < boxes.length; i += 6)
+                if (boxes[i + 4] > 0) validBoxes.push([boxes[i], boxes[i + 1], boxes[i + 2], boxes[i + 3], boxes[i + 5]]);
+            drawBoxes(offscreenCanvas, validBoxes, targetWidth, targetHeight, offsetX, offsetY);
            requestAnimationFrame(processFrame);
        }
-
        requestAnimationFrame(processFrame);

        function drawBoxes(offscreenCanvas, boxes, targetWidth, targetHeight, offsetX, offsetY) {
@@ -190,8 +200,8 @@
            const scaleX = canvas.width / targetWidth;
            const scaleY = canvas.height / targetHeight;

-            boxes.forEach(([x1, y1, x2, y2, label]) => {
-                const classIndex = yolo_classes.indexOf(label);
+            boxes.forEach(([x1, y1, x2, y2, classIndex]) => {
+                const label = yolo_classes[classIndex];
                const color = classColors[classIndex];
                ctx.strokeStyle = color;
                ctx.fillStyle = color;
@@ -219,21 +229,13 @@
                net = await yolov8.load(device, "./net.safetensors");
                loadingContainer.style.display = "none";
            }
-            let start = performance.now();
-            const [input,img_width,img_height] = await prepareInput(offscreenContext);
-            console.log("Preprocess took: " + (performance.now() - start) + " ms");
-            start = performance.now();
+            const input = await prepareInput(offscreenContext);
            const output = await net(new Float32Array(input));
-            console.log("Inference took: " + (performance.now() - start) + " ms");
-            start = performance.now();
-            let out = processOutput(output[0],img_width,img_height);
-            console.log("Postprocess took: " + (performance.now() - start) + " ms");
-            return out;
+            return output[0];
        }

        async function prepareInput(offscreenContext) {
            return new Promise(resolve => {
-                const [img_width,img_height] = [modelInputSize, modelInputSize]
                const imgData = offscreenContext.getImageData(0,0,modelInputSize,modelInputSize);
                const pixels = imgData.data;
                const red = [], green = [], blue = [];
@@ -244,7 +246,7 @@
                    blue.push(pixels[index+2]/255.0);
                }
                const input = [...red, ...green, ...blue];
-                resolve([input, img_width, img_height])
+                resolve(input)
            })
        }

@@ -252,62 +254,10 @@
            if (!navigator.gpu) return false;
            const adapter = await navigator.gpu.requestAdapter();
            return await adapter.requestDevice({
-                requiredFeatures: ["shader-f16"],
                powerPreference: "high-performance"
 		    });
        };
        
-        function processOutput(output, img_width, img_height) {
-            let boxes = [];
-            const numPredictions = Math.pow(modelInputSize/32, 2) * 21;
-            for (let index=0;index<numPredictions;index++) {
-                const [class_id,prob] = [...Array(80).keys()]
-                    .map(col => [col, output[numPredictions*(col+4)+index]])
-                    .reduce((accum, item) => item[1]>accum[1] ? item : accum,[0,0]);
-
-                if (prob < 0.25) continue;
-                const label = yolo_classes[class_id];
-                const xc = output[index];
-                const yc = output[numPredictions+index];
-                const w = output[2*numPredictions+index];
-                const h = output[3*numPredictions+index];
-                const x1 = (xc-w/2)/modelInputSize*img_width;
-                const y1 = (yc-h/2)/modelInputSize*img_height;
-                const x2 = (xc+w/2)/modelInputSize*img_width;
-                const y2 = (yc+h/2)/modelInputSize*img_height;
-                boxes.push([x1,y1,x2,y2,label,prob]);
-            }
-
-            boxes = boxes.sort((box1,box2) => box2[5]-box1[5])
-            const result = [];
-            while (boxes.length>0) {
-                result.push(boxes[0]);
-                boxes = boxes.filter(box => iou(boxes[0],box)<0.7);
-            }
-            return result;
-        }
-
-        function iou(box1,box2) {
-            return intersection(box1,box2)/union(box1,box2);
-        }
-
-        function union(box1,box2) {
-            const [box1_x1,box1_y1,box1_x2,box1_y2] = box1;
-            const [box2_x1,box2_y1,box2_x2,box2_y2] = box2;
-            const box1_area = (box1_x2-box1_x1)*(box1_y2-box1_y1)
-            const box2_area = (box2_x2-box2_x1)*(box2_y2-box2_y1)
-            return box1_area + box2_area - intersection(box1,box2)
-        }
-
-        function intersection(box1,box2) {
-            const [box1_x1,box1_y1,box1_x2,box1_y2] = box1;
-            const [box2_x1,box2_y1,box2_x2,box2_y2] = box2;
-            const x1 = Math.max(box1_x1,box2_x1);
-            const y1 = Math.max(box1_y1,box2_y1);
-            const x2 = Math.min(box1_x2,box2_x2);
-            const y2 = Math.min(box1_y2,box2_y2);
-            return (x2-x1)*(y2-y1)
-        }

        const yolo_classes = [
            'person', 'bicycle', 'car', 'motorcycle', 'airplane', 'bus', 'train', 'truck', 'boat',
@@ -42,69 +42,8 @@ def preprocess(im, imgsz=640, model_stride=32, model_pt=True):
  im = im / 255.0  # 0 - 255 to 0.0 - 1.0
  return im

-# Post Processing functions
-def box_area(box):
-  return (box[:, 2] - box[:, 0]) * (box[:, 3] - box[:, 1])

-def box_iou(box1, box2):
-  lt = np.maximum(box1[:, None, :2], box2[:, :2])
-  rb = np.minimum(box1[:, None, 2:], box2[:, 2:])
-  wh = np.clip(rb - lt, 0, None)
-  inter = wh[:, :, 0] * wh[:, :, 1]
-  area1 = box_area(box1)[:, None]
-  area2 = box_area(box2)[None, :]
-  iou = inter / (area1 + area2 - inter)
-  return iou
-
-def compute_nms(boxes, scores, iou_threshold):
-  order, keep = scores.argsort()[::-1], []
-  while order.size > 0:
-    i = order[0]
-    keep.append(i)
-    if order.size == 1:
-      break
-    iou = box_iou(boxes[i][None, :], boxes[order[1:]])
-    inds = np.where(np.atleast_1d(iou.squeeze()) <= iou_threshold)[0]
-    order = order[inds + 1]
-  return np.array(keep)
-
-def non_max_suppression(prediction, conf_thres=0.25, iou_thres=0.45, agnostic=False, max_det=300, nc=0, max_wh=7680):
-  prediction = prediction[0] if isinstance(prediction, (list, tuple)) else prediction
-  bs, nc = prediction.shape[0], nc or (prediction.shape[1] - 4)
-  xc = np.amax(prediction[:, 4:4 + nc], axis=1) > conf_thres
-  nm = prediction.shape[1] - nc - 4
-  output = [np.zeros((0, 6 + nm))] * bs
-
-  for xi, x in enumerate(prediction):
-    x = x.swapaxes(0, -1)[xc[xi]]
-    if not x.shape[0]: continue
-    box, cls, mask = np.split(x, [4, 4 + nc], axis=1)
-    conf, j = np.max(cls, axis=1, keepdims=True), np.argmax(cls, axis=1, keepdims=True)
-    x = np.concatenate((xywh2xyxy(box), conf, j.astype(np.float32), mask), axis=1)
-    x = x[conf.ravel() > conf_thres]
-    if not x.shape[0]: continue
-    x = x[np.argsort(-x[:, 4])]
-    c = x[:, 5:6] * (0 if agnostic else max_wh)
-    boxes, scores = x[:, :4] + c, x[:, 4]
-    i = compute_nms(boxes, scores, iou_thres)[:max_det]
-    output[xi] = x[i]
-  return output
-
-def postprocess(preds, img, orig_imgs):
-  print('copying to CPU now for post processing')
-  #if you are on CPU, this causes an overflow runtime error. doesn't "seem" to make any difference in the predictions though.
-  # TODO: make non_max_suppression in tinygrad - to make this faster
-  preds = preds.numpy() if isinstance(preds, Tensor) else preds
-  preds = non_max_suppression(prediction=preds, conf_thres=0.25, iou_thres=0.7, agnostic=False, max_det=300)
-  all_preds = []
-  for i, pred in enumerate(preds):
-    orig_img = orig_imgs[i] if isinstance(orig_imgs, list) else orig_imgs
-    if not isinstance(orig_imgs, Tensor):
-      pred[:, :4] = scale_boxes(img.shape[2:], pred[:, :4], orig_img.shape)
-      all_preds.append(pred)
-  return all_preds
-
-def draw_bounding_boxes_and_save(orig_img_paths, output_img_paths, all_predictions, class_labels, iou_threshold=0.5):
+def draw_bounding_boxes_and_save(orig_img_path, output_img_path, predictions, class_labels):
  color_dict = {label: tuple((((i+1) * 50) % 256, ((i+1) * 100) % 256, ((i+1) * 150) % 256)) for i, label in enumerate(class_labels)}
  font = cv2.FONT_HERSHEY_SIMPLEX

@@ -113,52 +52,32 @@ def draw_bounding_boxes_and_save(orig_img_paths, output_img_paths, all_predictio
    brightness = (r * 299 + g * 587 + b * 114) / 1000
    return brightness > 127

-  for img_idx, (orig_img_path, output_img_path, predictions) in enumerate(zip(orig_img_paths, output_img_paths, all_predictions)):
-    predictions = np.array(predictions)
-    orig_img = cv2.imread(orig_img_path) if not isinstance(orig_img_path, np.ndarray) else cv2.imdecode(orig_img_path, 1)
-    height, width, _ = orig_img.shape
-    box_thickness = int((height + width) / 400)
-    font_scale = (height + width) / 2500
+  orig_img = cv2.imread(orig_img_path) if not isinstance(orig_img_path, np.ndarray) else cv2.imdecode(orig_img_path, 1)
+  height, width, _ = orig_img.shape
+  box_thickness = int((height + width) / 400)
+  font_scale = (height + width) / 2500
+  object_count = defaultdict(int)

-    grouped_preds = defaultdict(list)
-    object_count = defaultdict(int)
+  for pred in predictions:
+    x1, y1, x2, y2, conf, class_id = pred
+    if conf == 0: continue
+    x1, y1, x2, y2, class_id = map(int, (x1, y1, x2, y2, class_id))
+    color = color_dict[class_labels[class_id]]
+    cv2.rectangle(orig_img, (x1, y1), (x2, y2), color, box_thickness)
+    label = f"{class_labels[class_id]} {conf:.2f}"
+    text_size, _ = cv2.getTextSize(label, font, font_scale, 1)
+    label_y, bg_y = (y1 - 4, y1 - text_size[1] - 4) if y1 - text_size[1] - 4 > 0 else (y1 + text_size[1], y1)
+    cv2.rectangle(orig_img, (x1, bg_y), (x1 + text_size[0], bg_y + text_size[1]), color, -1)
+    font_color = (0, 0, 0) if is_bright_color(color) else (255, 255, 255)
+    cv2.putText(orig_img, label, (x1, label_y), font, font_scale, font_color, 1, cv2.LINE_AA)
+    object_count[class_labels[class_id]] += 1

-    for pred_np in predictions:
-      grouped_preds[int(pred_np[-1])].append(pred_np)
+  print("Objects detected:")
+  for obj, count in object_count.items():
+    print(f"- {obj}: {count}")

-    def draw_box_and_label(pred, color):
-      x1, y1, x2, y2, conf, _ = pred
-      x1, y1, x2, y2 = map(int, (x1, y1, x2, y2))
-      cv2.rectangle(orig_img, (x1, y1), (x2, y2), color, box_thickness)
-      label = f"{class_labels[class_id]} {conf:.2f}"
-      text_size, _ = cv2.getTextSize(label, font, font_scale, 1)
-      label_y, bg_y = (y1 - 4, y1 - text_size[1] - 4) if y1 - text_size[1] - 4 > 0 else (y1 + text_size[1], y1)
-      cv2.rectangle(orig_img, (x1, bg_y), (x1 + text_size[0], bg_y + text_size[1]), color, -1)
-      font_color = (0, 0, 0) if is_bright_color(color) else (255, 255, 255)
-      cv2.putText(orig_img, label, (x1, label_y), font, font_scale, font_color, 1, cv2.LINE_AA)
-
-    for class_id, pred_list in grouped_preds.items():
-      pred_list = np.array(pred_list)
-      while len(pred_list) > 0:
-        max_conf_idx = np.argmax(pred_list[:, 4])
-        max_conf_pred = pred_list[max_conf_idx]
-        pred_list = np.delete(pred_list, max_conf_idx, axis=0)
-        color = color_dict[class_labels[class_id]]
-        draw_box_and_label(max_conf_pred, color)
-        object_count[class_labels[class_id]] += 1
-        iou_scores = box_iou(np.array([max_conf_pred[:4]]), pred_list[:, :4])
-        low_iou_indices = np.where(iou_scores[0] < iou_threshold)[0]
-        pred_list = pred_list[low_iou_indices]
-        for low_conf_pred in pred_list:
-          draw_box_and_label(low_conf_pred, color)
-
-    print(f"Image {img_idx + 1}:")
-    print("Objects detected:")
-    for obj, count in object_count.items():
-      print(f"- {obj}: {count}")
-
-    cv2.imwrite(output_img_path, orig_img)
-    print(f'saved detections at {output_img_path}')
+  cv2.imwrite(output_img_path, orig_img)
+  print(f'saved detections at {output_img_path}')

 # utility functions for forward pass.
 def dist2bbox(distance, anchor_points, xywh=True, dim=-1):
@@ -202,34 +121,26 @@ def clip_boxes(boxes, shape):
  boxes[..., [1, 3]] = np.clip(boxes[..., [1, 3]], 0, shape[0])  # y1, y2
  return boxes

-def scale_boxes(img1_shape, boxes, img0_shape, ratio_pad=None):
+def scale_boxes(img1_shape, predictions, img0_shape, ratio_pad=None):
  gain = ratio_pad if ratio_pad else min(img1_shape[0] / img0_shape[0], img1_shape[1] / img0_shape[1])
  pad = ((img1_shape[1] - img0_shape[1] * gain) / 2, (img1_shape[0] - img0_shape[0] * gain) / 2)
-  boxes_np = boxes.numpy() if isinstance(boxes, Tensor) else boxes
-  boxes_np[..., [0, 2]] -= pad[0]
-  boxes_np[..., [1, 3]] -= pad[1]
-  boxes_np[..., :4] /= gain
-  boxes_np = clip_boxes(boxes_np, img0_shape)
-  return boxes_np
-
-def xywh2xyxy(x):
-  xy = x[..., :2]  # center x, y
-  wh = x[..., 2:4]  # width, height
-  xy1 = xy - wh / 2  # top left x, y
-  xy2 = xy + wh / 2  # bottom right x, y
-  result = np.concatenate((xy1, xy2), axis=-1)
-  return Tensor(result) if isinstance(x, Tensor) else result
+  for pred in predictions:
+    boxes_np = pred[:4].numpy() if isinstance(pred[:4], Tensor) else pred[:4]
+    boxes_np[..., [0, 2]] -= pad[0]
+    boxes_np[..., [1, 3]] -= pad[1]
+    boxes_np[..., :4] /= gain
+    boxes_np = clip_boxes(boxes_np, img0_shape)
+    pred[:4] = boxes_np
+  return predictions

 def get_variant_multiples(variant):
  return {'n':(0.33, 0.25, 2.0), 's':(0.33, 0.50, 2.0), 'm':(0.67, 0.75, 1.5), 'l':(1.0, 1.0, 1.0), 'x':(1, 1.25, 1.0) }.get(variant, None)

 def label_predictions(all_predictions):
  class_index_count = defaultdict(int)
-  for predictions in all_predictions:
-    predictions = np.array(predictions)
-    for pred_np in predictions:
-      class_id = int(pred_np[-1])
-      class_index_count[class_id] += 1
+  for pred in all_predictions:
+    class_id = int(pred[-1])
+    if pred[-2] != 0: class_index_count[class_id] += 1

  return dict(class_index_count)

@@ -380,7 +291,9 @@ class YOLOv8:
  def __call__(self, x):
    x = self.net(x)
    x = self.fpn(*x)
-    return self.head(x)
+    x = self.head(x)
+    # TODO: postprocess needs to be in the model to be compiled to webgpu
+    return postprocess(x)

  def return_all_trainable_modules(self):
    backbone_modules = [*range(10)]
@@ -403,16 +316,45 @@ def convert_f16_safetensor_to_f32(input_file: Path, output_file: Path):
    f.write(new_metadata_bytes)
    float32_values.tofile(f)

+def compute_iou_matrix(boxes):
+  x1, y1, x2, y2 = boxes[:, 0], boxes[:, 1], boxes[:, 2], boxes[:, 3]
+  areas = (x2 - x1) * (y2 - y1)
+  x1 = Tensor.maximum(x1[:, None], x1[None, :])
+  y1 = Tensor.maximum(y1[:, None], y1[None, :])
+  x2 = Tensor.minimum(x2[:, None], x2[None, :])
+  y2 = Tensor.minimum(y2[:, None], y2[None, :])
+  w = Tensor.maximum(Tensor(0), x2 - x1)
+  h = Tensor.maximum(Tensor(0), y2 - y1)
+  intersection = w * h
+  union = areas[:, None] + areas[None, :] - intersection
+  return intersection / union
+
+def postprocess(output, max_det=300, conf_threshold=0.25, iou_threshold=0.45):
+  xc, yc, w, h, class_scores = output[0][0], output[0][1], output[0][2], output[0][3], output[0][4:]
+  class_ids = Tensor.argmax(class_scores, axis=0)
+  probs = Tensor.max(class_scores, axis=0)
+  probs = Tensor.where(probs >= conf_threshold, probs, 0)
+  x1 = xc - w / 2
+  y1 = yc - h / 2
+  x2 = xc + w / 2
+  y2 = yc + h / 2
+  boxes = Tensor.stack(x1, y1, x2, y2, probs, class_ids, dim=1)
+  order = Tensor.topk(probs, max_det)[1]
+  boxes = boxes[order]
+  iou = compute_iou_matrix(boxes[:, :4])
+  iou = Tensor.triu(iou, diagonal=1)
+  same_class_mask = boxes[:, -1][:, None] == boxes[:, -1][None, :]
+  high_iou_mask = (iou > iou_threshold) & same_class_mask
+  no_overlap_mask = high_iou_mask.sum(axis=0) == 0
+  boxes = boxes * no_overlap_mask.unsqueeze(-1)
+  return boxes
+
 def get_weights_location(yolo_variant: str) -> Path:
  weights_location = Path(__file__).parents[1] / "weights" / f'yolov8{yolo_variant}.safetensors'
  fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{yolo_variant}.safetensors', weights_location)
-
-  if not is_dtype_supported(dtypes.half):
-    f32_weights = weights_location.with_name(f"{weights_location.stem}_f32.safetensors")
-    if not f32_weights.exists(): convert_f16_safetensor_to_f32(weights_location, f32_weights)
-    weights_location = f32_weights
-
-  return weights_location
+  f32_weights = weights_location.with_name(f"{weights_location.stem}_f32.safetensors")
+  if not f32_weights.exists(): convert_f16_safetensor_to_f32(weights_location, f32_weights)
+  return f32_weights

 if __name__ == '__main__':

@@ -428,14 +370,13 @@ if __name__ == '__main__':
  output_folder_path = Path('./outputs_yolov8')
  output_folder_path.mkdir(parents=True, exist_ok=True)
  #absolute image path or URL
-  image_location = [np.frombuffer(fetch(img_path).read_bytes(), np.uint8)]
-  image = [cv2.imdecode(image_location[0], 1)]
-  out_paths = [(output_folder_path / f"{Path(img_path).stem}_output{Path(img_path).suffix or '.png'}").as_posix()]
+  image_location = np.frombuffer(fetch(img_path).read_bytes(), np.uint8)
+  image = [cv2.imdecode(image_location, 1)]
+  out_path = (output_folder_path / f"{Path(img_path).stem}_output{Path(img_path).suffix or '.png'}").as_posix()
  if not isinstance(image[0], np.ndarray):
    print('Error in image loading. Check your image file.')
    sys.exit(1)
  pre_processed_image = preprocess(image)
-
  # Different YOLOv8 variants use different w , r, and d multiples. For a list , refer to this yaml file (the scales section) https://github.com/ultralytics/ultralytics/blob/main/ultralytics/cfg/models/v8/yolov8.yaml
  depth, width, ratio = get_variant_multiples(yolo_variant)
  yolo_infer = YOLOv8(w=width, r=ratio, d=depth, num_classes=80)
@@ -443,15 +384,13 @@ if __name__ == '__main__':
  load_state_dict(yolo_infer, state_dict)

  st = time.time()
-  predictions = yolo_infer(pre_processed_image)
+  predictions = yolo_infer(pre_processed_image).numpy()
+
  print(f'did inference in {int(round(((time.time() - st) * 1000)))}ms')
-
-  post_predictions = postprocess(preds=predictions, img=pre_processed_image, orig_imgs=image)
-
  #v8 and v3 have same 80 class names for Object Detection
  class_labels = fetch('https://raw.githubusercontent.com/pjreddie/darknet/master/data/coco.names').read_text().split("\n")
-
-  draw_bounding_boxes_and_save(orig_img_paths=image_location, output_img_paths=out_paths, all_predictions=post_predictions, class_labels=class_labels)
+  predictions = scale_boxes(pre_processed_image.shape[2:], predictions, image[0].shape)
+  draw_bounding_boxes_and_save(orig_img_path=image_location, output_img_path=out_path, predictions=predictions, class_labels=class_labels)

 # TODO for later:
 #  1. Fix SPPF minor difference due to maxpool
@@ -1,14 +1,14 @@
 #!/usr/bin/env python3

 import time, mmap, sys, shutil, os, glob, subprocess
-from tinygrad.helpers import to_mv, DEBUG, colored, ansilen
+from tinygrad.helpers import DEBUG, colored, ansilen
 from tinygrad.runtime.autogen import libc
-from tinygrad.runtime.autogen.am import smu_v13_0_0
+from tinygrad.runtime.autogen.am import am
+from tinygrad.runtime.support.hcq import MMIOInterface
 from tinygrad.runtime.support.am.amdev import AMDev, AMMemoryManager
 from tinygrad.runtime.support.am.ip import AM_SOC, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA

-AM_VERSION = 0xA0000002
-SMU_11_0_GFX_BUSY_THRESHOLD = 15
+AM_VERSION = 0xA0000004

 def bold(s): return f"\033[1m{s}\033[0m"

@@ -16,6 +16,10 @@ def trim(s:str, length:int) -> str:
  if len(s) > length: return s[:length-3] + "..."
  return s

+def pad(x:str, length:int) -> str:
+  if len(x) < length: return x + " " * (length - len(x))
+  return x
+
 def color_temp(temp):
  if temp >= 87: return colored(f"{temp:>3}", "red")
  elif temp >= 80: return colored(f"{temp:>3}", "yellow")
@@ -38,7 +42,7 @@ def same_line(strs:list[list[str]|None], split=8) -> list[str]:
  for i in range(max_height):
    line = []
    for bid, block in enumerate(strs):
-      if i < len(block): line.append(block[i] + ' ' * (split + max_width_in_block[bid] - ansilen(block[i])))
+      if i < len(block): line.append(block[i] + (' ' * (split + max_width_in_block[bid] - ansilen(block[i])) if bid != len(strs) - 1 else ''))
      else: line.append(' ' * (split + max_width_in_block[bid]))
    ret.append(' '.join(line))
  return ret
@@ -55,9 +59,9 @@ def get_bar0_size(pcibus):
  return int(end_hex, 16) - int(start_hex, 16) + 1

 class AMSMI(AMDev):
-  def __init__(self, pcibus, vram_bar:memoryview, doorbell_bar:memoryview, mmio_bar:memoryview):
+  def __init__(self, pcibus, vram_bar:MMIOInterface, doorbell_bar:MMIOInterface, mmio_bar:MMIOInterface):
    self.pcibus = pcibus
-    self.vram, self.doorbell64, self.mmio = vram_bar, doorbell_bar, mmio_bar
+    self.vram, self.doorbell64, self.mmio, self.dma_regions = vram_bar, doorbell_bar, mmio_bar, None
    self.pci_state = self.read_pci_state()
    if self.pci_state == "D0": self._init_from_d0()

@@ -103,9 +107,9 @@ class SMICtx:
      bar_fds = {bar: os.open(f"/sys/bus/pci/devices/{pcibus}/resource{bar}", os.O_RDWR | os.O_SYNC) for bar in [0, 2, 5]}
      bar_size = {0: get_bar0_size(pcibus), 2: os.fstat(bar_fds[2]).st_size, 5: os.fstat(bar_fds[5]).st_size}

-      def map_pci_range(bar):
-        return to_mv(libc.mmap(0, bar_size[bar], mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED, bar_fds[bar], 0), bar_size[bar])
-      self.opened_pci_resources[pcibus] = (map_pci_range(0), None, map_pci_range(5).cast('I'))
+      def map_pci_range(bar, fmt='B'):
+        return MMIOInterface(libc.mmap(0, bar_size[bar], mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED, bar_fds[bar], 0), bar_size[bar], fmt)
+      self.opened_pci_resources[pcibus] = (map_pci_range(0), None, map_pci_range(5, 'I'))

    try:
      self.devs.append(AMSMI(pcibus, *self.opened_pci_resources[pcibus]))
@@ -136,83 +140,95 @@ class SMICtx:

  def collect(self): return {d: d.smu.read_metrics() if d.pci_state == "D0" else None for d in self.devs}

+  def get_gfx_activity(self, dev, metrics): return metrics.SmuMetrics.AverageGfxActivity
+  def get_mem_activity(self, dev, metrics): return metrics.SmuMetrics.AverageUclkActivity
+
+  def get_temps(self, dev, metrics, compact=False):
+    temps_keys = [(k, name) for k, name in dev.smu.smu_mod.c__EA_TEMP_e__enumvalues.items()
+                  if k < dev.smu.smu_mod.TEMP_COUNT and metrics.SmuMetrics.AvgTemperature[k] != 0]
+    if compact: temps_keys = [(k, name) for k, name in temps_keys if k in (dev.smu.smu_mod.TEMP_HOTSPOT, dev.smu.smu_mod.TEMP_MEM)]
+    return {name: metrics.SmuMetrics.AvgTemperature[k] for k, name in temps_keys}
+
+  def get_voltage(self, dev, metrics, compact=False):
+    voltage_keys = [(k, name) for k, name in dev.smu.smu_mod.c__EA_SVI_PLANE_e__enumvalues.items()
+                        if k < dev.smu.smu_mod.SVI_PLANE_COUNT and metrics.SmuMetrics.AvgVoltage[k] != 0]
+    return {name: metrics.SmuMetrics.AvgVoltage[k] for k, name in voltage_keys}
+
+  def get_busy_threshold(self, dev):
+    match dev.ip_ver[am.MP1_HWIP]:
+      case (14, 0, 2): return 5
+      case _: return 15
+
+  def get_gfx_freq(self, dev, metrics):
+    return metrics.SmuMetrics.AverageGfxclkFrequencyPostDs if self.get_gfx_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
+          metrics.SmuMetrics.AverageGfxclkFrequencyPreDs
+
+  def get_mem_freq(self, dev, metrics):
+    return metrics.SmuMetrics.AverageMemclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
+           metrics.SmuMetrics.AverageMemclkFrequencyPreDs
+
+  def get_fckl_freq(self, dev, metrics):
+    return metrics.SmuMetrics.AverageFclkFrequencyPostDs if self.get_mem_activity(dev, metrics) <= self.get_busy_threshold(dev) else \
+           metrics.SmuMetrics.AverageFclkFrequencyPreDs
+
+  def get_fan_rpm_pwm(self, dev, metrics): return metrics.SmuMetrics.AvgFanRpm, metrics.SmuMetrics.AvgFanPwm
+
+  def get_power(self, dev, metrics): return metrics.SmuMetrics.AverageSocketPower, metrics.SmuMetrics.dGPU_W_MAX
+
  def draw(self):
    terminal_width, terminal_height = shutil.get_terminal_size()
    if self.prev_terminal_width != terminal_width or self.prev_terminal_height != terminal_height:
      os.system('clear')
    self.prev_terminal_width, self.prev_terminal_height = terminal_width, terminal_height

-    activity_line_width = 50 if self.prev_terminal_width > 170 else \
-                         (30 if self.prev_terminal_width > 130 else \
-                         (16 if self.prev_terminal_width > 92 else \
-                         max(0, self.prev_terminal_width - 77)))
-    max_col_size = terminal_width // 2
+    padding = 8
+    col_size = (terminal_width) // 2 - padding - 2
+    activity_line_width = 50 if terminal_width > 170 else \
+                         (30 if terminal_width > 130 else \
+                         (16 if terminal_width > 92 else \
+                         max(0, terminal_width - 77)))

    dev_metrics = self.collect()
    dev_content = []
    for dev, metrics in dev_metrics.items():
      if dev.pci_state != "D0":
-        dev_content.append([f"{colored('(sleep)', 'yellow')} {bold(dev.pcibus)}: {self.lspci[dev.pcibus[5:]]}"] +
-                           [f"PCI State: {dev.pci_state}"] + [" "*107])
+        dev_content.append([f"{colored('(sleep)', 'yellow')} {bold(dev.pcibus)}: {trim(self.lspci[dev.pcibus[5:]], col_size - 20)}"] +
+                           [pad(f"PCI State: {dev.pci_state}", col_size)])
        continue

-      device_line = [f"{bold(dev.pcibus)} {trim(self.lspci[dev.pcibus[5:]], max_col_size - 24)}"] + [""]
-      activity_line = [f"GFX Activity {draw_bar(metrics.SmuMetrics.AverageGfxActivity / 100, activity_line_width)}"] \
-                    + [f"MEM Activity {draw_bar(metrics.SmuMetrics.AverageUclkActivity / 100, activity_line_width)}"]
+      device_line = [f"{bold(dev.pcibus)} {trim(self.lspci[dev.pcibus[5:]], col_size - 20)}"] + [pad("", col_size)]
+      activity_line = [f"GFX Activity {draw_bar(self.get_gfx_activity(dev, metrics) / 100, activity_line_width)}"] \
+                    + [f"MEM Activity {draw_bar(self.get_mem_activity(dev, metrics) / 100, activity_line_width)}"]

-      # draw_metrics_table(metrics, dev)
-      temps_keys = [(k, name) for k, name in smu_v13_0_0.c__EA_TEMP_e__enumvalues.items()
-                                if k < smu_v13_0_0.TEMP_COUNT and metrics.SmuMetrics.AvgTemperature[k] != 0]
-      temps_table = ["=== Temps (°C) ==="] + [f"{name:<15}: {color_temp(metrics.SmuMetrics.AvgTemperature[k])}" for k, name in temps_keys]
-      temps_table_compact = [f"Temps (°C): {color_temp(metrics.SmuMetrics.AvgTemperature[smu_v13_0_0.TEMP_HOTSPOT])} hotspot /" \
-                          + f"{color_temp(metrics.SmuMetrics.AvgTemperature[smu_v13_0_0.TEMP_MEM])} mem"]
+      temps_data, temps_data_compact = self.get_temps(dev, metrics), self.get_temps(dev, metrics, compact=True)
+      temps_table = ["=== Temps (°C) ==="] + [f"{name:<16}: {color_temp(val)}" for name, val in temps_data.items()]
+      temps_table_compact = ["Temps (°C):" + '/'.join([f"{color_temp(val)} {name}" for name, val in temps_data_compact.items()])]

-      voltage_keys = [(k, name) for k, name in smu_v13_0_0.c__EA_SVI_PLANE_e__enumvalues.items() if k < smu_v13_0_0.SVI_PLANE_COUNT]
-      power_table = ["=== Power ==="] \
-                  + [f"Fan Speed: {metrics.SmuMetrics.AvgFanRpm} RPM"] \
-                  + [f"Fan Power: {metrics.SmuMetrics.AvgFanPwm}%"]
-      power_line = [f"Power: {metrics.SmuMetrics.AverageSocketPower:>3}W " +
-                       draw_bar(metrics.SmuMetrics.AverageSocketPower / metrics.SmuMetrics.dGPU_W_MAX, 16)]
-      power_line_compact = [f"Power:  {metrics.SmuMetrics.AverageSocketPower:>3}W " +
-                       draw_bar(metrics.SmuMetrics.AverageSocketPower / metrics.SmuMetrics.dGPU_W_MAX, activity_line_width)]
+      fan_rpm, fan_pwm = self.get_fan_rpm_pwm(dev, metrics)
+      power_table = ["=== Power ==="] + [f"Fan Speed: {fan_rpm} RPM"] + [f"Fan Power: {fan_pwm}%"]

-      voltage_table = ["=== Voltages ==="] + [f"{name:<20}: {color_voltage(metrics.SmuMetrics.AvgVoltage[k])}" for k, name in voltage_keys]
+      total_power, max_power = self.get_power(dev, metrics)
+      power_line = [f"Power: {total_power:>3}W " + draw_bar(total_power / max_power, 16)]
+      power_line_compact = [f"Power:  {total_power:>3}W " + draw_bar(total_power / max_power, activity_line_width)]

-      gfx_freq = (metrics.SmuMetrics.AverageGfxclkFrequencyPostDs if metrics.SmuMetrics.AverageGfxActivity <= SMU_11_0_GFX_BUSY_THRESHOLD else \
-                  metrics.SmuMetrics.AverageGfxclkFrequencyPreDs)
-      fclk_freq = (metrics.SmuMetrics.AverageFclkFrequencyPostDs if metrics.SmuMetrics.AverageUclkActivity <= SMU_11_0_GFX_BUSY_THRESHOLD else \
-                   metrics.SmuMetrics.AverageFclkFrequencyPreDs)
-      mclk_freq = (metrics.SmuMetrics.AverageMemclkFrequencyPostDs if metrics.SmuMetrics.AverageUclkActivity <= SMU_11_0_GFX_BUSY_THRESHOLD else \
-                   metrics.SmuMetrics.AverageMemclkFrequencyPreDs)
+      voltage_data = self.get_voltage(dev, metrics)
+      voltage_table = ["=== Voltages ==="] + [f"{name:<20}: {color_voltage(voltage)}" for name, voltage in voltage_data.items()]

-      frequency_table = ["=== Frequencies ===",
-        f"GFXCLK Target : {metrics.SmuMetrics.AverageGfxclkFrequencyTarget:>4} MHz",
-        f"GFXCLK PreDs  : {metrics.SmuMetrics.AverageGfxclkFrequencyPreDs:>4} MHz",
-        f"GFXCLK PostDs : {metrics.SmuMetrics.AverageGfxclkFrequencyPostDs:>4} MHz",
-        f"FCLK PreDs    : {metrics.SmuMetrics.AverageFclkFrequencyPreDs:>4} MHz",
-        f"FCLK PostDs   : {metrics.SmuMetrics.AverageFclkFrequencyPostDs:>4} MHz",
-        f"MCLK PreDs    : {metrics.SmuMetrics.AverageMemclkFrequencyPreDs:>4} MHz",
-        f"MCLK PostDs   : {metrics.SmuMetrics.AverageMemclkFrequencyPostDs:>4} MHz",
-        f"VCLK0         : {metrics.SmuMetrics.AverageVclk0Frequency:>4} MHz",
-        f"DCLK0         : {metrics.SmuMetrics.AverageDclk0Frequency:>4} MHz",
-        f"VCLK1         : {metrics.SmuMetrics.AverageVclk1Frequency:>4} MHz",
-        f"DCLK1         : {metrics.SmuMetrics.AverageDclk1Frequency:>4} MHz"]
+      gfx_freq = self.get_gfx_freq(dev, metrics)
+      mclk_freq = self.get_mem_freq(dev, metrics)
+      fclk_freq = self.get_fckl_freq(dev, metrics)

-      frequency_table_compact = ["=== Frequencies ===",
-        f"GFXCLK: {gfx_freq:>4} MHz",
-        f"FCLK  : {fclk_freq:>4} MHz",
-        f"MCLK  : {mclk_freq:>4} MHz"]
+      frequency_table = ["=== Frequencies ===", f"GFXCLK: {gfx_freq:>4} MHz", f"FCLK  : {fclk_freq:>4} MHz", f"MCLK  : {mclk_freq:>4} MHz"]

      if self.prev_terminal_width >= 231:
        power_table += power_line + [""] + voltage_table
        activity_line += [""]
      elif self.prev_terminal_width >= 171:
-        power_table += power_line + [""] + frequency_table_compact
+        power_table += power_line + [""] + frequency_table
        activity_line += [""]
        frequency_table = None
      elif self.prev_terminal_width >= 121:
        temps_table = None
-        frequency_table = frequency_table_compact
        activity_line += power_line_compact
      else:
        temps_table = None
@@ -224,7 +240,7 @@ class SMICtx:

    raw_text = 'AM Monitor'.center(terminal_width) + "\n" + "=" * terminal_width + "\n\n"
    for i in range(0, len(dev_content), 2):
-      if i + 1 < len(dev_content): raw_text += '\n'.join(same_line([dev_content[i], dev_content[i+1]]))
+      if i + 1 < len(dev_content): raw_text += '\n'.join(same_line([dev_content[i], dev_content[i+1]], split=padding))
      else: raw_text += '\n'.join(dev_content[i])
      if i + 2 < len(dev_content): raw_text += "\n" + "=" * terminal_width + "\n\n"

@@ -1,209 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _hdp_6_0_0_OFFSET_HEADER
-#define _hdp_6_0_0_OFFSET_HEADER
-
-
-
-// addressBlock: hdp_hdpdec
-// base address: 0x3c80
-#define regHDP_NONSURFACE_BASE                                                                          0x0040
-#define regHDP_NONSURFACE_BASE_BASE_IDX                                                                 0
-#define regHDP_NONSURFACE_INFO                                                                          0x0041
-#define regHDP_NONSURFACE_INFO_BASE_IDX                                                                 0
-#define regHDP_NONSURFACE_BASE_HI                                                                       0x0042
-#define regHDP_NONSURFACE_BASE_HI_BASE_IDX                                                              0
-#define regHDP_SURFACE_WRITE_FLAGS                                                                      0x00c4
-#define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX                                                             0
-#define regHDP_SURFACE_READ_FLAGS                                                                       0x00c5
-#define regHDP_SURFACE_READ_FLAGS_BASE_IDX                                                              0
-#define regHDP_SURFACE_WRITE_FLAGS_CLR                                                                  0x00c6
-#define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX                                                         0
-#define regHDP_SURFACE_READ_FLAGS_CLR                                                                   0x00c7
-#define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX                                                          0
-#define regHDP_NONSURF_FLAGS                                                                            0x00c8
-#define regHDP_NONSURF_FLAGS_BASE_IDX                                                                   0
-#define regHDP_NONSURF_FLAGS_CLR                                                                        0x00c9
-#define regHDP_NONSURF_FLAGS_CLR_BASE_IDX                                                               0
-#define regHDP_HOST_PATH_CNTL                                                                           0x00cc
-#define regHDP_HOST_PATH_CNTL_BASE_IDX                                                                  0
-#define regHDP_SW_SEMAPHORE                                                                             0x00cd
-#define regHDP_SW_SEMAPHORE_BASE_IDX                                                                    0
-#define regHDP_DEBUG0                                                                                   0x00ce
-#define regHDP_DEBUG0_BASE_IDX                                                                          0
-#define regHDP_LAST_SURFACE_HIT                                                                         0x00d0
-#define regHDP_LAST_SURFACE_HIT_BASE_IDX                                                                0
-#define regHDP_OUTSTANDING_REQ                                                                          0x00d2
-#define regHDP_OUTSTANDING_REQ_BASE_IDX                                                                 0
-#define regHDP_MISC_CNTL                                                                                0x00d3
-#define regHDP_MISC_CNTL_BASE_IDX                                                                       0
-#define regHDP_MEM_POWER_CTRL                                                                           0x00d4
-#define regHDP_MEM_POWER_CTRL_BASE_IDX                                                                  0
-#define regHDP_MMHUB_CNTL                                                                               0x00d5
-#define regHDP_MMHUB_CNTL_BASE_IDX                                                                      0
-#define regHDP_VERSION                                                                                  0x00d7
-#define regHDP_VERSION_BASE_IDX                                                                         0
-#define regHDP_CLK_CNTL                                                                                 0x00d8
-#define regHDP_CLK_CNTL_BASE_IDX                                                                        0
-#define regHDP_MEMIO_CNTL                                                                               0x00f6
-#define regHDP_MEMIO_CNTL_BASE_IDX                                                                      0
-#define regHDP_MEMIO_ADDR                                                                               0x00f7
-#define regHDP_MEMIO_ADDR_BASE_IDX                                                                      0
-#define regHDP_MEMIO_STATUS                                                                             0x00f8
-#define regHDP_MEMIO_STATUS_BASE_IDX                                                                    0
-#define regHDP_MEMIO_WR_DATA                                                                            0x00f9
-#define regHDP_MEMIO_WR_DATA_BASE_IDX                                                                   0
-#define regHDP_MEMIO_RD_DATA                                                                            0x00fa
-#define regHDP_MEMIO_RD_DATA_BASE_IDX                                                                   0
-#define regHDP_XDP_DIRECT2HDP_FIRST                                                                     0x0100
-#define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX                                                            0
-#define regHDP_XDP_D2H_FLUSH                                                                            0x0101
-#define regHDP_XDP_D2H_FLUSH_BASE_IDX                                                                   0
-#define regHDP_XDP_D2H_BAR_UPDATE                                                                       0x0102
-#define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX                                                              0
-#define regHDP_XDP_D2H_RSVD_3                                                                           0x0103
-#define regHDP_XDP_D2H_RSVD_3_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_4                                                                           0x0104
-#define regHDP_XDP_D2H_RSVD_4_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_5                                                                           0x0105
-#define regHDP_XDP_D2H_RSVD_5_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_6                                                                           0x0106
-#define regHDP_XDP_D2H_RSVD_6_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_7                                                                           0x0107
-#define regHDP_XDP_D2H_RSVD_7_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_8                                                                           0x0108
-#define regHDP_XDP_D2H_RSVD_8_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_9                                                                           0x0109
-#define regHDP_XDP_D2H_RSVD_9_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_10                                                                          0x010a
-#define regHDP_XDP_D2H_RSVD_10_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_11                                                                          0x010b
-#define regHDP_XDP_D2H_RSVD_11_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_12                                                                          0x010c
-#define regHDP_XDP_D2H_RSVD_12_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_13                                                                          0x010d
-#define regHDP_XDP_D2H_RSVD_13_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_14                                                                          0x010e
-#define regHDP_XDP_D2H_RSVD_14_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_15                                                                          0x010f
-#define regHDP_XDP_D2H_RSVD_15_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_16                                                                          0x0110
-#define regHDP_XDP_D2H_RSVD_16_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_17                                                                          0x0111
-#define regHDP_XDP_D2H_RSVD_17_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_18                                                                          0x0112
-#define regHDP_XDP_D2H_RSVD_18_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_19                                                                          0x0113
-#define regHDP_XDP_D2H_RSVD_19_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_20                                                                          0x0114
-#define regHDP_XDP_D2H_RSVD_20_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_21                                                                          0x0115
-#define regHDP_XDP_D2H_RSVD_21_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_22                                                                          0x0116
-#define regHDP_XDP_D2H_RSVD_22_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_23                                                                          0x0117
-#define regHDP_XDP_D2H_RSVD_23_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_24                                                                          0x0118
-#define regHDP_XDP_D2H_RSVD_24_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_25                                                                          0x0119
-#define regHDP_XDP_D2H_RSVD_25_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_26                                                                          0x011a
-#define regHDP_XDP_D2H_RSVD_26_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_27                                                                          0x011b
-#define regHDP_XDP_D2H_RSVD_27_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_28                                                                          0x011c
-#define regHDP_XDP_D2H_RSVD_28_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_29                                                                          0x011d
-#define regHDP_XDP_D2H_RSVD_29_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_30                                                                          0x011e
-#define regHDP_XDP_D2H_RSVD_30_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_31                                                                          0x011f
-#define regHDP_XDP_D2H_RSVD_31_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_32                                                                          0x0120
-#define regHDP_XDP_D2H_RSVD_32_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_33                                                                          0x0121
-#define regHDP_XDP_D2H_RSVD_33_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_34                                                                          0x0122
-#define regHDP_XDP_D2H_RSVD_34_BASE_IDX                                                                 0
-#define regHDP_XDP_DIRECT2HDP_LAST                                                                      0x0123
-#define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX                                                             0
-#define regHDP_XDP_P2P_BAR_CFG                                                                          0x0124
-#define regHDP_XDP_P2P_BAR_CFG_BASE_IDX                                                                 0
-#define regHDP_XDP_P2P_MBX_OFFSET                                                                       0x0125
-#define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX                                                              0
-#define regHDP_XDP_P2P_MBX_ADDR0                                                                        0x0126
-#define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR1                                                                        0x0127
-#define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR2                                                                        0x0128
-#define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR3                                                                        0x0129
-#define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR4                                                                        0x012a
-#define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR5                                                                        0x012b
-#define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR6                                                                        0x012c
-#define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX                                                               0
-#define regHDP_XDP_HDP_MBX_MC_CFG                                                                       0x012d
-#define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX                                                              0
-#define regHDP_XDP_HDP_MC_CFG                                                                           0x012e
-#define regHDP_XDP_HDP_MC_CFG_BASE_IDX                                                                  0
-#define regHDP_XDP_HST_CFG                                                                              0x012f
-#define regHDP_XDP_HST_CFG_BASE_IDX                                                                     0
-#define regHDP_XDP_HDP_IPH_CFG                                                                          0x0131
-#define regHDP_XDP_HDP_IPH_CFG_BASE_IDX                                                                 0
-#define regHDP_XDP_P2P_BAR0                                                                             0x0134
-#define regHDP_XDP_P2P_BAR0_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR1                                                                             0x0135
-#define regHDP_XDP_P2P_BAR1_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR2                                                                             0x0136
-#define regHDP_XDP_P2P_BAR2_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR3                                                                             0x0137
-#define regHDP_XDP_P2P_BAR3_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR4                                                                             0x0138
-#define regHDP_XDP_P2P_BAR4_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR5                                                                             0x0139
-#define regHDP_XDP_P2P_BAR5_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR6                                                                             0x013a
-#define regHDP_XDP_P2P_BAR6_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR7                                                                             0x013b
-#define regHDP_XDP_P2P_BAR7_BASE_IDX                                                                    0
-#define regHDP_XDP_FLUSH_ARMED_STS                                                                      0x013c
-#define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX                                                             0
-#define regHDP_XDP_FLUSH_CNTR0_STS                                                                      0x013d
-#define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX                                                             0
-#define regHDP_XDP_BUSY_STS                                                                             0x013e
-#define regHDP_XDP_BUSY_STS_BASE_IDX                                                                    0
-#define regHDP_XDP_STICKY                                                                               0x013f
-#define regHDP_XDP_STICKY_BASE_IDX                                                                      0
-#define regHDP_XDP_CHKN                                                                                 0x0140
-#define regHDP_XDP_CHKN_BASE_IDX                                                                        0
-#define regHDP_XDP_BARS_ADDR_39_36                                                                      0x0144
-#define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX                                                             0
-#define regHDP_XDP_MC_VM_FB_LOCATION_BASE                                                               0x0145
-#define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX                                                      0
-#define regHDP_XDP_MMHUB_ERROR                                                                          0x014a
-#define regHDP_XDP_MMHUB_ERROR_BASE_IDX                                                                 0
-
-#endif
@@ -1,646 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _hdp_6_0_0_SH_MASK_HEADER
-#define _hdp_6_0_0_SH_MASK_HEADER
-
-
-// addressBlock: hdp_hdpdec
-//HDP_NONSURFACE_BASE
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT                                                         0x0
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK                                                           0xFFFFFFFFL
-//HDP_NONSURFACE_INFO
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT                                                              0x4
-#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT                                                              0x8
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK                                                                0x00000030L
-#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK                                                                0x00000F00L
-//HDP_NONSURFACE_BASE_HI
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT                                                     0x0
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK                                                       0x000000FFL
-//HDP_SURFACE_WRITE_FLAGS
-#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT                                                      0x0
-#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT                                                      0x1
-#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK                                                        0x00000001L
-#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK                                                        0x00000002L
-//HDP_SURFACE_READ_FLAGS
-#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT                                                        0x0
-#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT                                                        0x1
-#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK                                                          0x00000001L
-#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK                                                          0x00000002L
-//HDP_SURFACE_WRITE_FLAGS_CLR
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT                                              0x0
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT                                              0x1
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK                                                0x00000001L
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK                                                0x00000002L
-//HDP_SURFACE_READ_FLAGS_CLR
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT                                                0x0
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT                                                0x1
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK                                                  0x00000001L
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK                                                  0x00000002L
-//HDP_NONSURF_FLAGS
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT                                                          0x0
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT                                                           0x1
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK                                                            0x00000001L
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK                                                             0x00000002L
-//HDP_NONSURF_FLAGS_CLR
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT                                                  0x0
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT                                                   0x1
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK                                                    0x00000001L
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK                                                     0x00000002L
-//HDP_HOST_PATH_CNTL
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT                                                             0x9
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT                                                             0xb
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT                                            0x12
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT                                                        0x13
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT                                                           0x15
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT                                                       0x16
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT                                                           0x1d
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK                                                               0x00000600L
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK                                                               0x00001800L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK                                              0x00040000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK                                                          0x00180000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK                                                             0x00200000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK                                                         0x00400000L
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK                                                             0x20000000L
-//HDP_SW_SEMAPHORE
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT                                                                 0x0
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK                                                                   0xFFFFFFFFL
-//HDP_DEBUG0
-#define HDP_DEBUG0__HDP_DEBUG__SHIFT                                                                          0x0
-#define HDP_DEBUG0__HDP_DEBUG_MASK                                                                            0xFFFFFFFFL
-//HDP_LAST_SURFACE_HIT
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT                                                         0x0
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK                                                           0x00000003L
-//HDP_OUTSTANDING_REQ
-#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT                                                                 0x0
-#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT                                                                  0x8
-#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK                                                                   0x000000FFL
-#define HDP_OUTSTANDING_REQ__READ_REQ_MASK                                                                    0x0000FF00L
-//HDP_MISC_CNTL
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT                                                            0x2
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT                                                    0x5
-#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT                                                        0x8
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT                                                       0xb
-#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT                                                           0xe
-#define HDP_MISC_CNTL__NACK_ENABLE__SHIFT                                                                     0x13
-#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT                                                              0x14
-#define HDP_MISC_CNTL__FED_ENABLE__SHIFT                                                                      0x15
-#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT                                                               0x16
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT                                                            0x18
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT                                                              0x1e
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK                                                              0x0000000CL
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK                                                      0x00000020L
-#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK                                                          0x00000100L
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK                                                         0x00000800L
-#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK                                                             0x0000C000L
-#define HDP_MISC_CNTL__NACK_ENABLE_MASK                                                                       0x00080000L
-#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK                                                                0x00100000L
-#define HDP_MISC_CNTL__FED_ENABLE_MASK                                                                        0x00200000L
-#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK                                                                 0x00400000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK                                                              0x01000000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK                                                                0x40000000L
-//HDP_MEM_POWER_CTRL
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT                                                   0x0
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT                                                     0x1
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT                                                     0x2
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT                                                     0x3
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT                                                 0x4
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT                                          0x8
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT                                          0xe
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT                                                       0x10
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT                                                         0x11
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT                                                         0x12
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT                                                         0x13
-#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT                                                     0x14
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT                                              0x18
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT                                              0x1e
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK                                                     0x00000001L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK                                                       0x00000002L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK                                                       0x00000004L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK                                                       0x00000008L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK                                                   0x00000070L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK                                            0x00003F00L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK                                            0x0000C000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK                                                         0x00010000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK                                                           0x00020000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK                                                           0x00040000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK                                                           0x00080000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK                                                       0x00700000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK                                                0x3F000000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK                                                0xC0000000L
-//HDP_MMHUB_CNTL
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT                                                                   0x0
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT                                                                  0x1
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT                                                                0x2
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK                                                                     0x00000001L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK                                                                    0x00000002L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK                                                                  0x00000004L
-//HDP_VERSION
-#define HDP_VERSION__MINVER__SHIFT                                                                            0x0
-#define HDP_VERSION__MAJVER__SHIFT                                                                            0x8
-#define HDP_VERSION__REV__SHIFT                                                                               0x10
-#define HDP_VERSION__MINVER_MASK                                                                              0x000000FFL
-#define HDP_VERSION__MAJVER_MASK                                                                              0x0000FF00L
-#define HDP_VERSION__REV_MASK                                                                                 0x00FF0000L
-//HDP_CLK_CNTL
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT                                                             0x0
-#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT                                                     0x1a
-#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT                                                         0x1b
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT                                                           0x1c
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT                                                            0x1d
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1e
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1f
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK                                                               0x0000000FL
-#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK                                                       0x04000000L
-#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK                                                           0x08000000L
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK                                                             0x10000000L
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK                                                              0x20000000L
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK                                                          0x40000000L
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK                                                          0x80000000L
-//HDP_MEMIO_CNTL
-#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT                                                                     0x0
-#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT                                                                       0x1
-#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT                                                                       0x2
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT                                                                0x6
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT                                                                0x7
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT                                                               0x8
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT                                                             0xe
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT                                                             0xf
-#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT                                                                       0x10
-#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT                                                                     0x11
-#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK                                                                       0x00000001L
-#define HDP_MEMIO_CNTL__MEMIO_OP_MASK                                                                         0x00000002L
-#define HDP_MEMIO_CNTL__MEMIO_BE_MASK                                                                         0x0000003CL
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK                                                                  0x00000040L
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK                                                                  0x00000080L
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK                                                                 0x00003F00L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK                                                               0x00004000L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK                                                               0x00008000L
-#define HDP_MEMIO_CNTL__MEMIO_VF_MASK                                                                         0x00010000L
-#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK                                                                       0x003E0000L
-//HDP_MEMIO_ADDR
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT                                                               0x0
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK                                                                 0xFFFFFFFFL
-//HDP_MEMIO_STATUS
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT                                                              0x0
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT                                                              0x1
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT                                                               0x2
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT                                                               0x3
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK                                                                0x00000001L
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK                                                                0x00000002L
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK                                                                 0x00000004L
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK                                                                 0x00000008L
-//HDP_MEMIO_WR_DATA
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT                                                               0x0
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK                                                                 0xFFFFFFFFL
-//HDP_MEMIO_RD_DATA
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT                                                               0x0
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK                                                                 0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_FIRST
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT                                                             0x0
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK                                                               0xFFFFFFFFL
-//HDP_XDP_D2H_FLUSH
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT                                                         0x0
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT                                                      0x4
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT                                                      0x8
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT                                                           0xb
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT                                                         0x10
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT                                                   0x12
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT                                                            0x13
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT                                                            0x14
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK                                                           0x0000000FL
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK                                                        0x000000F0L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK                                                        0x00000700L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK                                                             0x0000F800L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK                                                           0x00010000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK                                                     0x00040000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK                                                              0x00080000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK                                                              0x00100000L
-//HDP_XDP_D2H_BAR_UPDATE
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT                                                    0x0
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT                                               0x10
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT                                                 0x14
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK                                                      0x0000FFFFL
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK                                                 0x000F0000L
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK                                                   0x00700000L
-//HDP_XDP_D2H_RSVD_3
-#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_4
-#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_5
-#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_6
-#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_7
-#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_8
-#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_9
-#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_10
-#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_11
-#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_12
-#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_13
-#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_14
-#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_15
-#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_16
-#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_17
-#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_18
-#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_19
-#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_20
-#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_21
-#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_22
-#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_23
-#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_24
-#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_25
-#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_26
-#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_27
-#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_28
-#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_29
-#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_30
-#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_31
-#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_32
-#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_33
-#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_34
-#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_LAST
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT                                                              0x0
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK                                                                0xFFFFFFFFL
-//HDP_XDP_P2P_BAR_CFG
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT                                                     0x0
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT                                                      0x4
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK                                                       0x0000000FL
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK                                                        0x00000030L
-//HDP_XDP_P2P_MBX_OFFSET
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT                                                         0x0
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK                                                           0x0001FFFFL
-//HDP_XDP_P2P_MBX_ADDR0
-#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR1
-#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR2
-#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR3
-#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR4
-#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR5
-#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR6
-#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_HDP_MBX_MC_CFG
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT                                           0x0
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT                                          0x4
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT                                          0x8
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT                                            0xc
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT                                           0xd
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT                                         0xe
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK                                             0x0000000FL
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK                                            0x00000030L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK                                            0x00000F00L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK                                              0x00001000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK                                             0x00002000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK                                           0x00004000L
-//HDP_XDP_HDP_MC_CFG
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT                                               0x3
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT                                                0x4
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT                                                0x8
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT                                                  0xc
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT                                                 0xd
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT                                           0xe
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK                                                 0x00000008L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK                                                  0x00000030L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK                                                  0x00000F00L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK                                                    0x00001000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK                                                   0x00002000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK                                             0x000FC000L
-//HDP_XDP_HST_CFG
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT                                                         0x0
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT                                                      0x1
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT                                                           0x3
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT                                                     0x4
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT                                          0x5
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK                                                           0x00000001L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK                                                        0x00000006L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK                                                             0x00000008L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK                                                       0x00000010L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK                                            0x00000020L
-//HDP_XDP_HDP_IPH_CFG
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT                                     0xc
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT                                                     0xd
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK                                       0x00001000L
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK                                                       0x00002000L
-//HDP_XDP_P2P_BAR0
-#define HDP_XDP_P2P_BAR0__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR0__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR0__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR0__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR0__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR1
-#define HDP_XDP_P2P_BAR1__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR1__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR1__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR1__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR1__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR2
-#define HDP_XDP_P2P_BAR2__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR2__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR2__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR2__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR2__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR3
-#define HDP_XDP_P2P_BAR3__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR3__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR3__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR3__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR3__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR4
-#define HDP_XDP_P2P_BAR4__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR4__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR4__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR4__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR4__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR5
-#define HDP_XDP_P2P_BAR5__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR5__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR5__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR5__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR5__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR6
-#define HDP_XDP_P2P_BAR6__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR6__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR6__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR6__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR6__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR7
-#define HDP_XDP_P2P_BAR7__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR7__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR7__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR7__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR7__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_FLUSH_ARMED_STS
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT                                                       0x0
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK                                                         0xFFFFFFFFL
-//HDP_XDP_FLUSH_CNTR0_STS
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT                                                       0x0
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK                                                         0x03FFFFFFL
-//HDP_XDP_BUSY_STS
-#define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT                                                                  0x0
-#define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT                                                                  0x1
-#define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT                                                                  0x2
-#define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT                                                                  0x3
-#define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT                                                                  0x4
-#define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT                                                                  0x5
-#define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT                                                                  0x6
-#define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT                                                                  0x7
-#define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT                                                                  0x8
-#define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT                                                                  0x9
-#define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT                                                                 0xa
-#define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT                                                                 0xb
-#define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT                                                                 0xc
-#define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT                                                                 0xd
-#define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT                                                                 0xe
-#define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT                                                                 0xf
-#define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT                                                                 0x10
-#define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT                                                                 0x11
-#define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT                                                                 0x12
-#define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT                                                                 0x13
-#define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT                                                                 0x14
-#define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT                                                                 0x15
-#define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT                                                                 0x16
-#define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT                                                                 0x17
-#define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT                                                                  0x18
-#define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK                                                                    0x00000001L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK                                                                    0x00000002L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK                                                                    0x00000004L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK                                                                    0x00000008L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK                                                                    0x00000010L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK                                                                    0x00000020L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK                                                                    0x00000040L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK                                                                    0x00000080L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK                                                                    0x00000100L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK                                                                    0x00000200L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK                                                                   0x00000400L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK                                                                   0x00000800L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK                                                                   0x00001000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK                                                                   0x00002000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK                                                                   0x00004000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK                                                                   0x00008000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK                                                                   0x00010000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK                                                                   0x00020000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK                                                                   0x00040000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK                                                                   0x00080000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK                                                                   0x00100000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK                                                                   0x00200000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK                                                                   0x00400000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK                                                                   0x00800000L
-#define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK                                                                    0x01000000L
-//HDP_XDP_STICKY
-#define HDP_XDP_STICKY__STICKY_STS__SHIFT                                                                     0x0
-#define HDP_XDP_STICKY__STICKY_W1C__SHIFT                                                                     0x10
-#define HDP_XDP_STICKY__STICKY_STS_MASK                                                                       0x0000FFFFL
-#define HDP_XDP_STICKY__STICKY_W1C_MASK                                                                       0xFFFF0000L
-//HDP_XDP_CHKN
-#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT                                                                      0x0
-#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT                                                                      0x8
-#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT                                                                      0x10
-#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT                                                                      0x18
-#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK                                                                        0x000000FFL
-#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK                                                                        0x0000FF00L
-#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK                                                                        0x00FF0000L
-#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK                                                                        0xFF000000L
-//HDP_XDP_BARS_ADDR_39_36
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT                                                       0x0
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT                                                       0x4
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT                                                       0x8
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT                                                       0xc
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT                                                       0x10
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT                                                       0x14
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT                                                       0x18
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT                                                       0x1c
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK                                                         0x0000000FL
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK                                                         0x000000F0L
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK                                                         0x00000F00L
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK                                                         0x0000F000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK                                                         0x000F0000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK                                                         0x00F00000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK                                                         0x0F000000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK                                                         0xF0000000L
-//HDP_XDP_MC_VM_FB_LOCATION_BASE
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                        0x0
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                          0x03FFFFFFL
-//HDP_XDP_MMHUB_ERROR
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT                                                              0x1
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT                                                              0x2
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT                                                              0x3
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED__SHIFT                                                             0x4
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT                                                         0x5
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT                                                         0x6
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT                                                         0x7
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT                                                              0x9
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT                                                              0xa
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT                                                              0xb
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED__SHIFT                                                             0xc
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT                                                         0xd
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT                                                         0xe
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT                                                         0xf
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT                                                              0x11
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT                                                              0x12
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT                                                              0x13
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT                                                         0x15
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT                                                         0x16
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT                                                         0x17
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK                                                                0x00000002L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK                                                                0x00000004L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK                                                                0x00000008L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_FED_MASK                                                               0x00000010L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK                                                           0x00000020L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK                                                           0x00000040L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK                                                           0x00000080L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK                                                                0x00000200L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK                                                                0x00000400L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK                                                                0x00000800L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_FED_MASK                                                               0x00001000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK                                                           0x00002000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK                                                           0x00004000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK                                                           0x00008000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK                                                                0x00020000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK                                                                0x00040000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK                                                                0x00080000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK                                                           0x00200000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK                                                           0x00400000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK                                                           0x00800000L
-
-#endif
@@ -1,219 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _hdp_7_0_0_OFFSET_HEADER
-#define _hdp_7_0_0_OFFSET_HEADER
-
-
-
-// addressBlock: hdp_hdpdec
-// base address: 0x3c80
-#define regHDP_MMHUB_TLVL                                                                               0x0008
-#define regHDP_MMHUB_TLVL_BASE_IDX                                                                      0
-#define regHDP_MMHUB_UNITID                                                                             0x0009
-#define regHDP_MMHUB_UNITID_BASE_IDX                                                                    0
-#define regHDP_NONSURFACE_BASE                                                                          0x0040
-#define regHDP_NONSURFACE_BASE_BASE_IDX                                                                 0
-#define regHDP_NONSURFACE_INFO                                                                          0x0041
-#define regHDP_NONSURFACE_INFO_BASE_IDX                                                                 0
-#define regHDP_NONSURFACE_BASE_HI                                                                       0x0042
-#define regHDP_NONSURFACE_BASE_HI_BASE_IDX                                                              0
-#define regHDP_SURFACE_WRITE_FLAGS                                                                      0x00c4
-#define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX                                                             0
-#define regHDP_SURFACE_READ_FLAGS                                                                       0x00c5
-#define regHDP_SURFACE_READ_FLAGS_BASE_IDX                                                              0
-#define regHDP_SURFACE_WRITE_FLAGS_CLR                                                                  0x00c6
-#define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX                                                         0
-#define regHDP_SURFACE_READ_FLAGS_CLR                                                                   0x00c7
-#define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX                                                          0
-#define regHDP_NONSURF_FLAGS                                                                            0x00c8
-#define regHDP_NONSURF_FLAGS_BASE_IDX                                                                   0
-#define regHDP_NONSURF_FLAGS_CLR                                                                        0x00c9
-#define regHDP_NONSURF_FLAGS_CLR_BASE_IDX                                                               0
-#define regHDP_SW_SEMAPHORE                                                                             0x00cd
-#define regHDP_SW_SEMAPHORE_BASE_IDX                                                                    0
-#define regHDP_DEBUG0                                                                                   0x00ce
-#define regHDP_DEBUG0_BASE_IDX                                                                          0
-#define regHDP_LAST_SURFACE_HIT                                                                         0x00d0
-#define regHDP_LAST_SURFACE_HIT_BASE_IDX                                                                0
-#define regHDP_OUTSTANDING_REQ                                                                          0x00d1
-#define regHDP_OUTSTANDING_REQ_BASE_IDX                                                                 0
-#define regHDP_HOST_PATH_CNTL                                                                           0x00d2
-#define regHDP_HOST_PATH_CNTL_BASE_IDX                                                                  0
-#define regHDP_MISC_CNTL                                                                                0x00d3
-#define regHDP_MISC_CNTL_BASE_IDX                                                                       0
-#define regHDP_MEM_POWER_CTRL                                                                           0x00d4
-#define regHDP_MEM_POWER_CTRL_BASE_IDX                                                                  0
-#define regHDP_CLK_CNTL                                                                                 0x00d5
-#define regHDP_CLK_CNTL_BASE_IDX                                                                        0
-#define regHDP_MMHUB_CNTL                                                                               0x00d6
-#define regHDP_MMHUB_CNTL_BASE_IDX                                                                      0
-#define regHDP_XDP_BUSY_STS                                                                             0x00d7
-#define regHDP_XDP_BUSY_STS_BASE_IDX                                                                    0
-#define regHDP_XDP_MMHUB_ERROR                                                                          0x00d8
-#define regHDP_XDP_MMHUB_ERROR_BASE_IDX                                                                 0
-#define regHDP_XDP_MMHUB_ERROR_CLR                                                                      0x00da
-#define regHDP_XDP_MMHUB_ERROR_CLR_BASE_IDX                                                             0
-#define regHDP_VERSION                                                                                  0x00db
-#define regHDP_VERSION_BASE_IDX                                                                         0
-#define regHDP_MEMIO_CNTL                                                                               0x00f6
-#define regHDP_MEMIO_CNTL_BASE_IDX                                                                      0
-#define regHDP_MEMIO_ADDR                                                                               0x00f7
-#define regHDP_MEMIO_ADDR_BASE_IDX                                                                      0
-#define regHDP_MEMIO_STATUS                                                                             0x00f8
-#define regHDP_MEMIO_STATUS_BASE_IDX                                                                    0
-#define regHDP_MEMIO_WR_DATA                                                                            0x00f9
-#define regHDP_MEMIO_WR_DATA_BASE_IDX                                                                   0
-#define regHDP_MEMIO_RD_DATA                                                                            0x00fa
-#define regHDP_MEMIO_RD_DATA_BASE_IDX                                                                   0
-#define regHDP_XDP_DIRECT2HDP_FIRST                                                                     0x0100
-#define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX                                                            0
-#define regHDP_XDP_D2H_FLUSH                                                                            0x0101
-#define regHDP_XDP_D2H_FLUSH_BASE_IDX                                                                   0
-#define regHDP_XDP_D2H_BAR_UPDATE                                                                       0x0102
-#define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX                                                              0
-#define regHDP_XDP_D2H_RSVD_3                                                                           0x0103
-#define regHDP_XDP_D2H_RSVD_3_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_4                                                                           0x0104
-#define regHDP_XDP_D2H_RSVD_4_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_5                                                                           0x0105
-#define regHDP_XDP_D2H_RSVD_5_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_6                                                                           0x0106
-#define regHDP_XDP_D2H_RSVD_6_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_7                                                                           0x0107
-#define regHDP_XDP_D2H_RSVD_7_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_8                                                                           0x0108
-#define regHDP_XDP_D2H_RSVD_8_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_9                                                                           0x0109
-#define regHDP_XDP_D2H_RSVD_9_BASE_IDX                                                                  0
-#define regHDP_XDP_D2H_RSVD_10                                                                          0x010a
-#define regHDP_XDP_D2H_RSVD_10_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_11                                                                          0x010b
-#define regHDP_XDP_D2H_RSVD_11_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_12                                                                          0x010c
-#define regHDP_XDP_D2H_RSVD_12_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_13                                                                          0x010d
-#define regHDP_XDP_D2H_RSVD_13_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_14                                                                          0x010e
-#define regHDP_XDP_D2H_RSVD_14_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_15                                                                          0x010f
-#define regHDP_XDP_D2H_RSVD_15_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_16                                                                          0x0110
-#define regHDP_XDP_D2H_RSVD_16_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_17                                                                          0x0111
-#define regHDP_XDP_D2H_RSVD_17_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_18                                                                          0x0112
-#define regHDP_XDP_D2H_RSVD_18_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_19                                                                          0x0113
-#define regHDP_XDP_D2H_RSVD_19_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_20                                                                          0x0114
-#define regHDP_XDP_D2H_RSVD_20_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_21                                                                          0x0115
-#define regHDP_XDP_D2H_RSVD_21_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_22                                                                          0x0116
-#define regHDP_XDP_D2H_RSVD_22_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_23                                                                          0x0117
-#define regHDP_XDP_D2H_RSVD_23_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_24                                                                          0x0118
-#define regHDP_XDP_D2H_RSVD_24_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_25                                                                          0x0119
-#define regHDP_XDP_D2H_RSVD_25_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_26                                                                          0x011a
-#define regHDP_XDP_D2H_RSVD_26_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_27                                                                          0x011b
-#define regHDP_XDP_D2H_RSVD_27_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_28                                                                          0x011c
-#define regHDP_XDP_D2H_RSVD_28_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_29                                                                          0x011d
-#define regHDP_XDP_D2H_RSVD_29_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_30                                                                          0x011e
-#define regHDP_XDP_D2H_RSVD_30_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_31                                                                          0x011f
-#define regHDP_XDP_D2H_RSVD_31_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_32                                                                          0x0120
-#define regHDP_XDP_D2H_RSVD_32_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_33                                                                          0x0121
-#define regHDP_XDP_D2H_RSVD_33_BASE_IDX                                                                 0
-#define regHDP_XDP_D2H_RSVD_34                                                                          0x0122
-#define regHDP_XDP_D2H_RSVD_34_BASE_IDX                                                                 0
-#define regHDP_XDP_DIRECT2HDP_LAST                                                                      0x0123
-#define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX                                                             0
-#define regHDP_XDP_P2P_BAR_CFG                                                                          0x0124
-#define regHDP_XDP_P2P_BAR_CFG_BASE_IDX                                                                 0
-#define regHDP_XDP_P2P_MBX_OFFSET                                                                       0x0125
-#define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX                                                              0
-#define regHDP_XDP_P2P_MBX_ADDR0                                                                        0x0126
-#define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR1                                                                        0x0127
-#define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR2                                                                        0x0128
-#define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR3                                                                        0x0129
-#define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR4                                                                        0x012a
-#define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR5                                                                        0x012b
-#define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX                                                               0
-#define regHDP_XDP_P2P_MBX_ADDR6                                                                        0x012c
-#define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX                                                               0
-#define regHDP_XDP_HDP_MBX_MC_CFG                                                                       0x012d
-#define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX                                                              0
-#define regHDP_XDP_HDP_MC_CFG                                                                           0x012e
-#define regHDP_XDP_HDP_MC_CFG_BASE_IDX                                                                  0
-#define regHDP_XDP_HST_CFG                                                                              0x012f
-#define regHDP_XDP_HST_CFG_BASE_IDX                                                                     0
-#define regHDP_XDP_HDP_IPH_CFG                                                                          0x0131
-#define regHDP_XDP_HDP_IPH_CFG_BASE_IDX                                                                 0
-#define regHDP_XDP_P2P_BAR0                                                                             0x0134
-#define regHDP_XDP_P2P_BAR0_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR1                                                                             0x0135
-#define regHDP_XDP_P2P_BAR1_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR2                                                                             0x0136
-#define regHDP_XDP_P2P_BAR2_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR3                                                                             0x0137
-#define regHDP_XDP_P2P_BAR3_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR4                                                                             0x0138
-#define regHDP_XDP_P2P_BAR4_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR5                                                                             0x0139
-#define regHDP_XDP_P2P_BAR5_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR6                                                                             0x013a
-#define regHDP_XDP_P2P_BAR6_BASE_IDX                                                                    0
-#define regHDP_XDP_P2P_BAR7                                                                             0x013b
-#define regHDP_XDP_P2P_BAR7_BASE_IDX                                                                    0
-#define regHDP_XDP_FLUSH_ARMED_STS                                                                      0x013c
-#define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX                                                             0
-#define regHDP_XDP_FLUSH_CNTR0_STS                                                                      0x013d
-#define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX                                                             0
-#define regHDP_XDP_STICKY                                                                               0x013f
-#define regHDP_XDP_STICKY_BASE_IDX                                                                      0
-#define regHDP_XDP_CHKN                                                                                 0x0140
-#define regHDP_XDP_CHKN_BASE_IDX                                                                        0
-#define regHDP_XDP_BARS_ADDR_39_36                                                                      0x0144
-#define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX                                                             0
-#define regHDP_XDP_MC_VM_FB_LOCATION_BASE                                                               0x0145
-#define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX                                                      0
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG                                                                0x0148
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                       0
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG2                                                               0x0149
-#define regHDP_XDP_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                      0
-
-#endif
@@ -1,735 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _hdp_7_0_0_SH_MASK_HEADER
-#define _hdp_7_0_0_SH_MASK_HEADER
-
-
-// addressBlock: hdp_hdpdec
-//HDP_MMHUB_TLVL
-#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT                                                                    0x0
-#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT                                                                    0x4
-#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT                                                                    0x8
-#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT                                                                    0xc
-#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT                                                                0x10
-#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK                                                                      0x0000000FL
-#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK                                                                      0x000000F0L
-#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK                                                                      0x00000F00L
-#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK                                                                      0x0000F000L
-#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK                                                                  0x000F0000L
-//HDP_MMHUB_UNITID
-#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT                                                                   0x0
-#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT                                                                   0x8
-#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT                                                               0x10
-#define HDP_MMHUB_UNITID__HDP_UNITID_MASK                                                                     0x0000003FL
-#define HDP_MMHUB_UNITID__XDP_UNITID_MASK                                                                     0x00003F00L
-#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK                                                                 0x003F0000L
-//HDP_NONSURFACE_BASE
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT                                                         0x0
-#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK                                                           0xFFFFFFFFL
-//HDP_NONSURFACE_INFO
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT                                                              0x4
-#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT                                                              0x8
-#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK                                                                0x00000030L
-#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK                                                                0x00000F00L
-//HDP_NONSURFACE_BASE_HI
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT                                                     0x0
-#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK                                                       0x000000FFL
-//HDP_SURFACE_WRITE_FLAGS
-#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT                                                      0x0
-#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT                                                      0x1
-#define HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK                                                        0x00000001L
-#define HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK                                                        0x00000002L
-//HDP_SURFACE_READ_FLAGS
-#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT                                                        0x0
-#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT                                                        0x1
-#define HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK                                                          0x00000001L
-#define HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK                                                          0x00000002L
-//HDP_SURFACE_WRITE_FLAGS_CLR
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT                                              0x0
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT                                              0x1
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK                                                0x00000001L
-#define HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK                                                0x00000002L
-//HDP_SURFACE_READ_FLAGS_CLR
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT                                                0x0
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT                                                0x1
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK                                                  0x00000001L
-#define HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK                                                  0x00000002L
-//HDP_NONSURF_FLAGS
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT                                                          0x0
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT                                                           0x1
-#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK                                                            0x00000001L
-#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK                                                             0x00000002L
-//HDP_NONSURF_FLAGS_CLR
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT                                                  0x0
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT                                                   0x1
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK                                                    0x00000001L
-#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK                                                     0x00000002L
-//HDP_SW_SEMAPHORE
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT                                                                 0x0
-#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK                                                                   0xFFFFFFFFL
-//HDP_DEBUG0
-#define HDP_DEBUG0__HDP_DEBUG__SHIFT                                                                          0x0
-#define HDP_DEBUG0__HDP_DEBUG_MASK                                                                            0xFFFFFFFFL
-//HDP_LAST_SURFACE_HIT
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT                                                         0x0
-#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK                                                           0x00000003L
-//HDP_OUTSTANDING_REQ
-#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT                                                                 0x0
-#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT                                                                  0x8
-#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK                                                                   0x000000FFL
-#define HDP_OUTSTANDING_REQ__READ_REQ_MASK                                                                    0x0000FF00L
-//HDP_HOST_PATH_CNTL
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT                                                             0x9
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT                                                             0xb
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT                                            0x12
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT                                                        0x13
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT                                                           0x15
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT                                                       0x16
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT                                                           0x1d
-#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK                                                               0x00000600L
-#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK                                                               0x00001800L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK                                              0x00040000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK                                                          0x00180000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK                                                             0x00200000L
-#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK                                                         0x00400000L
-#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK                                                             0x20000000L
-//HDP_MISC_CNTL
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT                                                            0x2
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT                                                    0x5
-#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT                                                        0x8
-#define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE__SHIFT                                              0x9
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT                                                       0xb
-#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT                                                           0xe
-#define HDP_MISC_CNTL__NACK_ENABLE__SHIFT                                                                     0x13
-#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT                                                              0x14
-#define HDP_MISC_CNTL__FED_ENABLE__SHIFT                                                                      0x15
-#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT                                                               0x16
-#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT                                                         0x17
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT                                                            0x18
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT                                                              0x1e
-#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK                                                              0x0000000CL
-#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK                                                      0x00000020L
-#define HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK                                                          0x00000100L
-#define HDP_MISC_CNTL__EARLY_WRACK_MISSING_PROTECT_ENABLE_MASK                                                0x00000200L
-#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK                                                         0x00000800L
-#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK                                                             0x0000C000L
-#define HDP_MISC_CNTL__NACK_ENABLE_MASK                                                                       0x00080000L
-#define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE_MASK                                                                0x00100000L
-#define HDP_MISC_CNTL__FED_ENABLE_MASK                                                                        0x00200000L
-#define HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK                                                                 0x00400000L
-#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK                                                           0x00800000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK                                                              0x01000000L
-#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK                                                                0x40000000L
-//HDP_MEM_POWER_CTRL
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN__SHIFT                                                   0x0
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN__SHIFT                                                     0x1
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN__SHIFT                                                     0x2
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN__SHIFT                                                     0x3
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS__SHIFT                                                 0x4
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY__SHIFT                                          0x8
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT                                          0xe
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT                                                       0x10
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT                                                         0x11
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT                                                         0x12
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT                                                         0x13
-#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT                                                     0x14
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT                                              0x18
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT                                              0x1e
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_CTRL_EN_MASK                                                     0x00000001L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK                                                       0x00000002L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK                                                       0x00000004L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK                                                       0x00000008L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_IDLE_HYSTERESIS_MASK                                                   0x00000070L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_UP_RECOVER_DELAY_MASK                                            0x00003F00L
-#define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY_MASK                                            0x0000C000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK                                                         0x00010000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK                                                           0x00020000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK                                                           0x00040000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK                                                           0x00080000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK                                                       0x00700000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK                                                0x3F000000L
-#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_ENTER_DELAY_MASK                                                0xC0000000L
-//HDP_CLK_CNTL
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT                                                             0x0
-#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE__SHIFT                                                     0x1a
-#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT                                                         0x1b
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT                                                           0x1c
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT                                                            0x1d
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1e
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1f
-#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK                                                               0x0000000FL
-#define HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK                                                       0x04000000L
-#define HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK                                                           0x08000000L
-#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK                                                             0x10000000L
-#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK                                                              0x20000000L
-#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK                                                          0x40000000L
-#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK                                                          0x80000000L
-//HDP_MMHUB_CNTL
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT                                                                   0x0
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT                                                                  0x1
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT                                                                0x2
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT                                                          0x4
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE__SHIFT                                                         0x5
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE__SHIFT                                                       0x6
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK                                                                     0x00000001L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK                                                                    0x00000002L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK                                                                  0x00000004L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK                                                            0x00000010L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_OVERRIDE_MASK                                                           0x00000020L
-#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_OVERRIDE_MASK                                                         0x00000040L
-//HDP_XDP_BUSY_STS
-#define HDP_XDP_BUSY_STS__BUSY_BITS_0__SHIFT                                                                  0x0
-#define HDP_XDP_BUSY_STS__BUSY_BITS_1__SHIFT                                                                  0x1
-#define HDP_XDP_BUSY_STS__BUSY_BITS_2__SHIFT                                                                  0x2
-#define HDP_XDP_BUSY_STS__BUSY_BITS_3__SHIFT                                                                  0x3
-#define HDP_XDP_BUSY_STS__BUSY_BITS_4__SHIFT                                                                  0x4
-#define HDP_XDP_BUSY_STS__BUSY_BITS_5__SHIFT                                                                  0x5
-#define HDP_XDP_BUSY_STS__BUSY_BITS_6__SHIFT                                                                  0x6
-#define HDP_XDP_BUSY_STS__BUSY_BITS_7__SHIFT                                                                  0x7
-#define HDP_XDP_BUSY_STS__BUSY_BITS_8__SHIFT                                                                  0x8
-#define HDP_XDP_BUSY_STS__BUSY_BITS_9__SHIFT                                                                  0x9
-#define HDP_XDP_BUSY_STS__BUSY_BITS_10__SHIFT                                                                 0xa
-#define HDP_XDP_BUSY_STS__BUSY_BITS_11__SHIFT                                                                 0xb
-#define HDP_XDP_BUSY_STS__BUSY_BITS_12__SHIFT                                                                 0xc
-#define HDP_XDP_BUSY_STS__BUSY_BITS_13__SHIFT                                                                 0xd
-#define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT                                                                 0xe
-#define HDP_XDP_BUSY_STS__BUSY_BITS_15__SHIFT                                                                 0xf
-#define HDP_XDP_BUSY_STS__BUSY_BITS_16__SHIFT                                                                 0x10
-#define HDP_XDP_BUSY_STS__BUSY_BITS_17__SHIFT                                                                 0x11
-#define HDP_XDP_BUSY_STS__BUSY_BITS_18__SHIFT                                                                 0x12
-#define HDP_XDP_BUSY_STS__BUSY_BITS_19__SHIFT                                                                 0x13
-#define HDP_XDP_BUSY_STS__BUSY_BITS_20__SHIFT                                                                 0x14
-#define HDP_XDP_BUSY_STS__BUSY_BITS_21__SHIFT                                                                 0x15
-#define HDP_XDP_BUSY_STS__BUSY_BITS_22__SHIFT                                                                 0x16
-#define HDP_XDP_BUSY_STS__BUSY_BITS_23__SHIFT                                                                 0x17
-#define HDP_XDP_BUSY_STS__Z_FENCE_BIT__SHIFT                                                                  0x18
-#define HDP_XDP_BUSY_STS__BUSY_BITS_0_MASK                                                                    0x00000001L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_1_MASK                                                                    0x00000002L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_2_MASK                                                                    0x00000004L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_3_MASK                                                                    0x00000008L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_4_MASK                                                                    0x00000010L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_5_MASK                                                                    0x00000020L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_6_MASK                                                                    0x00000040L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_7_MASK                                                                    0x00000080L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_8_MASK                                                                    0x00000100L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_9_MASK                                                                    0x00000200L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_10_MASK                                                                   0x00000400L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_11_MASK                                                                   0x00000800L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_12_MASK                                                                   0x00001000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_13_MASK                                                                   0x00002000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_14_MASK                                                                   0x00004000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_15_MASK                                                                   0x00008000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_16_MASK                                                                   0x00010000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_17_MASK                                                                   0x00020000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_18_MASK                                                                   0x00040000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_19_MASK                                                                   0x00080000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_20_MASK                                                                   0x00100000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_21_MASK                                                                   0x00200000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_22_MASK                                                                   0x00400000L
-#define HDP_XDP_BUSY_STS__BUSY_BITS_23_MASK                                                                   0x00800000L
-#define HDP_XDP_BUSY_STS__Z_FENCE_BIT_MASK                                                                    0x01000000L
-//HDP_XDP_MMHUB_ERROR
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT                                                              0x1
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT                                                              0x2
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT                                                              0x3
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT                                                         0x5
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT                                                         0x6
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT                                                         0x7
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT                                                              0x9
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT                                                              0xa
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT                                                              0xb
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT                                                         0xd
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT                                                         0xe
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT                                                         0xf
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT                                                              0x11
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT                                                              0x12
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT                                                              0x13
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT                                                         0x15
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT                                                         0x16
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT                                                         0x17
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK                                                                0x00000002L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK                                                                0x00000004L
-#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK                                                                0x00000008L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK                                                           0x00000020L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK                                                           0x00000040L
-#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK                                                           0x00000080L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK                                                                0x00000200L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK                                                                0x00000400L
-#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK                                                                0x00000800L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK                                                           0x00002000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK                                                           0x00004000L
-#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK                                                           0x00008000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK                                                                0x00020000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK                                                                0x00040000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK                                                                0x00080000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK                                                           0x00200000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK                                                           0x00400000L
-#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK                                                           0x00800000L
-//HDP_XDP_MMHUB_ERROR_CLR
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_01_CLR__SHIFT                                                      0x1
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_10_CLR__SHIFT                                                      0x2
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_11_CLR__SHIFT                                                      0x3
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_FED_CLR__SHIFT                                                     0x4
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_01_CLR__SHIFT                                                 0x5
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_10_CLR__SHIFT                                                 0x6
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_11_CLR__SHIFT                                                 0x7
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_01_CLR__SHIFT                                                      0x9
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_10_CLR__SHIFT                                                      0xa
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_11_CLR__SHIFT                                                      0xb
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_FED_CLR__SHIFT                                                     0xc
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_01_CLR__SHIFT                                                 0xd
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR__SHIFT                                                 0xe
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_11_CLR__SHIFT                                                 0xf
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_WUSER_FED_CLR__SHIFT                                                     0x10
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_01_CLR__SHIFT                                                      0x11
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_10_CLR__SHIFT                                                      0x12
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_11_CLR__SHIFT                                                      0x13
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_01_CLR__SHIFT                                                 0x15
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_10_CLR__SHIFT                                                 0x16
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_11_CLR__SHIFT                                                 0x17
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_01_CLR_MASK                                                        0x00000002L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_10_CLR_MASK                                                        0x00000004L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BRESP_11_CLR_MASK                                                        0x00000008L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_FED_CLR_MASK                                                       0x00000010L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_01_CLR_MASK                                                   0x00000020L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_10_CLR_MASK                                                   0x00000040L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_BUSER_NACK_11_CLR_MASK                                                   0x00000080L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_01_CLR_MASK                                                        0x00000200L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_10_CLR_MASK                                                        0x00000400L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RRESP_11_CLR_MASK                                                        0x00000800L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_FED_CLR_MASK                                                       0x00001000L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_01_CLR_MASK                                                   0x00002000L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR_MASK                                                   0x00004000L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_11_CLR_MASK                                                   0x00008000L
-#define HDP_XDP_MMHUB_ERROR_CLR__HDP_WUSER_FED_CLR_MASK                                                       0x00010000L
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_01_CLR_MASK                                                        0x00020000L
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_10_CLR_MASK                                                        0x00040000L
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BRESP_11_CLR_MASK                                                        0x00080000L
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_01_CLR_MASK                                                   0x00200000L
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_10_CLR_MASK                                                   0x00400000L
-#define HDP_XDP_MMHUB_ERROR_CLR__XDP_BUSER_NACK_11_CLR_MASK                                                   0x00800000L
-//HDP_VERSION
-#define HDP_VERSION__MINVER__SHIFT                                                                            0x0
-#define HDP_VERSION__MAJVER__SHIFT                                                                            0x8
-#define HDP_VERSION__REV__SHIFT                                                                               0x10
-#define HDP_VERSION__MINVER_MASK                                                                              0x000000FFL
-#define HDP_VERSION__MAJVER_MASK                                                                              0x0000FF00L
-#define HDP_VERSION__REV_MASK                                                                                 0x00FF0000L
-//HDP_MEMIO_CNTL
-#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT                                                                     0x0
-#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT                                                                       0x1
-#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT                                                                       0x2
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT                                                                0x6
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT                                                                0x7
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT                                                               0x8
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT                                                             0xe
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT                                                             0xf
-#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT                                                                       0x10
-#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT                                                                     0x11
-#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK                                                                       0x00000001L
-#define HDP_MEMIO_CNTL__MEMIO_OP_MASK                                                                         0x00000002L
-#define HDP_MEMIO_CNTL__MEMIO_BE_MASK                                                                         0x0000003CL
-#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK                                                                  0x00000040L
-#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK                                                                  0x00000080L
-#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK                                                                 0x00003F00L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK                                                               0x00004000L
-#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK                                                               0x00008000L
-#define HDP_MEMIO_CNTL__MEMIO_VF_MASK                                                                         0x00010000L
-#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK                                                                       0x003E0000L
-//HDP_MEMIO_ADDR
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT                                                               0x0
-#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK                                                                 0xFFFFFFFFL
-//HDP_MEMIO_STATUS
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT                                                              0x0
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT                                                              0x1
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT                                                               0x2
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT                                                               0x3
-#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK                                                                0x00000001L
-#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK                                                                0x00000002L
-#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK                                                                 0x00000004L
-#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK                                                                 0x00000008L
-//HDP_MEMIO_WR_DATA
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT                                                               0x0
-#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK                                                                 0xFFFFFFFFL
-//HDP_MEMIO_RD_DATA
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT                                                               0x0
-#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK                                                                 0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_FIRST
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT                                                             0x0
-#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK                                                               0xFFFFFFFFL
-//HDP_XDP_D2H_FLUSH
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT                                                         0x0
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT                                                      0x4
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT                                                      0x8
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT                                                           0xb
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT                                                         0x10
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT                                                   0x12
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT                                                            0x13
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT                                                            0x14
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK                                                           0x0000000FL
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK                                                        0x000000F0L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK                                                        0x00000700L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK                                                             0x0000F800L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK                                                           0x00010000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK                                                     0x00040000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK                                                              0x00080000L
-#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK                                                              0x00100000L
-//HDP_XDP_D2H_BAR_UPDATE
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT                                                    0x0
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT                                               0x10
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT                                                 0x14
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK                                                      0x0000FFFFL
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK                                                 0x000F0000L
-#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK                                                   0x00700000L
-//HDP_XDP_D2H_RSVD_3
-#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_4
-#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_5
-#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_6
-#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_7
-#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_8
-#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_9
-#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT                                                                   0x0
-#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK                                                                     0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_10
-#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_11
-#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_12
-#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_13
-#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_14
-#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_15
-#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_16
-#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_17
-#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_18
-#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_19
-#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_20
-#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_21
-#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_22
-#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_23
-#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_24
-#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_25
-#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_26
-#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_27
-#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_28
-#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_29
-#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_30
-#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_31
-#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_32
-#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_33
-#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_D2H_RSVD_34
-#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT                                                                  0x0
-#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK                                                                    0xFFFFFFFFL
-//HDP_XDP_DIRECT2HDP_LAST
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT                                                              0x0
-#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK                                                                0xFFFFFFFFL
-//HDP_XDP_P2P_BAR_CFG
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT                                                     0x0
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT                                                      0x4
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK                                                       0x0000000FL
-#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK                                                        0x00000030L
-//HDP_XDP_P2P_MBX_OFFSET
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT                                                         0x0
-#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK                                                           0x0001FFFFL
-//HDP_XDP_P2P_MBX_ADDR0
-#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR1
-#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR2
-#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR3
-#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR4
-#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR5
-#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_P2P_MBX_ADDR6
-#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT                                                                   0x0
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT                                                              0x3
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT                                                              0x14
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT                                                              0x18
-#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK                                                                     0x00000001L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK                                                                0x000FFFF8L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK                                                                0x00F00000L
-#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK                                                                0xFF000000L
-//HDP_XDP_HDP_MBX_MC_CFG
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT                                           0x0
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT                                          0x4
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT                                          0x8
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT                                            0xc
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT                                           0xd
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT                                         0xe
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK                                             0x0000000FL
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK                                            0x00000030L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK                                            0x00000F00L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK                                              0x00001000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK                                             0x00002000L
-#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK                                           0x00004000L
-//HDP_XDP_HDP_MC_CFG
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE__SHIFT                                      0x0
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE__SHIFT                                        0x1
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE__SHIFT                                         0x2
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT                                               0x3
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT                                                0x4
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT                                                0x8
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT                                                  0xc
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT                                                 0xd
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT                                           0xe
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_OVERRIDE_MASK                                        0x00000001L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_OVERRIDE_MASK                                          0x00000002L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_OVERRIDE_MASK                                           0x00000004L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK                                                 0x00000008L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK                                                  0x00000030L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK                                                  0x00000F00L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK                                                    0x00001000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK                                                   0x00002000L
-#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK                                             0x000FC000L
-//HDP_XDP_HST_CFG
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT                                                         0x0
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT                                                      0x1
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT                                                           0x3
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT                                                     0x4
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT                                          0x5
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK                                                           0x00000001L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK                                                        0x00000006L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK                                                             0x00000008L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK                                                       0x00000010L
-#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK                                            0x00000020L
-//HDP_XDP_HDP_IPH_CFG
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT                                     0xc
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT                                                     0xd
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK                                       0x00001000L
-#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK                                                       0x00002000L
-//HDP_XDP_P2P_BAR0
-#define HDP_XDP_P2P_BAR0__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR0__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR0__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR0__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR0__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR1
-#define HDP_XDP_P2P_BAR1__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR1__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR1__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR1__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR1__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR2
-#define HDP_XDP_P2P_BAR2__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR2__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR2__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR2__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR2__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR3
-#define HDP_XDP_P2P_BAR3__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR3__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR3__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR3__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR3__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR4
-#define HDP_XDP_P2P_BAR4__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR4__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR4__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR4__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR4__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR5
-#define HDP_XDP_P2P_BAR5__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR5__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR5__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR5__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR5__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR6
-#define HDP_XDP_P2P_BAR6__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR6__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR6__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR6__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR6__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_P2P_BAR7
-#define HDP_XDP_P2P_BAR7__ADDR__SHIFT                                                                         0x0
-#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT                                                                        0x10
-#define HDP_XDP_P2P_BAR7__VALID__SHIFT                                                                        0x14
-#define HDP_XDP_P2P_BAR7__ADDR_MASK                                                                           0x0000FFFFL
-#define HDP_XDP_P2P_BAR7__FLUSH_MASK                                                                          0x000F0000L
-#define HDP_XDP_P2P_BAR7__VALID_MASK                                                                          0x00100000L
-//HDP_XDP_FLUSH_ARMED_STS
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT                                                       0x0
-#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK                                                         0xFFFFFFFFL
-//HDP_XDP_FLUSH_CNTR0_STS
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT                                                       0x0
-#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK                                                         0x03FFFFFFL
-//HDP_XDP_STICKY
-#define HDP_XDP_STICKY__STICKY_STS__SHIFT                                                                     0x0
-#define HDP_XDP_STICKY__STICKY_W1C__SHIFT                                                                     0x10
-#define HDP_XDP_STICKY__STICKY_STS_MASK                                                                       0x0000FFFFL
-#define HDP_XDP_STICKY__STICKY_W1C_MASK                                                                       0xFFFF0000L
-//HDP_XDP_CHKN
-#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT                                                                      0x0
-#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT                                                                      0x8
-#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT                                                                      0x10
-#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT                                                                      0x18
-#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK                                                                        0x000000FFL
-#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK                                                                        0x0000FF00L
-#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK                                                                        0x00FF0000L
-#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK                                                                        0xFF000000L
-//HDP_XDP_BARS_ADDR_39_36
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT                                                       0x0
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT                                                       0x4
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT                                                       0x8
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT                                                       0xc
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT                                                       0x10
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT                                                       0x14
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT                                                       0x18
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT                                                       0x1c
-#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK                                                         0x0000000FL
-#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK                                                         0x000000F0L
-#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK                                                         0x00000F00L
-#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK                                                         0x0000F000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK                                                         0x000F0000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK                                                         0x00F00000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK                                                         0x0F000000L
-#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK                                                         0xF0000000L
-//HDP_XDP_MC_VM_FB_LOCATION_BASE
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                        0x0
-#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                          0x03FFFFFFL
-//HDP_XDP_GPU_IOV_VIOLATION_LOG
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                0x0
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                       0x1
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                         0x2
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT                                                          0x12
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                              0x13
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                            0x14
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                  0x00000001L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                         0x00000002L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                           0x0003FFFCL
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK                                                            0x00040000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                0x00080000L
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                              0x01F00000L
-//HDP_XDP_GPU_IOV_VIOLATION_LOG2
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                   0x0
-#define HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                     0x000003FFL
-
-#endif
@@ -1,365 +0,0 @@
-/*
- * Copyright (C) 2018  Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _mp_11_0_2_OFFSET_HEADER
-#define _mp_11_0_2_OFFSET_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-// base address: 0x0
-#define mmMP0_SMN_C2PMSG_32                                                                            0x0060
-#define mmMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_33                                                                            0x0061
-#define mmMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_34                                                                            0x0062
-#define mmMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_35                                                                            0x0063
-#define mmMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_36                                                                            0x0064
-#define mmMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_37                                                                            0x0065
-#define mmMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_38                                                                            0x0066
-#define mmMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_39                                                                            0x0067
-#define mmMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_40                                                                            0x0068
-#define mmMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_41                                                                            0x0069
-#define mmMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_42                                                                            0x006a
-#define mmMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_43                                                                            0x006b
-#define mmMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_44                                                                            0x006c
-#define mmMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_45                                                                            0x006d
-#define mmMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_46                                                                            0x006e
-#define mmMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_47                                                                            0x006f
-#define mmMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_48                                                                            0x0070
-#define mmMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_49                                                                            0x0071
-#define mmMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_50                                                                            0x0072
-#define mmMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_51                                                                            0x0073
-#define mmMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_52                                                                            0x0074
-#define mmMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_53                                                                            0x0075
-#define mmMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_54                                                                            0x0076
-#define mmMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_55                                                                            0x0077
-#define mmMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_56                                                                            0x0078
-#define mmMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_57                                                                            0x0079
-#define mmMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_58                                                                            0x007a
-#define mmMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_59                                                                            0x007b
-#define mmMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_60                                                                            0x007c
-#define mmMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_61                                                                            0x007d
-#define mmMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_62                                                                            0x007e
-#define mmMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_63                                                                            0x007f
-#define mmMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_64                                                                            0x0080
-#define mmMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_65                                                                            0x0081
-#define mmMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_66                                                                            0x0082
-#define mmMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_67                                                                            0x0083
-#define mmMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_68                                                                            0x0084
-#define mmMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_69                                                                            0x0085
-#define mmMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_70                                                                            0x0086
-#define mmMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_71                                                                            0x0087
-#define mmMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_72                                                                            0x0088
-#define mmMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_73                                                                            0x0089
-#define mmMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_74                                                                            0x008a
-#define mmMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_75                                                                            0x008b
-#define mmMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_76                                                                            0x008c
-#define mmMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_77                                                                            0x008d
-#define mmMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_78                                                                            0x008e
-#define mmMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_79                                                                            0x008f
-#define mmMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_80                                                                            0x0090
-#define mmMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_81                                                                            0x0091
-#define mmMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_82                                                                            0x0092
-#define mmMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_83                                                                            0x0093
-#define mmMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_84                                                                            0x0094
-#define mmMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_85                                                                            0x0095
-#define mmMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_86                                                                            0x0096
-#define mmMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_87                                                                            0x0097
-#define mmMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_88                                                                            0x0098
-#define mmMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_89                                                                            0x0099
-#define mmMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_90                                                                            0x009a
-#define mmMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_91                                                                            0x009b
-#define mmMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_92                                                                            0x009c
-#define mmMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_93                                                                            0x009d
-#define mmMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_94                                                                            0x009e
-#define mmMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_95                                                                            0x009f
-#define mmMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_96                                                                            0x00a0
-#define mmMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_97                                                                            0x00a1
-#define mmMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_98                                                                            0x00a2
-#define mmMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_99                                                                            0x00a3
-#define mmMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
-#define mmMP0_SMN_C2PMSG_100                                                                           0x00a4
-#define mmMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
-#define mmMP0_SMN_C2PMSG_101                                                                           0x00a5
-#define mmMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
-#define mmMP0_SMN_C2PMSG_102                                                                           0x00a6
-#define mmMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
-#define mmMP0_SMN_C2PMSG_103                                                                           0x00a7
-#define mmMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
-#define mmMP0_SMN_ACTIVE_FCN_ID                                                                        0x00c0
-#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX                                                               0
-#define mmMP0_SMN_IH_CREDIT                                                                            0x00c1
-#define mmMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
-#define mmMP0_SMN_IH_SW_INT                                                                            0x00c2
-#define mmMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
-#define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
-#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-// base address: 0x0
-#define mmMP1_SMN_C2PMSG_32                                                                            0x0260
-#define mmMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_33                                                                            0x0261
-#define mmMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_34                                                                            0x0262
-#define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_35                                                                            0x0263
-#define mmMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_36                                                                            0x0264
-#define mmMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_37                                                                            0x0265
-#define mmMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_38                                                                            0x0266
-#define mmMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_39                                                                            0x0267
-#define mmMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_40                                                                            0x0268
-#define mmMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_41                                                                            0x0269
-#define mmMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_42                                                                            0x026a
-#define mmMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_43                                                                            0x026b
-#define mmMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_44                                                                            0x026c
-#define mmMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_45                                                                            0x026d
-#define mmMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_46                                                                            0x026e
-#define mmMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_47                                                                            0x026f
-#define mmMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_48                                                                            0x0270
-#define mmMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_49                                                                            0x0271
-#define mmMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_50                                                                            0x0272
-#define mmMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_51                                                                            0x0273
-#define mmMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_52                                                                            0x0274
-#define mmMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_53                                                                            0x0275
-#define mmMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_54                                                                            0x0276
-#define mmMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_55                                                                            0x0277
-#define mmMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_56                                                                            0x0278
-#define mmMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_57                                                                            0x0279
-#define mmMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_58                                                                            0x027a
-#define mmMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_59                                                                            0x027b
-#define mmMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_60                                                                            0x027c
-#define mmMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_61                                                                            0x027d
-#define mmMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_62                                                                            0x027e
-#define mmMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_63                                                                            0x027f
-#define mmMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_64                                                                            0x0280
-#define mmMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_65                                                                            0x0281
-#define mmMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
-#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_67                                                                            0x0283
-#define mmMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_68                                                                            0x0284
-#define mmMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_69                                                                            0x0285
-#define mmMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_70                                                                            0x0286
-#define mmMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_71                                                                            0x0287
-#define mmMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_72                                                                            0x0288
-#define mmMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_73                                                                            0x0289
-#define mmMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_74                                                                            0x028a
-#define mmMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_75                                                                            0x028b
-#define mmMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_76                                                                            0x028c
-#define mmMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_77                                                                            0x028d
-#define mmMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_78                                                                            0x028e
-#define mmMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_79                                                                            0x028f
-#define mmMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_80                                                                            0x0290
-#define mmMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_81                                                                            0x0291
-#define mmMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
-#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_83                                                                            0x0293
-#define mmMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_84                                                                            0x0294
-#define mmMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_85                                                                            0x0295
-#define mmMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_86                                                                            0x0296
-#define mmMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_87                                                                            0x0297
-#define mmMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_88                                                                            0x0298
-#define mmMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_89                                                                            0x0299
-#define mmMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
-#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_91                                                                            0x029b
-#define mmMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_92                                                                            0x029c
-#define mmMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_93                                                                            0x029d
-#define mmMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_94                                                                            0x029e
-#define mmMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_95                                                                            0x029f
-#define mmMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_96                                                                            0x02a0
-#define mmMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_97                                                                            0x02a1
-#define mmMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_98                                                                            0x02a2
-#define mmMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_99                                                                            0x02a3
-#define mmMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
-#define mmMP1_SMN_C2PMSG_100                                                                           0x02a4
-#define mmMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
-#define mmMP1_SMN_C2PMSG_101                                                                           0x02a5
-#define mmMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
-#define mmMP1_SMN_C2PMSG_102                                                                           0x02a6
-#define mmMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
-#define mmMP1_SMN_C2PMSG_103                                                                           0x02a7
-#define mmMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
-#define mmMP1_SMN_ACTIVE_FCN_ID                                                                        0x02c0
-#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX                                                               0
-#define mmMP1_SMN_IH_CREDIT                                                                            0x02c1
-#define mmMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
-#define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
-#define mmMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
-#define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
-#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
-#define mmMP1_SMN_FPS_CNT                                                                              0x02c4
-#define mmMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
-#define mmMP1_SMN_PUB_CTRL                                                                             0x02c5
-#define mmMP1_SMN_PUB_CTRL_BASE_IDX                                                                    0
-#define mmMP1_SMN_EXT_SCRATCH0                                                                         0x03c0
-#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH1                                                                         0x03c1
-#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH2                                                                         0x03c2
-#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH3                                                                         0x03c3
-#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH4                                                                         0x03c4
-#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH5                                                                         0x03c5
-#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH6                                                                         0x03c6
-#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                0
-#define mmMP1_SMN_EXT_SCRATCH7                                                                         0x03c7
-#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0
-
-/*
- * addressBlock: mp_SmuMp1Pub_MmuDec
- * base address: 0x0
- */
-#define smnMP1_PMI_3_START                                                                              0x3030204
-#define smnMP1_PMI_3_FIFO                                                                               0x3030208
-#define smnMP1_PMI_3                                                                                    0x3030600
-
-#endif
@@ -1,975 +0,0 @@
-/*
- * Copyright (C) 2018  Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _mp_11_0_2_SH_MASK_HEADER
-#define _mp_11_0_2_SH_MASK_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-//MP0_SMN_C2PMSG_32
-#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_33
-#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_34
-#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_35
-#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_36
-#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_37
-#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_38
-#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_39
-#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_40
-#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_41
-#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_42
-#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_43
-#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_44
-#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_45
-#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_46
-#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_47
-#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_48
-#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_49
-#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_50
-#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_51
-#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_52
-#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_53
-#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_54
-#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_55
-#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_56
-#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_57
-#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_58
-#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_59
-#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_60
-#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_61
-#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_62
-#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_63
-#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_64
-#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_65
-#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_66
-#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_67
-#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_68
-#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_69
-#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_70
-#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_71
-#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_72
-#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_73
-#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_74
-#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_75
-#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_76
-#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_77
-#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_78
-#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_79
-#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_80
-#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_81
-#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_82
-#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_83
-#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_84
-#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_85
-#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_86
-#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_87
-#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_88
-#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_89
-#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_90
-#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_91
-#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_92
-#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_93
-#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_94
-#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_95
-#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_96
-#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_97
-#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_98
-#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_99
-#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_100
-#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_C2PMSG_101
-#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_C2PMSG_102
-#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_C2PMSG_103
-#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_ACTIVE_FCN_ID
-#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT                                                                    0x0
-#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT                                                                      0x1f
-#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK                                                                      0x0000001FL
-#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK                                                                        0x80000000L
-//MP0_SMN_IH_CREDIT
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
-#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
-#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
-//MP0_SMN_IH_SW_INT
-#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
-#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
-#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
-#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
-//MP0_SMN_IH_SW_INT_CTRL
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
-
-
-//MP1_FIRMWARE_FLAGS
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                         0x0
-#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                   0x1
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                           0x00000001L
-#define MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                                     0xFFFFFFFEL
-//MP1_PUB_SCRATCH0
-#define MP1_PUB_SCRATCH0__DATA__SHIFT                                                                         0x0
-#define MP1_PUB_SCRATCH0__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_PUB_SCRATCH1
-#define MP1_PUB_SCRATCH1__DATA__SHIFT                                                                         0x0
-#define MP1_PUB_SCRATCH1__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_PUB_SCRATCH2
-#define MP1_PUB_SCRATCH2__DATA__SHIFT                                                                         0x0
-#define MP1_PUB_SCRATCH2__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_PUB_SCRATCH3
-#define MP1_PUB_SCRATCH3__DATA__SHIFT                                                                         0x0
-#define MP1_PUB_SCRATCH3__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_0
-#define MP1_C2PMSG_0__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_1
-#define MP1_C2PMSG_1__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_2
-#define MP1_C2PMSG_2__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_3
-#define MP1_C2PMSG_3__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_4
-#define MP1_C2PMSG_4__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_4__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_5
-#define MP1_C2PMSG_5__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_5__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_6
-#define MP1_C2PMSG_6__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_6__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_7
-#define MP1_C2PMSG_7__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_7__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_8
-#define MP1_C2PMSG_8__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_8__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_9
-#define MP1_C2PMSG_9__CONTENT__SHIFT                                                                          0x0
-#define MP1_C2PMSG_9__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_10
-#define MP1_C2PMSG_10__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_10__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_11
-#define MP1_C2PMSG_11__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_11__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_12
-#define MP1_C2PMSG_12__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_12__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_13
-#define MP1_C2PMSG_13__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_13__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_14
-#define MP1_C2PMSG_14__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_14__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_15
-#define MP1_C2PMSG_15__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_15__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_16
-#define MP1_C2PMSG_16__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_16__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_17
-#define MP1_C2PMSG_17__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_17__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_18
-#define MP1_C2PMSG_18__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_18__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_19
-#define MP1_C2PMSG_19__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_19__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_20
-#define MP1_C2PMSG_20__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_20__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_21
-#define MP1_C2PMSG_21__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_21__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_22
-#define MP1_C2PMSG_22__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_22__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_23
-#define MP1_C2PMSG_23__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_23__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_24
-#define MP1_C2PMSG_24__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_24__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_25
-#define MP1_C2PMSG_25__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_25__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_26
-#define MP1_C2PMSG_26__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_26__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_27
-#define MP1_C2PMSG_27__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_27__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_28
-#define MP1_C2PMSG_28__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_28__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_29
-#define MP1_C2PMSG_29__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_29__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_30
-#define MP1_C2PMSG_30__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_30__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_31
-#define MP1_C2PMSG_31__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_31__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_P2CMSG_0
-#define MP1_P2CMSG_0__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2CMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2CMSG_1
-#define MP1_P2CMSG_1__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2CMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2CMSG_2
-#define MP1_P2CMSG_2__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2CMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2CMSG_3
-#define MP1_P2CMSG_3__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2CMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2CMSG_INTEN
-#define MP1_P2CMSG_INTEN__INTEN__SHIFT                                                                        0x0
-#define MP1_P2CMSG_INTEN__INTEN_MASK                                                                          0x0000000FL
-//MP1_P2CMSG_INTSTS
-#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
-#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
-#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
-#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
-#define MP1_P2CMSG_INTSTS__INTSTS0_MASK                                                                       0x00000001L
-#define MP1_P2CMSG_INTSTS__INTSTS1_MASK                                                                       0x00000002L
-#define MP1_P2CMSG_INTSTS__INTSTS2_MASK                                                                       0x00000004L
-#define MP1_P2CMSG_INTSTS__INTSTS3_MASK                                                                       0x00000008L
-//MP1_P2SMSG_0
-#define MP1_P2SMSG_0__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2SMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2SMSG_1
-#define MP1_P2SMSG_1__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2SMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2SMSG_2
-#define MP1_P2SMSG_2__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2SMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2SMSG_3
-#define MP1_P2SMSG_3__CONTENT__SHIFT                                                                          0x0
-#define MP1_P2SMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_P2SMSG_INTSTS
-#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
-#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
-#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
-#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
-#define MP1_P2SMSG_INTSTS__INTSTS0_MASK                                                                       0x00000001L
-#define MP1_P2SMSG_INTSTS__INTSTS1_MASK                                                                       0x00000002L
-#define MP1_P2SMSG_INTSTS__INTSTS2_MASK                                                                       0x00000004L
-#define MP1_P2SMSG_INTSTS__INTSTS3_MASK                                                                       0x00000008L
-//MP1_S2PMSG_0
-#define MP1_S2PMSG_0__CONTENT__SHIFT                                                                          0x0
-#define MP1_S2PMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
-//MP1_C2PMSG_32
-#define MP1_C2PMSG_32__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_32__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_33
-#define MP1_C2PMSG_33__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_33__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_34
-#define MP1_C2PMSG_34__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_34__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_35
-#define MP1_C2PMSG_35__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_35__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_36
-#define MP1_C2PMSG_36__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_36__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_37
-#define MP1_C2PMSG_37__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_37__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_38
-#define MP1_C2PMSG_38__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_38__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_39
-#define MP1_C2PMSG_39__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_39__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_40
-#define MP1_C2PMSG_40__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_40__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_41
-#define MP1_C2PMSG_41__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_41__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_42
-#define MP1_C2PMSG_42__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_42__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_43
-#define MP1_C2PMSG_43__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_43__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_44
-#define MP1_C2PMSG_44__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_44__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_45
-#define MP1_C2PMSG_45__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_45__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_46
-#define MP1_C2PMSG_46__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_46__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_47
-#define MP1_C2PMSG_47__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_47__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_48
-#define MP1_C2PMSG_48__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_48__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_49
-#define MP1_C2PMSG_49__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_49__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_50
-#define MP1_C2PMSG_50__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_50__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_51
-#define MP1_C2PMSG_51__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_51__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_52
-#define MP1_C2PMSG_52__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_52__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_53
-#define MP1_C2PMSG_53__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_53__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_54
-#define MP1_C2PMSG_54__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_54__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_55
-#define MP1_C2PMSG_55__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_55__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_56
-#define MP1_C2PMSG_56__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_56__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_57
-#define MP1_C2PMSG_57__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_57__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_58
-#define MP1_C2PMSG_58__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_58__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_59
-#define MP1_C2PMSG_59__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_59__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_60
-#define MP1_C2PMSG_60__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_60__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_61
-#define MP1_C2PMSG_61__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_61__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_62
-#define MP1_C2PMSG_62__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_62__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_63
-#define MP1_C2PMSG_63__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_63__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_64
-#define MP1_C2PMSG_64__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_64__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_65
-#define MP1_C2PMSG_65__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_65__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_66
-#define MP1_C2PMSG_66__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_66__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_67
-#define MP1_C2PMSG_67__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_67__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_68
-#define MP1_C2PMSG_68__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_68__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_69
-#define MP1_C2PMSG_69__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_69__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_70
-#define MP1_C2PMSG_70__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_70__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_71
-#define MP1_C2PMSG_71__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_71__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_72
-#define MP1_C2PMSG_72__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_72__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_73
-#define MP1_C2PMSG_73__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_73__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_74
-#define MP1_C2PMSG_74__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_74__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_75
-#define MP1_C2PMSG_75__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_75__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_76
-#define MP1_C2PMSG_76__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_76__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_77
-#define MP1_C2PMSG_77__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_77__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_78
-#define MP1_C2PMSG_78__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_78__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_79
-#define MP1_C2PMSG_79__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_79__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_80
-#define MP1_C2PMSG_80__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_80__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_81
-#define MP1_C2PMSG_81__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_81__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_82
-#define MP1_C2PMSG_82__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_82__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_83
-#define MP1_C2PMSG_83__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_83__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_84
-#define MP1_C2PMSG_84__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_84__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_85
-#define MP1_C2PMSG_85__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_85__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_86
-#define MP1_C2PMSG_86__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_86__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_87
-#define MP1_C2PMSG_87__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_87__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_88
-#define MP1_C2PMSG_88__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_88__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_89
-#define MP1_C2PMSG_89__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_89__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_90
-#define MP1_C2PMSG_90__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_90__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_91
-#define MP1_C2PMSG_91__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_91__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_92
-#define MP1_C2PMSG_92__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_92__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_93
-#define MP1_C2PMSG_93__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_93__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_94
-#define MP1_C2PMSG_94__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_94__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_95
-#define MP1_C2PMSG_95__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_95__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_96
-#define MP1_C2PMSG_96__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_96__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_97
-#define MP1_C2PMSG_97__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_97__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_98
-#define MP1_C2PMSG_98__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_98__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_99
-#define MP1_C2PMSG_99__CONTENT__SHIFT                                                                         0x0
-#define MP1_C2PMSG_99__CONTENT_MASK                                                                           0xFFFFFFFFL
-//MP1_C2PMSG_100
-#define MP1_C2PMSG_100__CONTENT__SHIFT                                                                        0x0
-#define MP1_C2PMSG_100__CONTENT_MASK                                                                          0xFFFFFFFFL
-//MP1_C2PMSG_101
-#define MP1_C2PMSG_101__CONTENT__SHIFT                                                                        0x0
-#define MP1_C2PMSG_101__CONTENT_MASK                                                                          0xFFFFFFFFL
-//MP1_C2PMSG_102
-#define MP1_C2PMSG_102__CONTENT__SHIFT                                                                        0x0
-#define MP1_C2PMSG_102__CONTENT_MASK                                                                          0xFFFFFFFFL
-//MP1_C2PMSG_103
-#define MP1_C2PMSG_103__CONTENT__SHIFT                                                                        0x0
-#define MP1_C2PMSG_103__CONTENT_MASK                                                                          0xFFFFFFFFL
-//MP1_ACTIVE_FCN_ID
-#define MP1_ACTIVE_FCN_ID__VFID__SHIFT                                                                        0x0
-#define MP1_ACTIVE_FCN_ID__VF__SHIFT                                                                          0x1f
-#define MP1_ACTIVE_FCN_ID__VFID_MASK                                                                          0x0000001FL
-#define MP1_ACTIVE_FCN_ID__VF_MASK                                                                            0x80000000L
-//MP1_IH_CREDIT
-#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                    0x0
-#define MP1_IH_CREDIT__CLIENT_ID__SHIFT                                                                       0x10
-#define MP1_IH_CREDIT__CREDIT_VALUE_MASK                                                                      0x00000003L
-#define MP1_IH_CREDIT__CLIENT_ID_MASK                                                                         0x00FF0000L
-//MP1_IH_SW_INT
-#define MP1_IH_SW_INT__ID__SHIFT                                                                              0x0
-#define MP1_IH_SW_INT__VALID__SHIFT                                                                           0x8
-#define MP1_IH_SW_INT__ID_MASK                                                                                0x000000FFL
-#define MP1_IH_SW_INT__VALID_MASK                                                                             0x00000100L
-//MP1_IH_SW_INT_CTRL
-#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                                   0x0
-#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                    0x8
-#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK                                                                     0x00000001L
-#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK                                                                      0x00000100L
-//MP1_FPS_CNT
-#define MP1_FPS_CNT__COUNT__SHIFT                                                                             0x0
-#define MP1_FPS_CNT__COUNT_MASK                                                                               0xFFFFFFFFL
-//MP1_PUB_CTRL
-#define MP1_PUB_CTRL__RESET__SHIFT                                                                        0x0
-#define MP1_PUB_CTRL__RESET_MASK                                                                          0x00000001L
-//MP1_EXT_SCRATCH0
-#define MP1_EXT_SCRATCH0__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH0__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH1
-#define MP1_EXT_SCRATCH1__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH1__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH2
-#define MP1_EXT_SCRATCH2__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH2__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH3
-#define MP1_EXT_SCRATCH3__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH3__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH4
-#define MP1_EXT_SCRATCH4__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH4__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH5
-#define MP1_EXT_SCRATCH5__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH5__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH6
-#define MP1_EXT_SCRATCH6__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH6__DATA_MASK                                                                           0xFFFFFFFFL
-//MP1_EXT_SCRATCH7
-#define MP1_EXT_SCRATCH7__DATA__SHIFT                                                                         0x0
-#define MP1_EXT_SCRATCH7__DATA_MASK                                                                           0xFFFFFFFFL
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-//MP1_SMN_C2PMSG_32
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_33
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_34
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_35
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_36
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_37
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_38
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_39
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_40
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_41
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_42
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_43
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_44
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_45
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_46
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_47
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_48
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_49
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_50
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_51
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_52
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_53
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_54
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_55
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_56
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_57
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_58
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_59
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_60
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_61
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_62
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_63
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_64
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_65
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_66
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_67
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_68
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_69
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_70
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_71
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_72
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_73
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_74
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_75
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_76
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_77
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_78
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_79
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_80
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_81
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_82
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_83
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_84
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_85
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_86
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_87
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_88
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_89
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_90
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_91
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_92
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_93
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_94
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_95
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_96
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_97
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_98
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_99
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_100
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_101
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_102
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_103
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_ACTIVE_FCN_ID
-#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT                                                                    0x0
-#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT                                                                      0x1f
-#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK                                                                      0x0000001FL
-#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK                                                                        0x80000000L
-//MP1_SMN_IH_CREDIT
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
-//MP1_SMN_IH_SW_INT
-#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
-#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
-#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
-//MP1_SMN_IH_SW_INT_CTRL
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
-//MP1_SMN_FPS_CNT
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
-//MP1_SMN_PUB_CTRL
-#define MP1_SMN_PUB_CTRL__RESET__SHIFT                                                                        0x0
-#define MP1_SMN_PUB_CTRL__RESET_MASK                                                                          0x00000001L
-//MP1_SMN_EXT_SCRATCH0
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH1
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH2
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH3
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH4
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH5
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH6
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH7
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
-
-// MP1_PMI_3_START
-#define MP1_PMI_3_START__ENABLE_MASK                       0x80000000L
-// MP1_PMI_3_FIFO
-#define MP1_PMI_3_FIFO__DEPTH_MASK                         0x00000fffL
-
-// MP1_PMI_3_START
-#define MP1_PMI_3_START__ENABLE__SHIFT                     0x0000001f
-// MP1_PMI_3_FIFO
-#define MP1_PMI_3_FIFO__DEPTH__SHIFT                       0x00000000
-
-
-
-
-#endif
@@ -1,461 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _mp_13_0_0_OFFSET_HEADER
-#define _mp_13_0_0_OFFSET_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-// base address: 0x0
-#define regMP0_SMN_C2PMSG_32                                                                            0x0060
-#define regMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_33                                                                            0x0061
-#define regMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_34                                                                            0x0062
-#define regMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_35                                                                            0x0063
-#define regMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_36                                                                            0x0064
-#define regMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_37                                                                            0x0065
-#define regMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_38                                                                            0x0066
-#define regMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_39                                                                            0x0067
-#define regMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_40                                                                            0x0068
-#define regMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_41                                                                            0x0069
-#define regMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_42                                                                            0x006a
-#define regMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_43                                                                            0x006b
-#define regMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_44                                                                            0x006c
-#define regMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_45                                                                            0x006d
-#define regMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_46                                                                            0x006e
-#define regMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_47                                                                            0x006f
-#define regMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_48                                                                            0x0070
-#define regMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_49                                                                            0x0071
-#define regMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_50                                                                            0x0072
-#define regMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_51                                                                            0x0073
-#define regMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_52                                                                            0x0074
-#define regMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_53                                                                            0x0075
-#define regMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_54                                                                            0x0076
-#define regMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_55                                                                            0x0077
-#define regMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_56                                                                            0x0078
-#define regMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_57                                                                            0x0079
-#define regMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_58                                                                            0x007a
-#define regMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_59                                                                            0x007b
-#define regMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_60                                                                            0x007c
-#define regMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_61                                                                            0x007d
-#define regMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_62                                                                            0x007e
-#define regMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_63                                                                            0x007f
-#define regMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_64                                                                            0x0080
-#define regMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_65                                                                            0x0081
-#define regMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_66                                                                            0x0082
-#define regMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_67                                                                            0x0083
-#define regMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_68                                                                            0x0084
-#define regMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_69                                                                            0x0085
-#define regMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_70                                                                            0x0086
-#define regMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_71                                                                            0x0087
-#define regMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_72                                                                            0x0088
-#define regMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_73                                                                            0x0089
-#define regMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_74                                                                            0x008a
-#define regMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_75                                                                            0x008b
-#define regMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_76                                                                            0x008c
-#define regMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_77                                                                            0x008d
-#define regMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_78                                                                            0x008e
-#define regMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_79                                                                            0x008f
-#define regMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_80                                                                            0x0090
-#define regMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_81                                                                            0x0091
-#define regMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_82                                                                            0x0092
-#define regMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_83                                                                            0x0093
-#define regMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_84                                                                            0x0094
-#define regMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_85                                                                            0x0095
-#define regMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_86                                                                            0x0096
-#define regMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_87                                                                            0x0097
-#define regMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_88                                                                            0x0098
-#define regMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_89                                                                            0x0099
-#define regMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_90                                                                            0x009a
-#define regMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_91                                                                            0x009b
-#define regMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_92                                                                            0x009c
-#define regMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_93                                                                            0x009d
-#define regMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_94                                                                            0x009e
-#define regMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_95                                                                            0x009f
-#define regMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_96                                                                            0x00a0
-#define regMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_97                                                                            0x00a1
-#define regMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_98                                                                            0x00a2
-#define regMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_99                                                                            0x00a3
-#define regMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
-#define regMP0_SMN_C2PMSG_100                                                                           0x00a4
-#define regMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
-#define regMP0_SMN_C2PMSG_101                                                                           0x00a5
-#define regMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
-#define regMP0_SMN_C2PMSG_102                                                                           0x00a6
-#define regMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
-#define regMP0_SMN_C2PMSG_103                                                                           0x00a7
-#define regMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
-#define regMP0_SMN_IH_CREDIT                                                                            0x00c1
-#define regMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
-#define regMP0_SMN_IH_SW_INT                                                                            0x00c2
-#define regMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
-#define regMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
-#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-// base address: 0x0
-#define regMP1_SMN_C2PMSG_32                                                                            0x0260
-#define regMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_33                                                                            0x0261
-#define regMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_34                                                                            0x0262
-#define regMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_35                                                                            0x0263
-#define regMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_36                                                                            0x0264
-#define regMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_37                                                                            0x0265
-#define regMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_38                                                                            0x0266
-#define regMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_39                                                                            0x0267
-#define regMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_40                                                                            0x0268
-#define regMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_41                                                                            0x0269
-#define regMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_42                                                                            0x026a
-#define regMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_43                                                                            0x026b
-#define regMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_44                                                                            0x026c
-#define regMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_45                                                                            0x026d
-#define regMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_46                                                                            0x026e
-#define regMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_47                                                                            0x026f
-#define regMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_48                                                                            0x0270
-#define regMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_49                                                                            0x0271
-#define regMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_50                                                                            0x0272
-#define regMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_51                                                                            0x0273
-#define regMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_52                                                                            0x0274
-#define regMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_53                                                                            0x0275
-#define regMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_54                                                                            0x0276
-#define regMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_55                                                                            0x0277
-#define regMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_56                                                                            0x0278
-#define regMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_57                                                                            0x0279
-#define regMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_58                                                                            0x027a
-#define regMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_59                                                                            0x027b
-#define regMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_60                                                                            0x027c
-#define regMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_61                                                                            0x027d
-#define regMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_62                                                                            0x027e
-#define regMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_63                                                                            0x027f
-#define regMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_64                                                                            0x0280
-#define regMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_65                                                                            0x0281
-#define regMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_66                                                                            0x0282
-#define regMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_67                                                                            0x0283
-#define regMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_68                                                                            0x0284
-#define regMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_69                                                                            0x0285
-#define regMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_70                                                                            0x0286
-#define regMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_71                                                                            0x0287
-#define regMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_72                                                                            0x0288
-#define regMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_73                                                                            0x0289
-#define regMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_74                                                                            0x028a
-#define regMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_75                                                                            0x028b
-#define regMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_76                                                                            0x028c
-#define regMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_77                                                                            0x028d
-#define regMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_78                                                                            0x028e
-#define regMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_79                                                                            0x028f
-#define regMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_80                                                                            0x0290
-#define regMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_81                                                                            0x0291
-#define regMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_82                                                                            0x0292
-#define regMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_83                                                                            0x0293
-#define regMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_84                                                                            0x0294
-#define regMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_85                                                                            0x0295
-#define regMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_86                                                                            0x0296
-#define regMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_87                                                                            0x0297
-#define regMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_88                                                                            0x0298
-#define regMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_89                                                                            0x0299
-#define regMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_90                                                                            0x029a
-#define regMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_91                                                                            0x029b
-#define regMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_92                                                                            0x029c
-#define regMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_93                                                                            0x029d
-#define regMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_94                                                                            0x029e
-#define regMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_95                                                                            0x029f
-#define regMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_96                                                                            0x02a0
-#define regMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_97                                                                            0x02a1
-#define regMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_98                                                                            0x02a2
-#define regMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_99                                                                            0x02a3
-#define regMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_100                                                                           0x02a4
-#define regMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_101                                                                           0x02a5
-#define regMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_102                                                                           0x02a6
-#define regMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_103                                                                           0x02a7
-#define regMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_104                                                                           0x02a8
-#define regMP1_SMN_C2PMSG_104_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_105                                                                           0x02a9
-#define regMP1_SMN_C2PMSG_105_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_106                                                                           0x02aa
-#define regMP1_SMN_C2PMSG_106_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_107                                                                           0x02ab
-#define regMP1_SMN_C2PMSG_107_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_108                                                                           0x02ac
-#define regMP1_SMN_C2PMSG_108_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_109                                                                           0x02ad
-#define regMP1_SMN_C2PMSG_109_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_110                                                                           0x02ae
-#define regMP1_SMN_C2PMSG_110_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_111                                                                           0x02af
-#define regMP1_SMN_C2PMSG_111_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_112                                                                           0x02b0
-#define regMP1_SMN_C2PMSG_112_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_113                                                                           0x02b1
-#define regMP1_SMN_C2PMSG_113_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_114                                                                           0x02b2
-#define regMP1_SMN_C2PMSG_114_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_115                                                                           0x02b3
-#define regMP1_SMN_C2PMSG_115_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_116                                                                           0x02b4
-#define regMP1_SMN_C2PMSG_116_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_117                                                                           0x02b5
-#define regMP1_SMN_C2PMSG_117_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_118                                                                           0x02b6
-#define regMP1_SMN_C2PMSG_118_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_119                                                                           0x02b7
-#define regMP1_SMN_C2PMSG_119_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_120                                                                           0x02b8
-#define regMP1_SMN_C2PMSG_120_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_121                                                                           0x02b9
-#define regMP1_SMN_C2PMSG_121_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_122                                                                           0x02ba
-#define regMP1_SMN_C2PMSG_122_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_123                                                                           0x02bb
-#define regMP1_SMN_C2PMSG_123_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_124                                                                           0x02bc
-#define regMP1_SMN_C2PMSG_124_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_125                                                                           0x02bd
-#define regMP1_SMN_C2PMSG_125_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_126                                                                           0x02be
-#define regMP1_SMN_C2PMSG_126_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_127                                                                           0x02bf
-#define regMP1_SMN_C2PMSG_127_BASE_IDX                                                                  0
-#define regMP1_SMN_IH_CREDIT                                                                            0x02c1
-#define regMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
-#define regMP1_SMN_IH_SW_INT                                                                            0x02c2
-#define regMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
-#define regMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
-#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
-#define regMP1_SMN_FPS_CNT                                                                              0x02c4
-#define regMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
-#define regMP1_SMN_PUB_CTRL                                                                             0x02c5
-#define regMP1_SMN_PUB_CTRL_BASE_IDX                                                                    0
-#define regMP1_SMN_EXT_SCRATCH0                                                                         0x0340
-#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH1                                                                         0x0341
-#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH2                                                                         0x0342
-#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH3                                                                         0x0343
-#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH4                                                                         0x0344
-#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH5                                                                         0x0345
-#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH6                                                                         0x0346
-#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH7                                                                         0x0347
-#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH8                                                                         0x0348
-#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH10                                                                        0x034a
-#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH11                                                                        0x034b
-#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH12                                                                        0x034c
-#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH13                                                                        0x034d
-#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH14                                                                        0x034e
-#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH15                                                                        0x034f
-#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH16                                                                        0x0350
-#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH17                                                                        0x0351
-#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH18                                                                        0x0352
-#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH19                                                                        0x0353
-#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH20                                                                        0x0354
-#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH21                                                                        0x0355
-#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH22                                                                        0x0356
-#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH23                                                                        0x0357
-#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH24                                                                        0x0358
-#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH25                                                                        0x0359
-#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH26                                                                        0x035a
-#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH27                                                                        0x035b
-#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH28                                                                        0x035c
-#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH29                                                                        0x035d
-#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH30                                                                        0x035e
-#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH31                                                                        0x035f
-#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX                                                               0
-
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-// base address: 0x0
-#define regMP1_FIRMWARE_FLAGS                                                                           0xbee009
-#define regMP1_FIRMWARE_FLAGS_BASE_IDX                                                                  0
-
-
-// addressBlock: mp_SmuMpIOPub_CruDec
-// base address: 0x0
-#define regMPIO_FIRMWARE_FLAGS                                                                          0xbee009
-#define regMPIO_FIRMWARE_FLAGS_BASE_IDX                                                                 0
-
-
-#endif
@@ -1,682 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _mp_13_0_0_SH_MASK_HEADER
-#define _mp_13_0_0_SH_MASK_HEADER
-
-
-// addressBlock: mp_SmuMp0_SmnDec
-//MP0_SMN_C2PMSG_32
-#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_33
-#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_34
-#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_35
-#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_36
-#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_37
-#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_38
-#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_39
-#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_40
-#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_41
-#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_42
-#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_43
-#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_44
-#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_45
-#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_46
-#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_47
-#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_48
-#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_49
-#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_50
-#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_51
-#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_52
-#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_53
-#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_54
-#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_55
-#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_56
-#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_57
-#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_58
-#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_59
-#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_60
-#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_61
-#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_62
-#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_63
-#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_64
-#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_65
-#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_66
-#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_67
-#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_68
-#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_69
-#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_70
-#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_71
-#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_72
-#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_73
-#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_74
-#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_75
-#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_76
-#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_77
-#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_78
-#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_79
-#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_80
-#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_81
-#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_82
-#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_83
-#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_84
-#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_85
-#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_86
-#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_87
-#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_88
-#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_89
-#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_90
-#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_91
-#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_92
-#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_93
-#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_94
-#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_95
-#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_96
-#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_97
-#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_98
-#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_99
-#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
-#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP0_SMN_C2PMSG_100
-#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_C2PMSG_101
-#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_C2PMSG_102
-#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_C2PMSG_103
-#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
-#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP0_SMN_IH_CREDIT
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
-#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
-#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
-//MP0_SMN_IH_SW_INT
-#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
-#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
-#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
-#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
-//MP0_SMN_IH_SW_INT_CTRL
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
-#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
-#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-//MP1_SMN_C2PMSG_32
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_33
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_34
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_35
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_36
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_37
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_38
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_39
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_40
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_41
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_42
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_43
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_44
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_45
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_46
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_47
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_48
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_49
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_50
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_51
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_52
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_53
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_54
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_55
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_56
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_57
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_58
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_59
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_60
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_61
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_62
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_63
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_64
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_65
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_66
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_67
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_68
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_69
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_70
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_71
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_72
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_73
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_74
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_75
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_76
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_77
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_78
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_79
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_80
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_81
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_82
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_83
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_84
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_85
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_86
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_87
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_88
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_89
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_90
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_91
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_92
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_93
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_94
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_95
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_96
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_97
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_98
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_99
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_100
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_101
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_102
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_103
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_104
-#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_104__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_105
-#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_105__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_106
-#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_106__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_107
-#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_107__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_108
-#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_108__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_109
-#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_109__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_110
-#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_110__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_111
-#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_111__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_112
-#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_112__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_113
-#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_113__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_114
-#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_114__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_115
-#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_115__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_116
-#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_116__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_117
-#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_117__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_118
-#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_118__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_119
-#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_119__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_120
-#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_120__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_121
-#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_121__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_122
-#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_122__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_123
-#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_123__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_124
-#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_124__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_125
-#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_125__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_126
-#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_126__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_127
-#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_127__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_IH_CREDIT
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
-//MP1_SMN_IH_SW_INT
-#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
-#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
-#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
-//MP1_SMN_IH_SW_INT_CTRL
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
-//MP1_SMN_FPS_CNT
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
-//MP1_SMN_PUB_CTRL
-#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT                                                                    0x0
-#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK                                                                      0x00000001L
-//MP1_SMN_EXT_SCRATCH0
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH1
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH2
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH3
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH4
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH5
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH6
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH7
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH8
-#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH8__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH10
-#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH10__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH11
-#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH11__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH12
-#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH12__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH13
-#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH13__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH14
-#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH14__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH15
-#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH15__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH16
-#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH16__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH17
-#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH17__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH18
-#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH18__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH19
-#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH19__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH20
-#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH20__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH21
-#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH21__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH22
-#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH22__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH23
-#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH23__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH24
-#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH24__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH25
-#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH25__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH26
-#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH26__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH27
-#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH27__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH28
-#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH28__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH29
-#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH29__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH30
-#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH30__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH31
-#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH31__DATA_MASK                                                                      0xFFFFFFFFL
-
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-//MP1_FIRMWARE_FLAGS
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                         0x0
-#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                   0x1
-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                           0x00000001L
-#define MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                                     0xFFFFFFFEL
-
-
-// addressBlock: mp_SmuMpIOPub_CruDec
-//MPIO_FIRMWARE_FLAGS
-#define MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                        0x0
-#define MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                  0x1
-#define MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                          0x00000001L
-#define MPIO_FIRMWARE_FLAGS__RESERVED_MASK                                                                    0xFFFFFFFEL
-
-
-#endif
@@ -1,359 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- *
- */
-#ifndef _mp_14_0_0_OFFSET_HEADER
-#define _mp_14_0_0_OFFSET_HEADER
-
-// addressBlock: mp_SmuMp1_SmnDec
-// base address: 0x0
-#define regMP1_SMN_C2PMSG_0                                                                             0x0240
-#define regMP1_SMN_C2PMSG_0_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_1                                                                             0x0241
-#define regMP1_SMN_C2PMSG_1_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_2                                                                             0x0242
-#define regMP1_SMN_C2PMSG_2_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_3                                                                             0x0243
-#define regMP1_SMN_C2PMSG_3_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_4                                                                             0x0244
-#define regMP1_SMN_C2PMSG_4_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_5                                                                             0x0245
-#define regMP1_SMN_C2PMSG_5_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_6                                                                             0x0246
-#define regMP1_SMN_C2PMSG_6_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_7                                                                             0x0247
-#define regMP1_SMN_C2PMSG_7_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_8                                                                             0x0248
-#define regMP1_SMN_C2PMSG_8_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_9                                                                             0x0249
-#define regMP1_SMN_C2PMSG_9_BASE_IDX                                                                    0
-#define regMP1_SMN_C2PMSG_10                                                                            0x024a
-#define regMP1_SMN_C2PMSG_10_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_11                                                                            0x024b
-#define regMP1_SMN_C2PMSG_11_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_12                                                                            0x024c
-#define regMP1_SMN_C2PMSG_12_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_13                                                                            0x024d
-#define regMP1_SMN_C2PMSG_13_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_14                                                                            0x024e
-#define regMP1_SMN_C2PMSG_14_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_15                                                                            0x024f
-#define regMP1_SMN_C2PMSG_15_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_16                                                                            0x0250
-#define regMP1_SMN_C2PMSG_16_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_17                                                                            0x0251
-#define regMP1_SMN_C2PMSG_17_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_18                                                                            0x0252
-#define regMP1_SMN_C2PMSG_18_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_19                                                                            0x0253
-#define regMP1_SMN_C2PMSG_19_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_20                                                                            0x0254
-#define regMP1_SMN_C2PMSG_20_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_21                                                                            0x0255
-#define regMP1_SMN_C2PMSG_21_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_22                                                                            0x0256
-#define regMP1_SMN_C2PMSG_22_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_23                                                                            0x0257
-#define regMP1_SMN_C2PMSG_23_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_24                                                                            0x0258
-#define regMP1_SMN_C2PMSG_24_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_25                                                                            0x0259
-#define regMP1_SMN_C2PMSG_25_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_26                                                                            0x025a
-#define regMP1_SMN_C2PMSG_26_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_27                                                                            0x025b
-#define regMP1_SMN_C2PMSG_27_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_28                                                                            0x025c
-#define regMP1_SMN_C2PMSG_28_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_29                                                                            0x025d
-#define regMP1_SMN_C2PMSG_29_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_30                                                                            0x025e
-#define regMP1_SMN_C2PMSG_30_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_31                                                                            0x025f
-#define regMP1_SMN_C2PMSG_31_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_32                                                                            0x0260
-#define regMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_33                                                                            0x0261
-#define regMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_34                                                                            0x0262
-#define regMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_35                                                                            0x0263
-#define regMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_36                                                                            0x0264
-#define regMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_37                                                                            0x0265
-#define regMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_38                                                                            0x0266
-#define regMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_39                                                                            0x0267
-#define regMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_40                                                                            0x0268
-#define regMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_41                                                                            0x0269
-#define regMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_42                                                                            0x026a
-#define regMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_43                                                                            0x026b
-#define regMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_44                                                                            0x026c
-#define regMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_45                                                                            0x026d
-#define regMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_46                                                                            0x026e
-#define regMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_47                                                                            0x026f
-#define regMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_48                                                                            0x0270
-#define regMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_49                                                                            0x0271
-#define regMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_50                                                                            0x0272
-#define regMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_51                                                                            0x0273
-#define regMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_52                                                                            0x0274
-#define regMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_53                                                                            0x0275
-#define regMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_54                                                                            0x0276
-#define regMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_55                                                                            0x0277
-#define regMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_56                                                                            0x0278
-#define regMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_57                                                                            0x0279
-#define regMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_58                                                                            0x027a
-#define regMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_59                                                                            0x027b
-#define regMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_60                                                                            0x027c
-#define regMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_61                                                                            0x027d
-#define regMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_62                                                                            0x027e
-#define regMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_63                                                                            0x027f
-#define regMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_64                                                                            0x0280
-#define regMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_65                                                                            0x0281
-#define regMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_66                                                                            0x0282
-#define regMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_67                                                                            0x0283
-#define regMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_68                                                                            0x0284
-#define regMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_69                                                                            0x0285
-#define regMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_70                                                                            0x0286
-#define regMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_71                                                                            0x0287
-#define regMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_72                                                                            0x0288
-#define regMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_73                                                                            0x0289
-#define regMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_74                                                                            0x028a
-#define regMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_75                                                                            0x028b
-#define regMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_76                                                                            0x028c
-#define regMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_77                                                                            0x028d
-#define regMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_78                                                                            0x028e
-#define regMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_79                                                                            0x028f
-#define regMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_80                                                                            0x0290
-#define regMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_81                                                                            0x0291
-#define regMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_82                                                                            0x0292
-#define regMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_83                                                                            0x0293
-#define regMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_84                                                                            0x0294
-#define regMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_85                                                                            0x0295
-#define regMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_86                                                                            0x0296
-#define regMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_87                                                                            0x0297
-#define regMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_88                                                                            0x0298
-#define regMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_89                                                                            0x0299
-#define regMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_90                                                                            0x029a
-#define regMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_91                                                                            0x029b
-#define regMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_92                                                                            0x029c
-#define regMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_93                                                                            0x029d
-#define regMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_94                                                                            0x029e
-#define regMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_95                                                                            0x029f
-#define regMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_96                                                                            0x02a0
-#define regMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_97                                                                            0x02a1
-#define regMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_98                                                                            0x02a2
-#define regMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_99                                                                            0x02a3
-#define regMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
-#define regMP1_SMN_C2PMSG_100                                                                           0x02a4
-#define regMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_101                                                                           0x02a5
-#define regMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_102                                                                           0x02a6
-#define regMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_103                                                                           0x02a7
-#define regMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_104                                                                           0x02a8
-#define regMP1_SMN_C2PMSG_104_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_105                                                                           0x02a9
-#define regMP1_SMN_C2PMSG_105_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_106                                                                           0x02aa
-#define regMP1_SMN_C2PMSG_106_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_107                                                                           0x02ab
-#define regMP1_SMN_C2PMSG_107_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_108                                                                           0x02ac
-#define regMP1_SMN_C2PMSG_108_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_109                                                                           0x02ad
-#define regMP1_SMN_C2PMSG_109_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_110                                                                           0x02ae
-#define regMP1_SMN_C2PMSG_110_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_111                                                                           0x02af
-#define regMP1_SMN_C2PMSG_111_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_112                                                                           0x02b0
-#define regMP1_SMN_C2PMSG_112_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_113                                                                           0x02b1
-#define regMP1_SMN_C2PMSG_113_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_114                                                                           0x02b2
-#define regMP1_SMN_C2PMSG_114_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_115                                                                           0x02b3
-#define regMP1_SMN_C2PMSG_115_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_116                                                                           0x02b4
-#define regMP1_SMN_C2PMSG_116_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_117                                                                           0x02b5
-#define regMP1_SMN_C2PMSG_117_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_118                                                                           0x02b6
-#define regMP1_SMN_C2PMSG_118_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_119                                                                           0x02b7
-#define regMP1_SMN_C2PMSG_119_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_120                                                                           0x02b8
-#define regMP1_SMN_C2PMSG_120_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_121                                                                           0x02b9
-#define regMP1_SMN_C2PMSG_121_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_122                                                                           0x02ba
-#define regMP1_SMN_C2PMSG_122_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_123                                                                           0x02bb
-#define regMP1_SMN_C2PMSG_123_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_124                                                                           0x02bc
-#define regMP1_SMN_C2PMSG_124_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_125                                                                           0x02bd
-#define regMP1_SMN_C2PMSG_125_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_126                                                                           0x02be
-#define regMP1_SMN_C2PMSG_126_BASE_IDX                                                                  0
-#define regMP1_SMN_C2PMSG_127                                                                           0x02bf
-#define regMP1_SMN_C2PMSG_127_BASE_IDX                                                                  0
-#define regMP1_SMN_IH_CREDIT                                                                            0x0340
-#define regMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
-#define regMP1_SMN_IH_SW_INT                                                                            0x0341
-#define regMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
-#define regMP1_SMN_IH_SW_INT_CTRL                                                                       0x0342
-#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
-#define regMP1_SMN_FPS_CNT                                                                              0x0343
-#define regMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
-#define regMP1_SMN_EXT_SCRATCH0                                                                         0x03c0
-#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH1                                                                         0x03c1
-#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH2                                                                         0x03c2
-#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH3                                                                         0x03c3
-#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH4                                                                         0x03c4
-#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH5                                                                         0x03c5
-#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH6                                                                         0x03c6
-#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH7                                                                         0x03c7
-#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH8                                                                         0x03c8
-#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH9                                                                         0x03c9
-#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX                                                                0
-#define regMP1_SMN_EXT_SCRATCH10                                                                        0x03ca
-#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH11                                                                        0x03cb
-#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH12                                                                        0x03cc
-#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH13                                                                        0x03cd
-#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH14                                                                        0x03ce
-#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH15                                                                        0x03cf
-#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH16                                                                        0x03d0
-#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH17                                                                        0x03d1
-#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH18                                                                        0x03d2
-#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH19                                                                        0x03d3
-#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH20                                                                        0x03d4
-#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH21                                                                        0x03d5
-#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH22                                                                        0x03d6
-#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH23                                                                        0x03d7
-#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH24                                                                        0x03d8
-#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH25                                                                        0x03d9
-#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH26                                                                        0x03da
-#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH27                                                                        0x03db
-#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH28                                                                        0x03dc
-#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH29                                                                        0x03dd
-#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH30                                                                        0x03de
-#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX                                                               0
-#define regMP1_SMN_EXT_SCRATCH31                                                                        0x03df
-#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX                                                               0
-
-
-#endif
@@ -1,534 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _mp_14_0_0_SH_MASK_HEADER
-#define _mp_14_0_0_SH_MASK_HEADER
-
-// addressBlock: mp_SmuMp1Pub_CruDec
-//MP1_CRU1_MP1_FIRMWARE_FLAGS
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                0x0
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                          0x1
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                  0x00000001L
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                            0xFFFFFFFEL
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-//MP1_SMN_C2PMSG_0
-#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_0__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_1
-#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_1__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_2
-#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_2__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_3
-#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_3__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_4
-#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_4__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_5
-#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_5__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_6
-#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_6__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_7
-#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_7__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_8
-#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_8__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_9
-#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_9__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_10
-#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_10__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_11
-#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_11__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_12
-#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_12__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_13
-#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_13__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_14
-#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_14__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_15
-#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_15__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_16
-#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_16__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_17
-#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_17__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_18
-#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_18__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_19
-#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_19__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_20
-#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_20__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_21
-#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_21__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_22
-#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_22__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_23
-#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_23__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_24
-#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_24__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_25
-#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_25__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_26
-#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_26__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_27
-#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_27__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_28
-#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_28__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_29
-#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_29__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_30
-#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_30__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_31
-#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_31__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_32
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_33
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_34
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_35
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_36
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_37
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_38
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_39
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_40
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_41
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_42
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_43
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_44
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_45
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_46
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_47
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_48
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_49
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_50
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_51
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_52
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_53
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_54
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_55
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_56
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_57
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_58
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_59
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_60
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_61
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_62
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_63
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_64
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_65
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_66
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_67
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_68
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_69
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_70
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_71
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_72
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_73
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_74
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_75
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_76
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_77
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_78
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_79
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_80
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_81
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_82
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_83
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_84
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_85
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_86
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_87
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_88
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_89
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_90
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_91
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_92
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_93
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_94
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_95
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_96
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_97
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_98
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_99
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_100
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_101
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_102
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_103
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_104
-#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_104__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_105
-#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_105__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_106
-#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_106__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_107
-#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_107__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_108
-#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_108__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_109
-#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_109__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_110
-#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_110__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_111
-#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_111__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_112
-#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_112__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_113
-#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_113__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_114
-#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_114__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_115
-#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_115__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_116
-#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_116__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_117
-#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_117__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_118
-#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_118__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_119
-#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_119__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_120
-#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_120__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_121
-#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_121__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_122
-#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_122__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_123
-#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_123__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_124
-#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_124__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_125
-#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_125__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_126
-#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_126__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_127
-#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_127__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_IH_CREDIT
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
-//MP1_SMN_IH_SW_INT
-#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
-#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
-#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
-//MP1_SMN_IH_SW_INT_CTRL
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
-//MP1_SMN_FPS_CNT
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH0
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH1
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH2
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH3
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH4
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH5
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH6
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH7
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH8
-#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH8__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH9
-#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH9__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH10
-#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH10__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH11
-#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH11__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH12
-#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH12__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH13
-#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH13__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH14
-#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH14__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH15
-#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH15__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH16
-#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH16__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH17
-#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH17__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH18
-#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH18__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH19
-#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH19__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH20
-#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH20__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH21
-#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH21__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH22
-#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH22__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH23
-#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH23__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH24
-#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH24__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH25
-#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH25__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH26
-#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH26__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH27
-#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH27__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH28
-#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH28__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH29
-#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH29__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH30
-#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH30__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH31
-#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH31__DATA_MASK                                                                      0xFFFFFFFFL
-
-#endif
@@ -1,468 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _mp_14_0_2_OFFSET_HEADER
-#define _mp_14_0_2_OFFSET_HEADER
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-// base address: 0x0
-#define regMP1_SMN_C2PMSG_0                                                                             0x0040
-#define regMP1_SMN_C2PMSG_0_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_1                                                                             0x0041
-#define regMP1_SMN_C2PMSG_1_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_2                                                                             0x0042
-#define regMP1_SMN_C2PMSG_2_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_3                                                                             0x0043
-#define regMP1_SMN_C2PMSG_3_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_4                                                                             0x0044
-#define regMP1_SMN_C2PMSG_4_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_5                                                                             0x0045
-#define regMP1_SMN_C2PMSG_5_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_6                                                                             0x0046
-#define regMP1_SMN_C2PMSG_6_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_7                                                                             0x0047
-#define regMP1_SMN_C2PMSG_7_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_8                                                                             0x0048
-#define regMP1_SMN_C2PMSG_8_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_9                                                                             0x0049
-#define regMP1_SMN_C2PMSG_9_BASE_IDX                                                                    1
-#define regMP1_SMN_C2PMSG_10                                                                            0x004a
-#define regMP1_SMN_C2PMSG_10_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_11                                                                            0x004b
-#define regMP1_SMN_C2PMSG_11_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_12                                                                            0x004c
-#define regMP1_SMN_C2PMSG_12_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_13                                                                            0x004d
-#define regMP1_SMN_C2PMSG_13_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_14                                                                            0x004e
-#define regMP1_SMN_C2PMSG_14_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_15                                                                            0x004f
-#define regMP1_SMN_C2PMSG_15_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_16                                                                            0x0050
-#define regMP1_SMN_C2PMSG_16_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_17                                                                            0x0051
-#define regMP1_SMN_C2PMSG_17_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_18                                                                            0x0052
-#define regMP1_SMN_C2PMSG_18_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_19                                                                            0x0053
-#define regMP1_SMN_C2PMSG_19_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_20                                                                            0x0054
-#define regMP1_SMN_C2PMSG_20_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_21                                                                            0x0055
-#define regMP1_SMN_C2PMSG_21_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_22                                                                            0x0056
-#define regMP1_SMN_C2PMSG_22_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_23                                                                            0x0057
-#define regMP1_SMN_C2PMSG_23_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_24                                                                            0x0058
-#define regMP1_SMN_C2PMSG_24_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_25                                                                            0x0059
-#define regMP1_SMN_C2PMSG_25_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_26                                                                            0x005a
-#define regMP1_SMN_C2PMSG_26_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_27                                                                            0x005b
-#define regMP1_SMN_C2PMSG_27_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_28                                                                            0x005c
-#define regMP1_SMN_C2PMSG_28_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_29                                                                            0x005d
-#define regMP1_SMN_C2PMSG_29_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_30                                                                            0x005e
-#define regMP1_SMN_C2PMSG_30_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_31                                                                            0x005f
-#define regMP1_SMN_C2PMSG_31_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_32                                                                            0x0060
-#define regMP1_SMN_C2PMSG_32_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_33                                                                            0x0061
-#define regMP1_SMN_C2PMSG_33_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_34                                                                            0x0062
-#define regMP1_SMN_C2PMSG_34_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_35                                                                            0x0063
-#define regMP1_SMN_C2PMSG_35_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_36                                                                            0x0064
-#define regMP1_SMN_C2PMSG_36_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_37                                                                            0x0065
-#define regMP1_SMN_C2PMSG_37_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_38                                                                            0x0066
-#define regMP1_SMN_C2PMSG_38_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_39                                                                            0x0067
-#define regMP1_SMN_C2PMSG_39_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_40                                                                            0x0068
-#define regMP1_SMN_C2PMSG_40_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_41                                                                            0x0069
-#define regMP1_SMN_C2PMSG_41_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_42                                                                            0x006a
-#define regMP1_SMN_C2PMSG_42_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_43                                                                            0x006b
-#define regMP1_SMN_C2PMSG_43_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_44                                                                            0x006c
-#define regMP1_SMN_C2PMSG_44_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_45                                                                            0x006d
-#define regMP1_SMN_C2PMSG_45_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_46                                                                            0x006e
-#define regMP1_SMN_C2PMSG_46_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_47                                                                            0x006f
-#define regMP1_SMN_C2PMSG_47_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_48                                                                            0x0070
-#define regMP1_SMN_C2PMSG_48_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_49                                                                            0x0071
-#define regMP1_SMN_C2PMSG_49_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_50                                                                            0x0072
-#define regMP1_SMN_C2PMSG_50_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_51                                                                            0x0073
-#define regMP1_SMN_C2PMSG_51_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_52                                                                            0x0074
-#define regMP1_SMN_C2PMSG_52_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_53                                                                            0x0075
-#define regMP1_SMN_C2PMSG_53_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_54                                                                            0x0076
-#define regMP1_SMN_C2PMSG_54_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_55                                                                            0x0077
-#define regMP1_SMN_C2PMSG_55_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_56                                                                            0x0078
-#define regMP1_SMN_C2PMSG_56_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_57                                                                            0x0079
-#define regMP1_SMN_C2PMSG_57_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_58                                                                            0x007a
-#define regMP1_SMN_C2PMSG_58_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_59                                                                            0x007b
-#define regMP1_SMN_C2PMSG_59_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_60                                                                            0x007c
-#define regMP1_SMN_C2PMSG_60_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_61                                                                            0x007d
-#define regMP1_SMN_C2PMSG_61_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_62                                                                            0x007e
-#define regMP1_SMN_C2PMSG_62_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_63                                                                            0x007f
-#define regMP1_SMN_C2PMSG_63_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_64                                                                            0x0080
-#define regMP1_SMN_C2PMSG_64_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_65                                                                            0x0081
-#define regMP1_SMN_C2PMSG_65_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_66                                                                            0x0082
-#define regMP1_SMN_C2PMSG_66_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_67                                                                            0x0083
-#define regMP1_SMN_C2PMSG_67_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_68                                                                            0x0084
-#define regMP1_SMN_C2PMSG_68_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_69                                                                            0x0085
-#define regMP1_SMN_C2PMSG_69_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_70                                                                            0x0086
-#define regMP1_SMN_C2PMSG_70_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_71                                                                            0x0087
-#define regMP1_SMN_C2PMSG_71_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_72                                                                            0x0088
-#define regMP1_SMN_C2PMSG_72_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_73                                                                            0x0089
-#define regMP1_SMN_C2PMSG_73_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_74                                                                            0x008a
-#define regMP1_SMN_C2PMSG_74_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_75                                                                            0x008b
-#define regMP1_SMN_C2PMSG_75_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_76                                                                            0x008c
-#define regMP1_SMN_C2PMSG_76_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_77                                                                            0x008d
-#define regMP1_SMN_C2PMSG_77_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_78                                                                            0x008e
-#define regMP1_SMN_C2PMSG_78_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_79                                                                            0x008f
-#define regMP1_SMN_C2PMSG_79_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_80                                                                            0x0090
-#define regMP1_SMN_C2PMSG_80_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_81                                                                            0x0091
-#define regMP1_SMN_C2PMSG_81_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_82                                                                            0x0092
-#define regMP1_SMN_C2PMSG_82_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_83                                                                            0x0093
-#define regMP1_SMN_C2PMSG_83_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_84                                                                            0x0094
-#define regMP1_SMN_C2PMSG_84_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_85                                                                            0x0095
-#define regMP1_SMN_C2PMSG_85_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_86                                                                            0x0096
-#define regMP1_SMN_C2PMSG_86_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_87                                                                            0x0097
-#define regMP1_SMN_C2PMSG_87_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_88                                                                            0x0098
-#define regMP1_SMN_C2PMSG_88_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_89                                                                            0x0099
-#define regMP1_SMN_C2PMSG_89_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_90                                                                            0x009a
-#define regMP1_SMN_C2PMSG_90_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_91                                                                            0x009b
-#define regMP1_SMN_C2PMSG_91_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_92                                                                            0x009c
-#define regMP1_SMN_C2PMSG_92_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_93                                                                            0x009d
-#define regMP1_SMN_C2PMSG_93_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_94                                                                            0x009e
-#define regMP1_SMN_C2PMSG_94_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_95                                                                            0x009f
-#define regMP1_SMN_C2PMSG_95_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_96                                                                            0x00a0
-#define regMP1_SMN_C2PMSG_96_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_97                                                                            0x00a1
-#define regMP1_SMN_C2PMSG_97_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_98                                                                            0x00a2
-#define regMP1_SMN_C2PMSG_98_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_99                                                                            0x00a3
-#define regMP1_SMN_C2PMSG_99_BASE_IDX                                                                   1
-#define regMP1_SMN_C2PMSG_100                                                                           0x00a4
-#define regMP1_SMN_C2PMSG_100_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_101                                                                           0x00a5
-#define regMP1_SMN_C2PMSG_101_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_102                                                                           0x00a6
-#define regMP1_SMN_C2PMSG_102_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_103                                                                           0x00a7
-#define regMP1_SMN_C2PMSG_103_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_104                                                                           0x00a8
-#define regMP1_SMN_C2PMSG_104_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_105                                                                           0x00a9
-#define regMP1_SMN_C2PMSG_105_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_106                                                                           0x00aa
-#define regMP1_SMN_C2PMSG_106_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_107                                                                           0x00ab
-#define regMP1_SMN_C2PMSG_107_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_108                                                                           0x00ac
-#define regMP1_SMN_C2PMSG_108_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_109                                                                           0x00ad
-#define regMP1_SMN_C2PMSG_109_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_110                                                                           0x00ae
-#define regMP1_SMN_C2PMSG_110_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_111                                                                           0x00af
-#define regMP1_SMN_C2PMSG_111_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_112                                                                           0x00b0
-#define regMP1_SMN_C2PMSG_112_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_113                                                                           0x00b1
-#define regMP1_SMN_C2PMSG_113_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_114                                                                           0x00b2
-#define regMP1_SMN_C2PMSG_114_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_115                                                                           0x00b3
-#define regMP1_SMN_C2PMSG_115_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_116                                                                           0x00b4
-#define regMP1_SMN_C2PMSG_116_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_117                                                                           0x00b5
-#define regMP1_SMN_C2PMSG_117_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_118                                                                           0x00b6
-#define regMP1_SMN_C2PMSG_118_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_119                                                                           0x00b7
-#define regMP1_SMN_C2PMSG_119_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_120                                                                           0x00b8
-#define regMP1_SMN_C2PMSG_120_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_121                                                                           0x00b9
-#define regMP1_SMN_C2PMSG_121_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_122                                                                           0x00ba
-#define regMP1_SMN_C2PMSG_122_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_123                                                                           0x00bb
-#define regMP1_SMN_C2PMSG_123_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_124                                                                           0x00bc
-#define regMP1_SMN_C2PMSG_124_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_125                                                                           0x00bd
-#define regMP1_SMN_C2PMSG_125_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_126                                                                           0x00be
-#define regMP1_SMN_C2PMSG_126_BASE_IDX                                                                  1
-#define regMP1_SMN_C2PMSG_127                                                                           0x00bf
-#define regMP1_SMN_C2PMSG_127_BASE_IDX                                                                  1
-#define regMP1_SMN_IH_CREDIT                                                                            0x0140
-#define regMP1_SMN_IH_CREDIT_BASE_IDX                                                                   1
-#define regMP1_SMN_IH_SW_INT                                                                            0x0141
-#define regMP1_SMN_IH_SW_INT_BASE_IDX                                                                   1
-#define regMP1_SMN_IH_SW_INT_CTRL                                                                       0x0142
-#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              1
-#define regMP1_SMN_FPS_CNT                                                                              0x0143
-#define regMP1_SMN_FPS_CNT_BASE_IDX                                                                     1
-#define regMP1_SMN_PUB_CTRL                                                                             0x0144
-#define regMP1_SMN_PUB_CTRL_BASE_IDX                                                                    1
-#define regMP1_SMN_EXT_SCRATCH0                                                                         0x01c0
-#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH1                                                                         0x01c1
-#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH2                                                                         0x01c2
-#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH3                                                                         0x01c3
-#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH4                                                                         0x01c4
-#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH5                                                                         0x01c5
-#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH6                                                                         0x01c6
-#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH7                                                                         0x01c7
-#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH8                                                                         0x01c8
-#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH9                                                                         0x01c9
-#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX                                                                1
-#define regMP1_SMN_EXT_SCRATCH10                                                                        0x01ca
-#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH11                                                                        0x01cb
-#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH12                                                                        0x01cc
-#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH13                                                                        0x01cd
-#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH14                                                                        0x01ce
-#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH15                                                                        0x01cf
-#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH16                                                                        0x01d0
-#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH17                                                                        0x01d1
-#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH18                                                                        0x01d2
-#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH19                                                                        0x01d3
-#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH20                                                                        0x01d4
-#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH21                                                                        0x01d5
-#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH22                                                                        0x01d6
-#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH23                                                                        0x01d7
-#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH24                                                                        0x01d8
-#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH25                                                                        0x01d9
-#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH26                                                                        0x01da
-#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH27                                                                        0x01db
-#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH28                                                                        0x01dc
-#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH29                                                                        0x01dd
-#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH30                                                                        0x01de
-#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX                                                               1
-#define regMP1_SMN_EXT_SCRATCH31                                                                        0x01df
-#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX                                                               1
-
-
-// addressBlock: mp_SmuMpASP_SmnDec
-// base address: 0x0
-#define regMPASP_SMN_C2PMSG_32                                                                          0x0060
-#define regMPASP_SMN_C2PMSG_32_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_33                                                                          0x0061
-#define regMPASP_SMN_C2PMSG_33_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_34                                                                          0x0062
-#define regMPASP_SMN_C2PMSG_34_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_35                                                                          0x0063
-#define regMPASP_SMN_C2PMSG_35_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_36                                                                          0x0064
-#define regMPASP_SMN_C2PMSG_36_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_37                                                                          0x0065
-#define regMPASP_SMN_C2PMSG_37_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_38                                                                          0x0066
-#define regMPASP_SMN_C2PMSG_38_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_39                                                                          0x0067
-#define regMPASP_SMN_C2PMSG_39_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_60                                                                          0x007c
-#define regMPASP_SMN_C2PMSG_60_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_61                                                                          0x007d
-#define regMPASP_SMN_C2PMSG_61_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_62                                                                          0x007e
-#define regMPASP_SMN_C2PMSG_62_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_63                                                                          0x007f
-#define regMPASP_SMN_C2PMSG_63_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_64                                                                          0x0080
-#define regMPASP_SMN_C2PMSG_64_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_65                                                                          0x0081
-#define regMPASP_SMN_C2PMSG_65_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_66                                                                          0x0082
-#define regMPASP_SMN_C2PMSG_66_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_67                                                                          0x0083
-#define regMPASP_SMN_C2PMSG_67_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_68                                                                          0x0084
-#define regMPASP_SMN_C2PMSG_68_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_69                                                                          0x0085
-#define regMPASP_SMN_C2PMSG_69_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_70                                                                          0x0086
-#define regMPASP_SMN_C2PMSG_70_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_71                                                                          0x0087
-#define regMPASP_SMN_C2PMSG_71_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_72                                                                          0x0088
-#define regMPASP_SMN_C2PMSG_72_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_73                                                                          0x0089
-#define regMPASP_SMN_C2PMSG_73_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_74                                                                          0x008a
-#define regMPASP_SMN_C2PMSG_74_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_75                                                                          0x008b
-#define regMPASP_SMN_C2PMSG_75_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_76                                                                          0x008c
-#define regMPASP_SMN_C2PMSG_76_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_77                                                                          0x008d
-#define regMPASP_SMN_C2PMSG_77_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_78                                                                          0x008e
-#define regMPASP_SMN_C2PMSG_78_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_79                                                                          0x008f
-#define regMPASP_SMN_C2PMSG_79_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_80                                                                          0x0090
-#define regMPASP_SMN_C2PMSG_80_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_81                                                                          0x0091
-#define regMPASP_SMN_C2PMSG_81_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_82                                                                          0x0092
-#define regMPASP_SMN_C2PMSG_82_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_83                                                                          0x0093
-#define regMPASP_SMN_C2PMSG_83_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_84                                                                          0x0094
-#define regMPASP_SMN_C2PMSG_84_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_85                                                                          0x0095
-#define regMPASP_SMN_C2PMSG_85_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_86                                                                          0x0096
-#define regMPASP_SMN_C2PMSG_86_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_87                                                                          0x0097
-#define regMPASP_SMN_C2PMSG_87_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_88                                                                          0x0098
-#define regMPASP_SMN_C2PMSG_88_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_89                                                                          0x0099
-#define regMPASP_SMN_C2PMSG_89_BASE_IDX                                                                 0
-#define regMPASP_SMN_C2PMSG_100                                                                         0x00a4
-#define regMPASP_SMN_C2PMSG_100_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_101                                                                         0x00a5
-#define regMPASP_SMN_C2PMSG_101_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_102                                                                         0x00a6
-#define regMPASP_SMN_C2PMSG_102_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_103                                                                         0x00a7
-#define regMPASP_SMN_C2PMSG_103_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_109                                                                         0x00ad
-#define regMPASP_SMN_C2PMSG_109_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_115                                                                         0x00b3
-#define regMPASP_SMN_C2PMSG_115_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_116                                                                         0x00b4
-#define regMPASP_SMN_C2PMSG_116_BASE_IDX                                                                0
-#define regMPASP_SMN_C2PMSG_119_BASE_IDX                                                                0
-#define regMPASP_SMN_IH_CREDIT                                                                          0x0140
-#define regMPASP_SMN_IH_CREDIT_BASE_IDX                                                                 0
-#define regMPASP_SMN_IH_SW_INT                                                                          0x0141
-#define regMPASP_SMN_IH_SW_INT_BASE_IDX                                                                 0
-#define regMPASP_SMN_IH_SW_INT_CTRL                                                                     0x0142
-#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX                                                            0
-
-
-// addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec
-// base address: 0x3b00000
-#define regMP1_CRU1_MP1_FIRMWARE_FLAGS                                                                  0x4009
-#define regMP1_CRU1_MP1_FIRMWARE_FLAGS_BASE_IDX                                                         7
-
-
-#endif
@@ -1,692 +0,0 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef _mp_14_0_2_SH_MASK_HEADER
-#define _mp_14_0_2_SH_MASK_HEADER
-
-
-// addressBlock: mp_SmuMp1_SmnDec
-//MP1_SMN_C2PMSG_0
-#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_0__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_1
-#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_1__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_2
-#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_2__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_3
-#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_3__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_4
-#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_4__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_5
-#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_5__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_6
-#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_6__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_7
-#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_7__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_8
-#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_8__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_9
-#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT                                                                      0x0
-#define MP1_SMN_C2PMSG_9__CONTENT_MASK                                                                        0xFFFFFFFFL
-//MP1_SMN_C2PMSG_10
-#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_10__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_11
-#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_11__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_12
-#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_12__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_13
-#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_13__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_14
-#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_14__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_15
-#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_15__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_16
-#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_16__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_17
-#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_17__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_18
-#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_18__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_19
-#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_19__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_20
-#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_20__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_21
-#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_21__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_22
-#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_22__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_23
-#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_23__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_24
-#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_24__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_25
-#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_25__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_26
-#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_26__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_27
-#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_27__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_28
-#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_28__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_29
-#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_29__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_30
-#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_30__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_31
-#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_31__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_32
-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_33
-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_34
-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_35
-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_36
-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_37
-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_38
-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_39
-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_40
-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_41
-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_42
-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_43
-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_44
-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_45
-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_46
-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_47
-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_48
-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_49
-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_50
-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_51
-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_52
-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_53
-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_54
-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_55
-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_56
-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_57
-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_58
-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_59
-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_60
-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_61
-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_62
-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_63
-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_64
-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_65
-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_66
-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_67
-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_68
-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_69
-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_70
-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_71
-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_72
-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_73
-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_74
-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_75
-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_76
-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_77
-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_78
-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_79
-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_80
-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_81
-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_82
-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_83
-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_84
-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_85
-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_86
-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_87
-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_88
-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_89
-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_90
-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_91
-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_92
-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_93
-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_94
-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_95
-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_96
-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_97
-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_98
-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_99
-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
-#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_C2PMSG_100
-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_101
-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_102
-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_103
-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_104
-#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_104__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_105
-#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_105__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_106
-#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_106__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_107
-#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_107__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_108
-#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_108__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_109
-#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_109__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_110
-#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_110__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_111
-#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_111__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_112
-#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_112__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_113
-#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_113__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_114
-#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_114__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_115
-#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_115__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_116
-#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_116__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_117
-#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_117__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_118
-#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_118__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_119
-#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_119__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_120
-#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_120__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_121
-#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_121__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_122
-#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_122__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_123
-#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_123__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_124
-#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_124__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_125
-#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_125__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_126
-#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_126__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_C2PMSG_127
-#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT                                                                    0x0
-#define MP1_SMN_C2PMSG_127__CONTENT_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_IH_CREDIT
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
-//MP1_SMN_IH_SW_INT
-#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
-#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
-#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
-#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
-//MP1_SMN_IH_SW_INT_CTRL
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
-#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
-#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
-//MP1_SMN_FPS_CNT
-#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
-#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
-//MP1_SMN_PUB_CTRL
-#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT                                                                    0x0
-#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK                                                                      0x00000001L
-//MP1_SMN_EXT_SCRATCH0
-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH1
-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH2
-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH3
-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH4
-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH5
-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH6
-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH7
-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH8
-#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH8__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH9
-#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT                                                                     0x0
-#define MP1_SMN_EXT_SCRATCH9__DATA_MASK                                                                       0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH10
-#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH10__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH11
-#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH11__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH12
-#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH12__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH13
-#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH13__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH14
-#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH14__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH15
-#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH15__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH16
-#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH16__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH17
-#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH17__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH18
-#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH18__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH19
-#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH19__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH20
-#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH20__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH21
-#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH21__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH22
-#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH22__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH23
-#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH23__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH24
-#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH24__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH25
-#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH25__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH26
-#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH26__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH27
-#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH27__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH28
-#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH28__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH29
-#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH29__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH30
-#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH30__DATA_MASK                                                                      0xFFFFFFFFL
-//MP1_SMN_EXT_SCRATCH31
-#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT                                                                    0x0
-#define MP1_SMN_EXT_SCRATCH31__DATA_MASK                                                                      0xFFFFFFFFL
-
-
-// addressBlock: mp_SmuMpASP_SmnDec
-//MPASP_SMN_C2PMSG_32
-#define MPASP_SMN_C2PMSG_32__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_32__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_33
-#define MPASP_SMN_C2PMSG_33__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_33__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_34
-#define MPASP_SMN_C2PMSG_34__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_34__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_35
-#define MPASP_SMN_C2PMSG_35__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_35__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_36
-#define MPASP_SMN_C2PMSG_36__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_36__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_37
-#define MPASP_SMN_C2PMSG_37__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_37__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_38
-#define MPASP_SMN_C2PMSG_38__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_38__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_39
-#define MPASP_SMN_C2PMSG_39__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_39__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_60
-#define MPASP_SMN_C2PMSG_60__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_60__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_61
-#define MPASP_SMN_C2PMSG_61__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_61__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_62
-#define MPASP_SMN_C2PMSG_62__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_62__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_63
-#define MPASP_SMN_C2PMSG_63__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_63__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_64
-#define MPASP_SMN_C2PMSG_64__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_64__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_65
-#define MPASP_SMN_C2PMSG_65__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_65__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_66
-#define MPASP_SMN_C2PMSG_66__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_66__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_67
-#define MPASP_SMN_C2PMSG_67__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_67__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_68
-#define MPASP_SMN_C2PMSG_68__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_68__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_69
-#define MPASP_SMN_C2PMSG_69__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_69__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_70
-#define MPASP_SMN_C2PMSG_70__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_70__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_71
-#define MPASP_SMN_C2PMSG_71__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_71__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_72
-#define MPASP_SMN_C2PMSG_72__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_72__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_73
-#define MPASP_SMN_C2PMSG_73__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_73__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_74
-#define MPASP_SMN_C2PMSG_74__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_74__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_75
-#define MPASP_SMN_C2PMSG_75__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_75__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_76
-#define MPASP_SMN_C2PMSG_76__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_76__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_77
-#define MPASP_SMN_C2PMSG_77__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_77__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_78
-#define MPASP_SMN_C2PMSG_78__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_78__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_79
-#define MPASP_SMN_C2PMSG_79__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_79__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_80
-#define MPASP_SMN_C2PMSG_80__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_80__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_81
-#define MPASP_SMN_C2PMSG_81__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_81__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_82
-#define MPASP_SMN_C2PMSG_82__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_82__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_83
-#define MPASP_SMN_C2PMSG_83__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_83__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_84
-#define MPASP_SMN_C2PMSG_84__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_84__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_85
-#define MPASP_SMN_C2PMSG_85__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_85__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_86
-#define MPASP_SMN_C2PMSG_86__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_86__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_87
-#define MPASP_SMN_C2PMSG_87__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_87__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_88
-#define MPASP_SMN_C2PMSG_88__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_88__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_89
-#define MPASP_SMN_C2PMSG_89__CONTENT__SHIFT                                                                   0x0
-#define MPASP_SMN_C2PMSG_89__CONTENT_MASK                                                                     0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_100
-#define MPASP_SMN_C2PMSG_100__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_100__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_101
-#define MPASP_SMN_C2PMSG_101__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_101__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_102
-#define MPASP_SMN_C2PMSG_102__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_102__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_103
-#define MPASP_SMN_C2PMSG_103__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_103__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_109
-#define MPASP_SMN_C2PMSG_109__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_109__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_115
-#define MPASP_SMN_C2PMSG_115__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_115__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_C2PMSG_116
-#define MPASP_SMN_C2PMSG_116__CONTENT__SHIFT                                                                  0x0
-#define MPASP_SMN_C2PMSG_116__CONTENT_MASK                                                                    0xFFFFFFFFL
-//MPASP_SMN_IH_CREDIT
-#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                              0x0
-#define MPASP_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                 0x10
-#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                0x00000003L
-#define MPASP_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                   0x00FF0000L
-//MPASP_SMN_IH_SW_INT
-#define MPASP_SMN_IH_SW_INT__ID__SHIFT                                                                        0x0
-#define MPASP_SMN_IH_SW_INT__VALID__SHIFT                                                                     0x8
-#define MPASP_SMN_IH_SW_INT__ID_MASK                                                                          0x000000FFL
-#define MPASP_SMN_IH_SW_INT__VALID_MASK                                                                       0x00000100L
-//MPASP_SMN_IH_SW_INT_CTRL
-#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                             0x0
-#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                              0x8
-#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                               0x00000001L
-#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                0x00000100L
-
-
-// addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec
-//MP1_CRU1_MP1_FIRMWARE_FLAGS
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                0x0
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                          0x1
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                  0x00000001L
-#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                            0xFFFFFFFEL
-
-
-#endif
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